[llvm] [ARM] fix `r14` aliasing `lr` on `thumb-1` (PR #225746)
Folkert de Vries via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 12:07:30 PDT 2026
https://github.com/folkertdev updated https://github.com/llvm/llvm-project/pull/225746
>From ee8d246c772b9c6aaaa1678b309b2e9ddeef2cf5 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert at folkertdev.nl>
Date: Wed, 23 Sep 2026 14:22:18 +0200
Subject: [PATCH 1/2] rename `-check-prefix=CHECK` to `ARM_NONE`
using `CHECK` as a custom `check-prefix` is just really confusing
---
llvm/test/CodeGen/ARM/inline-asm-clobber.ll | 30 ++++++++++-----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
index cb84fa4fd032ae..24ba37f9a8a339 100644
--- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
+++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc <%s -mtriple=arm-none-eabi 2>&1 | FileCheck %s -check-prefix=CHECK
+; RUN: llc <%s -mtriple=arm-none-eabi 2>&1 | FileCheck %s -check-prefix=ARM_NONE
; RUN: llc <%s -mtriple=arm-none-eabi -relocation-model=rwpi 2>&1 \
; RUN: | FileCheck %s -check-prefix=RWPI
@@ -11,8 +11,8 @@
; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3
; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS3
-; CHECK: warning: inline asm clobber list contains reserved registers: SP, PC
-; CHECK: warning: inline asm clobber list contains reserved registers: R11
+; ARM_NONE: warning: inline asm clobber list contains reserved registers: SP, PC
+; ARM_NONE: warning: inline asm clobber list contains reserved registers: R11
; RWPI: warning: inline asm clobber list contains reserved registers: R9, SP, PC
; RWPI: warning: inline asm clobber list contains reserved registers: R11
; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11, SP, PC
@@ -35,12 +35,12 @@ define i32 @bar(i32 %i) {
; r14 is an alias for lr.
define void @clobber_r14() nounwind {
-; CHECK-LABEL: clobber_r14:
-; CHECK: .save {r11, lr}
-; CHECK: push {r11, lr}
-; CHECK-NEXT: @APP
-; CHECK-NEXT: @NO_APP
-; CHECK-NEXT: pop {r11, lr}
+; ARM_NONE-LABEL: clobber_r14:
+; ARM_NONE: .save {r11, lr}
+; ARM_NONE: push {r11, lr}
+; ARM_NONE-NEXT: @APP
+; ARM_NONE-NEXT: @NO_APP
+; ARM_NONE-NEXT: pop {r11, lr}
tail call void asm sideeffect "", "~{r14}"()
ret void
}
@@ -48,12 +48,12 @@ define void @clobber_r14() nounwind {
; r14 is an alias for lr.
define i32 @read_r14() nounwind {
start:
-; CHECK-LABEL: read_r14:
-; CHECK: push {r11, lr}
-; CHECK-NEXT: @APP
-; CHECK-NEXT: @NO_APP
-; CHECK-NEXT: mov r0, lr
-; CHECK-NEXT: pop {r11, lr}
+; ARM_NONE-LABEL: read_r14:
+; ARM_NONE: push {r11, lr}
+; ARM_NONE-NEXT: @APP
+; ARM_NONE-NEXT: @NO_APP
+; ARM_NONE-NEXT: mov r0, lr
+; ARM_NONE-NEXT: pop {r11, lr}
%1 = tail call i32 asm sideeffect alignstack "", "=&{r14},~{cc},~{memory}"()
ret i32 %1
}
>From 0db3b537a7e4e3e762f4fb64d6f3e40965d39017 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert at folkertdev.nl>
Date: Wed, 23 Sep 2026 14:23:22 +0200
Subject: [PATCH 2/2] fix `r14` aliasing `lr` on thumb-1
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
llvm/test/CodeGen/ARM/inline-asm-clobber.ll | 20 ++++++++++++++++++--
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 194b597bc77ba2..3e8ef08888ffdc 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20707,7 +20707,7 @@ RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
// r14 is an alias of lr.
if (StringRef("{r14}").equals_insensitive(Constraint))
- return std::make_pair(unsigned(ARM::LR), getRegClassFor(MVT::i32));
+ Constraint = "{lr}";
auto RCP = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
if (isIncompatibleReg(RCP.first, VT))
diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
index 24ba37f9a8a339..4260b625c95b12 100644
--- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
+++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll
@@ -11,6 +11,10 @@
; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3
; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS3
+; RUN: llc <%s -mtriple=thumbv6m-none-eabi 2>&1 | FileCheck %s -check-prefix=THUMB
+; RUN: llc <%s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s -check-prefix=THUMB
+; RUN: llc <%s -mtriple=thumbv7m-none-eabi 2>&1 | FileCheck %s -check-prefix=THUMB
+
; ARM_NONE: warning: inline asm clobber list contains reserved registers: SP, PC
; ARM_NONE: warning: inline asm clobber list contains reserved registers: R11
; RWPI: warning: inline asm clobber list contains reserved registers: R9, SP, PC
@@ -19,16 +23,17 @@
; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11
; IOS2: warning: inline asm clobber list contains reserved registers: R9, SP, PC
; IOS3: warning: inline asm clobber list contains reserved registers: SP, PC
+; THUMB: warning: inline asm clobber list contains reserved registers: SP, PC
define void @foo() nounwind {
- call void asm sideeffect "mov r7, #1",
+ call void asm sideeffect "movs r7, #1",
"~{r9},~{r11},~{r12},~{lr},~{sp},~{pc},~{r10}"()
ret void
}
define i32 @bar(i32 %i) {
%vla = alloca i32, i32 %i, align 4
- tail call void asm sideeffect "mov r7, #1", "~{r11}"()
+ tail call void asm sideeffect "movs r7, #1", "~{r11}"()
%1 = load volatile i32, ptr %vla, align 4
ret i32 %1
}
@@ -41,6 +46,11 @@ define void @clobber_r14() nounwind {
; ARM_NONE-NEXT: @APP
; ARM_NONE-NEXT: @NO_APP
; ARM_NONE-NEXT: pop {r11, lr}
+; THUMB-LABEL: clobber_r14:
+; THUMB: push {r7, lr}
+; THUMB-NEXT: @APP
+; THUMB-NEXT: @NO_APP
+; THUMB-NEXT: pop {r7, pc}
tail call void asm sideeffect "", "~{r14}"()
ret void
}
@@ -54,6 +64,12 @@ start:
; ARM_NONE-NEXT: @NO_APP
; ARM_NONE-NEXT: mov r0, lr
; ARM_NONE-NEXT: pop {r11, lr}
+; THUMB-LABEL: read_r14:
+; THUMB: push {r7, lr}
+; THUMB-NEXT: @APP
+; THUMB-NEXT: @NO_APP
+; THUMB-NEXT: mov r0, lr
+; THUMB-NEXT: pop {r7, pc}
%1 = tail call i32 asm sideeffect alignstack "", "=&{r14},~{cc},~{memory}"()
ret i32 %1
}
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