[llvm] PPC750cl, and initial support for paired singles (PR #211463)

[Lei Huang via llvm-commits]

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+//===-- PPCInstrPairedSingles.td - PPC750CL Paired Singles -*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the paired-singles instructions of the IBM PPC750CL
+// family of processors.
+//
+// It's important to note that Paired Singles aren't actually independent
+// registers. Instead each floating point register is actually like a pair
+// of 32 bit registers. Regular floating point operations write to both, and
+// ignore the second one. Only Paired Singles operations actually "see" the
+// second one. It's like a 64+32-bit register, or 64+64-bit when it's a
+// rename register.
+//
+//===----------------------------------------------------------------------===//
+
+class PSForm_QD<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin>, MemriOp {
+  bits<5>  FRT;
+  bits<12> D;
+  bits<5>  RA;
+  bits<1>  W;
+  bits<3>  QI;
+
+  let Pattern = pattern;
+
+  let Inst{6...10}  = FRT;
+  let Inst{11...15} = RA;
+  let Inst{16}      = W;
+  let Inst{17...19} = QI;
+  let Inst{20...31} = D;
+}
+
+class PSForm_QX<bits<6> xo, dag OOL, dag IOL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> FRT;
+  bits<5> RA;
+  bits<5> RB;
+  bits<1> W;
+  bits<3> QI;
+
+  let Pattern = pattern;
+
+  let Inst{6...10}  = FRT;
+  let Inst{11...15} = RA;
+  let Inst{16...20} = RB;
+  let Inst{21}      = W;
+  let Inst{22...24} = QI;
+  let Inst{25...30} = xo;
+  let Inst{31}      = 0;
+}
+
+// NOTE: this is differrent than `dcbzl`, *this is* `dcbz_l` which is 750CL specific,
+// has separate encodings, slightly different semantics, and requires a locked cache.
+class PSForm_DCBZL<bits<10> xo, dag OOL, dag IOL, string asmstr,
+                   InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> RA;
+  bits<5> RB;
+
+  let Pattern = pattern;
+
+  let Inst{6...10}  = 0;
+  let Inst{11...15} = RA;
+  let Inst{16...20} = RB;
+  let Inst{21...30} = xo;
+  let Inst{31}      = 0;
+}
+
+let DecoderNamespace = "PairedSingles", Predicates = [HasPairedSingles] in {
+
+let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
+// Load a PS from a specific memory location
----------------
lei137 wrote:

nit: all comments should end with '.'

https://github.com/llvm/llvm-project/pull/211463