[llvm] [CodeGen] Expand unsupported interleave to shuffles (PR #210494)
Kamlesh Kumar via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 07:24:56 PDT 2026
https://github.com/kamleshbhalui updated https://github.com/llvm/llvm-project/pull/210494
>From 6141b571ab4270c50ea7705e478766e1d6fa10e9 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Fri, 4 Sep 2026 11:58:46 +0000
Subject: [PATCH 1/2] [CodeGen] Add generic expand for interleave ops
Added generic expand for unsupported vector_(de)interleave
operation to prevent crashes.
Also unify the expand fragmented at multiple places to vector legalize.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 8 +
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 53 +-
.../SelectionDAG/LegalizeVectorOps.cpp | 13 +
.../SelectionDAG/SelectionDAGBuilder.cpp | 22 -
.../CodeGen/SelectionDAG/TargetLowering.cpp | 122 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
.../aarch64-interleaved-access-w-undef.ll | 103 +-
.../AArch64/aarch64-interleaved-ld-combine.ll | 71 +-
llvm/test/CodeGen/AArch64/binopshuffles.ll | 73 +-
...complex-deinterleaving-fmf-intersection.ll | 2 +-
.../complex-deinterleaving-multiuses.ll | 288 +-
.../complex-deinterleaving-reductions.ll | 16 +-
.../AArch64/fixed-deinterleave-intrinsics.ll | 898 +-
.../AArch64/fixed-length-sve-interleave.ll | 19 +-
.../AArch64/fixed-vector-deinterleave.ll | 131 +-
.../fixed-vector-interleave-odd-factor.ll | 132 +
.../AArch64/fixed-vector-interleave.ll | 100 +-
.../fixed_masked_deinterleaved_loads.ll | 14 +-
.../fixed_masked_interleaved_stores.ll | 10 +-
.../CodeGen/AArch64/interleaved-accesses.ll | 89 +-
.../AArch64/nontemporal-load-interleaved.ll | 522 +-
.../nontemporal-store-interleaved-optsize.ll | 183 +-
.../AArch64/nontemporal-store-interleaved.ll | 644 +-
.../AArch64/sve-fixed-length-shuffles.ll | 26 +-
.../AArch64/sve-interleaved-accesses.ll | 136 +-
...-streaming-mode-fixed-length-interleave.ll | 128 +-
...-streaming-mode-fixed-length-ld2-alloca.ll | 8 +-
...sve-streaming-mode-fixed-length-shuffle.ll | 15 +-
.../AArch64/sve-vector-deinterleave.ll | 32 +-
.../AArch64/sve-vector-interleave-widen.ll | 16 +-
.../CodeGen/AArch64/sve-vector-interleave.ll | 32 +-
llvm/test/CodeGen/AArch64/tbl-loops.ll | 231 +-
.../AArch64/vector-deinterleave-load.ll | 65 +-
.../AArch64/vector-interleave-store.ll | 90 +-
llvm/test/CodeGen/AArch64/vldn_shuffle.ll | 243 +-
.../rvv/fixed-vectors-interleave-store.ll | 59 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 554 +-
.../RISCV/rvv/vector-deinterleave-load.ll | 29 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 508 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 6028 +++++---
.../CodeGen/RISCV/rvv/vector-interleave.ll | 11715 +++++++++-------
.../RISCV/rvv/vp-vector-interleaved-access.ll | 28 +-
.../X86/vector-deinterleave-intrinsics.ll | 386 +
.../X86/vector-interleave-intrinsics.ll | 274 +
44 files changed, 13371 insertions(+), 10749 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
create mode 100644 llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll
create mode 100644 llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index c08d0e53ec34b3..a202bf16a078c6 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -6049,6 +6049,14 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// method accepts vectors as its arguments.
SDValue expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const;
+ /// Expand a VECTOR_INTERLEAVE without introducing wider vector types.
+ void expandVectorInterleave(SDNode *Node, SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const;
+
+ /// Expand a VECTOR_DEINTERLEAVE without introducing wider vector types.
+ void expandVectorDeinterleave(SDNode *Node, SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const;
+
/// Expand a vector VECTOR_COMPRESS into a sequence of extract element, store
/// temporarily, advance store position, before re-loading the final vector.
SDValue expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 15d82359e86820..f07dbf8a93a7e1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3768,57 +3768,12 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(TLI.expandVectorSplice(Node, DAG));
break;
}
- case ISD::VECTOR_DEINTERLEAVE: {
- unsigned Factor = Node->getNumOperands();
- if (Factor <= 2 || Factor % 2 != 0)
- break;
- SmallVector<SDValue, 8> Ops(Node->ops());
- EVT VecVT = Node->getValueType(0);
- SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
- // Deinterleave at Factor/2 so each result contains two factors interleaved:
- // a0b0 c0d0 a1b1 c1d1 -> [a0c0 b0d0] [a1c1 b1d1]
- SDValue L = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, HalfVTs,
- ArrayRef(Ops).take_front(Factor / 2));
- SDValue R = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, HalfVTs,
- ArrayRef(Ops).take_back(Factor / 2));
- Results.resize(Factor);
- // Deinterleave the 2 factors out:
- // [a0c0 a1c1] [b0d0 b1d1] -> a0a1 b0b1 c0c1 d0d1
- for (unsigned I = 0; I < Factor / 2; I++) {
- SDValue Deinterleave =
- DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, {VecVT, VecVT},
- {L.getValue(I), R.getValue(I)});
- Results[I] = Deinterleave.getValue(0);
- Results[I + Factor / 2] = Deinterleave.getValue(1);
- }
+ case ISD::VECTOR_INTERLEAVE:
+ TLI.expandVectorInterleave(Node, Results, DAG);
break;
- }
- case ISD::VECTOR_INTERLEAVE: {
- unsigned Factor = Node->getNumOperands();
- if (Factor <= 2 || Factor % 2 != 0)
- break;
- EVT VecVT = Node->getValueType(0);
- SmallVector<EVT> HalfVTs(Factor / 2, VecVT);
- SmallVector<SDValue, 8> LOps, ROps;
- // Interleave so we have 2 factors per result:
- // a0a1 b0b1 c0c1 d0d1 -> [a0c0 b0d0] [a1c1 b1d1]
- for (unsigned I = 0; I < Factor / 2; I++) {
- SDValue Interleave =
- DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, {VecVT, VecVT},
- {Node->getOperand(I), Node->getOperand(I + Factor / 2)});
- LOps.push_back(Interleave.getValue(0));
- ROps.push_back(Interleave.getValue(1));
- }
- // Interleave at Factor/2:
- // [a0c0 b0d0] [a1c1 b1d1] -> a0b0 c0d0 a1b1 c1d1
- SDValue L = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, HalfVTs, LOps);
- SDValue R = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, HalfVTs, ROps);
- for (unsigned I = 0; I < Factor / 2; I++)
- Results.push_back(L.getValue(I));
- for (unsigned I = 0; I < Factor / 2; I++)
- Results.push_back(R.getValue(I));
+ case ISD::VECTOR_DEINTERLEAVE:
+ TLI.expandVectorDeinterleave(Node, Results, DAG);
break;
- }
case ISD::EXTRACT_ELEMENT: {
EVT OpTy = Node->getOperand(0).getValueType();
if (Node->getConstantOperandVal(1)) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 5e3f252fdd3d48..24c5628c6cdab9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -490,6 +490,13 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::VECTOR_MATCH:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
+ case ISD::VECTOR_INTERLEAVE:
+ case ISD::VECTOR_DEINTERLEAVE: {
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ Action = TLI.getVectorInterleaveAction(Node->getOpcode(), Factor, VT);
+ break;
+ }
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
@@ -951,6 +958,12 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
Results.push_back(Node->getOperand(i));
return;
+ case ISD::VECTOR_INTERLEAVE:
+ TLI.expandVectorInterleave(Node, Results, DAG);
+ return;
+ case ISD::VECTOR_DEINTERLEAVE:
+ TLI.expandVectorDeinterleave(Node, Results, DAG);
+ return;
case ISD::SIGN_EXTEND_INREG:
if (SDValue Expanded = ExpandSEXTINREG(Node)) {
Results.push_back(Expanded);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 7d185031d7d379..b91598e99b4ec6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -13012,18 +13012,6 @@ void SelectionDAGBuilder::visitVectorDeinterleave(const CallInst &I,
DAG.getVectorIdxConstant(OutNumElts * i, DL));
}
- // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
- // from existing legalisation and combines.
- if (OutVT.isFixedLengthVector() && Factor == 2) {
- SDValue Even = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1],
- createStrideMask(0, 2, OutNumElts));
- SDValue Odd = DAG.getVectorShuffle(OutVT, DL, SubVecs[0], SubVecs[1],
- createStrideMask(1, 2, OutNumElts));
- SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc());
- setValue(&I, Res);
- return;
- }
-
SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL,
DAG.getVTList(ValueVTs), SubVecs);
setValue(&I, Res);
@@ -13043,16 +13031,6 @@ void SelectionDAGBuilder::visitVectorInterleave(const CallInst &I,
"Expected VTs to be the same");
}
- // Use VECTOR_SHUFFLE for fixed-length vectors with factor of 2 to benefit
- // from existing legalisation and combines.
- if (OutVT.isFixedLengthVector() && Factor == 2) {
- unsigned NumElts = InVT.getVectorMinNumElements();
- SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, InVecs);
- setValue(&I, DAG.getVectorShuffle(OutVT, DL, V, DAG.getUNDEF(OutVT),
- createInterleaveMask(NumElts, 2)));
- return;
- }
-
SmallVector<EVT, 8> ValueVTs(Factor, InVT);
SDValue Res =
DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, DAG.getVTList(ValueVTs), InVecs);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7c97dfb2c806a1..1e835e28056a6b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -13514,6 +13514,128 @@ SDValue TargetLowering::expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) const {
return SDValue();
}
+void TargetLowering::expandVectorInterleave(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ assert(Node->getOpcode() == ISD::VECTOR_INTERLEAVE && "Unexpected opcode");
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ SDLoc DL(Node);
+
+ if (Factor > 2 && Factor % 2 == 0) {
+ SmallVector<EVT> HalfVTs(Factor / 2, VT);
+ SmallVector<SDValue, 8> LOps, ROps;
+ // Interleave so we have 2 factors per result:
+ // a0a1 b0b1 c0c1 d0d1 -> [a0c0 b0d0] [a1c1 b1d1]
+ for (unsigned I = 0; I < Factor / 2; I++) {
+ SDValue Interleave =
+ DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, {VT, VT},
+ {Node->getOperand(I), Node->getOperand(I + Factor / 2)});
+ LOps.push_back(Interleave.getValue(0));
+ ROps.push_back(Interleave.getValue(1));
+ }
+ // Interleave at Factor/2:
+ // [a0c0 b0d0] [a1c1 b1d1] -> a0b0 c0d0 a1b1 c1d1
+ SDValue L = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, HalfVTs, LOps);
+ SDValue R = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, HalfVTs, ROps);
+ for (unsigned I = 0; I < Factor / 2; I++)
+ Results.push_back(L.getValue(I));
+ for (unsigned I = 0; I < Factor / 2; I++)
+ Results.push_back(R.getValue(I));
+ return;
+ }
+
+ if (!VT.isFixedLengthVector())
+ return;
+
+ unsigned NumElts = VT.getVectorNumElements();
+ EVT EltVT = VT.getVectorElementType();
+
+ // A factor of two needs only same-width, two-input shuffles.
+ if (Factor == 2) {
+ SmallVector<int, 8> Mask = createInterleaveMask(NumElts, Factor);
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(DAG.getVectorShuffle(
+ VT, DL, Node->getOperand(0), Node->getOperand(1),
+ ArrayRef<int>(Mask).slice(I * NumElts, NumElts)));
+ return;
+ }
+
+ SmallVector<SDValue> InterleavedElts;
+ InterleavedElts.reserve(Factor * NumElts);
+ for (unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx)
+ for (unsigned OperandIdx = 0; OperandIdx != Factor; ++OperandIdx)
+ InterleavedElts.push_back(DAG.getExtractVectorElt(
+ DL, EltVT, Node->getOperand(OperandIdx), EltIdx));
+
+ for (unsigned ResultIdx = 0; ResultIdx != Factor; ++ResultIdx)
+ Results.push_back(DAG.getBuildVector(
+ VT, DL, ArrayRef(InterleavedElts).slice(ResultIdx * NumElts, NumElts)));
+}
+
+void TargetLowering::expandVectorDeinterleave(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ assert(Node->getOpcode() == ISD::VECTOR_DEINTERLEAVE && "Unexpected opcode");
+ EVT VT = Node->getValueType(0);
+ unsigned Factor = Node->getNumOperands();
+ SDLoc DL(Node);
+
+ if (Factor > 2 && Factor % 2 == 0) {
+ SmallVector<SDValue, 8> Ops(Node->ops());
+ SmallVector<EVT> HalfVTs(Factor / 2, VT);
+ // Deinterleave at Factor/2 so each result contains two factors interleaved:
+ // a0b0 c0d0 a1b1 c1d1 -> [a0c0 b0d0] [a1c1 b1d1]
+ SDValue L = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, HalfVTs,
+ ArrayRef(Ops).take_front(Factor / 2));
+ SDValue R = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, HalfVTs,
+ ArrayRef(Ops).take_back(Factor / 2));
+ Results.resize(Factor);
+ // Deinterleave the 2 factors out:
+ // [a0c0 a1c1] [b0d0 b1d1] -> a0a1 b0b1 c0c1 d0d1
+ for (unsigned I = 0; I < Factor / 2; I++) {
+ SDValue Deinterleave = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, {VT, VT},
+ {L.getValue(I), R.getValue(I)});
+ Results[I] = Deinterleave.getValue(0);
+ Results[I + Factor / 2] = Deinterleave.getValue(1);
+ }
+ return;
+ }
+
+ if (!VT.isFixedLengthVector())
+ return;
+
+ unsigned NumElts = VT.getVectorNumElements();
+ EVT EltVT = VT.getVectorElementType();
+
+ // A factor of two needs only same-width, two-input shuffles.
+ if (Factor == 2) {
+ for (unsigned I = 0; I != Factor; ++I)
+ Results.push_back(
+ DAG.getVectorShuffle(VT, DL, Node->getOperand(0), Node->getOperand(1),
+ createStrideMask(I, Factor, NumElts)));
+ return;
+ }
+
+ SmallVector<SDValue> ConcatElts;
+ ConcatElts.reserve(Factor * NumElts);
+ for (unsigned OperandIdx = 0; OperandIdx != Factor; ++OperandIdx)
+ for (unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx)
+ ConcatElts.push_back(DAG.getExtractVectorElt(
+ DL, EltVT, Node->getOperand(OperandIdx), EltIdx));
+
+ SmallVector<SDValue> DeinterleavedElts;
+ DeinterleavedElts.reserve(Factor * NumElts);
+ for (unsigned ResultIdx = 0; ResultIdx != Factor; ++ResultIdx)
+ for (unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx)
+ DeinterleavedElts.push_back(ConcatElts[ResultIdx + EltIdx * Factor]);
+
+ for (unsigned ResultIdx = 0; ResultIdx != Factor; ++ResultIdx)
+ Results.push_back(DAG.getBuildVector(
+ VT, DL,
+ ArrayRef(DeinterleavedElts).slice(ResultIdx * NumElts, NumElts)));
+}
+
SDValue TargetLowering::expandVectorSplice(SDNode *Node,
SelectionDAG &DAG) const {
assert((Node->getOpcode() == ISD::VECTOR_SPLICE_LEFT ||
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7a5905fc4b3ea5..97b3c6ca103f35 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1618,7 +1618,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setVectorInterleaveAction(
{ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
- {2, 3, 4, 5, 6, 7, 8}, VT, Custom);
+ {3, 4, 5, 6, 7, 8}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT},
VT, Custom);
@@ -1798,7 +1798,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setVectorInterleaveAction(
{ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
- {2, 3, 4, 5, 6, 7, 8}, VT, Custom);
+ {3, 4, 5, 6, 7, 8}, VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE,
ISD::MGATHER, ISD::MSCATTER},
diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
index 6b49ba0a65340a..3f5fe571063106 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll
@@ -157,6 +157,12 @@ define void @f_undef_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
+; CHECK-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%S = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> poison, <8 x i64> poison)
@@ -179,6 +185,12 @@ define void @f_poison_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_poison_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
+; CHECK-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: zip1 v1.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #32]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q1, q0, [x0, #96]
; CHECK-IADISABLED-NEXT: ret
BB:
%S = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> poison, <8 x i64> poison)
@@ -202,8 +214,14 @@ define void @f_undef_15_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_15_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: dup v1.2d, v0.d[1]
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x0]
+; CHECK-IADISABLED-NEXT: // kill: def $q0 killed $q0 def $q0_q1
+; CHECK-IADISABLED-NEXT: mov x8, x0
+; CHECK-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: st2 { v0.2d, v1.2d }, [x8], #32
+; CHECK-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v0.2d
+; CHECK-IADISABLED-NEXT: stp q0, q2, [x0, #64]
+; CHECK-IADISABLED-NEXT: stp q0, q2, [x0, #96]
+; CHECK-IADISABLED-NEXT: st2 { v0.2d, v1.2d }, [x8]
; CHECK-IADISABLED-NEXT: ret
BB:
%a.0 = extractelement <8 x i64> %a, i64 0
@@ -236,18 +254,19 @@ define void @f_undef_1_intrinsic(<8 x i64> %a, ptr %dst) {
;
; CHECK-IADISABLED-LABEL: f_undef_1_intrinsic:
; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: dup v4.2d, v3.d[1]
-; CHECK-IADISABLED-NEXT: dup v3.2d, v3.d[0]
-; CHECK-IADISABLED-NEXT: dup v5.2d, v2.d[1]
-; CHECK-IADISABLED-NEXT: dup v2.2d, v2.d[0]
-; CHECK-IADISABLED-NEXT: stp q3, q4, [x0, #96]
-; CHECK-IADISABLED-NEXT: dup v4.2d, v1.d[1]
-; CHECK-IADISABLED-NEXT: dup v1.2d, v1.d[0]
-; CHECK-IADISABLED-NEXT: dup v3.2d, v0.d[1]
-; CHECK-IADISABLED-NEXT: dup v0.2d, v0.d[0]
-; CHECK-IADISABLED-NEXT: stp q2, q5, [x0, #64]
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
+; CHECK-IADISABLED-NEXT: mov v5.16b, v2.16b
+; CHECK-IADISABLED-NEXT: mov v16.16b, v0.16b
+; CHECK-IADISABLED-NEXT: // kill: def $q3 killed $q3 def $q3_q4
+; CHECK-IADISABLED-NEXT: // kill: def $q1 killed $q1 def $q1_q2
+; CHECK-IADISABLED-NEXT: add x8, x0, #64
+; CHECK-IADISABLED-NEXT: mov v4.16b, v3.16b
+; CHECK-IADISABLED-NEXT: mov v2.16b, v1.16b
+; CHECK-IADISABLED-NEXT: mov v6.16b, v5.16b
+; CHECK-IADISABLED-NEXT: mov v17.16b, v16.16b
+; CHECK-IADISABLED-NEXT: st2 { v5.2d, v6.2d }, [x8], #32
+; CHECK-IADISABLED-NEXT: st2 { v3.2d, v4.2d }, [x8]
+; CHECK-IADISABLED-NEXT: st2 { v16.2d, v17.2d }, [x0], #32
+; CHECK-IADISABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
; CHECK-IADISABLED-NEXT: ret
BB:
%even = insertelement <8 x i64> %a, i64 poison, i64 6
@@ -258,25 +277,15 @@ BB:
define void @noundefs_intrinsic(<8 x i32> %a, <8 x i32> %b, ptr %dst) {
-; CHECK-IAENABLED-LABEL: noundefs_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %BB
-; CHECK-IAENABLED-NEXT: mov v5.16b, v2.16b
-; CHECK-IAENABLED-NEXT: // kill: def $q3 killed $q3 def $q2_q3
-; CHECK-IAENABLED-NEXT: mov v4.16b, v0.16b
-; CHECK-IAENABLED-NEXT: mov v2.16b, v1.16b
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: noundefs_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: zip2 v4.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: noundefs_intrinsic:
+; CHECK: // %bb.0: // %BB
+; CHECK-NEXT: mov v5.16b, v2.16b
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
BB:
%even = insertelement <8 x i32> %a, i32 poison, i64 6
%S = call <16 x i32> @llvm.vector.interleave2.v16i32(<8 x i32> %even, <8 x i32> %b)
@@ -286,25 +295,15 @@ BB:
define void @undefs_intrinsic(<8 x i32> %a, <8 x i32> %b, ptr %dst) {
-; CHECK-IAENABLED-LABEL: undefs_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %BB
-; CHECK-IAENABLED-NEXT: mov v5.16b, v2.16b
-; CHECK-IAENABLED-NEXT: // kill: def $q3 killed $q3 def $q2_q3
-; CHECK-IAENABLED-NEXT: mov v4.16b, v0.16b
-; CHECK-IAENABLED-NEXT: mov v2.16b, v1.16b
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: undefs_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %BB
-; CHECK-IADISABLED-NEXT: zip2 v4.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v2.4s
-; CHECK-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; CHECK-IADISABLED-NEXT: stp q0, q3, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: undefs_intrinsic:
+; CHECK: // %bb.0: // %BB
+; CHECK-NEXT: mov v5.16b, v2.16b
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
BB:
%a.3 = extractelement <8 x i32> %a, i64 3
%a.7 = extractelement <8 x i32> %a, i64 7
diff --git a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
index f83739ef6f44f4..c56b492bb33cd5 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
@@ -896,31 +896,17 @@ define void @aarch64_ilc_idx_ld2_intrinsic(ptr %ptr, i64 %idx) {
; CHECK-NEXT: store <4 x float> [[M4_7]], ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
-; AS-IAENABLED-LABEL: aarch64_ilc_idx_ld2_intrinsic:
-; AS-IAENABLED: // %bb.0: // %entry
-; AS-IAENABLED-NEXT: lsl x8, x1, #2
-; AS-IAENABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; AS-IAENABLED-NEXT: add x8, x8, #16
-; AS-IAENABLED-NEXT: add x10, x0, x9
-; AS-IAENABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; AS-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x10]
-; AS-IAENABLED-NEXT: str q0, [x0, x9]
-; AS-IAENABLED-NEXT: str q1, [x0, x8]
-; AS-IAENABLED-NEXT: ret
-;
-; AS-IADISABLED-LABEL: aarch64_ilc_idx_ld2_intrinsic:
-; AS-IADISABLED: // %bb.0: // %entry
-; AS-IADISABLED-NEXT: lsl x8, x1, #2
-; AS-IADISABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; AS-IADISABLED-NEXT: add x8, x8, #16
-; AS-IADISABLED-NEXT: add x9, x0, x9
-; AS-IADISABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; AS-IADISABLED-NEXT: ldp q1, q0, [x9]
-; AS-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: str q2, [x9]
-; AS-IADISABLED-NEXT: str q0, [x0, x8]
-; AS-IADISABLED-NEXT: ret
+; AS-LABEL: aarch64_ilc_idx_ld2_intrinsic:
+; AS: // %bb.0: // %entry
+; AS-NEXT: lsl x8, x1, #2
+; AS-NEXT: and x9, x8, #0xfffffffffffffff0
+; AS-NEXT: add x8, x8, #16
+; AS-NEXT: add x10, x0, x9
+; AS-NEXT: and x8, x8, #0xfffffffffffffff0
+; AS-NEXT: ld2 { v0.4s, v1.4s }, [x10]
+; AS-NEXT: str q0, [x0, x9]
+; AS-NEXT: str q1, [x0, x8]
+; AS-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%a1 = add i64 %idx, 4
@@ -1009,30 +995,17 @@ define void @aarch64_ilc_i32_idx_intrinsic(ptr %ptr, i32 %idx) {
; CHECK-NEXT: store <4 x float> [[M4_7]], ptr [[GEP2]], align 16
; CHECK-NEXT: ret void
;
-; AS-IAENABLED-LABEL: aarch64_ilc_i32_idx_intrinsic:
-; AS-IAENABLED: // %bb.0: // %entry
-; AS-IAENABLED-NEXT: lsr w8, w1, #2
-; AS-IAENABLED-NEXT: ubfiz x8, x8, #4, #32
-; AS-IAENABLED-NEXT: add x9, x0, x8
-; AS-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x9]
-; AS-IAENABLED-NEXT: add w9, w1, #4
-; AS-IAENABLED-NEXT: lsr w9, w9, #2
-; AS-IAENABLED-NEXT: str q0, [x0, x8]
-; AS-IAENABLED-NEXT: str q1, [x0, w9, uxtw #4]
-; AS-IAENABLED-NEXT: ret
-;
-; AS-IADISABLED-LABEL: aarch64_ilc_i32_idx_intrinsic:
-; AS-IADISABLED: // %bb.0: // %entry
-; AS-IADISABLED-NEXT: lsr w8, w1, #2
-; AS-IADISABLED-NEXT: add w9, w1, #4
-; AS-IADISABLED-NEXT: lsr w9, w9, #2
-; AS-IADISABLED-NEXT: add x8, x0, w8, uxtw #4
-; AS-IADISABLED-NEXT: ldp q1, q0, [x8]
-; AS-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; AS-IADISABLED-NEXT: str q2, [x8]
-; AS-IADISABLED-NEXT: str q0, [x0, w9, uxtw #4]
-; AS-IADISABLED-NEXT: ret
+; AS-LABEL: aarch64_ilc_i32_idx_intrinsic:
+; AS: // %bb.0: // %entry
+; AS-NEXT: lsr w8, w1, #2
+; AS-NEXT: ubfiz x8, x8, #4, #32
+; AS-NEXT: add x9, x0, x8
+; AS-NEXT: ld2 { v0.4s, v1.4s }, [x9]
+; AS-NEXT: add w9, w1, #4
+; AS-NEXT: lsr w9, w9, #2
+; AS-NEXT: str q0, [x0, x8]
+; AS-NEXT: str q1, [x0, w9, uxtw #4]
+; AS-NEXT: ret
entry:
%idx1 = lshr i32 %idx, 2
%a1 = add i32 %idx, 4
diff --git a/llvm/test/CodeGen/AArch64/binopshuffles.ll b/llvm/test/CodeGen/AArch64/binopshuffles.ll
index 3ee9df3165c985..ab4e106c6362ed 100644
--- a/llvm/test/CodeGen/AArch64/binopshuffles.ll
+++ b/llvm/test/CodeGen/AArch64/binopshuffles.ll
@@ -251,25 +251,13 @@ entry:
}
define <4 x float> @twosrc_intrinsic(ptr %pSrc1, ptr %pSrc2) {
-; CHECK-IAENABLED-LABEL: twosrc_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v3.4s, v4.4s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v3.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v4.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: twosrc_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1]
-; CHECK-IADISABLED-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: twosrc_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: ld2 { v3.4s, v4.4s }, [x1]
+; CHECK-NEXT: fmul v0.4s, v3.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v4.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
@@ -286,25 +274,13 @@ entry:
}
define <4 x float> @twosrc2_intrinsic(ptr %pSrc1, ptr %pSrc2) {
-; CHECK-IAENABLED-LABEL: twosrc2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ld2 { v3.4s, v4.4s }, [x1]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v3.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v4.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: twosrc2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x1]
-; CHECK-IADISABLED-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: uzp2 v2.4s, v3.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v5.4s, v4.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: twosrc2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: ld2 { v3.4s, v4.4s }, [x1]
+; CHECK-NEXT: fmul v0.4s, v3.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v4.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc1, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
@@ -321,21 +297,12 @@ entry:
}
define <4 x float> @vld2_intrinsic(ptr %pSrc) {
-; CHECK-IAENABLED-LABEL: vld2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x0]
-; CHECK-IAENABLED-NEXT: fmul v0.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmla v0.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0]
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v0.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v0.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x0]
+; CHECK-NEXT: fmul v0.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmla v0.4s, v2.4s, v2.4s
+; CHECK-NEXT: ret
entry:
%intrinsic.load.0 = load <8 x float>, ptr %pSrc, align 4
%ldN = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %intrinsic.load.0)
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-fmf-intersection.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-fmf-intersection.ll
index a1d18c2861886d..718711f2fe3cf9 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-fmf-intersection.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-fmf-intersection.ll
@@ -68,8 +68,8 @@ define <4 x double> @fcmla_symmetric_scale_mixed_fmf(<4 x double> %a, <4 x doubl
; CHECK-LABEL: fcmla_symmetric_scale_mixed_fmf:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d6 killed $d6 def $q6
-; CHECK-NEXT: fmul v1.2d, v1.2d, v6.d[0]
; CHECK-NEXT: fmul v0.2d, v0.2d, v6.d[0]
+; CHECK-NEXT: fmul v1.2d, v1.2d, v6.d[0]
; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #0
; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #0
; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #90
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
index 0e4b3eee1f9910..8df834af2e2df8 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll
@@ -525,10 +525,10 @@ define <4 x float> @mul_triangle_external_use_intrinsic(<4 x float> %a, <4 x flo
; CHECK-NEXT: mov d3, v0.d[1]
; CHECK-NEXT: mov d4, v1.d[1]
; CHECK-NEXT: movi v2.2s, #128, lsl #24
-; CHECK-NEXT: zip2 v5.2s, v0.2s, v3.2s
-; CHECK-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-NEXT: zip1 v0.2s, v0.2s, v3.2s
-; CHECK-NEXT: zip2 v1.2s, v1.2s, v4.2s
+; CHECK-NEXT: uzp2 v5.2s, v0.2s, v3.2s
+; CHECK-NEXT: uzp1 v6.2s, v1.2s, v4.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v3.2s
+; CHECK-NEXT: uzp2 v1.2s, v1.2s, v4.2s
; CHECK-NEXT: fmul v3.2s, v5.2s, v6.2s
; CHECK-NEXT: fmls v2.2s, v1.2s, v5.2s
; CHECK-NEXT: fmla v3.2s, v0.2s, v1.2s
@@ -539,9 +539,7 @@ define <4 x float> @mul_triangle_external_use_intrinsic(<4 x float> %a, <4 x flo
; CHECK-NEXT: str d3, [x0]
; CHECK-NEXT: fmla v4.2s, v5.2s, v2.2s
; CHECK-NEXT: fmla v1.2s, v0.2s, v2.2s
-; CHECK-NEXT: mov v1.d[1], v4.d[0]
-; CHECK-NEXT: rev64 v0.4s, v1.4s
-; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: zip1 v0.4s, v1.4s, v4.4s
; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
@@ -569,64 +567,33 @@ entry:
define <4 x float> @multiple_muls_shuffle_external_intrinsic(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_shuffle_external_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov d4, v1.d[1]
-; CHECK-IAENABLED-NEXT: mov d5, v0.d[1]
-; CHECK-IAENABLED-NEXT: mov d16, v2.d[1]
-; CHECK-IAENABLED-NEXT: movi v17.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip2 v7.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-IAENABLED-NEXT: movi v5.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: fmul v4.2s, v6.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmls v5.2s, v1.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v0.2s, v1.2s
-; CHECK-IAENABLED-NEXT: zip1 v1.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: fmla v5.2s, v0.2s, v6.2s
-; CHECK-IAENABLED-NEXT: zip2 v6.2s, v2.2s, v16.2s
-; CHECK-IAENABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IAENABLED-NEXT: fmul v18.2s, v1.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
-; CHECK-IAENABLED-NEXT: str d5, [x0]
-; CHECK-IAENABLED-NEXT: fmla v18.2s, v5.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmls v17.2s, v6.2s, v4.2s
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
-; CHECK-IAENABLED-NEXT: fmla v17.2s, v5.2s, v1.2s
-; CHECK-IAENABLED-NEXT: st2 { v17.2s, v18.2s }, [x1]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_shuffle_external_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov d4, v1.d[1]
-; CHECK-IADISABLED-NEXT: mov d5, v0.d[1]
-; CHECK-IADISABLED-NEXT: movi v16.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: zip1 v6.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip2 v7.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v1.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: mov d5, v2.d[1]
-; CHECK-IADISABLED-NEXT: fmul v4.2s, v6.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmls v16.2s, v1.2s, v7.2s
-; CHECK-IADISABLED-NEXT: zip2 v7.2s, v2.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v5.2s, v2.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fmla v4.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: fmla v16.2s, v0.2s, v6.2s
-; CHECK-IADISABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IADISABLED-NEXT: fmul v6.2s, v5.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmls v1.2s, v7.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
-; CHECK-IADISABLED-NEXT: str d16, [x0]
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v16.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v16.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v6.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v4.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v4.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_shuffle_external_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d4, v1.d[1]
+; CHECK-NEXT: mov d5, v0.d[1]
+; CHECK-NEXT: mov d16, v2.d[1]
+; CHECK-NEXT: movi v17.2s, #128, lsl #24
+; CHECK-NEXT: uzp1 v6.2s, v1.2s, v4.2s
+; CHECK-NEXT: uzp2 v7.2s, v0.2s, v5.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v5.2s
+; CHECK-NEXT: uzp2 v1.2s, v1.2s, v4.2s
+; CHECK-NEXT: movi v5.2s, #128, lsl #24
+; CHECK-NEXT: fmul v4.2s, v6.2s, v7.2s
+; CHECK-NEXT: fmls v5.2s, v1.2s, v7.2s
+; CHECK-NEXT: fmla v4.2s, v0.2s, v1.2s
+; CHECK-NEXT: uzp1 v1.2s, v2.2s, v16.2s
+; CHECK-NEXT: fmla v5.2s, v0.2s, v6.2s
+; CHECK-NEXT: uzp2 v6.2s, v2.2s, v16.2s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: fmul v18.2s, v1.2s, v4.2s
+; CHECK-NEXT: fcmla v0.4s, v2.4s, v3.4s, #0
+; CHECK-NEXT: str d5, [x0]
+; CHECK-NEXT: fmla v18.2s, v5.2s, v6.2s
+; CHECK-NEXT: fmls v17.2s, v6.2s, v4.2s
+; CHECK-NEXT: fcmla v0.4s, v2.4s, v3.4s, #90
+; CHECK-NEXT: fmla v17.2s, v5.2s, v1.2s
+; CHECK-NEXT: st2 { v17.2s, v18.2s }, [x1]
+; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
%strided.vec = extractvalue { <2 x float>, <2 x float> } %a.deinterleaved, 0
@@ -667,66 +634,30 @@ entry:
define <4 x float> @multiple_muls_shuffle_external_with_loads_intrinsic(ptr %ptr_a, ptr %ptr_b, ptr %ptr_c, ptr %ptr_d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-IAENABLED-NEXT: movi v4.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: ld2 { v2.2s, v3.2s }, [x1]
-; CHECK-IAENABLED-NEXT: fmls v4.2s, v3.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fmul v6.2s, v2.2s, v1.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v0.2s, v2.2s
-; CHECK-IAENABLED-NEXT: fmla v6.2s, v0.2s, v3.2s
-; CHECK-IAENABLED-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: str d4, [x4]
-; CHECK-IAENABLED-NEXT: ldr q5, [x2]
-; CHECK-IAENABLED-NEXT: mov d7, v5.d[1]
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v5.2s, v7.2s
-; CHECK-IAENABLED-NEXT: zip2 v3.2s, v5.2s, v7.2s
-; CHECK-IAENABLED-NEXT: fmul v2.2s, v0.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v2.2s, v4.2s, v3.2s
-; CHECK-IAENABLED-NEXT: fmls v1.2s, v3.2s, v6.2s
-; CHECK-IAENABLED-NEXT: fmla v1.2s, v4.2s, v0.2s
-; CHECK-IAENABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x5]
-; CHECK-IAENABLED-NEXT: ldr q1, [x3]
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v5.4s, v1.4s, #0
-; CHECK-IAENABLED-NEXT: fcmla v0.4s, v5.4s, v1.4s, #90
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-IADISABLED-NEXT: ldr q1, [x1]
-; CHECK-IADISABLED-NEXT: movi v6.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: mov d2, v0.d[1]
-; CHECK-IADISABLED-NEXT: mov d3, v1.d[1]
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: zip2 v5.2s, v1.2s, v3.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v2.2s
-; CHECK-IADISABLED-NEXT: zip1 v1.2s, v1.2s, v3.2s
-; CHECK-IADISABLED-NEXT: fmls v6.2s, v5.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v0.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmul v1.2s, v1.2s, v4.2s
-; CHECK-IADISABLED-NEXT: str d6, [x4]
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v0.2s, v5.2s
-; CHECK-IADISABLED-NEXT: movi v0.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: ldr q2, [x2]
-; CHECK-IADISABLED-NEXT: mov d3, v2.d[1]
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v2.2s, v3.2s
-; CHECK-IADISABLED-NEXT: zip1 v3.2s, v2.2s, v3.2s
-; CHECK-IADISABLED-NEXT: fmul v5.2s, v3.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmls v0.2s, v4.2s, v1.2s
-; CHECK-IADISABLED-NEXT: fmla v5.2s, v6.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmla v0.2s, v6.2s, v3.2s
-; CHECK-IADISABLED-NEXT: mov v0.d[1], v5.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: movi v0.2d, #0000000000000000
-; CHECK-IADISABLED-NEXT: str q1, [x5]
-; CHECK-IADISABLED-NEXT: ldr q1, [x3]
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v1.4s, #0
-; CHECK-IADISABLED-NEXT: fcmla v0.4s, v2.4s, v1.4s, #90
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_shuffle_external_with_loads_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-NEXT: movi v4.2s, #128, lsl #24
+; CHECK-NEXT: ld2 { v2.2s, v3.2s }, [x1]
+; CHECK-NEXT: fmls v4.2s, v3.2s, v1.2s
+; CHECK-NEXT: fmul v5.2s, v2.2s, v1.2s
+; CHECK-NEXT: fmla v4.2s, v0.2s, v2.2s
+; CHECK-NEXT: fmla v5.2s, v0.2s, v3.2s
+; CHECK-NEXT: movi v1.2s, #128, lsl #24
+; CHECK-NEXT: str d4, [x4]
+; CHECK-NEXT: ldr q6, [x2]
+; CHECK-NEXT: uzp1 v0.4s, v6.4s, v0.4s
+; CHECK-NEXT: uzp2 v3.4s, v6.4s, v0.4s
+; CHECK-NEXT: fmul v2.2s, v0.2s, v5.2s
+; CHECK-NEXT: fmla v2.2s, v4.2s, v3.2s
+; CHECK-NEXT: fmls v1.2s, v3.2s, v5.2s
+; CHECK-NEXT: fmla v1.2s, v4.2s, v0.2s
+; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: st2 { v1.2s, v2.2s }, [x5]
+; CHECK-NEXT: ldr q1, [x3]
+; CHECK-NEXT: fcmla v0.4s, v6.4s, v1.4s, #0
+; CHECK-NEXT: fcmla v0.4s, v6.4s, v1.4s, #90
+; CHECK-NEXT: ret
entry:
%a = load <4 x float>, ptr %ptr_a
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
@@ -771,80 +702,39 @@ entry:
define <4 x float> @multiple_muls_mul_external_intrinsic(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, ptr %p1, ptr %p2) {
-; CHECK-IAENABLED-LABEL: multiple_muls_mul_external_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov d4, v0.d[1]
-; CHECK-IAENABLED-NEXT: mov d5, v1.d[1]
-; CHECK-IAENABLED-NEXT: mov d6, v2.d[1]
-; CHECK-IAENABLED-NEXT: mov d7, v3.d[1]
-; CHECK-IAENABLED-NEXT: movi v16.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: zip2 v17.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip2 v18.2s, v1.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip1 v19.2s, v2.2s, v6.2s
-; CHECK-IAENABLED-NEXT: zip2 v20.2s, v3.2s, v7.2s
-; CHECK-IAENABLED-NEXT: zip1 v0.2s, v0.2s, v4.2s
-; CHECK-IAENABLED-NEXT: zip1 v1.2s, v1.2s, v5.2s
-; CHECK-IAENABLED-NEXT: zip2 v2.2s, v2.2s, v6.2s
-; CHECK-IAENABLED-NEXT: movi v4.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: zip1 v3.2s, v3.2s, v7.2s
-; CHECK-IAENABLED-NEXT: movi v6.2s, #128, lsl #24
-; CHECK-IAENABLED-NEXT: fmls v16.2s, v17.2s, v18.2s
-; CHECK-IAENABLED-NEXT: fmul v5.2s, v19.2s, v20.2s
-; CHECK-IAENABLED-NEXT: fmls v4.2s, v2.2s, v20.2s
-; CHECK-IAENABLED-NEXT: fmla v16.2s, v1.2s, v0.2s
-; CHECK-IAENABLED-NEXT: fmul v0.2s, v0.2s, v18.2s
-; CHECK-IAENABLED-NEXT: fmla v5.2s, v3.2s, v2.2s
-; CHECK-IAENABLED-NEXT: fmla v4.2s, v3.2s, v19.2s
-; CHECK-IAENABLED-NEXT: fmla v0.2s, v1.2s, v17.2s
-; CHECK-IAENABLED-NEXT: str d16, [x0]
-; CHECK-IAENABLED-NEXT: fmul v7.2s, v16.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmla v7.2s, v4.2s, v0.2s
-; CHECK-IAENABLED-NEXT: fmls v6.2s, v0.2s, v5.2s
-; CHECK-IAENABLED-NEXT: fmla v6.2s, v4.2s, v16.2s
-; CHECK-IAENABLED-NEXT: mov v4.d[1], v5.d[0]
-; CHECK-IAENABLED-NEXT: rev64 v0.4s, v4.4s
-; CHECK-IAENABLED-NEXT: st2 { v6.2s, v7.2s }, [x1]
-; CHECK-IAENABLED-NEXT: uzp1 v0.4s, v4.4s, v0.4s
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: multiple_muls_mul_external_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov d4, v0.d[1]
-; CHECK-IADISABLED-NEXT: mov d5, v1.d[1]
-; CHECK-IADISABLED-NEXT: mov d6, v2.d[1]
-; CHECK-IADISABLED-NEXT: mov d7, v3.d[1]
-; CHECK-IADISABLED-NEXT: movi v16.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: zip2 v17.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip1 v0.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: zip2 v4.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip1 v18.2s, v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: zip2 v19.2s, v3.2s, v7.2s
-; CHECK-IADISABLED-NEXT: zip1 v1.2s, v1.2s, v5.2s
-; CHECK-IADISABLED-NEXT: zip2 v2.2s, v2.2s, v6.2s
-; CHECK-IADISABLED-NEXT: zip1 v3.2s, v3.2s, v7.2s
-; CHECK-IADISABLED-NEXT: fmul v5.2s, v0.2s, v4.2s
-; CHECK-IADISABLED-NEXT: fmls v16.2s, v17.2s, v4.2s
-; CHECK-IADISABLED-NEXT: movi v4.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: fmul v6.2s, v18.2s, v19.2s
-; CHECK-IADISABLED-NEXT: fmla v5.2s, v1.2s, v17.2s
-; CHECK-IADISABLED-NEXT: fmla v16.2s, v1.2s, v0.2s
-; CHECK-IADISABLED-NEXT: movi v1.2s, #128, lsl #24
-; CHECK-IADISABLED-NEXT: fmla v6.2s, v3.2s, v2.2s
-; CHECK-IADISABLED-NEXT: fmls v4.2s, v2.2s, v19.2s
-; CHECK-IADISABLED-NEXT: str d16, [x0]
-; CHECK-IADISABLED-NEXT: fmla v4.2s, v3.2s, v18.2s
-; CHECK-IADISABLED-NEXT: fmul v0.2s, v16.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fmls v1.2s, v5.2s, v6.2s
-; CHECK-IADISABLED-NEXT: fmla v0.2s, v4.2s, v5.2s
-; CHECK-IADISABLED-NEXT: fmla v1.2s, v4.2s, v16.2s
-; CHECK-IADISABLED-NEXT: mov v4.d[1], v6.d[0]
-; CHECK-IADISABLED-NEXT: mov v1.d[1], v0.d[0]
-; CHECK-IADISABLED-NEXT: rev64 v0.4s, v4.4s
-; CHECK-IADISABLED-NEXT: rev64 v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v0.4s, v4.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v2.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: multiple_muls_mul_external_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov d4, v0.d[1]
+; CHECK-NEXT: mov d5, v1.d[1]
+; CHECK-NEXT: mov d6, v2.d[1]
+; CHECK-NEXT: mov d7, v3.d[1]
+; CHECK-NEXT: movi v16.2s, #128, lsl #24
+; CHECK-NEXT: uzp2 v17.2s, v0.2s, v4.2s
+; CHECK-NEXT: uzp2 v18.2s, v1.2s, v5.2s
+; CHECK-NEXT: uzp1 v19.2s, v2.2s, v6.2s
+; CHECK-NEXT: uzp2 v20.2s, v3.2s, v7.2s
+; CHECK-NEXT: uzp1 v0.2s, v0.2s, v4.2s
+; CHECK-NEXT: uzp1 v1.2s, v1.2s, v5.2s
+; CHECK-NEXT: uzp2 v2.2s, v2.2s, v6.2s
+; CHECK-NEXT: movi v4.2s, #128, lsl #24
+; CHECK-NEXT: uzp1 v3.2s, v3.2s, v7.2s
+; CHECK-NEXT: movi v6.2s, #128, lsl #24
+; CHECK-NEXT: fmls v16.2s, v17.2s, v18.2s
+; CHECK-NEXT: fmul v5.2s, v19.2s, v20.2s
+; CHECK-NEXT: fmls v4.2s, v2.2s, v20.2s
+; CHECK-NEXT: fmla v16.2s, v1.2s, v0.2s
+; CHECK-NEXT: fmul v0.2s, v0.2s, v18.2s
+; CHECK-NEXT: fmla v5.2s, v3.2s, v2.2s
+; CHECK-NEXT: fmla v4.2s, v3.2s, v19.2s
+; CHECK-NEXT: fmla v0.2s, v1.2s, v17.2s
+; CHECK-NEXT: str d16, [x0]
+; CHECK-NEXT: fmul v7.2s, v16.2s, v5.2s
+; CHECK-NEXT: fmla v7.2s, v4.2s, v0.2s
+; CHECK-NEXT: fmls v6.2s, v0.2s, v5.2s
+; CHECK-NEXT: zip1 v0.4s, v4.4s, v5.4s
+; CHECK-NEXT: fmla v6.2s, v4.2s, v16.2s
+; CHECK-NEXT: st2 { v6.2s, v7.2s }, [x1]
+; CHECK-NEXT: ret
entry:
%a.deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %a)
%strided.vec = extractvalue { <2 x float>, <2 x float> } %a.deinterleaved, 0
diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
index 355adec955e4ba..ad6f77773d9fcd 100644
--- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
+++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions.ll
@@ -31,8 +31,8 @@ define dso_local %"struct.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp2 v2.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: faddp d1, v2.2d
; CHECK-NEXT: ret
@@ -98,8 +98,8 @@ define %"struct.std::complex" @complex_mul_nonzero_init_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v0.2d, v4.2d, v2.2d, #90
; CHECK-NEXT: b.ne .LBB1_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v2.2d, v1.2d, v0.2d
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp2 v2.2d, v1.2d, v0.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v0.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: faddp d1, v2.2d
; CHECK-NEXT: ret
@@ -168,10 +168,10 @@ define %"struct.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) {
; CHECK-NEXT: fcmla v3.2d, v18.2d, v16.2d, #90
; CHECK-NEXT: b.ne .LBB2_1
; CHECK-NEXT: // %bb.2: // %middle.block
-; CHECK-NEXT: zip2 v4.2d, v0.2d, v3.2d
-; CHECK-NEXT: zip1 v0.2d, v0.2d, v3.2d
-; CHECK-NEXT: zip2 v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: zip1 v1.2d, v2.2d, v1.2d
+; CHECK-NEXT: uzp2 v4.2d, v0.2d, v3.2d
+; CHECK-NEXT: uzp1 v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: uzp2 v3.2d, v2.2d, v1.2d
+; CHECK-NEXT: uzp1 v1.2d, v2.2d, v1.2d
; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d
; CHECK-NEXT: fadd v1.2d, v4.2d, v3.2d
; CHECK-NEXT: faddp d0, v0.2d
diff --git a/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll b/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
index 09b6072e8aee27..d9289db8953293 100644
--- a/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-deinterleave-intrinsics.ll
@@ -5,91 +5,18 @@
; RUN: llc -mtriple=aarch64-linux-gnu --lower-interleaved-accesses=false < %s -mattr=+sve -force-streaming-compatible | FileCheck %s --check-prefixes=SVE-FIXED,SVE-FIXED-IADISABLED
define void @deinterleave_i8_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i8_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i8_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.16b, v1.16b, v0.16b
-; NEON-IADISABLED-NEXT: uzp2 v0.16b, v1.16b, v0.16b
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i8_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i8_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
-; SVE-FIXED-NEXT: .cfi_def_cfa_offset 16
-; SVE-FIXED-NEXT: .cfi_offset b8, -16
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z5.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[7]
-; SVE-FIXED-NEXT: mov z7.b, z1.b[5]
-; SVE-FIXED-NEXT: mov z18.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z21.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[3]
-; SVE-FIXED-NEXT: mov z17.b, z1.b[1]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: mov z22.b, z1.b[6]
-; SVE-FIXED-NEXT: mov z23.b, z1.b[4]
-; SVE-FIXED-NEXT: zip1 z19.b, z21.b, z20.b
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[2]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z26.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z27.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z28.b, z0.b[8]
-; SVE-FIXED-NEXT: mov z29.b, z0.b[6]
-; SVE-FIXED-NEXT: mov z30.b, z0.b[4]
-; SVE-FIXED-NEXT: mov z31.b, z0.b[2]
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: mov z7.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z16.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[7]
-; SVE-FIXED-NEXT: mov z18.b, z0.b[5]
-; SVE-FIXED-NEXT: mov z8.b, z0.b[3]
-; SVE-FIXED-NEXT: zip1 z20.b, z21.b, z20.b
-; SVE-FIXED-NEXT: mov z21.b, z0.b[1]
-; SVE-FIXED-NEXT: zip1 z22.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z1.b, z1.b, z24.b
-; SVE-FIXED-NEXT: zip1 z23.b, z26.b, z25.b
-; SVE-FIXED-NEXT: zip1 z24.b, z28.b, z27.b
-; SVE-FIXED-NEXT: zip1 z25.b, z30.b, z29.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z31.b
-; SVE-FIXED-NEXT: zip1 z7.b, z16.b, z7.b
-; SVE-FIXED-NEXT: zip1 z16.b, z18.b, z17.b
-; SVE-FIXED-NEXT: zip1 z17.b, z21.b, z8.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z20.h, z19.h
-; SVE-FIXED-NEXT: zip1 z1.h, z1.h, z22.h
-; SVE-FIXED-NEXT: zip1 z18.h, z24.h, z23.h
-; SVE-FIXED-NEXT: zip1 z4.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z25.h
-; SVE-FIXED-NEXT: zip1 z5.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z6.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z2.s, z4.s, z2.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z18.s
-; SVE-FIXED-NEXT: zip1 z3.s, z6.s, z5.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
-; SVE-FIXED-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
+; SVE-FIXED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <32 x i8>, ptr %ptr, align 1
%deinterleave = tail call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %load)
@@ -101,55 +28,18 @@ define void @deinterleave_i8_factor2(ptr %ptr) {
}
define void @deinterleave_i16_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: uzp2 v0.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i16_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: mov z2.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z16.h, z0.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[2]
-; SVE-FIXED-NEXT: mov z18.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z19.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z20.h, z1.h[2]
-; SVE-FIXED-NEXT: mov z4.h, z0.h[3]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[1]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z21.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z22.h, z1.h[3]
-; SVE-FIXED-NEXT: mov z23.h, z1.h[1]
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z16.h, z7.h
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z17.h
-; SVE-FIXED-NEXT: zip1 z7.h, z19.h, z18.h
-; SVE-FIXED-NEXT: zip1 z1.h, z1.h, z20.h
-; SVE-FIXED-NEXT: zip1 z4.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z5.h, z21.h, z6.h
-; SVE-FIXED-NEXT: zip1 z6.h, z23.h, z22.h
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z3.s
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z7.s
-; SVE-FIXED-NEXT: zip1 z2.s, z4.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z6.s, z5.s
-; SVE-FIXED-NEXT: zip1 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <16 x i16>, ptr %ptr, align 2
%deinterleave = tail call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %load)
@@ -161,39 +51,18 @@ define void @deinterleave_i16_factor2(ptr %ptr) {
}
define void @deinterleave_8xi32_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_8xi32_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_8xi32_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_8xi32_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_8xi32_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z3.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z4.s, z0.s[2]
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z5.s, z1.s[1]
-; SVE-FIXED-NEXT: mov z6.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z7.s, z0.s[1]
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z4.s
-; SVE-FIXED-NEXT: zip1 z2.s, z5.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z7.s, z6.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <8 x i32>, ptr %ptr, align 4
%deinterleave = tail call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %load)
@@ -205,29 +74,18 @@ define void @deinterleave_8xi32_factor2(ptr %ptr) {
}
define void @deinterleave_i64_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_i64_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_i64_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_i64_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_i64_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x i64>, ptr %ptr, align 8
%deinterleave = tail call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %load)
@@ -239,39 +97,18 @@ define void @deinterleave_i64_factor2(ptr %ptr) {
}
define void @deinterleave_float_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_float_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_float_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_float_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_float_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q0, q1, [x0]
-; SVE-FIXED-NEXT: mov z3.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z4.s, z0.s[2]
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z5.s, z1.s[1]
-; SVE-FIXED-NEXT: mov z6.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z7.s, z0.s[1]
-; SVE-FIXED-NEXT: zip1 z1.s, z1.s, z3.s
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z4.s
-; SVE-FIXED-NEXT: zip1 z2.s, z5.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z7.s, z6.s
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
-; SVE-FIXED-NEXT: // fake_use: $q1 $z1
+; SVE-FIXED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <8 x float>, ptr %ptr, align 4
%deinterleave = tail call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %load)
@@ -283,29 +120,18 @@ define void @deinterleave_float_factor2(ptr %ptr) {
}
define void @deinterleave_double_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_double_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_double_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_double_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_double_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x double>, ptr %ptr, align 8
%deinterleave = tail call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %load)
@@ -317,29 +143,18 @@ define void @deinterleave_double_factor2(ptr %ptr) {
}
define void @deinterleave_ptr_factor2(ptr %ptr) {
-; NEON-IAENABLED-LABEL: deinterleave_ptr_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_ptr_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; NEON-IADISABLED-NEXT: // fake_use: $q2
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_ptr_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_ptr_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: ldp q1, q0, [x0]
-; SVE-FIXED-NEXT: zip1 z2.d, z1.d, z0.d
-; SVE-FIXED-NEXT: trn2 z0.d, z1.d, z0.d
-; SVE-FIXED-NEXT: // fake_use: $q2 $z2
-; SVE-FIXED-NEXT: // fake_use: $q0 $z0
+; SVE-FIXED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; SVE-FIXED-NEXT: // fake_use: $q0
+; SVE-FIXED-NEXT: // fake_use: $q1 $q0_q1
; SVE-FIXED-NEXT: ret
%load = load <4 x ptr>, ptr %ptr, align 8
%deinterleave = tail call { <2 x ptr>, <2 x ptr> } @llvm.vector.deinterleave2.v4p0(<4 x ptr> %load)
@@ -351,57 +166,19 @@ define void @deinterleave_ptr_factor2(ptr %ptr) {
}
define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
-; NEON-IAENABLED-LABEL: interleave_i8_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i8_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i8_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i8_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z5.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z7.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z18.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z22.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z23.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[8]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: zip1 z7.b, z21.b, z20.b
-; SVE-FIXED-NEXT: zip1 z16.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z1.b
-; SVE-FIXED-NEXT: zip1 z17.b, z25.b, z24.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.b, vl16
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2b { z0.b, z1.b }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r)
store <32 x i8> %interleave, ptr %ptr, align 1
@@ -409,41 +186,19 @@ define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
}
define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
-; NEON-IAENABLED-LABEL: interleave_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i16_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z4.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z16.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[4]
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z1.h
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.h, vl8
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2h { z0.h, z1.h }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r)
store <16 x i16> %interleave, ptr %ptr, align 2
@@ -451,33 +206,19 @@ define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
}
define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
-; NEON-IAENABLED-LABEL: interleave_i32_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i32_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i32_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i32_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r)
store <8 x i32> %interleave, ptr %ptr, align 4
@@ -485,27 +226,19 @@ define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
}
define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
-; NEON-IAENABLED-LABEL: interleave_i64_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i64_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i64_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i64_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r)
store <4 x i64> %interleave, ptr %ptr, align 8
@@ -513,33 +246,19 @@ define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
}
define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r) {
-; NEON-IAENABLED-LABEL: interleave_float_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_float_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_float_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_float_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r)
store <8 x float> %interleave, ptr %ptr, align 4
@@ -547,27 +266,19 @@ define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r)
}
define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> %r) {
-; NEON-IAENABLED-LABEL: interleave_double_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_double_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_double_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_double_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r)
store <4 x double> %interleave, ptr %ptr, align 4
@@ -575,27 +286,19 @@ define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> %
}
define void @interleave_ptr_factor2(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
-; NEON-IAENABLED-LABEL: interleave_ptr_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_ptr_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_ptr_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_ptr_factor2:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r)
store <4 x ptr> %interleave, ptr %ptr, align 4
@@ -603,29 +306,15 @@ define void @interleave_ptr_factor2(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
}
define void @deinterleave_wide_i16_factor2(ptr %ptr) #0 {
-; NEON-IAENABLED-LABEL: deinterleave_wide_i16_factor2:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0], #32
-; NEON-IAENABLED-NEXT: ld2 { v2.8h, v3.8h }, [x0]
-; NEON-IAENABLED-NEXT: // fake_use: $q0
-; NEON-IAENABLED-NEXT: // fake_use: $q2
-; NEON-IAENABLED-NEXT: // fake_use: $q1 $q0_q1
-; NEON-IAENABLED-NEXT: // fake_use: $q3 $q2_q3
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: deinterleave_wide_i16_factor2:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: ldp q1, q0, [x0]
-; NEON-IADISABLED-NEXT: ldp q3, q2, [x0, #32]
-; NEON-IADISABLED-NEXT: uzp1 v4.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: uzp2 v0.8h, v1.8h, v0.8h
-; NEON-IADISABLED-NEXT: uzp2 v5.8h, v3.8h, v2.8h
-; NEON-IADISABLED-NEXT: uzp1 v1.8h, v3.8h, v2.8h
-; NEON-IADISABLED-NEXT: // fake_use: $q4
-; NEON-IADISABLED-NEXT: // fake_use: $q1
-; NEON-IADISABLED-NEXT: // fake_use: $q0
-; NEON-IADISABLED-NEXT: // fake_use: $q5
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: deinterleave_wide_i16_factor2:
+; NEON: // %bb.0:
+; NEON-NEXT: ld2 { v0.8h, v1.8h }, [x0], #32
+; NEON-NEXT: ld2 { v2.8h, v3.8h }, [x0]
+; NEON-NEXT: // fake_use: $q0
+; NEON-NEXT: // fake_use: $q2
+; NEON-NEXT: // fake_use: $q1 $q0_q1
+; NEON-NEXT: // fake_use: $q3 $q2_q3
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: deinterleave_wide_i16_factor2:
; SVE-FIXED: // %bb.0:
@@ -727,18 +416,19 @@ define void @interleave_wide_ptr_factor2(ptr %ptr, <8 x ptr> %l, <8 x ptr> %r) {
;
; NEON-IADISABLED-LABEL: interleave_wide_ptr_factor2:
; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v16.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip1 v3.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip2 v7.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip2 v6.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: zip1 v1.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: stp q3, q16, [x0, #96]
-; NEON-IADISABLED-NEXT: zip2 v3.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: stp q1, q6, [x0, #32]
-; NEON-IADISABLED-NEXT: stp q2, q7, [x0, #64]
-; NEON-IADISABLED-NEXT: stp q0, q3, [x0]
+; NEON-IADISABLED-NEXT: // kill: def $q7 killed $q7 killed $q6_q7 def $q6_q7
+; NEON-IADISABLED-NEXT: mov v17.16b, v6.16b
+; NEON-IADISABLED-NEXT: // kill: def $q5 killed $q5 killed $q4_q5 def $q4_q5
+; NEON-IADISABLED-NEXT: mov v19.16b, v4.16b
+; NEON-IADISABLED-NEXT: add x8, x0, #64
+; NEON-IADISABLED-NEXT: mov v6.16b, v3.16b
+; NEON-IADISABLED-NEXT: mov v16.16b, v2.16b
+; NEON-IADISABLED-NEXT: mov v4.16b, v1.16b
+; NEON-IADISABLED-NEXT: mov v18.16b, v0.16b
+; NEON-IADISABLED-NEXT: st2 { v16.2d, v17.2d }, [x8], #32
+; NEON-IADISABLED-NEXT: st2 { v18.2d, v19.2d }, [x0], #32
+; NEON-IADISABLED-NEXT: st2 { v6.2d, v7.2d }, [x8]
+; NEON-IADISABLED-NEXT: st2 { v4.2d, v5.2d }, [x0]
; NEON-IADISABLED-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_wide_ptr_factor2:
@@ -770,27 +460,19 @@ define void @interleave_wide_ptr_factor2(ptr %ptr, <8 x ptr> %l, <8 x ptr> %r) {
}
define void @interleave_double_factor2_intrinsic(ptr %ptr, <2 x double> %l, <2 x double> %r) {
-; NEON-IAENABLED-LABEL: interleave_double_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_double_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_double_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_double_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r)
store <4 x double> %interleave, ptr %ptr, align 4
@@ -798,33 +480,19 @@ define void @interleave_double_factor2_intrinsic(ptr %ptr, <2 x double> %l, <2 x
}
define void @interleave_float_factor2_intrinsic(ptr %ptr, <4 x float> %l, <4 x float> %r) {
-; NEON-IAENABLED-LABEL: interleave_float_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_float_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_float_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_float_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r)
store <8 x float> %interleave, ptr %ptr, align 4
@@ -832,41 +500,19 @@ define void @interleave_float_factor2_intrinsic(ptr %ptr, <4 x float> %l, <4 x f
}
define void @interleave_i16_factor2_intrinsic(ptr %ptr, <8 x i16> %l, <8 x i16> %r) {
-; NEON-IAENABLED-LABEL: interleave_i16_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i16_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i16_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i16_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.h, z1.h[7]
-; SVE-FIXED-NEXT: mov z3.h, z0.h[7]
-; SVE-FIXED-NEXT: mov z4.h, z1.h[6]
-; SVE-FIXED-NEXT: mov z5.h, z0.h[6]
-; SVE-FIXED-NEXT: mov z6.h, z1.h[5]
-; SVE-FIXED-NEXT: mov z7.h, z0.h[5]
-; SVE-FIXED-NEXT: mov z16.h, z1.h[4]
-; SVE-FIXED-NEXT: mov z17.h, z0.h[4]
-; SVE-FIXED-NEXT: zip1 z0.h, z0.h, z1.h
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.h, vl8
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2h { z0.h, z1.h }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r)
store <16 x i16> %interleave, ptr %ptr, align 2
@@ -874,33 +520,19 @@ define void @interleave_i16_factor2_intrinsic(ptr %ptr, <8 x i16> %l, <8 x i16>
}
define void @interleave_i32_factor2_intrinsic(ptr %ptr, <4 x i32> %l, <4 x i32> %r) {
-; NEON-IAENABLED-LABEL: interleave_i32_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i32_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i32_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i32_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.s, z1.s[3]
-; SVE-FIXED-NEXT: mov z3.s, z0.s[3]
-; SVE-FIXED-NEXT: mov z4.s, z1.s[2]
-; SVE-FIXED-NEXT: mov z5.s, z0.s[2]
-; SVE-FIXED-NEXT: zip1 z0.s, z0.s, z1.s
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.s, vl4
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r)
store <8 x i32> %interleave, ptr %ptr, align 4
@@ -908,27 +540,19 @@ define void @interleave_i32_factor2_intrinsic(ptr %ptr, <4 x i32> %l, <4 x i32>
}
define void @interleave_i64_factor2_intrinsic(ptr %ptr, <2 x i64> %l, <2 x i64> %r) {
-; NEON-IAENABLED-LABEL: interleave_i64_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i64_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i64_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i64_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r)
store <4 x i64> %interleave, ptr %ptr, align 8
@@ -936,57 +560,19 @@ define void @interleave_i64_factor2_intrinsic(ptr %ptr, <2 x i64> %l, <2 x i64>
}
define void @interleave_i8_factor2_intrinsic(ptr %ptr, <16 x i8> %l, <16 x i8> %r) {
-; NEON-IAENABLED-LABEL: interleave_i8_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_i8_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_i8_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_i8_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: mov z2.b, z1.b[15]
-; SVE-FIXED-NEXT: mov z3.b, z0.b[15]
-; SVE-FIXED-NEXT: mov z4.b, z1.b[14]
-; SVE-FIXED-NEXT: mov z5.b, z0.b[14]
-; SVE-FIXED-NEXT: mov z6.b, z1.b[13]
-; SVE-FIXED-NEXT: mov z7.b, z0.b[13]
-; SVE-FIXED-NEXT: mov z16.b, z1.b[12]
-; SVE-FIXED-NEXT: mov z17.b, z0.b[12]
-; SVE-FIXED-NEXT: mov z18.b, z1.b[11]
-; SVE-FIXED-NEXT: mov z19.b, z0.b[11]
-; SVE-FIXED-NEXT: mov z20.b, z1.b[10]
-; SVE-FIXED-NEXT: mov z21.b, z0.b[10]
-; SVE-FIXED-NEXT: mov z22.b, z1.b[9]
-; SVE-FIXED-NEXT: mov z23.b, z0.b[9]
-; SVE-FIXED-NEXT: mov z24.b, z1.b[8]
-; SVE-FIXED-NEXT: mov z25.b, z0.b[8]
-; SVE-FIXED-NEXT: zip1 z2.b, z3.b, z2.b
-; SVE-FIXED-NEXT: zip1 z3.b, z5.b, z4.b
-; SVE-FIXED-NEXT: zip1 z4.b, z7.b, z6.b
-; SVE-FIXED-NEXT: zip1 z5.b, z17.b, z16.b
-; SVE-FIXED-NEXT: zip1 z6.b, z19.b, z18.b
-; SVE-FIXED-NEXT: zip1 z7.b, z21.b, z20.b
-; SVE-FIXED-NEXT: zip1 z16.b, z23.b, z22.b
-; SVE-FIXED-NEXT: zip1 z0.b, z0.b, z1.b
-; SVE-FIXED-NEXT: zip1 z17.b, z25.b, z24.b
-; SVE-FIXED-NEXT: zip1 z2.h, z3.h, z2.h
-; SVE-FIXED-NEXT: zip1 z3.h, z5.h, z4.h
-; SVE-FIXED-NEXT: zip1 z4.h, z7.h, z6.h
-; SVE-FIXED-NEXT: zip1 z5.h, z17.h, z16.h
-; SVE-FIXED-NEXT: zip1 z2.s, z3.s, z2.s
-; SVE-FIXED-NEXT: zip1 z3.s, z5.s, z4.s
-; SVE-FIXED-NEXT: zip1 z1.d, z3.d, z2.d
-; SVE-FIXED-NEXT: stp q0, q1, [x0]
+; SVE-FIXED-NEXT: ptrue p0.b, vl16
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2b { z0.b, z1.b }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r)
store <32 x i8> %interleave, ptr %ptr, align 1
@@ -994,27 +580,19 @@ define void @interleave_i8_factor2_intrinsic(ptr %ptr, <16 x i8> %l, <16 x i8> %
}
define void @interleave_ptr_factor2_intrinsic(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) {
-; NEON-IAENABLED-LABEL: interleave_ptr_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: interleave_ptr_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: interleave_ptr_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_ptr_factor2_intrinsic:
; SVE-FIXED: // %bb.0:
-; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 def $z0
-; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 def $z1
-; SVE-FIXED-NEXT: trn2 z2.d, z0.d, z1.d
-; SVE-FIXED-NEXT: zip1 z0.d, z0.d, z1.d
-; SVE-FIXED-NEXT: stp q0, q2, [x0]
+; SVE-FIXED-NEXT: ptrue p0.d, vl2
+; SVE-FIXED-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; SVE-FIXED-NEXT: st2d { z0.d, z1.d }, p0, [x0]
; SVE-FIXED-NEXT: ret
%interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r)
store <4 x ptr> %interleave, ptr %ptr, align 4
@@ -1043,18 +621,19 @@ define void @interleave_wide_ptr_factor2_intrinsic(ptr %ptr, <8 x ptr> %l, <8 x
;
; NEON-IADISABLED-LABEL: interleave_wide_ptr_factor2_intrinsic:
; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v16.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip1 v3.2d, v3.2d, v7.2d
-; NEON-IADISABLED-NEXT: zip2 v7.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip1 v2.2d, v2.2d, v6.2d
-; NEON-IADISABLED-NEXT: zip2 v6.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: zip1 v1.2d, v1.2d, v5.2d
-; NEON-IADISABLED-NEXT: stp q3, q16, [x0, #96]
-; NEON-IADISABLED-NEXT: zip2 v3.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v4.2d
-; NEON-IADISABLED-NEXT: stp q1, q6, [x0, #32]
-; NEON-IADISABLED-NEXT: stp q2, q7, [x0, #64]
-; NEON-IADISABLED-NEXT: stp q0, q3, [x0]
+; NEON-IADISABLED-NEXT: // kill: def $q7 killed $q7 killed $q6_q7 def $q6_q7
+; NEON-IADISABLED-NEXT: mov v17.16b, v6.16b
+; NEON-IADISABLED-NEXT: // kill: def $q5 killed $q5 killed $q4_q5 def $q4_q5
+; NEON-IADISABLED-NEXT: mov v19.16b, v4.16b
+; NEON-IADISABLED-NEXT: add x8, x0, #64
+; NEON-IADISABLED-NEXT: mov v6.16b, v3.16b
+; NEON-IADISABLED-NEXT: mov v16.16b, v2.16b
+; NEON-IADISABLED-NEXT: mov v4.16b, v1.16b
+; NEON-IADISABLED-NEXT: mov v18.16b, v0.16b
+; NEON-IADISABLED-NEXT: st2 { v16.2d, v17.2d }, [x8], #32
+; NEON-IADISABLED-NEXT: st2 { v18.2d, v19.2d }, [x0], #32
+; NEON-IADISABLED-NEXT: st2 { v6.2d, v7.2d }, [x8]
+; NEON-IADISABLED-NEXT: st2 { v4.2d, v5.2d }, [x0]
; NEON-IADISABLED-NEXT: ret
;
; SVE-FIXED-LABEL: interleave_wide_ptr_factor2_intrinsic:
@@ -1086,6 +665,5 @@ define void @interleave_wide_ptr_factor2_intrinsic(ptr %ptr, <8 x ptr> %l, <8 x
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NEON: {{.*}}
; SVE-FIXED-IADISABLED: {{.*}}
; SVE-FIXED-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
index 1278606f5b63f4..3c0dc8d99dc769 100644
--- a/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-length-sve-interleave.ll
@@ -5,20 +5,15 @@
define void @store_factor2_intrinsic(ptr %ptr, <16 x i16> %v0, <16 x i16> %v1) vscale_range(2,2) {
; CHECK-LABEL: store_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI0_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI0_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x i16> @llvm.vector.interleave2.v32i16(<16 x i16> %v0, <16 x i16> %v1)
store <32 x i16> %interleaved.vec, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
index 426fb4b472cbee..625de777a9583f 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
@@ -1,25 +1,16 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false -global-isel -global-isel-abort=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
-; CHECK-SD-LABEL: vector_deinterleave_v2f16_v4f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: dup v1.2s, v0.s[1]
-; CHECK-SD-NEXT: zip1 v2.4h, v0.4h, v1.4h
-; CHECK-SD-NEXT: trn2 v1.4h, v0.4h, v1.4h
-; CHECK-SD-NEXT: fmov d0, d2
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vector_deinterleave_v2f16_v4f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: uzp1 v2.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: uzp2 v1.4h, v0.4h, v0.4h
-; CHECK-GI-NEXT: fmov d0, d2
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: uzp1 v2.4h, v0.4h, v0.4h
+; CHECK-NEXT: uzp2 v1.4h, v0.4h, v0.4h
+; CHECK-NEXT: fmov d0, d2
+; CHECK-NEXT: ret
%retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)
ret {<2 x half>, <2 x half>} %retval
}
@@ -51,8 +42,8 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %
; CHECK-SD-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov d1, v0.d[1]
-; CHECK-SD-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: zip2 v1.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: uzp1 v2.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: uzp2 v1.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: fmov d0, d2
; CHECK-SD-NEXT: ret
;
@@ -79,12 +70,19 @@ ret {<4 x float>, <4 x float>} %retval
}
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
-; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vector_deinterleave_v2f64_v4f64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: uzp2 v1.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vector_deinterleave_v2f64_v4f64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: zip1 v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: zip2 v1.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval
}
@@ -125,12 +123,19 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) {
}
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
-; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vector_deinterleave_v2i64_v4i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: uzp2 v1.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: mov v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vector_deinterleave_v2i64_v4i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: zip1 v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: zip2 v1.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: mov v0.16b, v2.16b
+; CHECK-GI-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval
}
@@ -505,11 +510,12 @@ define {<2 x double>, <2 x double>, <2 x double>, <2 x double>, <2 x double>, <2
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.2d, v6.2d, v7.2d }, [x8]
; CHECK-NEXT: ld3 { v16.2d, v17.2d, v18.2d }, [x9]
; CHECK-NEXT: uzp1 v0.2d, v16.2d, v5.2d
@@ -535,11 +541,12 @@ define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.4s, v6.4s, v7.4s }, [x8]
; CHECK-NEXT: ld3 { v16.4s, v17.4s, v18.4s }, [x9]
; CHECK-NEXT: uzp1 v0.4s, v16.4s, v5.4s
@@ -565,11 +572,12 @@ define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: stp d4, d5, [sp, #32]
-; CHECK-NEXT: add x8, sp, #24
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp d2, d3, [sp, #16]
-; CHECK-NEXT: stp d0, d1, [sp]
+; CHECK-NEXT: stp d4, d5, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: str d3, [sp]
+; CHECK-NEXT: stp d1, d2, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #24]
; CHECK-NEXT: ld3 { v5.2s, v6.2s, v7.2s }, [x8]
; CHECK-NEXT: ld3 { v16.2s, v17.2s, v18.2s }, [x9]
; CHECK-NEXT: uzp1 v0.2s, v16.2s, v5.2s
@@ -595,11 +603,12 @@ define {<8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.8h, v6.8h, v7.8h }, [x8]
; CHECK-NEXT: ld3 { v16.8h, v17.8h, v18.8h }, [x9]
; CHECK-NEXT: uzp1 v0.8h, v16.8h, v5.8h
@@ -625,11 +634,12 @@ define {<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: stp d4, d5, [sp, #32]
-; CHECK-NEXT: add x8, sp, #24
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp d2, d3, [sp, #16]
-; CHECK-NEXT: stp d0, d1, [sp]
+; CHECK-NEXT: stp d4, d5, [sp, #8]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: str d3, [sp]
+; CHECK-NEXT: stp d1, d2, [sp, #32]
+; CHECK-NEXT: str d0, [sp, #24]
; CHECK-NEXT: ld3 { v5.4h, v6.4h, v7.4h }, [x8]
; CHECK-NEXT: ld3 { v16.4h, v17.4h, v18.4h }, [x9]
; CHECK-NEXT: uzp1 v0.4h, v16.4h, v5.4h
@@ -655,11 +665,12 @@ define {<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>} @deint
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
; CHECK-NEXT: .cfi_def_cfa_offset 96
-; CHECK-NEXT: stp q0, q1, [sp]
-; CHECK-NEXT: add x8, sp, #48
-; CHECK-NEXT: mov x9, sp
-; CHECK-NEXT: stp q2, q3, [sp, #32]
-; CHECK-NEXT: stp q4, q5, [sp, #64]
+; CHECK-NEXT: stp q4, q5, [sp, #16]
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: str q3, [sp]
+; CHECK-NEXT: stp q1, q2, [sp, #64]
+; CHECK-NEXT: str q0, [sp, #48]
; CHECK-NEXT: ld3 { v5.16b, v6.16b, v7.16b }, [x8]
; CHECK-NEXT: ld3 { v16.16b, v17.16b, v18.16b }, [x9]
; CHECK-NEXT: uzp1 v0.16b, v16.16b, v5.16b
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
new file mode 100644
index 00000000000000..5dd9b3a4d8080b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave-odd-factor.ll
@@ -0,0 +1,132 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s
+
+define { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @deinterleave5_v10i16(<10 x i16> %vec) {
+; CHECK-LABEL: deinterleave5_v10i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s4, w4
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: fmov s3, w3
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: add x9, sp, #8
+; CHECK-NEXT: fmov s2, w2
+; CHECK-NEXT: mov v1.s[1], w6
+; CHECK-NEXT: ld1 { v4.h }[2], [x9]
+; CHECK-NEXT: mov v0.s[1], w5
+; CHECK-NEXT: ld1 { v3.h }[2], [x8]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
+; CHECK-NEXT: mov v2.s[1], w7
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: ret
+ %result = call { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @llvm.vector.deinterleave5.v10i16(<10 x i16> %vec)
+ ret { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } %result
+}
+
+define <10 x i16> @interleave5_v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) {
+; CHECK-LABEL: interleave5_v10i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v5.16b, v0.16b
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: mov w9, v0.s[1]
+; CHECK-NEXT: mov w10, v3.s[1]
+; CHECK-NEXT: mov w11, v4.s[1]
+; CHECK-NEXT: mov v5.h[1], v1.h[0]
+; CHECK-NEXT: fmov s0, w10
+; CHECK-NEXT: mov v5.h[2], v2.h[0]
+; CHECK-NEXT: mov v0.h[1], w11
+; CHECK-NEXT: mov v5.h[3], v3.h[0]
+; CHECK-NEXT: str s0, [x8, #16]
+; CHECK-NEXT: mov v5.h[4], v4.h[0]
+; CHECK-NEXT: mov v5.h[5], w9
+; CHECK-NEXT: mov w9, v1.s[1]
+; CHECK-NEXT: mov v5.h[6], w9
+; CHECK-NEXT: mov w9, v2.s[1]
+; CHECK-NEXT: mov v5.h[7], w9
+; CHECK-NEXT: str q5, [x8]
+; CHECK-NEXT: ret
+ %result = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
+ ret <10 x i16> %result
+}
+
+define { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @deinterleave7_v14i16(<14 x i16> %vec) {
+; CHECK-LABEL: deinterleave7_v14i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s3, w3
+; CHECK-NEXT: fmov s2, w2
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: fmov s1, w1
+; CHECK-NEXT: fmov s6, w6
+; CHECK-NEXT: add x9, sp, #8
+; CHECK-NEXT: fmov s5, w5
+; CHECK-NEXT: fmov s4, w4
+; CHECK-NEXT: add x10, sp, #16
+; CHECK-NEXT: fmov s0, w0
+; CHECK-NEXT: ld1 { v2.h }[2], [x9]
+; CHECK-NEXT: ld1 { v3.h }[2], [x10]
+; CHECK-NEXT: ld1 { v1.h }[2], [x8]
+; CHECK-NEXT: add x8, sp, #24
+; CHECK-NEXT: add x9, sp, #32
+; CHECK-NEXT: add x10, sp, #40
+; CHECK-NEXT: ld1 { v4.h }[2], [x8]
+; CHECK-NEXT: ld1 { v5.h }[2], [x9]
+; CHECK-NEXT: mov v0.s[1], w7
+; CHECK-NEXT: ld1 { v6.h }[2], [x10]
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 killed $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 killed $q4
+; CHECK-NEXT: // kill: def $d5 killed $d5 killed $q5
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d6 killed $d6 killed $q6
+; CHECK-NEXT: ret
+ %result = call { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } @llvm.vector.deinterleave7.v14i16(<14 x i16> %vec)
+ ret { <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16> } %result
+}
+
+define <14 x i16> @interleave7_v14i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f, <2 x i16> %g) {
+; CHECK-LABEL: interleave7_v14i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v7.16b, v0.16b
+; CHECK-NEXT: mov w9, v1.s[1]
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: // kill: def $d5 killed $d5 def $q5
+; CHECK-NEXT: // kill: def $d6 killed $d6 def $q6
+; CHECK-NEXT: mov w10, v2.s[1]
+; CHECK-NEXT: mov v7.h[1], v1.h[0]
+; CHECK-NEXT: fmov s16, w9
+; CHECK-NEXT: mov w9, v3.s[1]
+; CHECK-NEXT: mov v7.h[2], v2.h[0]
+; CHECK-NEXT: mov v16.h[1], w10
+; CHECK-NEXT: mov w10, v4.s[1]
+; CHECK-NEXT: mov v7.h[3], v3.h[0]
+; CHECK-NEXT: mov v16.h[2], w9
+; CHECK-NEXT: mov w9, v5.s[1]
+; CHECK-NEXT: mov v7.h[4], v4.h[0]
+; CHECK-NEXT: mov v16.h[3], w10
+; CHECK-NEXT: mov w10, v6.s[1]
+; CHECK-NEXT: mov v7.h[5], v5.h[0]
+; CHECK-NEXT: mov v16.h[4], w9
+; CHECK-NEXT: mov w9, v0.s[1]
+; CHECK-NEXT: mov v7.h[6], v6.h[0]
+; CHECK-NEXT: mov v16.h[5], w10
+; CHECK-NEXT: mov v7.h[7], w9
+; CHECK-NEXT: mov s0, v16.s[2]
+; CHECK-NEXT: str d16, [x8, #16]
+; CHECK-NEXT: str q7, [x8]
+; CHECK-NEXT: str s0, [x8, #24]
+; CHECK-NEXT: ret
+ %result = call <14 x i16> @llvm.vector.interleave7.v14i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f, <2 x i16> %g)
+ ret <14 x i16> %result
+}
diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
index ab06111fb52ff2..44a63298d18b84 100644
--- a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64-none-linux-gnu -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
@@ -14,22 +14,12 @@ define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
}
define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
-; CHECK-SD-LABEL: interleave2_v8f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: adrp x8, .LCPI1_0
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
-; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: interleave2_v8f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: interleave2_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
%retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
ret <8 x half> %retval
}
@@ -46,21 +36,12 @@ define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
}
define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
-; CHECK-SD-LABEL: interleave2_v4f32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: rev64 v1.4s, v0.4s
-; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: interleave2_v4f32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: interleave2_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
%retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
ret <4 x float> %retval
}
@@ -187,11 +168,10 @@ define <4 x i16> @interleave2_diff_nonconst_splat_v4i16(i16 %a, i16 %b) {
; CHECK-SD-LABEL: interleave2_diff_nonconst_splat_v4i16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fmov s0, w0
-; CHECK-SD-NEXT: mov v0.h[1], w0
-; CHECK-SD-NEXT: mov v0.h[2], w1
+; CHECK-SD-NEXT: mov v0.h[1], w1
+; CHECK-SD-NEXT: mov v0.h[2], w0
; CHECK-SD-NEXT: mov v0.h[3], w1
-; CHECK-SD-NEXT: rev32 v1.4h, v0.4h
-; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: interleave2_diff_nonconst_splat_v4i16:
@@ -565,20 +545,21 @@ define <12 x double> @interleave6_v12f64(<2 x double> %vec0, <2 x double> %vec1,
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: zip1 v18.2d, v2.2d, v5.2d
; CHECK-NEXT: zip2 v7.2d, v2.2d, v5.2d
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #48
; CHECK-NEXT: zip1 v17.2d, v1.2d, v4.2d
; CHECK-NEXT: zip2 v6.2d, v1.2d, v4.2d
; CHECK-NEXT: zip1 v16.2d, v0.2d, v3.2d
; CHECK-NEXT: zip2 v5.2d, v0.2d, v3.2d
; CHECK-NEXT: st3 { v16.2d, v17.2d, v18.2d }, [x9]
-; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.2d, v6.2d, v7.2d }, [x9]
-; CHECK-NEXT: ldp q2, q0, [sp, #64]
-; CHECK-NEXT: ldp q5, q1, [sp, #32]
-; CHECK-NEXT: ldp q3, q4, [sp]
-; CHECK-NEXT: stp q2, q0, [x8, #64]
+; CHECK-NEXT: ldp q2, q0, [sp, #16]
+; CHECK-NEXT: ldr q1, [sp]
+; CHECK-NEXT: ldp q3, q4, [sp, #48]
+; CHECK-NEXT: ldr q5, [sp, #80]
; CHECK-NEXT: stp q5, q1, [x8, #32]
; CHECK-NEXT: stp q3, q4, [x8]
+; CHECK-NEXT: stp q2, q0, [x8, #64]
; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret
%retval = call <12 x double> @llvm.vector.interleave6.v12f64(<2 x double> %vec0, <2 x double> %vec1, <2 x double> %vec2, <2 x double> %vec3, <2 x double> %vec4, <2 x double> %vec5)
@@ -592,20 +573,21 @@ define <24 x i32> @interleave6_v24i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: zip1 v18.4s, v2.4s, v5.4s
; CHECK-NEXT: zip2 v7.4s, v2.4s, v5.4s
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #48
; CHECK-NEXT: zip1 v17.4s, v1.4s, v4.4s
; CHECK-NEXT: zip2 v6.4s, v1.4s, v4.4s
; CHECK-NEXT: zip1 v16.4s, v0.4s, v3.4s
; CHECK-NEXT: zip2 v5.4s, v0.4s, v3.4s
; CHECK-NEXT: st3 { v16.4s, v17.4s, v18.4s }, [x9]
-; CHECK-NEXT: add x9, sp, #48
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.4s, v6.4s, v7.4s }, [x9]
-; CHECK-NEXT: ldp q2, q0, [sp, #64]
-; CHECK-NEXT: ldp q5, q1, [sp, #32]
-; CHECK-NEXT: ldp q3, q4, [sp]
-; CHECK-NEXT: stp q2, q0, [x8, #64]
+; CHECK-NEXT: ldp q2, q0, [sp, #16]
+; CHECK-NEXT: ldr q1, [sp]
+; CHECK-NEXT: ldp q3, q4, [sp, #48]
+; CHECK-NEXT: ldr q5, [sp, #80]
; CHECK-NEXT: stp q5, q1, [x8, #32]
; CHECK-NEXT: stp q3, q4, [x8]
+; CHECK-NEXT: stp q2, q0, [x8, #64]
; CHECK-NEXT: add sp, sp, #96
; CHECK-NEXT: ret
%retval = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5)
@@ -619,17 +601,18 @@ define <12 x i32> @interleave6_v12i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: zip1 v18.2s, v2.2s, v5.2s
; CHECK-NEXT: zip2 v7.2s, v2.2s, v5.2s
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #24
; CHECK-NEXT: zip1 v17.2s, v1.2s, v4.2s
; CHECK-NEXT: zip2 v6.2s, v1.2s, v4.2s
; CHECK-NEXT: zip1 v16.2s, v0.2s, v3.2s
; CHECK-NEXT: zip2 v5.2s, v0.2s, v3.2s
; CHECK-NEXT: st3 { v16.2s, v17.2s, v18.2s }, [x9]
-; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.2s, v6.2s, v7.2s }, [x9]
-; CHECK-NEXT: ldp d1, d0, [sp, #32]
-; CHECK-NEXT: ldp d3, d2, [sp, #16]
-; CHECK-NEXT: ldp d5, d4, [sp]
+; CHECK-NEXT: ldp d1, d0, [sp, #8]
+; CHECK-NEXT: ldr d2, [sp]
+; CHECK-NEXT: ldp d4, d3, [sp, #32]
+; CHECK-NEXT: ldr d5, [sp, #24]
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: mov v3.d[1], v2.d[0]
; CHECK-NEXT: mov v5.d[1], v4.d[0]
@@ -648,17 +631,18 @@ define <24 x i16> @interleave6_v24i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: zip1 v18.4h, v2.4h, v5.4h
; CHECK-NEXT: zip2 v7.4h, v2.4h, v5.4h
-; CHECK-NEXT: mov x9, sp
+; CHECK-NEXT: add x9, sp, #24
; CHECK-NEXT: zip1 v17.4h, v1.4h, v4.4h
; CHECK-NEXT: zip2 v6.4h, v1.4h, v4.4h
; CHECK-NEXT: zip1 v16.4h, v0.4h, v3.4h
; CHECK-NEXT: zip2 v5.4h, v0.4h, v3.4h
; CHECK-NEXT: st3 { v16.4h, v17.4h, v18.4h }, [x9]
-; CHECK-NEXT: add x9, sp, #24
+; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: st3 { v5.4h, v6.4h, v7.4h }, [x9]
-; CHECK-NEXT: ldp d1, d0, [sp, #32]
-; CHECK-NEXT: ldp d3, d2, [sp, #16]
-; CHECK-NEXT: ldp d5, d4, [sp]
+; CHECK-NEXT: ldp d1, d0, [sp, #8]
+; CHECK-NEXT: ldr d2, [sp]
+; CHECK-NEXT: ldp d4, d3, [sp, #32]
+; CHECK-NEXT: ldr d5, [sp, #24]
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: mov v3.d[1], v2.d[0]
; CHECK-NEXT: mov v5.d[1], v4.d[0]
diff --git a/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll b/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
index da917119c6b25c..0732c30c05992b 100644
--- a/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
+++ b/llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
@@ -349,10 +349,11 @@ define { <8 x i16>, <8 x i16> } @foo_ld2_v8i16(<8 x i1> %mask, ptr %p) {
define { <4 x float>, <4 x float> } @foo_ld2_v4f32(<4 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: shl v0.8b, v0.8b, #7
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
@@ -419,10 +420,11 @@ define { <4 x float>, <4 x float> } @foo_ld2_v4f32(<4 x i1> %mask, ptr %p) {
define { <2 x double>, <2 x double> } @foo_ld2_v2f64(<2 x i1> %mask, ptr %p) {
; CHECK-LABEL: foo_ld2_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
@@ -453,8 +455,8 @@ define { <2 x double>, <2 x double> } @foo_ld2_v2f64(<2 x i1> %mask, ptr %p) {
; CHECK-NEXT: add x8, x0, #24
; CHECK-NEXT: ld1 { v2.d }[1], [x8]
; CHECK-NEXT: .LBB3_8: // %else8
-; CHECK-NEXT: zip1 v0.2d, v1.2d, v2.2d
-; CHECK-NEXT: zip2 v1.2d, v1.2d, v2.2d
+; CHECK-NEXT: uzp1 v0.2d, v1.2d, v2.2d
+; CHECK-NEXT: uzp2 v1.2d, v1.2d, v2.2d
; CHECK-NEXT: ret
%interleaved.mask = call <4 x i1> @llvm.vector.interleave2.v4i1(<2 x i1> %mask, <2 x i1> %mask)
%wide.masked.vec = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 8, <4 x i1> %interleaved.mask, <4 x double> poison)
diff --git a/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll b/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
index 972be0fca20891..4d8a0e9e59b9a5 100644
--- a/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
+++ b/llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll
@@ -345,10 +345,11 @@ define void @foo_st2_v8i16(<8 x i1> %mask, <8 x i16> %val1, <8 x i16> %val2, ptr
define void @foo_st2_v4i32(<4 x i1> %mask, <4 x i32> %val1, <4 x i32> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: shl v0.8b, v0.8b, #7
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
@@ -413,10 +414,11 @@ define void @foo_st2_v4i32(<4 x i1> %mask, <4 x i32> %val1, <4 x i32> %val2, ptr
define void @foo_st2_v2i64(<2 x i1> %mask, <2 x i64> %val1, <2 x i64> %val2, ptr %p) {
; CHECK-LABEL: foo_st2_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: zip1 v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: shl v0.4h, v0.4h, #15
; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
; CHECK-NEXT: and v0.8b, v0.8b, v3.8b
diff --git a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
index 2e52b3b3734849..bfa6d5da749b02 100644
--- a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
@@ -2195,23 +2195,12 @@ define <4 x i1> @load_large_vector_intrinsic(ptr %p) {
}
define void @store_factor2_intrinsic(ptr %ptr, <8 x i8> %v0, <8 x i8> %v1) {
-; NEON-IAENABLED-LABEL: store_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; NEON-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; NEON-IAENABLED-NEXT: st2 { v0.8b, v1.8b }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; NEON-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; NEON-IADISABLED-NEXT: adrp x8, .LCPI41_0
-; NEON-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; NEON-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI41_0]
-; NEON-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; NEON-IADISABLED-NEXT: str q0, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; NEON-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; NEON-NEXT: st2 { v0.8b, v1.8b }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_factor2_intrinsic:
; NO_NEON: // %bb.0:
@@ -2247,25 +2236,15 @@ define void @store_factor2_intrinsic(ptr %ptr, <8 x i8> %v0, <8 x i8> %v1) {
}
define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i32> %v0, <8 x i32> %v1) {
-; NEON-IAENABLED-LABEL: store_factor2_wide_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: mov v5.16b, v2.16b
-; NEON-IAENABLED-NEXT: // kill: def $q3 killed $q3 def $q2_q3
-; NEON-IAENABLED-NEXT: mov v4.16b, v0.16b
-; NEON-IAENABLED-NEXT: mov v2.16b, v1.16b
-; NEON-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
-; NEON-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_factor2_wide_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v4.4s, v1.4s, v3.4s
-; NEON-IADISABLED-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; NEON-IADISABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v2.4s
-; NEON-IADISABLED-NEXT: stp q1, q4, [x0, #32]
-; NEON-IADISABLED-NEXT: stp q0, q3, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_factor2_wide_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: mov v5.16b, v2.16b
+; NEON-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; NEON-NEXT: mov v4.16b, v0.16b
+; NEON-NEXT: mov v2.16b, v1.16b
+; NEON-NEXT: st2 { v4.4s, v5.4s }, [x0], #32
+; NEON-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_factor2_wide_intrinsic:
; NO_NEON: // %bb.0:
@@ -2826,19 +2805,12 @@ define void @store_general_mask_factor4_undefmulti_intrinsic(ptr %ptr, <32 x i32
}
define void @store_ptrvec_factor2_intrinsic(ptr %ptr, <2 x ptr> %v0, <2 x ptr> %v1) {
-; NEON-IAENABLED-LABEL: store_ptrvec_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_ptrvec_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_ptrvec_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_ptrvec_factor2_intrinsic:
; NO_NEON: // %bb.0:
@@ -2895,19 +2867,12 @@ define void @store_ptrvec_factor4_intrinsic(ptr %ptr, <2 x ptr> %v0, <2 x ptr> %
}
define void @store_undef_mask_factor2_intrinsic(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
-; NEON-IAENABLED-LABEL: store_undef_mask_factor2_intrinsic:
-; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; NEON-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; NEON-IAENABLED-NEXT: ret
-;
-; NEON-IADISABLED-LABEL: store_undef_mask_factor2_intrinsic:
-; NEON-IADISABLED: // %bb.0:
-; NEON-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; NEON-IADISABLED-NEXT: stp q0, q2, [x0]
-; NEON-IADISABLED-NEXT: ret
+; NEON-LABEL: store_undef_mask_factor2_intrinsic:
+; NEON: // %bb.0:
+; NEON-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; NEON-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_undef_mask_factor2_intrinsic:
; NO_NEON: // %bb.0:
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll b/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
index 951f356ee1da57..32f43f03b2b160 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-load-interleaved.ll
@@ -2425,39 +2425,19 @@ entry:
}
define void @test_ldnp_interleaved_load2_v2i32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: str d2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x i32>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %loaded)
@@ -2470,37 +2450,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4i16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: xtn v1.4h, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.4h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x i16>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <4 x i16>, <4 x i16> } @llvm.vector.deinterleave2.v8i16(<8 x i16> %loaded)
@@ -2513,37 +2475,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8i8_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8b, v1.8b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: xtn v1.8b, v0.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v0.16b
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8b, v1.8b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8b }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8b }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8b, v1.8b }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.16b, v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.8b }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8b }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8b, v1.8b }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8b }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8b }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x i8>, ptr %ptr, align 1, !nontemporal !0
%deinterleaved = call { <8 x i8>, <8 x i8> } @llvm.vector.deinterleave2.v16i8(<16 x i8> %loaded)
@@ -2556,39 +2500,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2f32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-LE-IADISABLED-NEXT: str d2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2s, v0.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2s, v1.2s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x float>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2.v4f32(<4 x float> %loaded)
@@ -2601,37 +2525,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4f16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str d0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str d1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldr q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-LE-IADISABLED-NEXT: str d1, [x1]
-; CHECK-LE-IADISABLED-NEXT: str d0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4h, v1.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: str d0, [x1]
+; CHECK-LE-NEXT: str d1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v1.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v1.4h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4h, v1.4h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x half>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2.v8f16(<8 x half> %loaded)
@@ -2644,39 +2550,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2i64_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2d }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2d }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2i64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2d }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x i64>, ptr %ptr, align 8, !nontemporal !0
%deinterleaved = call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %loaded)
@@ -2689,39 +2575,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4i32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x i32>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %loaded)
@@ -2734,39 +2600,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8i16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x i16>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %loaded)
@@ -2779,39 +2625,19 @@ entry:
define void @test_ldnp_interleaved_load2_v16i8_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.16b, v1.16b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.16b }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.16b }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.16b }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v16i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.16b, v1.16b }, [x0]
+; CHECK-BE-NEXT: st1 { v0.16b }, [x1]
+; CHECK-BE-NEXT: st1 { v1.16b }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <32 x i8>, ptr %ptr, align 1, !nontemporal !0
%deinterleaved = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %loaded)
@@ -2824,39 +2650,19 @@ entry:
define void @test_ldnp_interleaved_load2_v2f64_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.2d }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.2d }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: zip1 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip2 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v2f64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.2d, v1.2d }, [x0]
+; CHECK-BE-NEXT: st1 { v0.2d }, [x1]
+; CHECK-BE-NEXT: st1 { v1.2d }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <4 x double>, ptr %ptr, align 8, !nontemporal !0
%deinterleaved = call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %loaded)
@@ -2869,39 +2675,19 @@ entry:
define void @test_ldnp_interleaved_load2_v4f32_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.4s }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.4s }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v4f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.4s, v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v0.4s }, [x1]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <8 x float>, ptr %ptr, align 4, !nontemporal !0
%deinterleaved = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %loaded)
@@ -2914,39 +2700,19 @@ entry:
define void @test_ldnp_interleaved_load2_v8f16_intrinsic(ptr %ptr, ptr %out0, ptr %out1) {
-; CHECK-LE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: str q0, [x1]
-; CHECK-LE-IAENABLED-NEXT: str q1, [x2]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: ldnp q0, q1, [x0]
-; CHECK-LE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: str q2, [x1]
-; CHECK-LE-IADISABLED-NEXT: str q0, [x2]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ld2 { v0.8h, v1.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: st1 { v0.8h }, [x1]
-; CHECK-BE-IAENABLED-NEXT: st1 { v1.8h }, [x2]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: str q0, [x1]
+; CHECK-LE-NEXT: str q1, [x2]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ld1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x1]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x2]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_ldnp_interleaved_load2_v8f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ld2 { v0.8h, v1.8h }, [x0]
+; CHECK-BE-NEXT: st1 { v0.8h }, [x1]
+; CHECK-BE-NEXT: st1 { v1.8h }, [x2]
+; CHECK-BE-NEXT: ret
entry:
%loaded = load <16 x half>, ptr %ptr, align 2, !nontemporal !0
%deinterleaved = call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2.v16f16(<16 x half> %loaded)
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
index ca1f86d83710c1..452e2e56c86251 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved-optsize.ll
@@ -166,39 +166,19 @@ entry:
}
define void @test_stnp_interleaved_store2_v2i32_Os_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #0 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Os_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -207,39 +187,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i32_Oz_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) #1 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: str q0, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_Oz_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -248,37 +208,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_Os_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #0 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Os_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -287,37 +229,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_Oz_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) #1 {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
-;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_Oz_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -328,6 +252,3 @@ entry:
attributes #0 = { optsize }
attributes #1 = { minsize optsize }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-BE: {{.*}}
-; CHECK-LE: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
index 76b77530f2d162..9cbc98fc968140 100644
--- a/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
+++ b/llvm/test/CodeGen/AArch64/nontemporal-store-interleaved.ll
@@ -2376,40 +2376,19 @@ entry:
}
define void @test_stnp_interleaved_store2_v2i32_intrinsic(<2 x i32> %v0, <2 x i32> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %v0, <2 x i32> %v1)
store <4 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2418,44 +2397,19 @@ entry:
define void @test_stnp_interleaved_store2_v4i16_intrinsic(<4 x i16> %v0, <4 x i16> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI39_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI39_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.4h, v1.4h
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4h, v0.4h
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4h, v2.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4h, v1.4h
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI39_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI39_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: rev16 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.4h, v1.4h
+; CHECK-BE-NEXT: rev64 v1.4h, v0.4h
+; CHECK-BE-NEXT: st2 { v1.4h, v2.4h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %v0, <4 x i16> %v1)
store <8 x i16> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2464,43 +2418,19 @@ entry:
define void @test_stnp_interleaved_store2_v8i8_intrinsic(<8 x i8> %v0, <8 x i8> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8b, v1.8b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI40_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI40_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.8b, v1.8b
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8b, v0.8b
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8b, v2.8b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.8b, v1.8b }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8b, v0.8b
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8b, v1.8b
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI40_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI40_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.8b, v1.8b
+; CHECK-BE-NEXT: rev64 v1.8b, v0.8b
+; CHECK-BE-NEXT: st2 { v1.8b, v2.8b }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x i8> @llvm.vector.interleave2.v16i8(<8 x i8> %v0, <8 x i8> %v1)
store <16 x i8> %interleave, ptr %ptr, align 1, !nontemporal !0
@@ -2509,40 +2439,19 @@ entry:
define void @test_stnp_interleaved_store2_v2f32_intrinsic(<2 x float> %v0, <2 x float> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-LE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.2s, v1.2s
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.2s, v0.2s
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.2s, v1.2s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.2s, v0.2s
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: uzp1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.2s, v1.2s
+; CHECK-BE-NEXT: rev64 v1.2s, v0.2s
+; CHECK-BE-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %v0, <2 x float> %v1)
store <4 x float> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2551,44 +2460,19 @@ entry:
define void @test_stnp_interleaved_store2_v4f16_intrinsic(<4 x half> %v0, <4 x half> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4h, v1.4h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-IADISABLED-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-IADISABLED-NEXT: adrp x8, .LCPI42_0
-; CHECK-LE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-LE-IADISABLED-NEXT: ldr q1, [x8, :lo12:.LCPI42_0]
-; CHECK-LE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-LE-IADISABLED-NEXT: mov d1, v0.d[1]
-; CHECK-LE-IADISABLED-NEXT: stnp d0, d1, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v2.4h, v1.4h
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4h, v0.4h
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4h, v2.4h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1
+; CHECK-LE-NEXT: st2 { v0.4h, v1.4h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4h, v0.4h
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4h, v1.4h
-; CHECK-BE-IADISABLED-NEXT: adrp x8, .LCPI42_0
-; CHECK-BE-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI42_0
-; CHECK-BE-IADISABLED-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-BE-IADISABLED-NEXT: ld1 { v1.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: rev16 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: tbl v0.16b, { v0.16b }, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v2.4h, v1.4h
+; CHECK-BE-NEXT: rev64 v1.4h, v0.4h
+; CHECK-BE-NEXT: st2 { v1.4h, v2.4h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %v0, <4 x half> %v1)
store <8 x half> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2597,37 +2481,19 @@ entry:
define void @test_stnp_interleaved_store2_v2i64_intrinsic(<2 x i64> %v0, <2 x i64> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %v0, <2 x i64> %v1)
store <4 x i64> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -2636,41 +2502,21 @@ entry:
define void @test_stnp_interleaved_store2_v4i32_intrinsic(<4 x i32> %v0, <4 x i32> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4s, v2.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4i32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.4s, v1.4s
+; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.4s, v2.4s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
store <8 x i32> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2679,41 +2525,21 @@ entry:
define void @test_stnp_interleaved_store2_v8i16_intrinsic(<8 x i16> %v0, <8 x i16> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8h, v2.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8i16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
+; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.8h, v2.8h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %v0, <8 x i16> %v1)
store <16 x i16> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -2722,41 +2548,21 @@ entry:
define void @test_stnp_interleaved_store2_v16i8_intrinsic(<16 x i8> %v0, <16 x i8> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.16b, v1.16b }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.16b, v1.16b
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.16b, v0.16b
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.16b, v2.16b }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.16b, v1.16b }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.16b, v0.16b
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.16b, v0.16b, v1.16b
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.16b }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.16b }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v16i8_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
+; CHECK-BE-NEXT: rev64 v0.16b, v0.16b
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.16b, v2.16b }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %v0, <16 x i8> %v1)
store <32 x i8> %interleave, ptr %ptr, align 1, !nontemporal !0
@@ -2765,37 +2571,19 @@ entry:
define void @test_stnp_interleaved_store2_v2f64_intrinsic(<2 x double> %v0, <2 x double> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.2d, v1.2d }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.2d, v2.2d }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.2d, v1.2d }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.2d, v0.2d, v1.2d
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.2d }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.2d }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2f64_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.2d, v2.2d }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %v0, <2 x double> %v1)
store <4 x double> %interleave, ptr %ptr, align 8, !nontemporal !0
@@ -2804,41 +2592,21 @@ entry:
define void @test_stnp_interleaved_store2_v4f32_intrinsic(<4 x float> %v0, <4 x float> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.4s, v2.4s }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.4s, v0.4s
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.4s }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.4s }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v4f32_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.4s, v1.4s
+; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.4s, v2.4s }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %v0, <4 x float> %v1)
store <8 x float> %interleave, ptr %ptr, align 4, !nontemporal !0
@@ -2847,41 +2615,21 @@ entry:
define void @test_stnp_interleaved_store2_v8f16_intrinsic(<8 x half> %v0, <8 x half> %v1, ptr %ptr) {
-; CHECK-LE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-LE-IAENABLED: // %bb.0: // %entry
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-LE-IAENABLED-NEXT: st2 { v0.8h, v1.8h }, [x0]
-; CHECK-LE-IAENABLED-NEXT: ret
-;
-; CHECK-LE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-LE-IADISABLED: // %bb.0: // %entry
-; CHECK-LE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-LE-IADISABLED-NEXT: stnp q0, q2, [x0]
-; CHECK-LE-IADISABLED-NEXT: ret
-;
-; CHECK-BE-IAENABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-BE-IAENABLED: // %bb.0: // %entry
-; CHECK-BE-IAENABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IAENABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IAENABLED-NEXT: ext v2.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IAENABLED-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IAENABLED-NEXT: st2 { v1.8h, v2.8h }, [x0]
-; CHECK-BE-IAENABLED-NEXT: ret
+; CHECK-LE-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
+; CHECK-LE: // %bb.0: // %entry
+; CHECK-LE-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-LE-NEXT: st2 { v0.8h, v1.8h }, [x0]
+; CHECK-LE-NEXT: ret
;
-; CHECK-BE-IADISABLED-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
-; CHECK-BE-IADISABLED: // %bb.0: // %entry
-; CHECK-BE-IADISABLED-NEXT: rev64 v1.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: rev64 v0.8h, v0.8h
-; CHECK-BE-IADISABLED-NEXT: add x8, x0, #16
-; CHECK-BE-IADISABLED-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-BE-IADISABLED-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-BE-IADISABLED-NEXT: zip2 v2.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: zip1 v0.8h, v0.8h, v1.8h
-; CHECK-BE-IADISABLED-NEXT: st1 { v2.8h }, [x8]
-; CHECK-BE-IADISABLED-NEXT: st1 { v0.8h }, [x0]
-; CHECK-BE-IADISABLED-NEXT: ret
+; CHECK-BE-LABEL: test_stnp_interleaved_store2_v8f16_intrinsic:
+; CHECK-BE: // %bb.0: // %entry
+; CHECK-BE-NEXT: rev64 v1.8h, v1.8h
+; CHECK-BE-NEXT: rev64 v0.8h, v0.8h
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-BE-NEXT: st2 { v1.8h, v2.8h }, [x0]
+; CHECK-BE-NEXT: ret
entry:
%interleave = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %v0, <8 x half> %v1)
store <16 x half> %interleave, ptr %ptr, align 2, !nontemporal !0
@@ -3503,11 +3251,14 @@ entry:
define void @test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic(<3 x i32> %v0, <3 x i32> %v1, ptr %ptr) {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: zip1 v2.4s, v0.4s, v1.4s
-; CHECK-LE-NEXT: zip2 v0.4s, v0.4s, v1.4s
-; CHECK-LE-NEXT: mov d3, v2.d[1]
-; CHECK-LE-NEXT: str d0, [x0, #16]
-; CHECK-LE-NEXT: stnp d2, d3, [x0]
+; CHECK-LE-NEXT: zip2 v2.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: ext v1.16b, v0.16b, v2.16b, #12
+; CHECK-LE-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-LE-NEXT: mov d2, v0.d[1]
+; CHECK-LE-NEXT: ext v1.16b, v1.16b, v0.16b, #4
+; CHECK-LE-NEXT: stnp d0, d2, [x0]
+; CHECK-LE-NEXT: str d1, [x0, #16]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic:
@@ -3518,6 +3269,9 @@ define void @test_stnp_interleaved_store2_v3i32_non_pow2_elt_count_intrinsic(<3
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: zip2 v2.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: zip1 v0.4s, v0.4s, v1.4s
+; CHECK-BE-NEXT: ext v1.16b, v0.16b, v2.16b, #12
+; CHECK-BE-NEXT: ext v2.16b, v1.16b, v0.16b, #4
+; CHECK-BE-NEXT: mov v0.s[3], v1.s[0]
; CHECK-BE-NEXT: rev64 v1.4s, v2.4s
; CHECK-BE-NEXT: st1 { v0.4s }, [x0]
; CHECK-BE-NEXT: str d1, [x0, #16]
@@ -3532,54 +3286,48 @@ entry:
define void @test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic(<2 x i24> %v0, <2 x i24> %v1, ptr %ptr) {
; CHECK-LE-LABEL: test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic:
; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-LE-NEXT: mov v2.16b, v0.16b
-; CHECK-LE-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-LE-NEXT: fmov w9, s0
+; CHECK-LE-NEXT: zip2 v2.2s, v0.2s, v1.2s
+; CHECK-LE-NEXT: zip1 v0.2s, v0.2s, v1.2s
+; CHECK-LE-NEXT: fmov w9, s2
+; CHECK-LE-NEXT: mov w8, v2.s[1]
+; CHECK-LE-NEXT: mov w10, v0.s[1]
+; CHECK-LE-NEXT: str h2, [x0, #6]
; CHECK-LE-NEXT: str h0, [x0]
-; CHECK-LE-NEXT: mov w8, v1.s[1]
-; CHECK-LE-NEXT: mov v2.d[1], v1.d[0]
; CHECK-LE-NEXT: lsr w9, w9, #16
-; CHECK-LE-NEXT: strb w9, [x0, #2]
-; CHECK-LE-NEXT: lsr w9, w8, #16
; CHECK-LE-NEXT: sturh w8, [x0, #9]
-; CHECK-LE-NEXT: rev64 v3.4s, v2.4s
-; CHECK-LE-NEXT: strb w9, [x0, #11]
-; CHECK-LE-NEXT: uzp1 v2.4s, v2.4s, v3.4s
-; CHECK-LE-NEXT: mov w10, v2.s[2]
-; CHECK-LE-NEXT: mov w11, v2.s[1]
-; CHECK-LE-NEXT: lsr w8, w10, #16
-; CHECK-LE-NEXT: lsr w9, w11, #16
-; CHECK-LE-NEXT: strh w10, [x0, #6]
-; CHECK-LE-NEXT: sturh w11, [x0, #3]
-; CHECK-LE-NEXT: strb w8, [x0, #8]
-; CHECK-LE-NEXT: strb w9, [x0, #5]
+; CHECK-LE-NEXT: lsr w8, w8, #16
+; CHECK-LE-NEXT: strb w9, [x0, #8]
+; CHECK-LE-NEXT: fmov w9, s0
+; CHECK-LE-NEXT: sturh w10, [x0, #3]
+; CHECK-LE-NEXT: lsr w10, w10, #16
+; CHECK-LE-NEXT: strb w8, [x0, #11]
+; CHECK-LE-NEXT: lsr w8, w9, #16
+; CHECK-LE-NEXT: strb w10, [x0, #5]
+; CHECK-LE-NEXT: strb w8, [x0, #2]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: test_stnp_interleaved_store2_v2i24_non_pow2_elt_size_intrinsic:
; CHECK-BE: // %bb.0: // %entry
-; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
; CHECK-BE-NEXT: rev64 v1.2s, v1.2s
-; CHECK-BE-NEXT: mov v2.16b, v0.16b
-; CHECK-BE-NEXT: fmov w9, s0
-; CHECK-BE-NEXT: mov w8, v1.s[1]
+; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
+; CHECK-BE-NEXT: zip2 v2.2s, v0.2s, v1.2s
+; CHECK-BE-NEXT: zip1 v0.2s, v0.2s, v1.2s
+; CHECK-BE-NEXT: fmov w9, s2
+; CHECK-BE-NEXT: mov w8, v2.s[1]
+; CHECK-BE-NEXT: mov w10, v0.s[1]
+; CHECK-BE-NEXT: stur b2, [x0, #8]
; CHECK-BE-NEXT: stur b0, [x0, #2]
-; CHECK-BE-NEXT: mov v2.d[1], v1.d[0]
; CHECK-BE-NEXT: lsr w9, w9, #8
; CHECK-BE-NEXT: strb w8, [x0, #11]
-; CHECK-BE-NEXT: strh w9, [x0]
-; CHECK-BE-NEXT: lsr w9, w8, #8
-; CHECK-BE-NEXT: rev64 v3.4s, v2.4s
-; CHECK-BE-NEXT: sturh w9, [x0, #9]
-; CHECK-BE-NEXT: uzp1 v2.4s, v2.4s, v3.4s
-; CHECK-BE-NEXT: mov w10, v2.s[2]
-; CHECK-BE-NEXT: mov w11, v2.s[1]
-; CHECK-BE-NEXT: lsr w8, w10, #8
-; CHECK-BE-NEXT: lsr w9, w11, #8
-; CHECK-BE-NEXT: strb w10, [x0, #8]
-; CHECK-BE-NEXT: strb w11, [x0, #5]
-; CHECK-BE-NEXT: strh w8, [x0, #6]
-; CHECK-BE-NEXT: sturh w9, [x0, #3]
+; CHECK-BE-NEXT: lsr w8, w8, #8
+; CHECK-BE-NEXT: strh w9, [x0, #6]
+; CHECK-BE-NEXT: fmov w9, s0
+; CHECK-BE-NEXT: strb w10, [x0, #5]
+; CHECK-BE-NEXT: lsr w10, w10, #8
+; CHECK-BE-NEXT: sturh w8, [x0, #9]
+; CHECK-BE-NEXT: lsr w8, w9, #8
+; CHECK-BE-NEXT: sturh w10, [x0, #3]
+; CHECK-BE-NEXT: strh w8, [x0]
; CHECK-BE-NEXT: ret
entry:
%interleave = call <4 x i24> @llvm.vector.interleave2.v4i24(<2 x i24> %v0, <2 x i24> %v1)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
index 4300bcf317d12e..1a51a03a4f5b3e 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
@@ -50,25 +50,13 @@ exit:
define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x i32> %b) vscale_range(2,2) #0 {
-; CHECK-IAENABLED-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
-; CHECK-IAENABLED: // %bb.0:
-; CHECK-IAENABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-IAENABLED-NEXT: dup v0.4s, v0.s[0]
-; CHECK-IAENABLED-NEXT: mov v1.16b, v0.16b
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
-; CHECK-IADISABLED: // %bb.0:
-; CHECK-IADISABLED-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-IADISABLED-NEXT: adrp x8, .LCPI2_0
-; CHECK-IADISABLED-NEXT: add x8, x8, :lo12:.LCPI2_0
-; CHECK-IADISABLED-NEXT: dup v0.4s, v0.s[0]
-; CHECK-IADISABLED-NEXT: ldr z1, [x8]
-; CHECK-IADISABLED-NEXT: mov z0.q, q0
-; CHECK-IADISABLED-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-IADISABLED-NEXT: str z0, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v0.4s, v0.s[0]
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x0]
+; CHECK-NEXT: ret
%splat = shufflevector <2 x i32> %b, <2 x i32> poison, <4 x i32> zeroinitializer
%interleaved.vec = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %splat, <4 x i32> %splat)
store <8 x i32> %interleaved.vec, ptr %a, align 4
diff --git a/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
index 30f944e0a050df..6d6473a6da5dab 100644
--- a/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/sve-interleaved-accesses.ll
@@ -1654,20 +1654,15 @@ define void @deinterleave_nxptr_factor2(ptr %ptr) #2 {
define void @store_factor2_intrinsic(ptr %ptr, <16 x i16> %v0, <16 x i16> %v1) #0 {
; CHECK-LABEL: store_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI29_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI29_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x i16> @llvm.vector.interleave2.v32i16(<16 x i16> %v0, <16 x i16> %v1)
store <32 x i16> %interleaved.vec, ptr %ptr, align 4
@@ -1722,20 +1717,15 @@ define void @store_factor4_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1, <4
define void @store_ptrvec_factor2_intrinsic(ptr %ptr, <4 x ptr> %v0, <4 x ptr> %v1) #0 {
; CHECK-LABEL: store_ptrvec_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI32_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI32_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.d, p0, z1.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: tbl z1.d, { z1.d }, z4.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z4.d
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x ptr> @llvm.vector.interleave2.v8p0(<4 x ptr> %v0, <4 x ptr> %v1)
store <8 x ptr> %interleaved.vec, ptr %ptr, align 4
@@ -1791,28 +1781,25 @@ define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i64> %v0, <8 x i64> %v1
; CHECK-LABEL: store_factor2_wide_intrinsic:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
+; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
-; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5
-; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
-; CHECK-NEXT: adrp x8, .LCPI35_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI35_0
-; CHECK-NEXT: splice z3.d, p0, z3.d, z7.d
-; CHECK-NEXT: splice z2.d, p0, z2.d, z6.d
-; CHECK-NEXT: splice z1.d, p0, z1.d, z5.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z4.d
-; CHECK-NEXT: ldr z7, [x8]
-; CHECK-NEXT: tbl z3.d, { z3.d }, z7.d
-; CHECK-NEXT: tbl z2.d, { z2.d }, z7.d
-; CHECK-NEXT: tbl z1.d, { z1.d }, z7.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z7.d
-; CHECK-NEXT: str z3, [x0, #3, mul vl]
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: splice z6.d, p0, z6.d, z7.d
+; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z5.d
+; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: zip2 z1.d, z2.d, z6.d
+; CHECK-NEXT: zip1 z2.d, z2.d, z6.d
+; CHECK-NEXT: zip2 z3.d, z0.d, z4.d
+; CHECK-NEXT: zip1 z0.d, z0.d, z4.d
+; CHECK-NEXT: str z1, [x0, #3, mul vl]
; CHECK-NEXT: str z2, [x0, #2, mul vl]
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
+; CHECK-NEXT: str z3, [x0, #1, mul vl]
; CHECK-NEXT: str z0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <16 x i64> @llvm.vector.interleave2.v16i64(<8 x i64> %v0, <8 x i64> %v1)
@@ -1823,22 +1810,15 @@ define void @store_factor2_wide_intrinsic(ptr %ptr, <8 x i64> %v0, <8 x i64> %v1
define void @store_min_not_max_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1) #1 {
; CHECK-LABEL: store_min_not_max_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI36_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI36_0
-; CHECK-NEXT: ptrue p1.d, vl4
-; CHECK-NEXT: splice z1.d, p0, z1.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: ld1d { z2.d }, p1/z, [x8]
-; CHECK-NEXT: mov x8, #4 // =0x4
-; CHECK-NEXT: tbl z1.d, { z1.d }, z2.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z2.d
-; CHECK-NEXT: st1d { z1.d }, p1, [x0, x8, lsl #3]
-; CHECK-NEXT: st1d { z0.d }, p1, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x i64> @llvm.vector.interleave2.v8i64(<4 x i64> %v0, <4 x i64> %v1)
store <8 x i64> %interleaved.vec, ptr %ptr, align 4
@@ -1848,20 +1828,15 @@ define void @store_min_not_max_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1)
define void @store_min_ge_type_intrinsic(ptr %ptr, <4 x i64> %v0, <4 x i64> %v1) #2 {
; CHECK-LABEL: store_min_ge_type_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: adrp x8, .LCPI37_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI37_0
-; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
-; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.d, p0, z5.d, z3.d
+; CHECK-NEXT: splice z4.d, p0, z4.d, z1.d
; CHECK-NEXT: ptrue p0.d, vl4
-; CHECK-NEXT: ldr z1, [x8]
-; CHECK-NEXT: splice z0.d, p0, z0.d, z2.d
-; CHECK-NEXT: tbl z0.d, { z0.d }, z1.d
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: st2d { z4.d, z5.d }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <8 x i64> @llvm.vector.interleave2.v8i64(<4 x i64> %v0, <4 x i64> %v1)
store <8 x i64> %interleaved.vec, ptr %ptr, align 4
@@ -1916,20 +1891,15 @@ define void @store_float_factor3_intrinsic(ptr %ptr, <8 x float> %v0, <8 x float
define void @store_half_factor2_intrinsic(ptr %ptr, <16 x half> %v0, <16 x half> %v1) #0 {
; CHECK-LABEL: store_half_factor2_intrinsic:
; CHECK: // %bb.0:
+; CHECK-NEXT: mov v5.16b, v2.16b
; CHECK-NEXT: ptrue p0.h, vl8
-; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
-; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
-; CHECK-NEXT: adrp x8, .LCPI40_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI40_0
-; CHECK-NEXT: ldr z4, [x8]
-; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h
-; CHECK-NEXT: splice z0.h, p0, z0.h, z2.h
-; CHECK-NEXT: tbl z1.h, { z1.h }, z4.h
-; CHECK-NEXT: tbl z0.h, { z0.h }, z4.h
-; CHECK-NEXT: str z1, [x0, #1, mul vl]
-; CHECK-NEXT: str z0, [x0]
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h
+; CHECK-NEXT: splice z4.h, p0, z4.h, z1.h
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: st2h { z4.h, z5.h }, p0, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x half> @llvm.vector.interleave2.v32f16(<16 x half> %v0, <16 x half> %v1)
store <32 x half> %interleaved.vec, ptr %ptr, align 4
@@ -1939,12 +1909,12 @@ define void @store_half_factor2_intrinsic(ptr %ptr, <16 x half> %v0, <16 x half>
define void @store_bfloat_factor2_intrinsic(ptr %ptr, <16 x bfloat> %v0, <16 x bfloat> %v1) #0 {
; CHECK-LABEL: store_bfloat_factor2_intrinsic:
; CHECK: // %bb.0:
-; CHECK-NEXT: zip2 v4.8h, v1.8h, v3.8h
-; CHECK-NEXT: zip1 v1.8h, v1.8h, v3.8h
-; CHECK-NEXT: zip2 v3.8h, v0.8h, v2.8h
-; CHECK-NEXT: zip1 v0.8h, v0.8h, v2.8h
-; CHECK-NEXT: stp q1, q4, [x0, #32]
-; CHECK-NEXT: stp q0, q3, [x0]
+; CHECK-NEXT: mov v5.16b, v2.16b
+; CHECK-NEXT: // kill: def $q3 killed $q3 def $q2_q3
+; CHECK-NEXT: mov v4.16b, v0.16b
+; CHECK-NEXT: mov v2.16b, v1.16b
+; CHECK-NEXT: st2 { v4.8h, v5.8h }, [x0], #32
+; CHECK-NEXT: st2 { v2.8h, v3.8h }, [x0]
; CHECK-NEXT: ret
%interleaved.vec = call <32 x bfloat> @llvm.vector.interleave2.v32bf16(<16 x bfloat> %v0, <16 x bfloat> %v1)
store <32 x bfloat> %interleaved.vec, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
index d87b6b04048742..4f4dac8fe9f651 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-interleave.ll
@@ -9,23 +9,15 @@ define void @store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1) {
; CHECK-COMPAT-LABEL: store_factor2_64bit:
; CHECK-COMPAT: // %bb.0:
; CHECK-COMPAT-NEXT: ptrue p0.s, vl2
-; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 def $z1
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI0_0
-; CHECK-COMPAT-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-COMPAT-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-COMPAT-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-COMPAT-NEXT: str q0, [x0]
+; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: store_factor2_64bit:
; CHECK-STREAMING: // %bb.0:
; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI0_0
-; CHECK-STREAMING-NEXT: splice z0.s, p0, { z0.s, z1.s }
-; CHECK-STREAMING-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
-; CHECK-STREAMING-NEXT: tbl z0.s, { z0.s }, z1.s
-; CHECK-STREAMING-NEXT: str q0, [x0]
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <4 x i32> @llvm.vector.interleave2.v4i32(
<2 x i32> %v0, <2 x i32> %v1)
@@ -36,30 +28,16 @@ define void @store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1) {
define void @store_factor2_128bit(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
; CHECK-COMPAT-LABEL: store_factor2_128bit:
; CHECK-COMPAT: // %bb.0:
-; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-COMPAT-NEXT: mov z2.s, z1.s[3]
-; CHECK-COMPAT-NEXT: mov z3.s, z0.s[3]
-; CHECK-COMPAT-NEXT: mov z4.s, z1.s[2]
-; CHECK-COMPAT-NEXT: mov z5.s, z0.s[2]
-; CHECK-COMPAT-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-COMPAT-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-COMPAT-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-COMPAT-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-COMPAT-NEXT: stp q0, q1, [x0]
+; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
+; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: store_factor2_128bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: mov z2.s, z1.s[3]
-; CHECK-STREAMING-NEXT: mov z3.s, z0.s[3]
-; CHECK-STREAMING-NEXT: mov z4.s, z1.s[2]
-; CHECK-STREAMING-NEXT: mov z5.s, z0.s[2]
-; CHECK-STREAMING-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-STREAMING-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-STREAMING-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-STREAMING-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-STREAMING-NEXT: stp q0, q1, [x0]
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <8 x i32> @llvm.vector.interleave2.v8i32(
<4 x i32> %v0, <4 x i32> %v1)
@@ -157,40 +135,22 @@ define void @masked_store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1,
; CHECK-COMPAT-LABEL: masked_store_factor2_64bit:
; CHECK-COMPAT: // %bb.0:
; CHECK-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-COMPAT-NEXT: mov z3.s, z2.s[1]
; CHECK-COMPAT-NEXT: ptrue p0.s, vl2
-; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 def $z1
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI6_0
-; CHECK-COMPAT-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z3.h
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-COMPAT-NEXT: uunpklo z2.s, z2.h
+; CHECK-COMPAT-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: lsl z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: asr z1.s, z2.s, #31
-; CHECK-COMPAT-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-COMPAT-NEXT: tbl z0.s, { z0.s }, z2.s
-; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z1.s, #0
-; CHECK-COMPAT-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-COMPAT-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1
+; CHECK-COMPAT-NEXT: asr z2.s, z2.s, #31
+; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: masked_store_factor2_64bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: mov z3.s, z2.s[1]
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI6_0
-; CHECK-STREAMING-NEXT: splice z0.s, p0, { z0.s, z1.s }
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z3.h
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-STREAMING-NEXT: uunpklo z2.s, z2.h
; CHECK-STREAMING-NEXT: lsl z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: asr z1.s, z2.s, #31
-; CHECK-STREAMING-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
-; CHECK-STREAMING-NEXT: tbl z0.s, { z0.s }, z2.s
-; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z1.s, #0
-; CHECK-STREAMING-NEXT: st1w { z0.s }, p1, [x0]
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl2
+; CHECK-STREAMING-NEXT: asr z2.s, z2.s, #31
+; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <4 x i32> @llvm.vector.interleave2.v4i32(
<2 x i32> %v0, <2 x i32> %v1)
@@ -204,61 +164,25 @@ define void @masked_store_factor2_64bit(ptr %ptr, <2 x i32> %v0, <2 x i32> %v1,
define void @masked_store_factor2_128bit(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i1> %mask) {
; CHECK-COMPAT-LABEL: masked_store_factor2_128bit:
; CHECK-COMPAT: // %bb.0:
-; CHECK-COMPAT-NEXT: adrp x8, .LCPI7_0
; CHECK-COMPAT-NEXT: // kill: def $d2 killed $d2 def $z2
-; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 def $z1
-; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 def $z0
-; CHECK-COMPAT-NEXT: mov z4.s, z1.s[3]
-; CHECK-COMPAT-NEXT: mov z5.s, z0.s[3]
-; CHECK-COMPAT-NEXT: ldr q3, [x8, :lo12:.LCPI7_0]
-; CHECK-COMPAT-NEXT: mov z6.s, z1.s[2]
-; CHECK-COMPAT-NEXT: mov z7.s, z0.s[2]
; CHECK-COMPAT-NEXT: ptrue p0.s, vl4
-; CHECK-COMPAT-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-COMPAT-NEXT: mov x8, #4 // =0x4
-; CHECK-COMPAT-NEXT: tbl z3.h, { z2.h }, z3.h
-; CHECK-COMPAT-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-COMPAT-NEXT: zip1 z4.s, z5.s, z4.s
-; CHECK-COMPAT-NEXT: zip1 z5.s, z7.s, z6.s
+; CHECK-COMPAT-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: uunpklo z2.s, z2.h
-; CHECK-COMPAT-NEXT: uunpklo z3.s, z3.h
+; CHECK-COMPAT-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
; CHECK-COMPAT-NEXT: lsl z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: lsl z3.s, z3.s, #31
; CHECK-COMPAT-NEXT: asr z2.s, z2.s, #31
-; CHECK-COMPAT-NEXT: asr z3.s, z3.s, #31
-; CHECK-COMPAT-NEXT: cmpne p2.s, p0/z, z2.s, #0
-; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z3.s, #0
-; CHECK-COMPAT-NEXT: zip1 z3.d, z5.d, z4.d
-; CHECK-COMPAT-NEXT: st1w { z3.s }, p1, [x0, x8, lsl #2]
-; CHECK-COMPAT-NEXT: st1w { z0.s }, p2, [x0]
+; CHECK-COMPAT-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-COMPAT-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-COMPAT-NEXT: ret
;
; CHECK-STREAMING-LABEL: masked_store_factor2_128bit:
; CHECK-STREAMING: // %bb.0:
-; CHECK-STREAMING-NEXT: adrp x8, .LCPI7_0
-; CHECK-STREAMING-NEXT: mov z4.s, z1.s[3]
-; CHECK-STREAMING-NEXT: mov z5.s, z0.s[3]
-; CHECK-STREAMING-NEXT: ldr q3, [x8, :lo12:.LCPI7_0]
-; CHECK-STREAMING-NEXT: mov z6.s, z1.s[2]
-; CHECK-STREAMING-NEXT: mov z7.s, z0.s[2]
-; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
-; CHECK-STREAMING-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-STREAMING-NEXT: mov x8, #4 // =0x4
-; CHECK-STREAMING-NEXT: tbl z3.h, { z2.h }, z3.h
-; CHECK-STREAMING-NEXT: zip1 z2.h, z2.h, z2.h
-; CHECK-STREAMING-NEXT: zip1 z4.s, z5.s, z4.s
-; CHECK-STREAMING-NEXT: zip1 z5.s, z7.s, z6.s
; CHECK-STREAMING-NEXT: uunpklo z2.s, z2.h
-; CHECK-STREAMING-NEXT: uunpklo z3.s, z3.h
+; CHECK-STREAMING-NEXT: ptrue p0.s, vl4
; CHECK-STREAMING-NEXT: lsl z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: lsl z3.s, z3.s, #31
; CHECK-STREAMING-NEXT: asr z2.s, z2.s, #31
-; CHECK-STREAMING-NEXT: asr z3.s, z3.s, #31
-; CHECK-STREAMING-NEXT: cmpne p2.s, p0/z, z2.s, #0
-; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z3.s, #0
-; CHECK-STREAMING-NEXT: zip1 z3.d, z5.d, z4.d
-; CHECK-STREAMING-NEXT: st1w { z3.s }, p1, [x0, x8, lsl #2]
-; CHECK-STREAMING-NEXT: st1w { z0.s }, p2, [x0]
+; CHECK-STREAMING-NEXT: cmpne p1.s, p0/z, z2.s, #0
+; CHECK-STREAMING-NEXT: st2w { z0.s, z1.s }, p1, [x0]
; CHECK-STREAMING-NEXT: ret
%interleaved = call <8 x i32> @llvm.vector.interleave2.v8i32(
<4 x i32> %v0, <4 x i32> %v1)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
index 133bac768d59e2..70f02aeb91c6f3 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
@@ -266,11 +266,9 @@ define void @alloc_v4i8_intrinsic(ptr %st_ptr) nounwind {
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x20]
; CHECK-NEXT: ptrue p0.s, vl2
-; CHECK-NEXT: mov z1.h, z0.h[2]
-; CHECK-NEXT: fmov w8, s0
-; CHECK-NEXT: fmov w9, s1
-; CHECK-NEXT: mov z0.s, w8
-; CHECK-NEXT: mov z1.s, w9
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: movprfx z1, z0
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
; CHECK-NEXT: st1b { z0.s }, p0, [x19]
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
index 986b776a9a5869..3d7e5eec7be63b 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
@@ -194,7 +194,9 @@ define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x
; CHECK-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.s, s0
-; CHECK-NEXT: stp q0, q0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: hang_when_merging_stores_after_legalisation_intrinsic:
@@ -219,15 +221,8 @@ define void @hang_when_merging_stores_after_legalisation_intrinsic(ptr %a, <2 x
define void @interleave_store_without_splat_intrinsic(ptr %a, <4 x i32> %v1, <4 x i32> %v2) {
; CHECK-LABEL: interleave_store_without_splat_intrinsic:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z2.s, z1.s[3]
-; CHECK-NEXT: mov z3.s, z0.s[3]
-; CHECK-NEXT: mov z4.s, z1.s[2]
-; CHECK-NEXT: mov z5.s, z0.s[2]
-; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
-; CHECK-NEXT: zip1 z2.s, z3.s, z2.s
-; CHECK-NEXT: zip1 z3.s, z5.s, z4.s
-; CHECK-NEXT: zip1 z1.d, z3.d, z2.d
-; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: interleave_store_without_splat_intrinsic:
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
index 98115a427b4ad1..5b3463fc0d1454 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
@@ -898,14 +898,14 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; SVE-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
; SVE-NEXT: .cfi_offset w29, -16
; SVE-NEXT: ptrue p0.d
-; SVE-NEXT: str z5, [sp, #5, mul vl]
-; SVE-NEXT: str z4, [sp, #4, mul vl]
-; SVE-NEXT: str z3, [sp, #3, mul vl]
-; SVE-NEXT: str z2, [sp, #2, mul vl]
-; SVE-NEXT: str z1, [sp, #1, mul vl]
-; SVE-NEXT: str z0, [sp]
-; SVE-NEXT: ld3d { z5.d - z7.d }, p0/z, [sp, #3, mul vl]
-; SVE-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp]
+; SVE-NEXT: str z5, [sp, #2, mul vl]
+; SVE-NEXT: str z4, [sp, #1, mul vl]
+; SVE-NEXT: str z3, [sp]
+; SVE-NEXT: str z2, [sp, #5, mul vl]
+; SVE-NEXT: str z1, [sp, #4, mul vl]
+; SVE-NEXT: str z0, [sp, #3, mul vl]
+; SVE-NEXT: ld3d { z5.d - z7.d }, p0/z, [sp]
+; SVE-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp, #3, mul vl]
; SVE-NEXT: uzp1 z0.d, z24.d, z5.d
; SVE-NEXT: uzp1 z1.d, z25.d, z6.d
; SVE-NEXT: uzp1 z2.d, z26.d, z7.d
@@ -923,14 +923,14 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; SME2-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x30, 0x1e, 0x22 // sp + 16 + 48 * VG
; SME2-NEXT: .cfi_offset w29, -16
; SME2-NEXT: ptrue p0.d
-; SME2-NEXT: str z5, [sp, #5, mul vl]
-; SME2-NEXT: str z4, [sp, #4, mul vl]
-; SME2-NEXT: str z3, [sp, #3, mul vl]
-; SME2-NEXT: str z2, [sp, #2, mul vl]
-; SME2-NEXT: str z1, [sp, #1, mul vl]
-; SME2-NEXT: str z0, [sp]
-; SME2-NEXT: ld3d { z3.d - z5.d }, p0/z, [sp, #3, mul vl]
-; SME2-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp]
+; SME2-NEXT: str z5, [sp, #2, mul vl]
+; SME2-NEXT: str z4, [sp, #1, mul vl]
+; SME2-NEXT: str z3, [sp]
+; SME2-NEXT: str z2, [sp, #5, mul vl]
+; SME2-NEXT: str z1, [sp, #4, mul vl]
+; SME2-NEXT: str z0, [sp, #3, mul vl]
+; SME2-NEXT: ld3d { z3.d - z5.d }, p0/z, [sp]
+; SME2-NEXT: ld3d { z24.d - z26.d }, p0/z, [sp, #3, mul vl]
; SME2-NEXT: uzp { z2.d, z3.d }, z24.d, z3.d
; SME2-NEXT: uzp { z6.d, z7.d }, z25.d, z4.d
; SME2-NEXT: uzp { z4.d, z5.d }, z26.d, z5.d
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll
index d67488981bbcd7..f0b3760dc30e17 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-interleave-widen.ll
@@ -206,16 +206,16 @@ define void @interleave6_v3fp32(ptr %dst, <vscale x 3 x float> %a, <vscale x 3
; CHECK-NEXT: addvl x9, sp, #31
; CHECK-NEXT: rdvl x10, #4
; CHECK-NEXT: ptrue p1.d
-; CHECK-NEXT: st3w { z24.s - z26.s }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ldr z1, [sp, #5, mul vl]
-; CHECK-NEXT: ldr z2, [sp, #4, mul vl]
-; CHECK-NEXT: ldr z0, [sp, #3, mul vl]
-; CHECK-NEXT: st3w { z5.s - z7.s }, p0, [sp]
+; CHECK-NEXT: st3w { z24.s - z26.s }, p0, [sp]
+; CHECK-NEXT: ldr z1, [sp, #2, mul vl]
+; CHECK-NEXT: ldr z2, [sp, #1, mul vl]
+; CHECK-NEXT: ldr z0, [sp]
+; CHECK-NEXT: st3w { z5.s - z7.s }, p0, [sp, #3, mul vl]
; CHECK-NEXT: whilelo p0.s, xzr, x8
; CHECK-NEXT: cntw x8, all, mul #3
-; CHECK-NEXT: ldr z3, [sp, #2, mul vl]
-; CHECK-NEXT: ldr z4, [sp, #1, mul vl]
-; CHECK-NEXT: ldr z5, [sp]
+; CHECK-NEXT: ldr z3, [sp, #5, mul vl]
+; CHECK-NEXT: ldr z4, [sp, #4, mul vl]
+; CHECK-NEXT: ldr z5, [sp, #3, mul vl]
; CHECK-NEXT: add x9, x9, x8
; CHECK-NEXT: str z1, [sp, #36, mul vl]
; CHECK-NEXT: str z2, [sp, #35, mul vl]
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
index 32689d88c09ea7..a5244f1879f579 100644
--- a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll
@@ -957,14 +957,14 @@ define <vscale x 12 x i64> @interleave6_nxv12i64(<vscale x 2 x i64> %vec0, <vsca
; SVE-NEXT: zip2 z1.d, z1.d, z4.d
; SVE-NEXT: zip2 z0.d, z0.d, z3.d
; SVE-NEXT: ptrue p0.d
-; SVE-NEXT: st3d { z24.d - z26.d }, p0, [sp]
-; SVE-NEXT: st3d { z0.d - z2.d }, p0, [sp, #3, mul vl]
-; SVE-NEXT: ldr z0, [sp]
-; SVE-NEXT: ldr z1, [sp, #1, mul vl]
-; SVE-NEXT: ldr z2, [sp, #2, mul vl]
-; SVE-NEXT: ldr z3, [sp, #3, mul vl]
-; SVE-NEXT: ldr z4, [sp, #4, mul vl]
-; SVE-NEXT: ldr z5, [sp, #5, mul vl]
+; SVE-NEXT: st3d { z24.d - z26.d }, p0, [sp, #3, mul vl]
+; SVE-NEXT: st3d { z0.d - z2.d }, p0, [sp]
+; SVE-NEXT: ldr z0, [sp, #3, mul vl]
+; SVE-NEXT: ldr z1, [sp, #4, mul vl]
+; SVE-NEXT: ldr z2, [sp, #5, mul vl]
+; SVE-NEXT: ldr z3, [sp]
+; SVE-NEXT: ldr z4, [sp, #1, mul vl]
+; SVE-NEXT: ldr z5, [sp, #2, mul vl]
; SVE-NEXT: addvl sp, sp, #6
; SVE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; SVE-NEXT: ret
@@ -983,14 +983,14 @@ define <vscale x 12 x i64> @interleave6_nxv12i64(<vscale x 2 x i64> %vec0, <vsca
; SME2-NEXT: mov z2.d, z25.d
; SME2-NEXT: mov z3.d, z7.d
; SME2-NEXT: ptrue p0.d
-; SME2-NEXT: st3d { z4.d - z6.d }, p0, [sp]
-; SME2-NEXT: ldr z0, [sp]
-; SME2-NEXT: st3d { z1.d - z3.d }, p0, [sp, #3, mul vl]
-; SME2-NEXT: ldr z1, [sp, #1, mul vl]
-; SME2-NEXT: ldr z2, [sp, #2, mul vl]
-; SME2-NEXT: ldr z3, [sp, #3, mul vl]
-; SME2-NEXT: ldr z4, [sp, #4, mul vl]
-; SME2-NEXT: ldr z5, [sp, #5, mul vl]
+; SME2-NEXT: st3d { z4.d - z6.d }, p0, [sp, #3, mul vl]
+; SME2-NEXT: ldr z0, [sp, #3, mul vl]
+; SME2-NEXT: st3d { z1.d - z3.d }, p0, [sp]
+; SME2-NEXT: ldr z1, [sp, #4, mul vl]
+; SME2-NEXT: ldr z2, [sp, #5, mul vl]
+; SME2-NEXT: ldr z3, [sp]
+; SME2-NEXT: ldr z4, [sp, #1, mul vl]
+; SME2-NEXT: ldr z5, [sp, #2, mul vl]
; SME2-NEXT: addvl sp, sp, #6
; SME2-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; SME2-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/tbl-loops.ll b/llvm/test/CodeGen/AArch64/tbl-loops.ll
index 4870243e0e4a43..731392f936eeb9 100644
--- a/llvm/test/CodeGen/AArch64/tbl-loops.ll
+++ b/llvm/test/CodeGen/AArch64/tbl-loops.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
; RUN: llc --lower-interleaved-accesses=false -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
@@ -1064,159 +1064,82 @@ for.body: ; preds = %for.body.preheader5
define void @loop2_intrinsic(ptr noalias nocapture noundef writeonly %dst, ptr nocapture noundef readonly %data, i32 noundef %width) {
-; CHECK-IAENABLED-LABEL: loop2_intrinsic:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: subs w8, w2, #1
-; CHECK-IAENABLED-NEXT: b.lt .LBB4_6
-; CHECK-IAENABLED-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-IAENABLED-NEXT: cmp w8, #2
-; CHECK-IAENABLED-NEXT: b.ls .LBB4_3
-; CHECK-IAENABLED-NEXT: // %bb.2: // %vector.memcheck
-; CHECK-IAENABLED-NEXT: ubfiz x9, x8, #1, #32
-; CHECK-IAENABLED-NEXT: add x9, x9, #2
-; CHECK-IAENABLED-NEXT: add x10, x0, x9
-; CHECK-IAENABLED-NEXT: add x9, x1, x9, lsl #2
-; CHECK-IAENABLED-NEXT: cmp x10, x1
-; CHECK-IAENABLED-NEXT: ccmp x9, x0, #0, hi
-; CHECK-IAENABLED-NEXT: b.ls .LBB4_7
-; CHECK-IAENABLED-NEXT: .LBB4_3:
-; CHECK-IAENABLED-NEXT: mov w10, wzr
-; CHECK-IAENABLED-NEXT: mov x8, x1
-; CHECK-IAENABLED-NEXT: mov x9, x0
-; CHECK-IAENABLED-NEXT: .LBB4_4: // %for.body.preheader1
-; CHECK-IAENABLED-NEXT: movi d0, #0000000000000000
-; CHECK-IAENABLED-NEXT: mov w11, #1132396544 // =0x437f0000
-; CHECK-IAENABLED-NEXT: sub w10, w2, w10
-; CHECK-IAENABLED-NEXT: fmov s1, w11
-; CHECK-IAENABLED-NEXT: .LBB4_5: // %for.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ldp s2, s3, [x8], #8
-; CHECK-IAENABLED-NEXT: fcmp s2, s1
-; CHECK-IAENABLED-NEXT: fcsel s4, s1, s2, gt
-; CHECK-IAENABLED-NEXT: fcmp s2, #0.0
-; CHECK-IAENABLED-NEXT: fcsel s2, s0, s4, mi
-; CHECK-IAENABLED-NEXT: fcmp s3, s1
-; CHECK-IAENABLED-NEXT: fcsel s4, s1, s3, gt
-; CHECK-IAENABLED-NEXT: fcmp s3, #0.0
-; CHECK-IAENABLED-NEXT: fcvtzs s2, s2
-; CHECK-IAENABLED-NEXT: fcsel s3, s0, s4, mi
-; CHECK-IAENABLED-NEXT: subs w10, w10, #1
-; CHECK-IAENABLED-NEXT: str b2, [x9]
-; CHECK-IAENABLED-NEXT: fcvtzs s3, s3
-; CHECK-IAENABLED-NEXT: stur b3, [x9, #1]
-; CHECK-IAENABLED-NEXT: add x9, x9, #2
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_5
-; CHECK-IAENABLED-NEXT: .LBB4_6: // %for.cond.cleanup
-; CHECK-IAENABLED-NEXT: ret
-; CHECK-IAENABLED-NEXT: .LBB4_7: // %vector.ph
-; CHECK-IAENABLED-NEXT: add x11, x8, #1
-; CHECK-IAENABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IAENABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IAENABLED-NEXT: dup v0.4s, w8
-; CHECK-IAENABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IAENABLED-NEXT: add x8, x1, x10, lsl #3
-; CHECK-IAENABLED-NEXT: add x9, x0, x10, lsl #1
-; CHECK-IAENABLED-NEXT: .LBB4_8: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld2 { v1.4s, v2.4s }, [x1], #32
-; CHECK-IAENABLED-NEXT: subs x12, x12, #4
-; CHECK-IAENABLED-NEXT: fcmgt v3.4s, v1.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fcmgt v4.4s, v2.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fcmlt v5.4s, v1.4s, #0.0
-; CHECK-IAENABLED-NEXT: bsl v3.16b, v0.16b, v1.16b
-; CHECK-IAENABLED-NEXT: bsl v4.16b, v0.16b, v2.16b
-; CHECK-IAENABLED-NEXT: fcmlt v1.4s, v2.4s, #0.0
-; CHECK-IAENABLED-NEXT: bic v2.16b, v3.16b, v5.16b
-; CHECK-IAENABLED-NEXT: bic v1.16b, v4.16b, v1.16b
-; CHECK-IAENABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: xtn v2.4h, v2.4s
-; CHECK-IAENABLED-NEXT: xtn v1.4h, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v1.8b, v2.8b, v1.8b
-; CHECK-IAENABLED-NEXT: str d1, [x0], #8
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_8
-; CHECK-IAENABLED-NEXT: // %bb.9: // %middle.block
-; CHECK-IAENABLED-NEXT: cmp x11, x10
-; CHECK-IAENABLED-NEXT: b.ne .LBB4_4
-; CHECK-IAENABLED-NEXT: b .LBB4_6
-;
-; CHECK-IADISABLED-LABEL: loop2_intrinsic:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: subs w8, w2, #1
-; CHECK-IADISABLED-NEXT: b.lt .LBB4_6
-; CHECK-IADISABLED-NEXT: // %bb.1: // %for.body.preheader
-; CHECK-IADISABLED-NEXT: cmp w8, #2
-; CHECK-IADISABLED-NEXT: b.ls .LBB4_3
-; CHECK-IADISABLED-NEXT: // %bb.2: // %vector.memcheck
-; CHECK-IADISABLED-NEXT: ubfiz x9, x8, #1, #32
-; CHECK-IADISABLED-NEXT: add x9, x9, #2
-; CHECK-IADISABLED-NEXT: add x10, x0, x9
-; CHECK-IADISABLED-NEXT: add x9, x1, x9, lsl #2
-; CHECK-IADISABLED-NEXT: cmp x10, x1
-; CHECK-IADISABLED-NEXT: ccmp x9, x0, #0, hi
-; CHECK-IADISABLED-NEXT: b.ls .LBB4_7
-; CHECK-IADISABLED-NEXT: .LBB4_3:
-; CHECK-IADISABLED-NEXT: mov w10, wzr
-; CHECK-IADISABLED-NEXT: mov x8, x1
-; CHECK-IADISABLED-NEXT: mov x9, x0
-; CHECK-IADISABLED-NEXT: .LBB4_4: // %for.body.preheader1
-; CHECK-IADISABLED-NEXT: movi d0, #0000000000000000
-; CHECK-IADISABLED-NEXT: mov w11, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: sub w10, w2, w10
-; CHECK-IADISABLED-NEXT: fmov s1, w11
-; CHECK-IADISABLED-NEXT: .LBB4_5: // %for.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp s2, s3, [x8], #8
-; CHECK-IADISABLED-NEXT: fcmp s2, s1
-; CHECK-IADISABLED-NEXT: fcsel s4, s1, s2, gt
-; CHECK-IADISABLED-NEXT: fcmp s2, #0.0
-; CHECK-IADISABLED-NEXT: fcsel s2, s0, s4, mi
-; CHECK-IADISABLED-NEXT: fcmp s3, s1
-; CHECK-IADISABLED-NEXT: fcsel s4, s1, s3, gt
-; CHECK-IADISABLED-NEXT: fcmp s3, #0.0
-; CHECK-IADISABLED-NEXT: fcvtzs s2, s2
-; CHECK-IADISABLED-NEXT: fcsel s3, s0, s4, mi
-; CHECK-IADISABLED-NEXT: subs w10, w10, #1
-; CHECK-IADISABLED-NEXT: str b2, [x9]
-; CHECK-IADISABLED-NEXT: fcvtzs s3, s3
-; CHECK-IADISABLED-NEXT: stur b3, [x9, #1]
-; CHECK-IADISABLED-NEXT: add x9, x9, #2
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_5
-; CHECK-IADISABLED-NEXT: .LBB4_6: // %for.cond.cleanup
-; CHECK-IADISABLED-NEXT: ret
-; CHECK-IADISABLED-NEXT: .LBB4_7: // %vector.ph
-; CHECK-IADISABLED-NEXT: add x11, x8, #1
-; CHECK-IADISABLED-NEXT: mov w8, #1132396544 // =0x437f0000
-; CHECK-IADISABLED-NEXT: and x10, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: dup v0.4s, w8
-; CHECK-IADISABLED-NEXT: and x12, x11, #0x1fffffffc
-; CHECK-IADISABLED-NEXT: add x8, x1, x10, lsl #3
-; CHECK-IADISABLED-NEXT: add x9, x0, x10, lsl #1
-; CHECK-IADISABLED-NEXT: .LBB4_8: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q2, q1, [x1], #32
-; CHECK-IADISABLED-NEXT: subs x12, x12, #4
-; CHECK-IADISABLED-NEXT: uzp1 v3.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fcmgt v2.4s, v3.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fcmgt v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: bsl v2.16b, v0.16b, v3.16b
-; CHECK-IADISABLED-NEXT: fcmlt v3.4s, v3.4s, #0.0
-; CHECK-IADISABLED-NEXT: bsl v4.16b, v0.16b, v1.16b
-; CHECK-IADISABLED-NEXT: fcmlt v1.4s, v1.4s, #0.0
-; CHECK-IADISABLED-NEXT: bic v2.16b, v2.16b, v3.16b
-; CHECK-IADISABLED-NEXT: bic v1.16b, v4.16b, v1.16b
-; CHECK-IADISABLED-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: xtn v2.4h, v2.4s
-; CHECK-IADISABLED-NEXT: xtn v1.4h, v1.4s
-; CHECK-IADISABLED-NEXT: trn1 v1.8b, v2.8b, v1.8b
-; CHECK-IADISABLED-NEXT: str d1, [x0], #8
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_8
-; CHECK-IADISABLED-NEXT: // %bb.9: // %middle.block
-; CHECK-IADISABLED-NEXT: cmp x11, x10
-; CHECK-IADISABLED-NEXT: b.ne .LBB4_4
-; CHECK-IADISABLED-NEXT: b .LBB4_6
+; CHECK-LABEL: loop2_intrinsic:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: subs w8, w2, #1
+; CHECK-NEXT: b.lt .LBB4_6
+; CHECK-NEXT: // %bb.1: // %for.body.preheader
+; CHECK-NEXT: cmp w8, #2
+; CHECK-NEXT: b.ls .LBB4_3
+; CHECK-NEXT: // %bb.2: // %vector.memcheck
+; CHECK-NEXT: ubfiz x9, x8, #1, #32
+; CHECK-NEXT: add x9, x9, #2
+; CHECK-NEXT: add x10, x0, x9
+; CHECK-NEXT: add x9, x1, x9, lsl #2
+; CHECK-NEXT: cmp x10, x1
+; CHECK-NEXT: ccmp x9, x0, #0, hi
+; CHECK-NEXT: b.ls .LBB4_7
+; CHECK-NEXT: .LBB4_3:
+; CHECK-NEXT: mov w10, wzr
+; CHECK-NEXT: mov x8, x1
+; CHECK-NEXT: mov x9, x0
+; CHECK-NEXT: .LBB4_4: // %for.body.preheader1
+; CHECK-NEXT: movi d0, #0000000000000000
+; CHECK-NEXT: mov w11, #1132396544 // =0x437f0000
+; CHECK-NEXT: sub w10, w2, w10
+; CHECK-NEXT: fmov s1, w11
+; CHECK-NEXT: .LBB4_5: // %for.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldp s2, s3, [x8], #8
+; CHECK-NEXT: fcmp s2, s1
+; CHECK-NEXT: fcsel s4, s1, s2, gt
+; CHECK-NEXT: fcmp s2, #0.0
+; CHECK-NEXT: fcsel s2, s0, s4, mi
+; CHECK-NEXT: fcmp s3, s1
+; CHECK-NEXT: fcsel s4, s1, s3, gt
+; CHECK-NEXT: fcmp s3, #0.0
+; CHECK-NEXT: fcvtzs s2, s2
+; CHECK-NEXT: fcsel s3, s0, s4, mi
+; CHECK-NEXT: subs w10, w10, #1
+; CHECK-NEXT: str b2, [x9]
+; CHECK-NEXT: fcvtzs s3, s3
+; CHECK-NEXT: stur b3, [x9, #1]
+; CHECK-NEXT: add x9, x9, #2
+; CHECK-NEXT: b.ne .LBB4_5
+; CHECK-NEXT: .LBB4_6: // %for.cond.cleanup
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB4_7: // %vector.ph
+; CHECK-NEXT: add x11, x8, #1
+; CHECK-NEXT: mov w8, #1132396544 // =0x437f0000
+; CHECK-NEXT: and x10, x11, #0x1fffffffc
+; CHECK-NEXT: dup v0.4s, w8
+; CHECK-NEXT: and x12, x11, #0x1fffffffc
+; CHECK-NEXT: add x8, x1, x10, lsl #3
+; CHECK-NEXT: add x9, x0, x10, lsl #1
+; CHECK-NEXT: .LBB4_8: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld2 { v1.4s, v2.4s }, [x1], #32
+; CHECK-NEXT: subs x12, x12, #4
+; CHECK-NEXT: fcmgt v3.4s, v1.4s, v0.4s
+; CHECK-NEXT: fcmgt v4.4s, v2.4s, v0.4s
+; CHECK-NEXT: fcmlt v5.4s, v1.4s, #0.0
+; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b
+; CHECK-NEXT: fcmlt v1.4s, v2.4s, #0.0
+; CHECK-NEXT: bic v2.16b, v3.16b, v5.16b
+; CHECK-NEXT: bic v1.16b, v4.16b, v1.16b
+; CHECK-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: xtn v2.4h, v2.4s
+; CHECK-NEXT: xtn v1.4h, v1.4s
+; CHECK-NEXT: zip1 v1.8h, v2.8h, v1.8h
+; CHECK-NEXT: xtn v1.8b, v1.8h
+; CHECK-NEXT: str d1, [x0], #8
+; CHECK-NEXT: b.ne .LBB4_8
+; CHECK-NEXT: // %bb.9: // %middle.block
+; CHECK-NEXT: cmp x11, x10
+; CHECK-NEXT: b.ne .LBB4_4
+; CHECK-NEXT: b .LBB4_6
entry:
%cmp19 = icmp sgt i32 %width, 0
br i1 %cmp19, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll b/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
index 6b2800fd2a944a..976da3ce85f808 100644
--- a/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/AArch64/vector-deinterleave-load.ll
@@ -3,31 +3,17 @@
; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
define void @aarch64_vector_deinterleave_idx_ld2(ptr %ptr, i64 %idx) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_deinterleave_idx_ld2:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: lsl x8, x1, #2
-; CHECK-IAENABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; CHECK-IAENABLED-NEXT: add x8, x8, #16
-; CHECK-IAENABLED-NEXT: add x10, x0, x9
-; CHECK-IAENABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; CHECK-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x10]
-; CHECK-IAENABLED-NEXT: str q0, [x0, x9]
-; CHECK-IAENABLED-NEXT: str q1, [x0, x8]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_deinterleave_idx_ld2:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: lsl x8, x1, #2
-; CHECK-IADISABLED-NEXT: and x9, x8, #0xfffffffffffffff0
-; CHECK-IADISABLED-NEXT: add x8, x8, #16
-; CHECK-IADISABLED-NEXT: add x9, x0, x9
-; CHECK-IADISABLED-NEXT: and x8, x8, #0xfffffffffffffff0
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: str q2, [x9]
-; CHECK-IADISABLED-NEXT: str q0, [x0, x8]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_deinterleave_idx_ld2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsl x8, x1, #2
+; CHECK-NEXT: and x9, x8, #0xfffffffffffffff0
+; CHECK-NEXT: add x8, x8, #16
+; CHECK-NEXT: add x10, x0, x9
+; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x10]
+; CHECK-NEXT: str q0, [x0, x9]
+; CHECK-NEXT: str q1, [x0, x8]
+; CHECK-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%a1 = add i64 %idx, 4
@@ -133,25 +119,13 @@ entry:
}
define void @aarch64_vector_deinterleave_v8f64_load(ptr %src, ptr %dst0, ptr %dst1) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_deinterleave_v8f64_load:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: ld2 { v0.2d, v1.2d }, [x0], #32
-; CHECK-IAENABLED-NEXT: ld2 { v2.2d, v3.2d }, [x0]
-; CHECK-IAENABLED-NEXT: stp q0, q2, [x1]
-; CHECK-IAENABLED-NEXT: stp q1, q3, [x2]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_deinterleave_v8f64_load:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0, #32]
-; CHECK-IADISABLED-NEXT: ldp q3, q2, [x0]
-; CHECK-IADISABLED-NEXT: zip1 v4.2d, v1.2d, v0.2d
-; CHECK-IADISABLED-NEXT: zip2 v0.2d, v1.2d, v0.2d
-; CHECK-IADISABLED-NEXT: zip1 v5.2d, v3.2d, v2.2d
-; CHECK-IADISABLED-NEXT: zip2 v1.2d, v3.2d, v2.2d
-; CHECK-IADISABLED-NEXT: stp q5, q4, [x1]
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x2]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_deinterleave_v8f64_load:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ld2 { v0.2d, v1.2d }, [x0], #32
+; CHECK-NEXT: ld2 { v2.2d, v3.2d }, [x0]
+; CHECK-NEXT: stp q0, q2, [x1]
+; CHECK-NEXT: stp q1, q3, [x2]
+; CHECK-NEXT: ret
entry:
%wide.vec = load <8 x double>, ptr %src, align 8
%strided.vec = tail call { <4 x double>, <4 x double> } @llvm.vector.deinterleave2.v8f64(<8 x double> %wide.vec)
@@ -206,3 +180,6 @@ entry:
store <4 x double> %stream3, ptr %dst3, align 8
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/vector-interleave-store.ll b/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
index e720275dc242ec..71b034c902e221 100644
--- a/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/AArch64/vector-interleave-store.ll
@@ -3,23 +3,14 @@
; RUN: llc -mtriple=aarch64-linux-gnu -lower-interleaved-accesses=false < %s | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
define void @aarch64_vector_interleave_idx_st2(ptr %ptr, i64 %idx, <4 x float> %v0, <4 x float> %v1) {
-; CHECK-IAENABLED-LABEL: aarch64_vector_interleave_idx_st2:
-; CHECK-IAENABLED: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: lsr x8, x1, #2
-; CHECK-IAENABLED-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
-; CHECK-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-IAENABLED-NEXT: add x8, x0, x8, lsl #4
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x8]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: aarch64_vector_interleave_idx_st2:
-; CHECK-IADISABLED: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: lsr x8, x1, #2
-; CHECK-IADISABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: zip1 v0.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: add x8, x0, x8, lsl #4
-; CHECK-IADISABLED-NEXT: stp q0, q2, [x8]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: aarch64_vector_interleave_idx_st2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: lsr x8, x1, #2
+; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: add x8, x0, x8, lsl #4
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x8]
+; CHECK-NEXT: ret
entry:
%idx1 = lshr i64 %idx, 2
%gep1 = getelementptr inbounds <4 x float>, ptr %ptr, i64 %idx1
@@ -69,25 +60,13 @@ entry:
}
define void @wide_vector_interleave_st2(ptr %input0, ptr %input1, ptr %output) {
-; CHECK-IAENABLED-LABEL: wide_vector_interleave_st2:
-; CHECK-IAENABLED: // %bb.0:
-; CHECK-IAENABLED-NEXT: ldp q0, q2, [x0]
-; CHECK-IAENABLED-NEXT: ldp q1, q3, [x1]
-; CHECK-IAENABLED-NEXT: st2 { v0.4s, v1.4s }, [x2], #32
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x2]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: wide_vector_interleave_st2:
-; CHECK-IADISABLED: // %bb.0:
-; CHECK-IADISABLED-NEXT: ldp q3, q0, [x1]
-; CHECK-IADISABLED-NEXT: ldp q2, q1, [x0]
-; CHECK-IADISABLED-NEXT: zip1 v4.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v2.4s, v2.4s, v3.4s
-; CHECK-IADISABLED-NEXT: stp q4, q0, [x2, #32]
-; CHECK-IADISABLED-NEXT: stp q1, q2, [x2]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: wide_vector_interleave_st2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q2, [x0]
+; CHECK-NEXT: ldp q1, q3, [x1]
+; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x2], #32
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x2]
+; CHECK-NEXT: ret
%v0 = load <8 x i32>, ptr %input0, align 4
%v1 = load <8 x i32>, ptr %input1, align 4
%interleaved.vec = tail call <16 x i32> @llvm.vector.interleave2.v16i32(<8 x i32> %v0, <8 x i32> %v1)
@@ -361,29 +340,27 @@ define void @wide_vector_interleave_st3_i16_dreg(ptr %output, ptr %input0, ptr %
; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: ldr q0, [x1]
; CHECK-NEXT: ldr d3, [x1, #16]
-; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x8, sp, #48
; CHECK-NEXT: ldr q1, [x2]
; CHECK-NEXT: ldr d4, [x2, #16]
; CHECK-NEXT: ldr q2, [x3]
; CHECK-NEXT: ldr d5, [x3, #16]
; CHECK-NEXT: st3 { v0.8h, v1.8h, v2.8h }, [x8]
-; CHECK-NEXT: add x8, sp, #48
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: st3 { v3.8h, v4.8h, v5.8h }, [x8]
-; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ldr q0, [sp, #80]
+; CHECK-NEXT: ldr x8, [sp, #16]
+; CHECK-NEXT: ldr q4, [sp]
; CHECK-NEXT: dup v1.2d, v0.d[1]
; CHECK-NEXT: str d1, [sp, #144]
-; CHECK-NEXT: ldr q1, [sp, #64]
+; CHECK-NEXT: ldp q2, q1, [sp, #48]
; CHECK-NEXT: ldr q3, [sp, #144]
-; CHECK-NEXT: str d1, [sp, #112]
-; CHECK-NEXT: ldp q2, q1, [sp]
+; CHECK-NEXT: str x8, [x0, #64]
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: ext v0.16b, v0.16b, v3.16b, #8
-; CHECK-NEXT: ldr q3, [sp, #48]
; CHECK-NEXT: stp q2, q1, [x0]
-; CHECK-NEXT: stp q0, q3, [x0, #32]
-; CHECK-NEXT: ldr q0, [sp, #112]
-; CHECK-NEXT: str d0, [x0, #64]
+; CHECK-NEXT: stp q0, q4, [x0, #32]
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: ret
%v0 = load <12 x i16>, ptr %input0, align 2
@@ -452,29 +429,27 @@ define void @wide_vector_interleave_st3_i8_dreg(ptr %output, ptr %input0, ptr %i
; CHECK-NEXT: .cfi_def_cfa_offset 192
; CHECK-NEXT: ldr q0, [x1]
; CHECK-NEXT: ldr d3, [x1, #16]
-; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: add x8, sp, #48
; CHECK-NEXT: ldr q1, [x2]
; CHECK-NEXT: ldr d4, [x2, #16]
; CHECK-NEXT: ldr q2, [x3]
; CHECK-NEXT: ldr d5, [x3, #16]
; CHECK-NEXT: st3 { v0.16b, v1.16b, v2.16b }, [x8]
-; CHECK-NEXT: add x8, sp, #48
+; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: st3 { v3.16b, v4.16b, v5.16b }, [x8]
-; CHECK-NEXT: ldr q0, [sp, #32]
+; CHECK-NEXT: ldr q0, [sp, #80]
+; CHECK-NEXT: ldr x8, [sp, #16]
+; CHECK-NEXT: ldr q4, [sp]
; CHECK-NEXT: dup v1.2d, v0.d[1]
; CHECK-NEXT: str d1, [sp, #144]
-; CHECK-NEXT: ldr q1, [sp, #64]
+; CHECK-NEXT: ldp q2, q1, [sp, #48]
; CHECK-NEXT: ldr q3, [sp, #144]
-; CHECK-NEXT: str d1, [sp, #112]
-; CHECK-NEXT: ldp q2, q1, [sp]
+; CHECK-NEXT: str x8, [x0, #64]
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
; CHECK-NEXT: mov v1.d[1], v0.d[0]
; CHECK-NEXT: ext v0.16b, v0.16b, v3.16b, #8
-; CHECK-NEXT: ldr q3, [sp, #48]
; CHECK-NEXT: stp q2, q1, [x0]
-; CHECK-NEXT: stp q0, q3, [x0, #32]
-; CHECK-NEXT: ldr q0, [sp, #112]
-; CHECK-NEXT: str d0, [x0, #64]
+; CHECK-NEXT: stp q0, q4, [x0, #32]
; CHECK-NEXT: add sp, sp, #192
; CHECK-NEXT: ret
%v0 = load <24 x i8>, ptr %input0, align 1
@@ -535,3 +510,6 @@ define void @wide_vector_interleave_st4_i8_dreg(ptr %output, ptr %input0, ptr %i
store <96 x i8> %interleave, ptr %output, align 1
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
index 963c28aeba32b6..fac725dd749995 100644
--- a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
@@ -1075,12 +1075,10 @@ define void @vld2_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: .LBB17_1: // %vector.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldp q1, q0, [x0], #32
-; CHECK-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: fmul v1.4s, v2.4s, v2.4s
-; CHECK-NEXT: fmla v1.4s, v0.4s, v0.4s
-; CHECK-NEXT: str q1, [x1, x8]
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
+; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
+; CHECK-NEXT: str q2, [x1, x8]
; CHECK-NEXT: add x8, x8, #16
; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
; CHECK-NEXT: b.ne .LBB17_1
@@ -1161,47 +1159,25 @@ while.end: ; preds = %vector.body
define void @vld4_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld4_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin19:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB19_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IAENABLED-NEXT: add x9, x1, x8
-; CHECK-IAENABLED-NEXT: add x8, x8, #32
-; CHECK-IAENABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IAENABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x9]
-; CHECK-IAENABLED-NEXT: b.ne .LBB19_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld4_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin19:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB19_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: add x8, x8, #32
-; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: b.ne .LBB19_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld4_intrinsic:
+; CHECK: .Lfunc_begin19:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB19_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
+; CHECK-NEXT: add x9, x1, x8
+; CHECK-NEXT: add x8, x8, #32
+; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
+; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
+; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
+; CHECK-NEXT: b.ne .LBB19_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1248,16 +1224,12 @@ define void @twosrc_intrinsic(ptr nocapture readonly %pSrc, ptr nocapture readon
; CHECK-NEXT: add x9, x0, x8
; CHECK-NEXT: add x10, x1, x8
; CHECK-NEXT: add x8, x8, #32
-; CHECK-NEXT: ldp q1, q0, [x9]
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x9]
; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-NEXT: ldp q3, q2, [x10]
-; CHECK-NEXT: uzp1 v4.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: uzp1 v5.4s, v3.4s, v2.4s
-; CHECK-NEXT: uzp2 v1.4s, v3.4s, v2.4s
-; CHECK-NEXT: fmul v2.4s, v5.4s, v4.4s
-; CHECK-NEXT: fmla v2.4s, v0.4s, v1.4s
-; CHECK-NEXT: str q2, [x2], #16
+; CHECK-NEXT: ld2 { v2.4s, v3.4s }, [x10]
+; CHECK-NEXT: fmul v4.4s, v2.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v3.4s
+; CHECK-NEXT: str q4, [x2], #16
; CHECK-NEXT: b.ne .LBB20_1
; CHECK-NEXT: // %bb.2: // %while.end
; CHECK-NEXT: ret
@@ -1295,41 +1267,22 @@ while.end: ; preds = %vector.body
define void @vld2_multiuse_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld2_multiuse_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin21:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB21_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
-; CHECK-IAENABLED-NEXT: fmul v2.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v2.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: str q2, [x1, x8]
-; CHECK-IAENABLED-NEXT: add x8, x8, #16
-; CHECK-IAENABLED-NEXT: cmp x8, #1, lsl #12 // =4096
-; CHECK-IAENABLED-NEXT: b.ne .LBB21_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld2_multiuse_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin21:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB21_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ldp q1, q0, [x0], #32
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: uzp2 v0.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v1.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v1.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: str q1, [x1, x8]
-; CHECK-IADISABLED-NEXT: add x8, x8, #16
-; CHECK-IADISABLED-NEXT: cmp x8, #1, lsl #12 // =4096
-; CHECK-IADISABLED-NEXT: b.ne .LBB21_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld2_multiuse_intrinsic:
+; CHECK: .Lfunc_begin21:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB21_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld2 { v0.4s, v1.4s }, [x0], #32
+; CHECK-NEXT: fmul v2.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v2.4s, v1.4s, v1.4s
+; CHECK-NEXT: str q2, [x1, x8]
+; CHECK-NEXT: add x8, x8, #16
+; CHECK-NEXT: cmp x8, #1, lsl #12 // =4096
+; CHECK-NEXT: b.ne .LBB21_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1402,47 +1355,25 @@ while.end: ; preds = %vector.body
define void @vld4_multiuse_intrinsic(ptr nocapture readonly %pSrc, ptr noalias nocapture %pDst, i32 %numSamples) {
-; CHECK-IAENABLED-LABEL: vld4_multiuse_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin23:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
-; CHECK-IAENABLED-NEXT: mov x8, xzr
-; CHECK-IAENABLED-NEXT: .LBB23_1: // %vector.body
-; CHECK-IAENABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IAENABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IAENABLED-NEXT: add x9, x1, x8
-; CHECK-IAENABLED-NEXT: add x8, x8, #32
-; CHECK-IAENABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IAENABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IAENABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IAENABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IAENABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.4s, v5.4s }, [x9]
-; CHECK-IAENABLED-NEXT: b.ne .LBB23_1
-; CHECK-IAENABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: vld4_multiuse_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin23:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0: // %entry
-; CHECK-IADISABLED-NEXT: mov x8, xzr
-; CHECK-IADISABLED-NEXT: .LBB23_1: // %vector.body
-; CHECK-IADISABLED-NEXT: // =>This Inner Loop Header: Depth=1
-; CHECK-IADISABLED-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
-; CHECK-IADISABLED-NEXT: add x9, x1, x8
-; CHECK-IADISABLED-NEXT: add x8, x8, #32
-; CHECK-IADISABLED-NEXT: cmp x8, #2, lsl #12 // =8192
-; CHECK-IADISABLED-NEXT: fmul v4.4s, v0.4s, v0.4s
-; CHECK-IADISABLED-NEXT: fmul v5.4s, v2.4s, v2.4s
-; CHECK-IADISABLED-NEXT: fmla v4.4s, v1.4s, v1.4s
-; CHECK-IADISABLED-NEXT: fmla v5.4s, v3.4s, v3.4s
-; CHECK-IADISABLED-NEXT: zip2 v0.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: zip1 v1.4s, v4.4s, v5.4s
-; CHECK-IADISABLED-NEXT: stp q1, q0, [x9]
-; CHECK-IADISABLED-NEXT: b.ne .LBB23_1
-; CHECK-IADISABLED-NEXT: // %bb.2: // %while.end
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: vld4_multiuse_intrinsic:
+; CHECK: .Lfunc_begin23:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: mov x8, xzr
+; CHECK-NEXT: .LBB23_1: // %vector.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0], #64
+; CHECK-NEXT: add x9, x1, x8
+; CHECK-NEXT: add x8, x8, #32
+; CHECK-NEXT: cmp x8, #2, lsl #12 // =8192
+; CHECK-NEXT: fmul v4.4s, v0.4s, v0.4s
+; CHECK-NEXT: fmla v4.4s, v1.4s, v1.4s
+; CHECK-NEXT: fmul v5.4s, v2.4s, v2.4s
+; CHECK-NEXT: fmla v5.4s, v3.4s, v3.4s
+; CHECK-NEXT: st2 { v4.4s, v5.4s }, [x9]
+; CHECK-NEXT: b.ne .LBB23_1
+; CHECK-NEXT: // %bb.2: // %while.end
+; CHECK-NEXT: ret
entry:
br label %vector.body
@@ -1534,18 +1465,18 @@ define void @transpose_s16_8x8_simpler2_intrinsic(ptr nocapture noundef %a) {
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: ldp q2, q3, [x0, #64]
-; CHECK-NEXT: ldp q4, q5, [x0, #96]
+; CHECK-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-NEXT: ldp q4, q5, [x0, #64]
+; CHECK-NEXT: ldp q6, q7, [x0, #96]
; CHECK-NEXT: trn1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: zip1 v1.8h, v2.8h, v3.8h
-; CHECK-NEXT: trn1 v2.8h, v4.8h, v5.8h
-; CHECK-NEXT: ldp q3, q4, [x0, #32]
-; CHECK-NEXT: zip1 v3.8h, v3.8h, v4.8h
-; CHECK-NEXT: dup v1.4s, v1.s[0]
-; CHECK-NEXT: uzp1 v2.4s, v0.4s, v2.4s
-; CHECK-NEXT: zip1 v1.4s, v1.4s, v3.4s
-; CHECK-NEXT: zip2 v0.4s, v0.4s, v2.4s
-; CHECK-NEXT: str q1, [x0]
+; CHECK-NEXT: zip1 v2.8h, v4.8h, v5.8h
+; CHECK-NEXT: trn1 v3.8h, v6.8h, v7.8h
+; CHECK-NEXT: trn1 v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: uzp1 v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: zip2 v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: str q2, [x0]
; CHECK-NEXT: str q0, [x0, #64]
; CHECK-NEXT: ret
entry:
@@ -1684,26 +1615,14 @@ define void @transpose_s16_8x8_intrinsic(ptr nocapture noundef %0, ptr nocapture
}
define void @store_factor2_intrinsic(ptr %ptr, <4 x i32> %a0, <4 x i32> %a1) {
-; CHECK-IAENABLED-LABEL: store_factor2_intrinsic:
-; CHECK-IAENABLED: .Lfunc_begin27:
-; CHECK-IAENABLED-NEXT: .cfi_startproc
-; CHECK-IAENABLED-NEXT: // %bb.0:
-; CHECK-IAENABLED-NEXT: trn1 v2.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v3.4s, v1.4s, v0.4s
-; CHECK-IAENABLED-NEXT: st2 { v2.4s, v3.4s }, [x0]
-; CHECK-IAENABLED-NEXT: ret
-;
-; CHECK-IADISABLED-LABEL: store_factor2_intrinsic:
-; CHECK-IADISABLED: .Lfunc_begin27:
-; CHECK-IADISABLED-NEXT: .cfi_startproc
-; CHECK-IADISABLED-NEXT: // %bb.0:
-; CHECK-IADISABLED-NEXT: uzp1 v2.4s, v0.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v1.4s, v1.4s, v0.4s
-; CHECK-IADISABLED-NEXT: ext v0.16b, v2.16b, v0.16b, #8
-; CHECK-IADISABLED-NEXT: uzp2 v1.4s, v2.4s, v1.4s
-; CHECK-IADISABLED-NEXT: uzp1 v0.4s, v2.4s, v0.4s
-; CHECK-IADISABLED-NEXT: stp q0, q1, [x0]
-; CHECK-IADISABLED-NEXT: ret
+; CHECK-LABEL: store_factor2_intrinsic:
+; CHECK: .Lfunc_begin27:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: trn1 v2.4s, v0.4s, v1.4s
+; CHECK-NEXT: trn1 v3.4s, v1.4s, v0.4s
+; CHECK-NEXT: st2 { v2.4s, v3.4s }, [x0]
+; CHECK-NEXT: ret
%v0 = shufflevector <4 x i32> %a0, <4 x i32> %a1, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%v1 = shufflevector <4 x i32> %a1, <4 x i32> %a0, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%interleaved.vec = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
index a5971fb1f0310c..34f57538deb41e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
@@ -9,21 +9,39 @@
define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: lui a1, 11
+; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
+; CHECK-NEXT: addi a1, a1, -1366
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 8
+; CHECK-NEXT: vslidedown.vi v11, v9, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v9, v11
+; CHECK-NEXT: vsll.vi v11, v12, 8
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v10, a1, v8
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
+; CHECK-NEXT: vmsne.vi v9, v10, 0
+; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v0, v8, 2
+; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 16
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vwaddu.vv v12, v8, v10
-; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vwmaccu.vx v12, a2, v10
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v12, 0
-; CHECK-NEXT: vsm.v v8, (a0)
+; CHECK-NEXT: vsm.v v9, (a0)
; CHECK-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
store <32 x i1> %res, ptr %p
@@ -34,10 +52,25 @@ define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr
define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v16i16_v8i16_align1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: li a1, 170
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vslidedown.vi v10, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v8, v13, 16
; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a1, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vse8.v v10, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index bce071e988f0ef..0ac5860e3299b7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -226,97 +226,145 @@ define {<3 x i32>, <3 x i32>, <3 x i32>} @vector_deinterleave3_v3i32_v9i32(<9 x
define {<15 x i32>, <15 x i32>, <15 x i32>} @vector_deinterleave3_v15i32_v45i32(<45 x i32> %v) nounwind {
; RV32-LABEL: vector_deinterleave3_v15i32_v45i32:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -640
-; RV32-NEXT: sw ra, 636(sp) # 4-byte Folded Spill
-; RV32-NEXT: sw s0, 632(sp) # 4-byte Folded Spill
-; RV32-NEXT: addi s0, sp, 640
+; RV32-NEXT: addi sp, sp, -656
+; RV32-NEXT: sw ra, 652(sp) # 4-byte Folded Spill
+; RV32-NEXT: sw s0, 648(sp) # 4-byte Folded Spill
+; RV32-NEXT: addi s0, sp, 656
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: andi sp, sp, -128
-; RV32-NEXT: addi a1, sp, 252
-; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-NEXT: vse32.v v23, (a1)
-; RV32-NEXT: addi a1, sp, 248
-; RV32-NEXT: vse32.v v22, (a1)
-; RV32-NEXT: addi a1, sp, 244
-; RV32-NEXT: vse32.v v21, (a1)
-; RV32-NEXT: addi a1, sp, 240
-; RV32-NEXT: vse32.v v20, (a1)
-; RV32-NEXT: addi a1, sp, 236
-; RV32-NEXT: vse32.v v19, (a1)
-; RV32-NEXT: addi a1, sp, 232
-; RV32-NEXT: vse32.v v18, (a1)
-; RV32-NEXT: addi a1, sp, 228
-; RV32-NEXT: vse32.v v17, (a1)
-; RV32-NEXT: addi a1, sp, 224
-; RV32-NEXT: vse32.v v16, (a1)
-; RV32-NEXT: addi a1, sp, 220
-; RV32-NEXT: vse32.v v15, (a1)
-; RV32-NEXT: addi a1, sp, 216
-; RV32-NEXT: vse32.v v14, (a1)
-; RV32-NEXT: addi a1, sp, 212
-; RV32-NEXT: vse32.v v13, (a1)
-; RV32-NEXT: addi a1, sp, 208
-; RV32-NEXT: vse32.v v12, (a1)
-; RV32-NEXT: addi a1, sp, 204
-; RV32-NEXT: vse32.v v11, (a1)
-; RV32-NEXT: addi a1, sp, 200
-; RV32-NEXT: vse32.v v10, (a1)
-; RV32-NEXT: addi a1, sp, 196
-; RV32-NEXT: vse32.v v9, (a1)
-; RV32-NEXT: addi a1, sp, 192
-; RV32-NEXT: vse32.v v8, (a1)
-; RV32-NEXT: addi a2, a0, 64
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vle32.v v8, (a2)
+; RV32-NEXT: vmv1r.v v2, v23
+; RV32-NEXT: vmv1r.v v0, v21
+; RV32-NEXT: vmv1r.v v24, v19
+; RV32-NEXT: addi a1, sp, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v24, v17
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v16, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v16, v15
+; RV32-NEXT: vmv1r.v v24, v13
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 6
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v24, v11
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vmv1r.v v24, v9
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 10
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 640
+; RV32-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: addi a1, a0, 64
+; RV32-NEXT: vle32.v v24, (a1)
; RV32-NEXT: addi a2, sp, 384
-; RV32-NEXT: vse32.v v8, (a2)
-; RV32-NEXT: addi a3, a0, 96
+; RV32-NEXT: vse32.v v24, (a2)
+; RV32-NEXT: addi a1, a0, 96
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vle32.v v8, (a3)
-; RV32-NEXT: addi a3, sp, 416
-; RV32-NEXT: vse32.v v8, (a3)
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: addi a3, sp, 64
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vse32.v v8, (a3)
+; RV32-NEXT: vle32.v v9, (a1)
+; RV32-NEXT: addi a1, sp, 416
+; RV32-NEXT: vse32.v v9, (a1)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle32.v v12, (a1)
+; RV32-NEXT: vle32.v v24, (a0)
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v12, 8
-; RV32-NEXT: mv a1, sp
-; RV32-NEXT: vslidedown.vi v8, v8, 8
+; RV32-NEXT: vslidedown.vi v28, v24, 8
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vse32.v v12, (a1)
-; RV32-NEXT: addi a3, sp, 32
-; RV32-NEXT: vse32.v v16, (a3)
-; RV32-NEXT: addi a3, sp, 96
-; RV32-NEXT: vse32.v v8, (a3)
+; RV32-NEXT: vse32.v v28, (a1)
; RV32-NEXT: lw a0, 112(a0)
; RV32-NEXT: sw a0, 432(sp)
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle32.v v8, (a2)
+; RV32-NEXT: vle32.v v28, (a2)
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV32-NEXT: vslidedown.vi v12, v8, 8
+; RV32-NEXT: vslidedown.vi v4, v28, 8
+; RV32-NEXT: vsetivli zero, 8, e32, m2, tu, ma
+; RV32-NEXT: vslideup.vi v22, v2, 1
+; RV32-NEXT: vslideup.vi v0, v22, 1
+; RV32-NEXT: vslideup.vi v20, v0, 1
+; RV32-NEXT: addi a0, sp, 640
+; RV32-NEXT: vl2r.v v22, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v22, v20, 1
+; RV32-NEXT: vslideup.vi v18, v22, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v20, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v20, v18, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v18, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v18, v20, 1
+; RV32-NEXT: vslideup.vi v14, v16, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 6
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v16, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v16, v14, 1
+; RV32-NEXT: vslideup.vi v12, v16, 1
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v14, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v14, v12, 1
+; RV32-NEXT: addi a0, sp, 96
+; RV32-NEXT: vse32.v v28, (a0)
+; RV32-NEXT: vslideup.vi v10, v14, 1
; RV32-NEXT: addi a0, sp, 128
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: vse32.v v4, (a0)
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 10
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 640
+; RV32-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vslideup.vi v12, v10, 1
+; RV32-NEXT: addi a0, sp, 224
+; RV32-NEXT: vse32.v v24, (a0)
+; RV32-NEXT: addi a0, sp, 192
+; RV32-NEXT: vslideup.vi v8, v12, 1
+; RV32-NEXT: vse32.v v18, (a0)
; RV32-NEXT: addi a0, sp, 160
-; RV32-NEXT: vse32.v v12, (a0)
-; RV32-NEXT: vlseg3e32.v v20, (a3)
-; RV32-NEXT: vlseg3e32.v v12, (a1)
+; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vlseg3e32.v v20, (a1)
+; RV32-NEXT: vlseg3e32.v v12, (a0)
; RV32-NEXT: vmv4r.v v28, v20
; RV32-NEXT: vmv2r.v v30, v8
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vslideup.vi v8, v28, 8
-; RV32-NEXT: vmv2r.v v12, v14
; RV32-NEXT: vmv2r.v v20, v22
-; RV32-NEXT: vslideup.vi v12, v20, 8
+; RV32-NEXT: vmv2r.v v12, v14
; RV32-NEXT: vslideup.vi v16, v24, 8
-; RV32-NEXT: addi sp, s0, -640
-; RV32-NEXT: lw ra, 636(sp) # 4-byte Folded Reload
-; RV32-NEXT: lw s0, 632(sp) # 4-byte Folded Reload
-; RV32-NEXT: addi sp, sp, 640
+; RV32-NEXT: vslideup.vi v12, v20, 8
+; RV32-NEXT: addi sp, s0, -656
+; RV32-NEXT: lw ra, 652(sp) # 4-byte Folded Reload
+; RV32-NEXT: lw s0, 648(sp) # 4-byte Folded Reload
+; RV32-NEXT: addi sp, sp, 656
; RV32-NEXT: ret
;
; RV64-LABEL: vector_deinterleave3_v15i32_v45i32:
@@ -325,92 +373,142 @@ define {<15 x i32>, <15 x i32>, <15 x i32>} @vector_deinterleave3_v15i32_v45i32(
; RV64-NEXT: sd ra, 632(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 624(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 640
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: andi sp, sp, -128
+; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64-NEXT: vmv1r.v v2, v23
+; RV64-NEXT: vmv1r.v v0, v21
+; RV64-NEXT: vmv1r.v v24, v19
+; RV64-NEXT: addi a1, sp, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v24, v17
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v16, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v16, v15
+; RV64-NEXT: vmv1r.v v24, v13
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 6
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v24, v11
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv1r.v v24, v9
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 10
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: addi a1, a0, 64
+; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: addi a1, a0, 112
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v24, (a1)
-; RV64-NEXT: addi a1, sp, 252
-; RV64-NEXT: vse32.v v23, (a1)
-; RV64-NEXT: addi a1, sp, 248
-; RV64-NEXT: vse32.v v22, (a1)
-; RV64-NEXT: addi a1, sp, 244
-; RV64-NEXT: vse32.v v21, (a1)
-; RV64-NEXT: addi a1, sp, 240
-; RV64-NEXT: vse32.v v20, (a1)
-; RV64-NEXT: addi a1, sp, 236
-; RV64-NEXT: vse32.v v19, (a1)
-; RV64-NEXT: addi a1, sp, 232
-; RV64-NEXT: vse32.v v18, (a1)
-; RV64-NEXT: addi a1, sp, 228
-; RV64-NEXT: vse32.v v17, (a1)
-; RV64-NEXT: addi a1, sp, 224
-; RV64-NEXT: vse32.v v16, (a1)
-; RV64-NEXT: addi a1, sp, 220
-; RV64-NEXT: vse32.v v15, (a1)
-; RV64-NEXT: addi a1, sp, 216
-; RV64-NEXT: vse32.v v14, (a1)
-; RV64-NEXT: addi a1, sp, 212
-; RV64-NEXT: vse32.v v13, (a1)
-; RV64-NEXT: addi a1, sp, 208
-; RV64-NEXT: vse32.v v12, (a1)
-; RV64-NEXT: addi a1, sp, 204
-; RV64-NEXT: vse32.v v11, (a1)
-; RV64-NEXT: addi a1, sp, 200
-; RV64-NEXT: vse32.v v10, (a1)
-; RV64-NEXT: addi a1, sp, 196
-; RV64-NEXT: vse32.v v9, (a1)
-; RV64-NEXT: addi a1, sp, 192
-; RV64-NEXT: vse32.v v8, (a1)
-; RV64-NEXT: addi a2, a0, 64
+; RV64-NEXT: vle32.v v9, (a1)
+; RV64-NEXT: addi a1, sp, 384
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vle32.v v8, (a2)
-; RV64-NEXT: addi a2, sp, 384
-; RV64-NEXT: vse32.v v8, (a2)
-; RV64-NEXT: addi a3, a0, 96
+; RV64-NEXT: vse32.v v24, (a1)
+; RV64-NEXT: addi a2, a0, 96
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64-NEXT: vle32.v v8, (a3)
-; RV64-NEXT: addi a3, sp, 416
-; RV64-NEXT: vse32.v v8, (a3)
-; RV64-NEXT: addi a3, sp, 432
+; RV64-NEXT: vle32.v v11, (a2)
+; RV64-NEXT: addi a2, sp, 416
+; RV64-NEXT: vse32.v v11, (a2)
+; RV64-NEXT: addi a2, sp, 432
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; RV64-NEXT: vse32.v v24, (a3)
+; RV64-NEXT: vse32.v v9, (a2)
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vle32.v v8, (a0)
+; RV64-NEXT: vle32.v v24, (a0)
+; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; RV64-NEXT: vslidedown.vi v28, v24, 8
; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vse32.v v8, (a0)
+; RV64-NEXT: vse32.v v28, (a0)
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vle32.v v12, (a1)
+; RV64-NEXT: vle32.v v28, (a1)
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV64-NEXT: vslidedown.vi v16, v12, 8
-; RV64-NEXT: mv a0, sp
-; RV64-NEXT: vslidedown.vi v8, v8, 8
-; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vse32.v v12, (a0)
-; RV64-NEXT: addi a1, sp, 32
-; RV64-NEXT: vse32.v v16, (a1)
+; RV64-NEXT: vslidedown.vi v4, v28, 8
+; RV64-NEXT: vsetivli zero, 8, e32, m2, tu, ma
+; RV64-NEXT: vslideup.vi v22, v2, 1
+; RV64-NEXT: vslideup.vi v0, v22, 1
+; RV64-NEXT: vslideup.vi v20, v0, 1
+; RV64-NEXT: addi a1, sp, 624
+; RV64-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v22, v20, 1
+; RV64-NEXT: vslideup.vi v18, v22, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v20, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v20, v18, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v18, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v18, v20, 1
+; RV64-NEXT: vslideup.vi v14, v16, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 6
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v16, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v16, v14, 1
+; RV64-NEXT: vslideup.vi v12, v16, 1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v14, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v14, v12, 1
; RV64-NEXT: addi a1, sp, 96
+; RV64-NEXT: vse32.v v28, (a1)
+; RV64-NEXT: vslideup.vi v10, v14, 1
+; RV64-NEXT: addi a1, sp, 128
+; RV64-NEXT: vse32.v v4, (a1)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 10
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 624
+; RV64-NEXT: vl2r.v v12, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vslideup.vi v12, v10, 1
+; RV64-NEXT: addi a1, sp, 224
+; RV64-NEXT: vse32.v v24, (a1)
+; RV64-NEXT: addi a1, sp, 192
+; RV64-NEXT: vslideup.vi v8, v12, 1
+; RV64-NEXT: vse32.v v18, (a1)
+; RV64-NEXT: addi a1, sp, 160
; RV64-NEXT: vse32.v v8, (a1)
-; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vle32.v v8, (a2)
-; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; RV64-NEXT: vslidedown.vi v12, v8, 8
-; RV64-NEXT: addi a2, sp, 128
-; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vse32.v v8, (a2)
-; RV64-NEXT: addi a2, sp, 160
-; RV64-NEXT: vse32.v v12, (a2)
-; RV64-NEXT: vlseg3e32.v v20, (a1)
-; RV64-NEXT: vlseg3e32.v v12, (a0)
+; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-NEXT: vlseg3e32.v v20, (a0)
+; RV64-NEXT: vlseg3e32.v v12, (a1)
; RV64-NEXT: vmv4r.v v28, v20
; RV64-NEXT: vmv2r.v v30, v8
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-NEXT: vslideup.vi v8, v28, 8
-; RV64-NEXT: vmv2r.v v12, v14
; RV64-NEXT: vmv2r.v v20, v22
-; RV64-NEXT: vslideup.vi v12, v20, 8
+; RV64-NEXT: vmv2r.v v12, v14
; RV64-NEXT: vslideup.vi v16, v24, 8
+; RV64-NEXT: vslideup.vi v12, v20, 8
; RV64-NEXT: addi sp, s0, -640
; RV64-NEXT: ld ra, 632(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 624(sp) # 8-byte Folded Reload
@@ -423,92 +521,142 @@ define {<15 x i32>, <15 x i32>, <15 x i32>} @vector_deinterleave3_v15i32_v45i32(
; ZVZIP-NEXT: sd ra, 632(sp) # 8-byte Folded Spill
; ZVZIP-NEXT: sd s0, 624(sp) # 8-byte Folded Spill
; ZVZIP-NEXT: addi s0, sp, 640
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: sub sp, sp, a1
; ZVZIP-NEXT: andi sp, sp, -128
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v2, v23
+; ZVZIP-NEXT: vmv1r.v v0, v21
+; ZVZIP-NEXT: vmv1r.v v24, v19
+; ZVZIP-NEXT: addi a1, sp, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v24, v17
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v16, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v16, v15
+; ZVZIP-NEXT: vmv1r.v v24, v13
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 6
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v24, v11
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: vmv1r.v v24, v9
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 10
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vs2r.v v24, (a1) # vscale x 16-byte Folded Spill
+; ZVZIP-NEXT: addi a1, a0, 64
+; ZVZIP-NEXT: vle32.v v24, (a1)
; ZVZIP-NEXT: addi a1, a0, 112
; ZVZIP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v24, (a1)
-; ZVZIP-NEXT: addi a1, sp, 252
-; ZVZIP-NEXT: vse32.v v23, (a1)
-; ZVZIP-NEXT: addi a1, sp, 248
-; ZVZIP-NEXT: vse32.v v22, (a1)
-; ZVZIP-NEXT: addi a1, sp, 244
-; ZVZIP-NEXT: vse32.v v21, (a1)
-; ZVZIP-NEXT: addi a1, sp, 240
-; ZVZIP-NEXT: vse32.v v20, (a1)
-; ZVZIP-NEXT: addi a1, sp, 236
-; ZVZIP-NEXT: vse32.v v19, (a1)
-; ZVZIP-NEXT: addi a1, sp, 232
-; ZVZIP-NEXT: vse32.v v18, (a1)
-; ZVZIP-NEXT: addi a1, sp, 228
-; ZVZIP-NEXT: vse32.v v17, (a1)
-; ZVZIP-NEXT: addi a1, sp, 224
-; ZVZIP-NEXT: vse32.v v16, (a1)
-; ZVZIP-NEXT: addi a1, sp, 220
-; ZVZIP-NEXT: vse32.v v15, (a1)
-; ZVZIP-NEXT: addi a1, sp, 216
-; ZVZIP-NEXT: vse32.v v14, (a1)
-; ZVZIP-NEXT: addi a1, sp, 212
-; ZVZIP-NEXT: vse32.v v13, (a1)
-; ZVZIP-NEXT: addi a1, sp, 208
-; ZVZIP-NEXT: vse32.v v12, (a1)
-; ZVZIP-NEXT: addi a1, sp, 204
-; ZVZIP-NEXT: vse32.v v11, (a1)
-; ZVZIP-NEXT: addi a1, sp, 200
-; ZVZIP-NEXT: vse32.v v10, (a1)
-; ZVZIP-NEXT: addi a1, sp, 196
-; ZVZIP-NEXT: vse32.v v9, (a1)
-; ZVZIP-NEXT: addi a1, sp, 192
-; ZVZIP-NEXT: vse32.v v8, (a1)
-; ZVZIP-NEXT: addi a2, a0, 64
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: addi a1, sp, 384
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a2)
-; ZVZIP-NEXT: addi a2, sp, 384
-; ZVZIP-NEXT: vse32.v v8, (a2)
-; ZVZIP-NEXT: addi a3, a0, 96
+; ZVZIP-NEXT: vse32.v v24, (a1)
+; ZVZIP-NEXT: addi a2, a0, 96
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a3)
-; ZVZIP-NEXT: addi a3, sp, 416
-; ZVZIP-NEXT: vse32.v v8, (a3)
-; ZVZIP-NEXT: addi a3, sp, 432
+; ZVZIP-NEXT: vle32.v v11, (a2)
+; ZVZIP-NEXT: addi a2, sp, 416
+; ZVZIP-NEXT: vse32.v v11, (a2)
+; ZVZIP-NEXT: addi a2, sp, 432
; ZVZIP-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVZIP-NEXT: vse32.v v24, (a3)
+; ZVZIP-NEXT: vse32.v v9, (a2)
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v24, (a0)
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v28, v24, 8
; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vse32.v v8, (a0)
+; ZVZIP-NEXT: vse32.v v28, (a0)
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vle32.v v12, (a1)
+; ZVZIP-NEXT: vle32.v v28, (a1)
; ZVZIP-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v16, v12, 8
-; ZVZIP-NEXT: mv a0, sp
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 8
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vse32.v v12, (a0)
-; ZVZIP-NEXT: addi a1, sp, 32
-; ZVZIP-NEXT: vse32.v v16, (a1)
+; ZVZIP-NEXT: vslidedown.vi v4, v28, 8
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v22, v2, 1
+; ZVZIP-NEXT: vslideup.vi v0, v22, 1
+; ZVZIP-NEXT: vslideup.vi v20, v0, 1
+; ZVZIP-NEXT: addi a1, sp, 624
+; ZVZIP-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v22, v20, 1
+; ZVZIP-NEXT: vslideup.vi v18, v22, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v20, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v20, v18, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v18, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v18, v20, 1
+; ZVZIP-NEXT: vslideup.vi v14, v16, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 6
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v16, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v16, v14, 1
+; ZVZIP-NEXT: vslideup.vi v12, v16, 1
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a1, a1, 3
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v14, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v14, v12, 1
; ZVZIP-NEXT: addi a1, sp, 96
+; ZVZIP-NEXT: vse32.v v28, (a1)
+; ZVZIP-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-NEXT: addi a1, sp, 128
+; ZVZIP-NEXT: vse32.v v4, (a1)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 10
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 624
+; ZVZIP-NEXT: vl2r.v v12, (a1) # vscale x 16-byte Folded Reload
+; ZVZIP-NEXT: vslideup.vi v12, v10, 1
+; ZVZIP-NEXT: addi a1, sp, 224
+; ZVZIP-NEXT: vse32.v v24, (a1)
+; ZVZIP-NEXT: addi a1, sp, 192
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vse32.v v18, (a1)
+; ZVZIP-NEXT: addi a1, sp, 160
; ZVZIP-NEXT: vse32.v v8, (a1)
-; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vle32.v v8, (a2)
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v12, v8, 8
-; ZVZIP-NEXT: addi a2, sp, 128
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vse32.v v8, (a2)
-; ZVZIP-NEXT: addi a2, sp, 160
-; ZVZIP-NEXT: vse32.v v12, (a2)
-; ZVZIP-NEXT: vlseg3e32.v v20, (a1)
-; ZVZIP-NEXT: vlseg3e32.v v12, (a0)
+; ZVZIP-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vlseg3e32.v v20, (a0)
+; ZVZIP-NEXT: vlseg3e32.v v12, (a1)
; ZVZIP-NEXT: vmv4r.v v28, v20
; ZVZIP-NEXT: vmv2r.v v30, v8
; ZVZIP-NEXT: vmv4r.v v8, v12
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v28, 8
-; ZVZIP-NEXT: vmv2r.v v12, v14
; ZVZIP-NEXT: vmv2r.v v20, v22
-; ZVZIP-NEXT: vslideup.vi v12, v20, 8
+; ZVZIP-NEXT: vmv2r.v v12, v14
; ZVZIP-NEXT: vslideup.vi v16, v24, 8
+; ZVZIP-NEXT: vslideup.vi v12, v20, 8
; ZVZIP-NEXT: addi sp, s0, -640
; ZVZIP-NEXT: ld ra, 632(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 624(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
index 23aaec74ce9de4..16689a6f1f86fc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
@@ -585,7 +585,10 @@ define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i
; CHECK-NEXT: vmv.v.v v13, v12
; CHECK-NEXT: vmv.v.v v14, v12
; CHECK-NEXT: vmv.v.v v15, v12
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vsseg4e8.v v12, (a1)
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: add a3, a1, a2
@@ -593,29 +596,27 @@ define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i
; CHECK-NEXT: vl1r.v v13, (a1)
; CHECK-NEXT: vmsne.vi v12, v12, 0
; CHECK-NEXT: vmsne.vi v0, v13, 0
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: vl1r.v v13, (a3)
+; CHECK-NEXT: slli a4, a2, 1
+; CHECK-NEXT: add a1, a1, a4
+; CHECK-NEXT: vl1r.v v13, (a1)
; CHECK-NEXT: srli a1, a2, 2
-; CHECK-NEXT: srli a4, a2, 3
+; CHECK-NEXT: srli a2, a2, 3
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v0, v12, a4
+; CHECK-NEXT: vslideup.vx v0, v12, a2
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, ma
; CHECK-NEXT: vmsne.vi v12, v13, 0
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vl1r.v v13, (a2)
-; CHECK-NEXT: add a4, a1, a4
-; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
+; CHECK-NEXT: add a3, a3, a4
+; CHECK-NEXT: vl1r.v v13, (a3)
+; CHECK-NEXT: add a2, a1, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v0, v12, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmsne.vi v12, v13, 0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v12, a4
+; CHECK-NEXT: vslideup.vx v0, v12, a2
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0), v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg4e8.v v8, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 6a23fb8f437fea..14c5d3da6d23ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -117,14 +117,14 @@ define {<vscale x 5 x i32>, <vscale x 5 x i32>, <vscale x 5 x i32>} @vector_dein
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv2r.v v8, v14
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vlseg3e32.v v12, (a0)
; CHECK-NEXT: vlseg3e32.v v20, (a1)
@@ -696,14 +696,14 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv1r.v v10, v13
; CHECK-NEXT: vmv1r.v v11, v14
; CHECK-NEXT: vmv1r.v v8, v21
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vmv1r.v v9, v12
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vmv1r.v v12, v15
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg5e8.v v8, (a0)
@@ -738,7 +738,10 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -746,10 +749,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e8.v v12, (a0)
; CHECK-NEXT: vlseg5e8.v v18, (a1)
@@ -779,7 +779,10 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -787,10 +790,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e16.v v12, (a0)
; CHECK-NEXT: vlseg5e16.v v18, (a1)
@@ -820,7 +820,10 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -828,10 +831,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e32.v v12, (a0)
; CHECK-NEXT: vlseg5e32.v v18, (a1)
@@ -861,7 +861,10 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -869,10 +872,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e64.v v12, (a0)
; CHECK-NEXT: vlseg5e64.v v18, (a1)
@@ -921,7 +921,10 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
@@ -929,10 +932,7 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vslidedown.vx v0, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg6e8.v v8, (a0)
@@ -969,16 +969,16 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e8.v v24, (a0)
; CHECK-NEXT: vlseg6e8.v v18, (a1)
@@ -1010,16 +1010,16 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e16.v v24, (a0)
; CHECK-NEXT: vlseg6e16.v v18, (a1)
@@ -1051,16 +1051,16 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e32.v v24, (a0)
; CHECK-NEXT: vlseg6e32.v v18, (a1)
@@ -1092,16 +1092,16 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e64.v v24, (a0)
; CHECK-NEXT: vlseg6e64.v v18, (a1)
@@ -1168,14 +1168,14 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv1r.v v8, v23
; CHECK-NEXT: vmv1r.v v9, v14
; CHECK-NEXT: vmv1r.v v12, v25
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vmv1r.v v13, v26
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vmv1r.v v14, v27
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg7e8.v v8, (a0)
@@ -1215,7 +1215,10 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1225,10 +1228,7 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e8.v v14, (a0)
; CHECK-NEXT: vlseg7e8.v v22, (a1)
@@ -1262,7 +1262,10 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1272,10 +1275,7 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e16.v v14, (a0)
; CHECK-NEXT: vlseg7e16.v v22, (a1)
@@ -1309,7 +1309,10 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1319,10 +1322,7 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e32.v v14, (a0)
; CHECK-NEXT: vlseg7e32.v v22, (a1)
@@ -1356,7 +1356,10 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -1366,10 +1369,7 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e64.v v14, (a0)
; CHECK-NEXT: vlseg7e64.v v22, (a1)
@@ -1431,17 +1431,17 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v26, v10, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg8e8.v v18, (a0)
@@ -1483,12 +1483,12 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg8e8.v v0, (a0)
@@ -1525,12 +1525,12 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlseg8e16.v v0, (a0)
@@ -1567,12 +1567,12 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vlseg8e32.v v0, (a0)
@@ -1609,12 +1609,12 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vlseg8e64.v v0, (a0)
@@ -2437,11 +2437,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2482,7 +2477,10 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2490,10 +2488,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e16.v v12, (a0)
; CHECK-NEXT: vlseg5e16.v v18, (a1)
@@ -2522,11 +2517,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2567,7 +2557,10 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2575,10 +2568,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e16.v v12, (a0)
; CHECK-NEXT: vlseg5e16.v v18, (a1)
@@ -2607,11 +2597,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -2652,7 +2637,10 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2660,10 +2648,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e32.v v12, (a0)
; CHECK-NEXT: vlseg5e32.v v18, (a1)
@@ -2712,7 +2697,10 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v26, v15
; CHECK-NEXT: vmv1r.v v27, v16
@@ -2720,10 +2708,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: vmv1r.v v25, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v28, v17
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg5e64.v v12, (a0)
; CHECK-NEXT: vlseg5e64.v v18, (a1)
@@ -2752,13 +2737,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2799,16 +2777,16 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e16.v v24, (a0)
; CHECK-NEXT: vlseg6e16.v v18, (a1)
@@ -2840,13 +2818,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -2887,16 +2858,16 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e16.v v24, (a0)
; CHECK-NEXT: vlseg6e16.v v18, (a1)
@@ -2928,13 +2899,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v11, a0
-; CHECK-NEXT: vslidedown.vx v11, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v11, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -2975,16 +2939,16 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e32.v v24, (a0)
; CHECK-NEXT: vlseg6e32.v v18, (a1)
@@ -3036,16 +3000,16 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv2r.v v28, v18
; CHECK-NEXT: vmv2r.v v24, v14
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv2r.v v26, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg6e64.v v24, (a0)
; CHECK-NEXT: vlseg6e64.v v18, (a1)
@@ -3077,13 +3041,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v12, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -3124,7 +3081,10 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3134,10 +3094,7 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e16.v v14, (a0)
; CHECK-NEXT: vlseg7e16.v v22, (a1)
@@ -3170,13 +3127,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v12, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
@@ -3217,7 +3167,10 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3227,10 +3180,7 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e16.v v14, (a0)
; CHECK-NEXT: vlseg7e16.v v22, (a1)
@@ -3263,13 +3213,6 @@ define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: srli a0, a0, 3
-; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v10, a0
-; CHECK-NEXT: vslideup.vx v10, v12, a0
-; CHECK-NEXT: vslidedown.vx v12, v9, a0
-; CHECK-NEXT: vslideup.vx v9, v12, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs4r.v v8, (a0)
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
@@ -3310,7 +3253,10 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3320,10 +3266,7 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e32.v v14, (a0)
; CHECK-NEXT: vlseg7e32.v v22, (a1)
@@ -3376,7 +3319,10 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v30, v21
; CHECK-NEXT: vmv1r.v v28, v19
@@ -3386,10 +3332,7 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v25, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: vlseg7e64.v v14, (a0)
; CHECK-NEXT: vlseg7e64.v v22, (a1)
@@ -3462,12 +3405,12 @@ define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlseg8e16.v v0, (a0)
@@ -3544,12 +3487,12 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlseg8e16.v v0, (a0)
@@ -3626,12 +3569,12 @@ define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscal
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vlseg8e32.v v0, (a0)
@@ -3688,12 +3631,12 @@ define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vlseg8e64.v v0, (a0)
@@ -3791,23 +3734,55 @@ define <vscale x 1 x float> @vector_deinterleave_nxv1f32_nxv8f32_oneactive2(<vsc
define { <8 x float>, <8 x float> } @interleave_deinterleave2(<8 x float> %a, <8 x float> %b) {
; V-LABEL: interleave_deinterleave2:
; V: # %bb.0: # %entry
-; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; V-NEXT: vwaddu.vv v12, v8, v10
-; V-NEXT: li a0, -1
-; V-NEXT: vwmaccu.vx v12, a0, v10
+; V-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; V-NEXT: vslidedown.vi v12, v10, 4
+; V-NEXT: vslidedown.vi v14, v8, 4
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; V-NEXT: vzext.vf2 v16, v12
; V-NEXT: li a0, 32
-; V-NEXT: vnsrl.wx v10, v12, a0
-; V-NEXT: vnsrl.wi v8, v12, 0
+; V-NEXT: vsll.vx v12, v16, a0
+; V-NEXT: li a1, 170
+; V-NEXT: vmv.s.x v0, a1
+; V-NEXT: vzext.vf2 v16, v14
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vmerge.vvm v12, v16, v12, v0
+; V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; V-NEXT: vwaddu.vv v14, v8, v10
+; V-NEXT: li a1, -1
+; V-NEXT: vwmaccu.vx v14, a1, v10
+; V-NEXT: vnsrl.wi v8, v14, 0
+; V-NEXT: vnsrl.wi v10, v12, 0
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vslideup.vi v8, v10, 4
+; V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; V-NEXT: vnsrl.wx v10, v14, a0
+; V-NEXT: vnsrl.wx v14, v12, a0
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vslideup.vi v10, v14, 4
; V-NEXT: ret
;
; ZVZIP-LABEL: interleave_deinterleave2:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: li a0, 32
-; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v12, v10, 4
+; ZVZIP-NEXT: vslidedown.vi v14, v8, 4
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; ZVZIP-NEXT: vzip.vv v16, v14, v9
+; ZVZIP-NEXT: vzip.vv v16, v9, v12, v0.t
; ZVZIP-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v10, v16, 0
+; ZVZIP-NEXT: vnsrl.wi v8, v12, 0
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v14, v16, a0
; ZVZIP-NEXT: vnsrl.wx v10, v12, a0
-; ZVZIP-NEXT: vnsrl.wi v8, v12, 0
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v14, 4
; ZVZIP-NEXT: ret
entry:
%0 = call <16 x float> @llvm.vector.interleave2.v16f32(<8 x float> %a, <8 x float> %b)
@@ -3822,19 +3797,44 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; V-NEXT: vnsrl.wx v12, v8, a0
; V-NEXT: vnsrl.wi v14, v8, 0
+; V-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; V-NEXT: vslidedown.vi v8, v12, 4
+; V-NEXT: vslidedown.vi v10, v14, 4
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; V-NEXT: vzext.vf2 v16, v8
+; V-NEXT: vsll.vx v16, v16, a0
+; V-NEXT: li a0, 170
+; V-NEXT: vmv.s.x v0, a0
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwaddu.vv v8, v14, v12
+; V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; V-NEXT: vzext.vf2 v14, v10
; V-NEXT: li a0, -1
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwmaccu.vx v8, a0, v12
+; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; V-NEXT: vmerge.vvm v12, v14, v16, v0
+; V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; V-NEXT: vslideup.vi v8, v12, 8
; V-NEXT: ret
;
; ZVZIP-LABEL: deinterleave_interleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a0, 32
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
-; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
+; ZVZIP-NEXT: vnsrl.wx v14, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v14, 4
+; ZVZIP-NEXT: vslidedown.vi v8, v16, 4
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v8, v9
+; ZVZIP-NEXT: vzip.vv v8, v16, v14
+; ZVZIP-NEXT: vzip.vv v12, v11, v10, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: ret
entry:
%0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 680e0d3a9e6499..a540b7aa3d5196 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -13,68 +13,119 @@
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: lui a0, 11
+; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
+; CHECK-NEXT: addi a0, a0, -1366
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 8
+; CHECK-NEXT: vslidedown.vi v11, v9, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v9, v11
+; CHECK-NEXT: vsll.vi v11, v12, 8
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v10, a0, v8
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
+; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 16
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vwaddu.vv v12, v8, v10
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vwmaccu.vx v12, a1, v10
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v32i1_v16i1:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVBB-NEXT: vmv.v.i v9, 0
+; ZVBB-NEXT: vmerge.vim v10, v9, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: lui a0, 11
+; ZVBB-NEXT: vmerge.vim v8, v9, 1, v0
+; ZVBB-NEXT: addi a0, a0, -1366
+; ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vi v9, v10, 8
+; ZVBB-NEXT: vslidedown.vi v11, v8, 8
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v9
+; ZVBB-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v9, v8, 8
+; ZVBB-NEXT: vwaddu.wv v9, v9, v10
+; ZVBB-NEXT: vwsll.vi v8, v11, 8
+; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVBB-NEXT: vmerge.vvm v8, v12, v8, v0
+; ZVBB-NEXT: vmsne.vi v0, v9, 0
+; ZVBB-NEXT: vmsne.vi v8, v8, 0
; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVBB-NEXT: vslideup.vi v0, v8, 2
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVBB-NEXT: vmv.v.i v8, 0
-; ZVBB-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVBB-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; ZVBB-NEXT: vslidedown.vi v10, v8, 16
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vwsll.vi v12, v10, 8
-; ZVBB-NEXT: vwaddu.wv v12, v12, v8
-; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v9, v0
+; ZVZIP-NEXT: vmv.v.i v10, 0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmerge.vim v8, v10, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v9
+; ZVZIP-NEXT: lui a0, 11
+; ZVZIP-NEXT: vmerge.vim v9, v10, 1, v0
+; ZVZIP-NEXT: addi a0, a0, -1366
+; ZVZIP-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 8
+; ZVZIP-NEXT: vslidedown.vi v11, v8, 8
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v13, v10, v12
+; ZVZIP-NEXT: vzip.vv v10, v9, v8
+; ZVZIP-NEXT: vzip.vv v13, v8, v11, v0.t
+; ZVZIP-NEXT: vmsne.vi v0, v10, 0
+; ZVZIP-NEXT: vmsne.vi v8, v13, 0
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vslideup.vi v0, v8, 2
-; ZVZIP-NEXT: li a0, 32
-; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVZIP-NEXT: vmv.v.i v8, 0
-; ZVZIP-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v10, v8, 16
-; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v8, v10
-; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP-ZVL2048: # %bb.0:
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v9, v0
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v10, 0
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v0, v8
+; ZVZIP-ZVL2048-NEXT: vmerge.vim v8, v10, 1, v0
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v0, v9
+; ZVZIP-ZVL2048-NEXT: lui a0, 11
+; ZVZIP-ZVL2048-NEXT: addi a0, a0, -1366
+; ZVZIP-ZVL2048-NEXT: vmerge.vim v9, v10, 1, v0
+; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v9, 8
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v10, v11
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 8
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf4, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v9, v8
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v10, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmsne.vi v0, v11, 0
+; ZVZIP-ZVL2048-NEXT: vmsne.vi v8, v12, 0
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v0, v8, 2
-; ZVZIP-ZVL2048-NEXT: li a0, 32
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v8, 0
-; ZVZIP-ZVL2048-NEXT: vmerge.vim v8, v8, 1, v0
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v8, 16
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmsne.vi v0, v10, 0
; ZVZIP-ZVL2048-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
@@ -83,35 +134,77 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vector_interleave_v16i16_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v10, v13, 16
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16i16_v8i16:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: li a0, 170
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vslidedown.vi v8, v8, 4
+; ZVBB-NEXT: vslidedown.vi v11, v9, 4
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v8, v9, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
-; ZVBB-NEXT: vwsll.vi v8, v10, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v8, v13
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: li a0, 170
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 8
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
@@ -121,37 +214,76 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vector_interleave_v8i32_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v8, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsll.vx v10, v12, a0
+; CHECK-NEXT: vzext.vf2 v12, v11
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8i32_v4i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: vslidedown.vi v8, v8, 2
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vwsll.vx v8, v10, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vx v8, v9, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vx v9, v11, a0
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 4
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v8, v13
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv.v.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
@@ -160,48 +292,42 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vector_interleave_v4i64_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: lui a0, 12304
-; CHECK-NEXT: addi a0, a0, 512
-; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4i64_v2i64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: lui a0, 12304
-; ZVBB-NEXT: addi a0, a0, 512
-; ZVBB-NEXT: vmv.s.x v10, a0
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vsext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
-; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v10, v9
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v11, v8
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
@@ -294,20 +420,8 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 24
-; CHECK-NEXT: vle32.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle32.v v10, (a1)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 2
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
@@ -317,39 +431,60 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 24
-; ZVBB-NEXT: vle32.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle32.v v10, (a1)
-; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 2
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vle64.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v12, v8
+; ZVZIP-NEXT: vpairo.vv v13, v9, v11
+; ZVZIP-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-NEXT: vpairo.vv v11, v8, v10
+; ZVZIP-NEXT: vslideup.vi v12, v10, 1
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-NEXT: vzip.vv v11, v8, v10
+; ZVZIP-NEXT: vzip.vv v8, v12, v9
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v9, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v10, v11, v12
+; ZVZIP-NEXT: vzip.vv v10, v11, v9, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP-ZVL2048: # %bb.0:
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v10
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v9, v12
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v9, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 6
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
@@ -641,7 +776,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
; CHECK-RV32-NEXT: vmv2r.v v22, v24
-; CHECK-RV32-NEXT: addi a3, sp, 672
+; CHECK-RV32-NEXT: addi a3, sp, 1056
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v16, (a3)
; CHECK-RV32-NEXT: csrr a5, vlenb
@@ -741,7 +876,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vmv2r.v v18, v20
; CHECK-RV32-NEXT: vslidedown.vx v20, v0, a1
; CHECK-RV32-NEXT: vmv2r.v v22, v24
-; CHECK-RV32-NEXT: addi a5, sp, 1696
+; CHECK-RV32-NEXT: addi a5, sp, 32
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v16, (a5)
; CHECK-RV32-NEXT: csrr a6, vlenb
@@ -845,7 +980,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
; CHECK-RV32-NEXT: vmv2r.v v22, v24
-; CHECK-RV32-NEXT: addi s5, sp, 1184
+; CHECK-RV32-NEXT: addi s5, sp, 544
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v16, (s5)
; CHECK-RV32-NEXT: csrr a6, vlenb
@@ -905,7 +1040,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vslidedown.vx v20, v8, a1
; CHECK-RV32-NEXT: vmv2r.v v22, v24
-; CHECK-RV32-NEXT: addi a6, sp, 928
+; CHECK-RV32-NEXT: addi a6, sp, 1312
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v16, (a6)
; CHECK-RV32-NEXT: csrr a7, vlenb
@@ -1011,7 +1146,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vslidedown.vx v12, v0, a1
; CHECK-RV32-NEXT: vmv2r.v v14, v20
-; CHECK-RV32-NEXT: addi s4, sp, 160
+; CHECK-RV32-NEXT: addi s4, sp, 1568
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v8, (s4)
; CHECK-RV32-NEXT: csrr a7, vlenb
@@ -1063,7 +1198,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a1
; CHECK-RV32-NEXT: vmv2r.v v10, v12
-; CHECK-RV32-NEXT: addi a7, sp, 1952
+; CHECK-RV32-NEXT: addi a7, sp, 288
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v4, (a7)
; CHECK-RV32-NEXT: csrr t0, vlenb
@@ -1111,7 +1246,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a1
; CHECK-RV32-NEXT: vmv2r.v v10, v12
-; CHECK-RV32-NEXT: addi t0, sp, 1440
+; CHECK-RV32-NEXT: addi t0, sp, 800
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v4, (t0)
; CHECK-RV32-NEXT: csrr t1, vlenb
@@ -1163,7 +1298,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t1, t1, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi s3, sp, 544
+; CHECK-RV32-NEXT: addi s3, sp, 1184
; CHECK-RV32-NEXT: vsseg4e8.v v8, (s3)
; CHECK-RV32-NEXT: csrr t1, vlenb
; CHECK-RV32-NEXT: slli t1, t1, 3
@@ -1204,7 +1339,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vslidedown.vx v8, v16, a1
; CHECK-RV32-NEXT: vmv2r.v v10, v12
-; CHECK-RV32-NEXT: addi t1, sp, 416
+; CHECK-RV32-NEXT: addi t1, sp, 1824
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vsseg4e8.v v4, (t1)
; CHECK-RV32-NEXT: csrr t2, vlenb
@@ -1249,7 +1384,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t2, t2, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi s2, sp, 1568
+; CHECK-RV32-NEXT: addi s2, sp, 160
; CHECK-RV32-NEXT: vsseg4e8.v v8, (s2)
; CHECK-RV32-NEXT: csrr t2, vlenb
; CHECK-RV32-NEXT: slli t2, t2, 4
@@ -1292,7 +1427,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t2, t2, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi t2, sp, 1056
+; CHECK-RV32-NEXT: addi t2, sp, 672
; CHECK-RV32-NEXT: vsseg4e8.v v8, (t2)
; CHECK-RV32-NEXT: csrr t3, vlenb
; CHECK-RV32-NEXT: slli t3, t3, 4
@@ -1347,7 +1482,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t3, t3, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi t3, sp, 800
+; CHECK-RV32-NEXT: addi t3, sp, 1440
; CHECK-RV32-NEXT: vsseg4e8.v v8, (t3)
; CHECK-RV32-NEXT: csrr t4, vlenb
; CHECK-RV32-NEXT: slli t4, t4, 3
@@ -1387,7 +1522,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t4, t4, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi s1, sp, 32
+; CHECK-RV32-NEXT: addi s1, sp, 1696
; CHECK-RV32-NEXT: vsseg4e8.v v8, (s1)
; CHECK-RV32-NEXT: csrr t4, vlenb
; CHECK-RV32-NEXT: slli t4, t4, 3
@@ -1434,7 +1569,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t4, t4, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi t4, sp, 1824
+; CHECK-RV32-NEXT: addi t4, sp, 416
; CHECK-RV32-NEXT: vsseg4e8.v v8, (t4)
; CHECK-RV32-NEXT: csrr t5, vlenb
; CHECK-RV32-NEXT: slli t5, t5, 4
@@ -1477,7 +1612,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi t5, t5, 33
; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v14, v16
-; CHECK-RV32-NEXT: addi t6, sp, 1312
+; CHECK-RV32-NEXT: addi t6, sp, 928
; CHECK-RV32-NEXT: vsseg4e8.v v8, (t6)
; CHECK-RV32-NEXT: csrr t5, vlenb
; CHECK-RV32-NEXT: slli t5, t5, 8
@@ -1514,9 +1649,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vmv2r.v v12, v16
; CHECK-RV32-NEXT: vmv2r.v v14, v24
-; CHECK-RV32-NEXT: addi t5, sp, 288
+; CHECK-RV32-NEXT: addi t5, sp, 1952
; CHECK-RV32-NEXT: vsseg4e8.v v8, (t5)
-; CHECK-RV32-NEXT: addi s6, sp, 768
+; CHECK-RV32-NEXT: addi s6, sp, 1152
; CHECK-RV32-NEXT: vle8.v v8, (s6)
; CHECK-RV32-NEXT: csrr s6, vlenb
; CHECK-RV32-NEXT: slli s6, s6, 4
@@ -1529,7 +1664,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s6, s6, 2047
; CHECK-RV32-NEXT: addi s6, s6, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s6, sp, 704
+; CHECK-RV32-NEXT: addi s6, sp, 1088
; CHECK-RV32-NEXT: vle8.v v8, (s6)
; CHECK-RV32-NEXT: csrr s6, vlenb
; CHECK-RV32-NEXT: slli s6, s6, 3
@@ -1542,7 +1677,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s6, s6, 2047
; CHECK-RV32-NEXT: addi s6, s6, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s6, sp, 1792
+; CHECK-RV32-NEXT: addi s6, sp, 128
; CHECK-RV32-NEXT: vle8.v v8, (s6)
; CHECK-RV32-NEXT: csrr s6, vlenb
; CHECK-RV32-NEXT: slli s6, s6, 5
@@ -1553,7 +1688,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s6, s6, 2047
; CHECK-RV32-NEXT: addi s6, s6, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s6, sp, 1728
+; CHECK-RV32-NEXT: addi s6, sp, 64
; CHECK-RV32-NEXT: vle8.v v8, (s6)
; CHECK-RV32-NEXT: csrr s6, vlenb
; CHECK-RV32-NEXT: slli s6, s6, 3
@@ -1566,13 +1701,13 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s6, s6, 2047
; CHECK-RV32-NEXT: addi s6, s6, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s6, sp, 1280
+; CHECK-RV32-NEXT: addi s6, sp, 640
; CHECK-RV32-NEXT: vle8.v v16, (s6)
-; CHECK-RV32-NEXT: addi s6, sp, 1248
+; CHECK-RV32-NEXT: addi s6, sp, 608
; CHECK-RV32-NEXT: vle8.v v8, (s6)
-; CHECK-RV32-NEXT: addi s6, sp, 1216
+; CHECK-RV32-NEXT: addi s6, sp, 576
; CHECK-RV32-NEXT: vle8.v v12, (s6)
-; CHECK-RV32-NEXT: addi s6, sp, 1024
+; CHECK-RV32-NEXT: addi s6, sp, 1408
; CHECK-RV32-NEXT: vle8.v v20, (s6)
; CHECK-RV32-NEXT: csrr s6, vlenb
; CHECK-RV32-NEXT: slli s6, s6, 4
@@ -1587,7 +1722,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v16, (s5)
-; CHECK-RV32-NEXT: addi s5, sp, 960
+; CHECK-RV32-NEXT: addi s5, sp, 1344
; CHECK-RV32-NEXT: vle8.v v20, (s5)
; CHECK-RV32-NEXT: csrr s5, vlenb
; CHECK-RV32-NEXT: slli s5, s5, 3
@@ -1601,10 +1736,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v16, v12, a1
; CHECK-RV32-NEXT: vmv.v.v v24, v16
-; CHECK-RV32-NEXT: addi s5, sp, 256
+; CHECK-RV32-NEXT: addi s5, sp, 1664
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v20, (s5)
-; CHECK-RV32-NEXT: addi s5, sp, 192
+; CHECK-RV32-NEXT: addi s5, sp, 1600
; CHECK-RV32-NEXT: vle8.v v16, (s5)
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v24, v8, a4
@@ -1614,8 +1749,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s5, s5, 2047
; CHECK-RV32-NEXT: addi s5, s5, 33
; CHECK-RV32-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi s5, sp, 2047
-; CHECK-RV32-NEXT: addi s5, s5, 1
+; CHECK-RV32-NEXT: addi s5, sp, 384
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (s5)
; CHECK-RV32-NEXT: csrr s5, vlenb
@@ -1633,7 +1767,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s5, s5, 2047
; CHECK-RV32-NEXT: addi s5, s5, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s5, sp, 1984
+; CHECK-RV32-NEXT: addi s5, sp, 320
; CHECK-RV32-NEXT: vle8.v v8, (s5)
; CHECK-RV32-NEXT: csrr s5, vlenb
; CHECK-RV32-NEXT: slli s5, s5, 4
@@ -1648,9 +1782,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s5, s5, 2047
; CHECK-RV32-NEXT: addi s5, s5, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s5, sp, 224
+; CHECK-RV32-NEXT: addi s5, sp, 1632
; CHECK-RV32-NEXT: vle8.v v8, (s5)
-; CHECK-RV32-NEXT: addi s5, sp, 1536
+; CHECK-RV32-NEXT: addi s5, sp, 896
; CHECK-RV32-NEXT: vle8.v v12, (s5)
; CHECK-RV32-NEXT: csrr s5, vlenb
; CHECK-RV32-NEXT: slli s5, s5, 3
@@ -1669,7 +1803,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vslideup.vx v8, v20, a1
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v24, (s4)
-; CHECK-RV32-NEXT: addi s4, sp, 1472
+; CHECK-RV32-NEXT: addi s4, sp, 832
; CHECK-RV32-NEXT: vle8.v v12, (s4)
; CHECK-RV32-NEXT: csrr s4, vlenb
; CHECK-RV32-NEXT: slli s4, s4, 5
@@ -1685,10 +1819,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v24, v16, a1
; CHECK-RV32-NEXT: vmv.v.v v0, v24
-; CHECK-RV32-NEXT: addi s4, sp, 640
+; CHECK-RV32-NEXT: addi s4, sp, 1280
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v20, (s4)
-; CHECK-RV32-NEXT: addi s4, sp, 576
+; CHECK-RV32-NEXT: addi s4, sp, 1216
; CHECK-RV32-NEXT: vle8.v v24, (s4)
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v0, v8, a4
@@ -1705,7 +1839,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s4, s4, 2047
; CHECK-RV32-NEXT: addi s4, s4, 33
; CHECK-RV32-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi s4, sp, 512
+; CHECK-RV32-NEXT: addi s4, sp, 1920
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (s4)
; CHECK-RV32-NEXT: csrr s4, vlenb
@@ -1719,7 +1853,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s4, s4, 2047
; CHECK-RV32-NEXT: addi s4, s4, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s4, sp, 448
+; CHECK-RV32-NEXT: addi s4, sp, 1856
; CHECK-RV32-NEXT: vle8.v v8, (s4)
; CHECK-RV32-NEXT: csrr s4, vlenb
; CHECK-RV32-NEXT: slli s4, s4, 3
@@ -1732,19 +1866,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s4, s4, 2047
; CHECK-RV32-NEXT: addi s4, s4, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s4, sp, 608
+; CHECK-RV32-NEXT: addi s4, sp, 1248
; CHECK-RV32-NEXT: vle8.v v8, (s4)
-; CHECK-RV32-NEXT: addi s4, sp, 1664
+; CHECK-RV32-NEXT: addi s4, sp, 256
; CHECK-RV32-NEXT: vle8.v v16, (s4)
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v20, a1
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v0, (s3)
-; CHECK-RV32-NEXT: addi s3, sp, 1600
+; CHECK-RV32-NEXT: addi s3, sp, 192
; CHECK-RV32-NEXT: vle8.v v20, (s3)
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v0, v24, a1
-; CHECK-RV32-NEXT: addi s3, sp, 1152
+; CHECK-RV32-NEXT: addi s3, sp, 768
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v12, (s3)
; CHECK-RV32-NEXT: csrr s3, vlenb
@@ -1760,7 +1894,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s3, s3, 2047
; CHECK-RV32-NEXT: addi s3, s3, 33
; CHECK-RV32-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s3, sp, 1088
+; CHECK-RV32-NEXT: addi s3, sp, 704
; CHECK-RV32-NEXT: vle8.v v24, (s3)
; CHECK-RV32-NEXT: csrr s3, vlenb
; CHECK-RV32-NEXT: slli s3, s3, 4
@@ -1784,7 +1918,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s3, s3, 2047
; CHECK-RV32-NEXT: addi s3, s3, 33
; CHECK-RV32-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi s3, sp, 896
+; CHECK-RV32-NEXT: addi s3, sp, 1536
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (s3)
; CHECK-RV32-NEXT: csrr s3, vlenb
@@ -1798,7 +1932,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s3, s3, 2047
; CHECK-RV32-NEXT: addi s3, s3, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s3, sp, 832
+; CHECK-RV32-NEXT: addi s3, sp, 1472
; CHECK-RV32-NEXT: vle8.v v8, (s3)
; CHECK-RV32-NEXT: csrr s3, vlenb
; CHECK-RV32-NEXT: slli s3, s3, 3
@@ -1811,19 +1945,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s3, s3, 2047
; CHECK-RV32-NEXT: addi s3, s3, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s3, sp, 1632
+; CHECK-RV32-NEXT: addi s3, sp, 224
; CHECK-RV32-NEXT: vle8.v v8, (s3)
-; CHECK-RV32-NEXT: addi s3, sp, 128
+; CHECK-RV32-NEXT: addi s3, sp, 1792
; CHECK-RV32-NEXT: vle8.v v24, (s3)
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v16, (s2)
-; CHECK-RV32-NEXT: addi s2, sp, 64
+; CHECK-RV32-NEXT: addi s2, sp, 1728
; CHECK-RV32-NEXT: vle8.v v28, (s2)
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV32-NEXT: addi s2, sp, 1920
+; CHECK-RV32-NEXT: addi s2, sp, 512
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v12, (s2)
; CHECK-RV32-NEXT: csrr s2, vlenb
@@ -1835,7 +1969,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s2, s2, 2047
; CHECK-RV32-NEXT: addi s2, s2, 33
; CHECK-RV32-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s2, sp, 1856
+; CHECK-RV32-NEXT: addi s2, sp, 448
; CHECK-RV32-NEXT: vle8.v v20, (s2)
; CHECK-RV32-NEXT: csrr s2, vlenb
; CHECK-RV32-NEXT: slli s2, s2, 3
@@ -1861,10 +1995,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s2, s2, 2047
; CHECK-RV32-NEXT: addi s2, s2, 33
; CHECK-RV32-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi s2, sp, 1408
+; CHECK-RV32-NEXT: addi s2, sp, 1024
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v4, (s2)
-; CHECK-RV32-NEXT: addi s2, sp, 1344
+; CHECK-RV32-NEXT: addi s2, sp, 960
; CHECK-RV32-NEXT: vle8.v v8, (s2)
; CHECK-RV32-NEXT: csrr s2, vlenb
; CHECK-RV32-NEXT: slli s2, s2, 5
@@ -1875,20 +2009,21 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi s2, s2, 2047
; CHECK-RV32-NEXT: addi s2, s2, 33
; CHECK-RV32-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
-; CHECK-RV32-NEXT: addi s2, sp, 96
+; CHECK-RV32-NEXT: addi s2, sp, 1760
; CHECK-RV32-NEXT: vle8.v v8, (s2)
-; CHECK-RV32-NEXT: addi s2, sp, 384
+; CHECK-RV32-NEXT: addi s2, sp, 2047
+; CHECK-RV32-NEXT: addi s2, s2, 1
; CHECK-RV32-NEXT: vle8.v v0, (s2)
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v8, v24, a1
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v16, (s1)
-; CHECK-RV32-NEXT: addi s1, sp, 320
+; CHECK-RV32-NEXT: addi s1, sp, 1984
; CHECK-RV32-NEXT: vmv2r.v v12, v28
; CHECK-RV32-NEXT: vle8.v v28, (s1)
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v16, v12, a1
-; CHECK-RV32-NEXT: addi s1, sp, 736
+; CHECK-RV32-NEXT: addi s1, sp, 1120
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v24, (s1)
; CHECK-RV32-NEXT: csrr s1, vlenb
@@ -1918,7 +2053,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi a3, a3, 2047
; CHECK-RV32-NEXT: addi a3, a3, 33
; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi a3, sp, 1760
+; CHECK-RV32-NEXT: addi a3, sp, 96
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
@@ -1944,9 +2079,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi a3, a3, 2047
; CHECK-RV32-NEXT: addi a3, a3, 33
; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi a3, sp, 1376
-; CHECK-RV32-NEXT: vle8.v v8, (a3)
; CHECK-RV32-NEXT: addi a3, sp, 992
+; CHECK-RV32-NEXT: vle8.v v8, (a3)
+; CHECK-RV32-NEXT: addi a3, sp, 1376
; CHECK-RV32-NEXT: vle8.v v24, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 3
@@ -1984,7 +2119,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v24, v12, a1
-; CHECK-RV32-NEXT: addi a3, sp, 2016
+; CHECK-RV32-NEXT: addi a3, sp, 352
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v16, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
@@ -2015,7 +2150,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi a3, a3, 2047
; CHECK-RV32-NEXT: addi a3, a3, 33
; CHECK-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi a3, sp, 1504
+; CHECK-RV32-NEXT: addi a3, sp, 864
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
@@ -2039,9 +2174,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: addi a3, a3, 2047
; CHECK-RV32-NEXT: addi a3, a3, 33
; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi a3, sp, 352
+; CHECK-RV32-NEXT: addi a3, sp, 2016
; CHECK-RV32-NEXT: vle8.v v16, (a3)
-; CHECK-RV32-NEXT: addi a3, sp, 480
+; CHECK-RV32-NEXT: addi a3, sp, 1888
; CHECK-RV32-NEXT: vle8.v v8, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 3
@@ -2065,7 +2200,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v0, v28, a1
-; CHECK-RV32-NEXT: addi a3, sp, 1120
+; CHECK-RV32-NEXT: addi a3, sp, 736
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
@@ -2083,14 +2218,14 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vslideup.vx v0, v16, a4
-; CHECK-RV32-NEXT: addi a3, sp, 864
+; CHECK-RV32-NEXT: addi a3, sp, 1504
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vle8.v v24, (a3)
; CHECK-RV32-NEXT: vle8.v v8, (t3)
; CHECK-RV32-NEXT: addi a3, sp, 2047
; CHECK-RV32-NEXT: addi a3, a3, 33
; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: addi a3, sp, 1888
+; CHECK-RV32-NEXT: addi a3, sp, 480
; CHECK-RV32-NEXT: vle8.v v8, (a3)
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 4
@@ -2854,7 +2989,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
; CHECK-RV64-NEXT: vmv2r.v v22, v24
-; CHECK-RV64-NEXT: addi a3, sp, 672
+; CHECK-RV64-NEXT: addi a3, sp, 1056
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v16, (a3)
; CHECK-RV64-NEXT: csrr a5, vlenb
@@ -2954,7 +3089,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vmv2r.v v18, v20
; CHECK-RV64-NEXT: vslidedown.vx v20, v0, a1
; CHECK-RV64-NEXT: vmv2r.v v22, v24
-; CHECK-RV64-NEXT: addi a5, sp, 1696
+; CHECK-RV64-NEXT: addi a5, sp, 32
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v16, (a5)
; CHECK-RV64-NEXT: csrr a6, vlenb
@@ -3058,7 +3193,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
; CHECK-RV64-NEXT: vmv2r.v v22, v24
-; CHECK-RV64-NEXT: addi s5, sp, 1184
+; CHECK-RV64-NEXT: addi s5, sp, 544
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v16, (s5)
; CHECK-RV64-NEXT: csrr a6, vlenb
@@ -3118,7 +3253,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vslidedown.vx v20, v8, a1
; CHECK-RV64-NEXT: vmv2r.v v22, v24
-; CHECK-RV64-NEXT: addi a6, sp, 928
+; CHECK-RV64-NEXT: addi a6, sp, 1312
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v16, (a6)
; CHECK-RV64-NEXT: csrr a7, vlenb
@@ -3224,7 +3359,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vslidedown.vx v12, v0, a1
; CHECK-RV64-NEXT: vmv2r.v v14, v20
-; CHECK-RV64-NEXT: addi s4, sp, 160
+; CHECK-RV64-NEXT: addi s4, sp, 1568
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v8, (s4)
; CHECK-RV64-NEXT: csrr a7, vlenb
@@ -3276,7 +3411,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a1
; CHECK-RV64-NEXT: vmv2r.v v10, v12
-; CHECK-RV64-NEXT: addi a7, sp, 1952
+; CHECK-RV64-NEXT: addi a7, sp, 288
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v4, (a7)
; CHECK-RV64-NEXT: csrr t0, vlenb
@@ -3324,7 +3459,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a1
; CHECK-RV64-NEXT: vmv2r.v v10, v12
-; CHECK-RV64-NEXT: addi t0, sp, 1440
+; CHECK-RV64-NEXT: addi t0, sp, 800
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v4, (t0)
; CHECK-RV64-NEXT: csrr t1, vlenb
@@ -3376,7 +3511,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t1, t1, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi s3, sp, 544
+; CHECK-RV64-NEXT: addi s3, sp, 1184
; CHECK-RV64-NEXT: vsseg4e8.v v8, (s3)
; CHECK-RV64-NEXT: csrr t1, vlenb
; CHECK-RV64-NEXT: slli t1, t1, 3
@@ -3417,7 +3552,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vslidedown.vx v8, v16, a1
; CHECK-RV64-NEXT: vmv2r.v v10, v12
-; CHECK-RV64-NEXT: addi t1, sp, 416
+; CHECK-RV64-NEXT: addi t1, sp, 1824
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vsseg4e8.v v4, (t1)
; CHECK-RV64-NEXT: csrr t2, vlenb
@@ -3462,7 +3597,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t2, t2, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi s2, sp, 1568
+; CHECK-RV64-NEXT: addi s2, sp, 160
; CHECK-RV64-NEXT: vsseg4e8.v v8, (s2)
; CHECK-RV64-NEXT: csrr t2, vlenb
; CHECK-RV64-NEXT: slli t2, t2, 4
@@ -3505,7 +3640,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t2, t2, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi t2, sp, 1056
+; CHECK-RV64-NEXT: addi t2, sp, 672
; CHECK-RV64-NEXT: vsseg4e8.v v8, (t2)
; CHECK-RV64-NEXT: csrr t3, vlenb
; CHECK-RV64-NEXT: slli t3, t3, 4
@@ -3560,7 +3695,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t3, t3, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi t3, sp, 800
+; CHECK-RV64-NEXT: addi t3, sp, 1440
; CHECK-RV64-NEXT: vsseg4e8.v v8, (t3)
; CHECK-RV64-NEXT: csrr t4, vlenb
; CHECK-RV64-NEXT: slli t4, t4, 3
@@ -3600,7 +3735,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t4, t4, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi s1, sp, 32
+; CHECK-RV64-NEXT: addi s1, sp, 1696
; CHECK-RV64-NEXT: vsseg4e8.v v8, (s1)
; CHECK-RV64-NEXT: csrr t4, vlenb
; CHECK-RV64-NEXT: slli t4, t4, 3
@@ -3647,7 +3782,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t4, t4, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi t4, sp, 1824
+; CHECK-RV64-NEXT: addi t4, sp, 416
; CHECK-RV64-NEXT: vsseg4e8.v v8, (t4)
; CHECK-RV64-NEXT: csrr t5, vlenb
; CHECK-RV64-NEXT: slli t5, t5, 4
@@ -3690,7 +3825,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi t5, t5, 33
; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v14, v16
-; CHECK-RV64-NEXT: addi t6, sp, 1312
+; CHECK-RV64-NEXT: addi t6, sp, 928
; CHECK-RV64-NEXT: vsseg4e8.v v8, (t6)
; CHECK-RV64-NEXT: csrr t5, vlenb
; CHECK-RV64-NEXT: slli t5, t5, 8
@@ -3727,9 +3862,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vmv2r.v v12, v16
; CHECK-RV64-NEXT: vmv2r.v v14, v24
-; CHECK-RV64-NEXT: addi t5, sp, 288
+; CHECK-RV64-NEXT: addi t5, sp, 1952
; CHECK-RV64-NEXT: vsseg4e8.v v8, (t5)
-; CHECK-RV64-NEXT: addi s6, sp, 768
+; CHECK-RV64-NEXT: addi s6, sp, 1152
; CHECK-RV64-NEXT: vle8.v v8, (s6)
; CHECK-RV64-NEXT: csrr s6, vlenb
; CHECK-RV64-NEXT: slli s6, s6, 4
@@ -3742,7 +3877,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s6, s6, 2047
; CHECK-RV64-NEXT: addi s6, s6, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s6, sp, 704
+; CHECK-RV64-NEXT: addi s6, sp, 1088
; CHECK-RV64-NEXT: vle8.v v8, (s6)
; CHECK-RV64-NEXT: csrr s6, vlenb
; CHECK-RV64-NEXT: slli s6, s6, 3
@@ -3755,7 +3890,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s6, s6, 2047
; CHECK-RV64-NEXT: addi s6, s6, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s6, sp, 1792
+; CHECK-RV64-NEXT: addi s6, sp, 128
; CHECK-RV64-NEXT: vle8.v v8, (s6)
; CHECK-RV64-NEXT: csrr s6, vlenb
; CHECK-RV64-NEXT: slli s6, s6, 5
@@ -3766,7 +3901,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s6, s6, 2047
; CHECK-RV64-NEXT: addi s6, s6, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s6, sp, 1728
+; CHECK-RV64-NEXT: addi s6, sp, 64
; CHECK-RV64-NEXT: vle8.v v8, (s6)
; CHECK-RV64-NEXT: csrr s6, vlenb
; CHECK-RV64-NEXT: slli s6, s6, 3
@@ -3779,13 +3914,13 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s6, s6, 2047
; CHECK-RV64-NEXT: addi s6, s6, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s6, sp, 1280
+; CHECK-RV64-NEXT: addi s6, sp, 640
; CHECK-RV64-NEXT: vle8.v v16, (s6)
-; CHECK-RV64-NEXT: addi s6, sp, 1248
+; CHECK-RV64-NEXT: addi s6, sp, 608
; CHECK-RV64-NEXT: vle8.v v8, (s6)
-; CHECK-RV64-NEXT: addi s6, sp, 1216
+; CHECK-RV64-NEXT: addi s6, sp, 576
; CHECK-RV64-NEXT: vle8.v v12, (s6)
-; CHECK-RV64-NEXT: addi s6, sp, 1024
+; CHECK-RV64-NEXT: addi s6, sp, 1408
; CHECK-RV64-NEXT: vle8.v v20, (s6)
; CHECK-RV64-NEXT: csrr s6, vlenb
; CHECK-RV64-NEXT: slli s6, s6, 4
@@ -3800,7 +3935,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (s5)
-; CHECK-RV64-NEXT: addi s5, sp, 960
+; CHECK-RV64-NEXT: addi s5, sp, 1344
; CHECK-RV64-NEXT: vle8.v v20, (s5)
; CHECK-RV64-NEXT: csrr s5, vlenb
; CHECK-RV64-NEXT: slli s5, s5, 3
@@ -3814,10 +3949,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v16, v12, a1
; CHECK-RV64-NEXT: vmv.v.v v24, v16
-; CHECK-RV64-NEXT: addi s5, sp, 256
+; CHECK-RV64-NEXT: addi s5, sp, 1664
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v20, (s5)
-; CHECK-RV64-NEXT: addi s5, sp, 192
+; CHECK-RV64-NEXT: addi s5, sp, 1600
; CHECK-RV64-NEXT: vle8.v v16, (s5)
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v24, v8, a4
@@ -3827,8 +3962,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s5, s5, 2047
; CHECK-RV64-NEXT: addi s5, s5, 33
; CHECK-RV64-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi s5, sp, 2047
-; CHECK-RV64-NEXT: addi s5, s5, 1
+; CHECK-RV64-NEXT: addi s5, sp, 384
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v8, (s5)
; CHECK-RV64-NEXT: csrr s5, vlenb
@@ -3846,7 +3980,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s5, s5, 2047
; CHECK-RV64-NEXT: addi s5, s5, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s5, sp, 1984
+; CHECK-RV64-NEXT: addi s5, sp, 320
; CHECK-RV64-NEXT: vle8.v v8, (s5)
; CHECK-RV64-NEXT: csrr s5, vlenb
; CHECK-RV64-NEXT: slli s5, s5, 4
@@ -3861,9 +3995,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s5, s5, 2047
; CHECK-RV64-NEXT: addi s5, s5, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s5, sp, 224
+; CHECK-RV64-NEXT: addi s5, sp, 1632
; CHECK-RV64-NEXT: vle8.v v8, (s5)
-; CHECK-RV64-NEXT: addi s5, sp, 1536
+; CHECK-RV64-NEXT: addi s5, sp, 896
; CHECK-RV64-NEXT: vle8.v v12, (s5)
; CHECK-RV64-NEXT: csrr s5, vlenb
; CHECK-RV64-NEXT: slli s5, s5, 3
@@ -3882,7 +4016,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vslideup.vx v8, v20, a1
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v24, (s4)
-; CHECK-RV64-NEXT: addi s4, sp, 1472
+; CHECK-RV64-NEXT: addi s4, sp, 832
; CHECK-RV64-NEXT: vle8.v v12, (s4)
; CHECK-RV64-NEXT: csrr s4, vlenb
; CHECK-RV64-NEXT: slli s4, s4, 5
@@ -3898,10 +4032,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v24, v16, a1
; CHECK-RV64-NEXT: vmv.v.v v0, v24
-; CHECK-RV64-NEXT: addi s4, sp, 640
+; CHECK-RV64-NEXT: addi s4, sp, 1280
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v20, (s4)
-; CHECK-RV64-NEXT: addi s4, sp, 576
+; CHECK-RV64-NEXT: addi s4, sp, 1216
; CHECK-RV64-NEXT: vle8.v v24, (s4)
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v0, v8, a4
@@ -3918,7 +4052,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s4, s4, 2047
; CHECK-RV64-NEXT: addi s4, s4, 33
; CHECK-RV64-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi s4, sp, 512
+; CHECK-RV64-NEXT: addi s4, sp, 1920
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v8, (s4)
; CHECK-RV64-NEXT: csrr s4, vlenb
@@ -3932,7 +4066,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s4, s4, 2047
; CHECK-RV64-NEXT: addi s4, s4, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s4, sp, 448
+; CHECK-RV64-NEXT: addi s4, sp, 1856
; CHECK-RV64-NEXT: vle8.v v8, (s4)
; CHECK-RV64-NEXT: csrr s4, vlenb
; CHECK-RV64-NEXT: slli s4, s4, 3
@@ -3945,19 +4079,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s4, s4, 2047
; CHECK-RV64-NEXT: addi s4, s4, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s4, sp, 608
+; CHECK-RV64-NEXT: addi s4, sp, 1248
; CHECK-RV64-NEXT: vle8.v v8, (s4)
-; CHECK-RV64-NEXT: addi s4, sp, 1664
+; CHECK-RV64-NEXT: addi s4, sp, 256
; CHECK-RV64-NEXT: vle8.v v16, (s4)
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v20, a1
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v0, (s3)
-; CHECK-RV64-NEXT: addi s3, sp, 1600
+; CHECK-RV64-NEXT: addi s3, sp, 192
; CHECK-RV64-NEXT: vle8.v v20, (s3)
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v0, v24, a1
-; CHECK-RV64-NEXT: addi s3, sp, 1152
+; CHECK-RV64-NEXT: addi s3, sp, 768
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v12, (s3)
; CHECK-RV64-NEXT: csrr s3, vlenb
@@ -3973,7 +4107,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s3, s3, 2047
; CHECK-RV64-NEXT: addi s3, s3, 33
; CHECK-RV64-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s3, sp, 1088
+; CHECK-RV64-NEXT: addi s3, sp, 704
; CHECK-RV64-NEXT: vle8.v v24, (s3)
; CHECK-RV64-NEXT: csrr s3, vlenb
; CHECK-RV64-NEXT: slli s3, s3, 4
@@ -3997,7 +4131,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s3, s3, 2047
; CHECK-RV64-NEXT: addi s3, s3, 33
; CHECK-RV64-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi s3, sp, 896
+; CHECK-RV64-NEXT: addi s3, sp, 1536
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v8, (s3)
; CHECK-RV64-NEXT: csrr s3, vlenb
@@ -4011,7 +4145,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s3, s3, 2047
; CHECK-RV64-NEXT: addi s3, s3, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s3, sp, 832
+; CHECK-RV64-NEXT: addi s3, sp, 1472
; CHECK-RV64-NEXT: vle8.v v8, (s3)
; CHECK-RV64-NEXT: csrr s3, vlenb
; CHECK-RV64-NEXT: slli s3, s3, 3
@@ -4024,19 +4158,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s3, s3, 2047
; CHECK-RV64-NEXT: addi s3, s3, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s3, sp, 1632
+; CHECK-RV64-NEXT: addi s3, sp, 224
; CHECK-RV64-NEXT: vle8.v v8, (s3)
-; CHECK-RV64-NEXT: addi s3, sp, 128
+; CHECK-RV64-NEXT: addi s3, sp, 1792
; CHECK-RV64-NEXT: vle8.v v24, (s3)
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v16, a1
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (s2)
-; CHECK-RV64-NEXT: addi s2, sp, 64
+; CHECK-RV64-NEXT: addi s2, sp, 1728
; CHECK-RV64-NEXT: vle8.v v28, (s2)
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v16, v20, a1
-; CHECK-RV64-NEXT: addi s2, sp, 1920
+; CHECK-RV64-NEXT: addi s2, sp, 512
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v12, (s2)
; CHECK-RV64-NEXT: csrr s2, vlenb
@@ -4048,7 +4182,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s2, s2, 2047
; CHECK-RV64-NEXT: addi s2, s2, 33
; CHECK-RV64-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s2, sp, 1856
+; CHECK-RV64-NEXT: addi s2, sp, 448
; CHECK-RV64-NEXT: vle8.v v20, (s2)
; CHECK-RV64-NEXT: csrr s2, vlenb
; CHECK-RV64-NEXT: slli s2, s2, 3
@@ -4074,10 +4208,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s2, s2, 2047
; CHECK-RV64-NEXT: addi s2, s2, 33
; CHECK-RV64-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi s2, sp, 1408
+; CHECK-RV64-NEXT: addi s2, sp, 1024
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v4, (s2)
-; CHECK-RV64-NEXT: addi s2, sp, 1344
+; CHECK-RV64-NEXT: addi s2, sp, 960
; CHECK-RV64-NEXT: vle8.v v8, (s2)
; CHECK-RV64-NEXT: csrr s2, vlenb
; CHECK-RV64-NEXT: slli s2, s2, 5
@@ -4088,20 +4222,21 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi s2, s2, 2047
; CHECK-RV64-NEXT: addi s2, s2, 33
; CHECK-RV64-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
-; CHECK-RV64-NEXT: addi s2, sp, 96
+; CHECK-RV64-NEXT: addi s2, sp, 1760
; CHECK-RV64-NEXT: vle8.v v8, (s2)
-; CHECK-RV64-NEXT: addi s2, sp, 384
+; CHECK-RV64-NEXT: addi s2, sp, 2047
+; CHECK-RV64-NEXT: addi s2, s2, 1
; CHECK-RV64-NEXT: vle8.v v0, (s2)
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v8, v24, a1
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (s1)
-; CHECK-RV64-NEXT: addi s1, sp, 320
+; CHECK-RV64-NEXT: addi s1, sp, 1984
; CHECK-RV64-NEXT: vmv2r.v v12, v28
; CHECK-RV64-NEXT: vle8.v v28, (s1)
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v16, v12, a1
-; CHECK-RV64-NEXT: addi s1, sp, 736
+; CHECK-RV64-NEXT: addi s1, sp, 1120
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v24, (s1)
; CHECK-RV64-NEXT: csrr s1, vlenb
@@ -4131,7 +4266,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi a3, a3, 2047
; CHECK-RV64-NEXT: addi a3, a3, 33
; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi a3, sp, 1760
+; CHECK-RV64-NEXT: addi a3, sp, 96
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v8, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
@@ -4157,9 +4292,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi a3, a3, 2047
; CHECK-RV64-NEXT: addi a3, a3, 33
; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi a3, sp, 1376
-; CHECK-RV64-NEXT: vle8.v v8, (a3)
; CHECK-RV64-NEXT: addi a3, sp, 992
+; CHECK-RV64-NEXT: vle8.v v8, (a3)
+; CHECK-RV64-NEXT: addi a3, sp, 1376
; CHECK-RV64-NEXT: vle8.v v24, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: slli a3, a3, 3
@@ -4197,7 +4332,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v24, v12, a1
-; CHECK-RV64-NEXT: addi a3, sp, 2016
+; CHECK-RV64-NEXT: addi a3, sp, 352
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
@@ -4228,7 +4363,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi a3, a3, 2047
; CHECK-RV64-NEXT: addi a3, a3, 33
; CHECK-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi a3, sp, 1504
+; CHECK-RV64-NEXT: addi a3, sp, 864
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v8, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
@@ -4252,9 +4387,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: addi a3, a3, 2047
; CHECK-RV64-NEXT: addi a3, a3, 33
; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi a3, sp, 352
+; CHECK-RV64-NEXT: addi a3, sp, 2016
; CHECK-RV64-NEXT: vle8.v v16, (a3)
-; CHECK-RV64-NEXT: addi a3, sp, 480
+; CHECK-RV64-NEXT: addi a3, sp, 1888
; CHECK-RV64-NEXT: vle8.v v8, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: slli a3, a3, 3
@@ -4278,7 +4413,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v0, v28, a1
-; CHECK-RV64-NEXT: addi a3, sp, 1120
+; CHECK-RV64-NEXT: addi a3, sp, 736
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v8, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
@@ -4296,14 +4431,14 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vslideup.vx v0, v16, a4
-; CHECK-RV64-NEXT: addi a3, sp, 864
+; CHECK-RV64-NEXT: addi a3, sp, 1504
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vle8.v v24, (a3)
; CHECK-RV64-NEXT: vle8.v v8, (t3)
; CHECK-RV64-NEXT: addi a3, sp, 2047
; CHECK-RV64-NEXT: addi a3, a3, 33
; CHECK-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: addi a3, sp, 1888
+; CHECK-RV64-NEXT: addi a3, sp, 480
; CHECK-RV64-NEXT: vle8.v v8, (a3)
; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: slli a3, a3, 4
@@ -5067,7 +5202,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
; ZVBB-RV32-NEXT: vmv2r.v v22, v24
-; ZVBB-RV32-NEXT: addi a3, sp, 672
+; ZVBB-RV32-NEXT: addi a3, sp, 1056
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v16, (a3)
; ZVBB-RV32-NEXT: csrr a5, vlenb
@@ -5167,7 +5302,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vmv2r.v v18, v20
; ZVBB-RV32-NEXT: vslidedown.vx v20, v0, a1
; ZVBB-RV32-NEXT: vmv2r.v v22, v24
-; ZVBB-RV32-NEXT: addi a5, sp, 1696
+; ZVBB-RV32-NEXT: addi a5, sp, 32
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v16, (a5)
; ZVBB-RV32-NEXT: csrr a6, vlenb
@@ -5271,7 +5406,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
; ZVBB-RV32-NEXT: vmv2r.v v22, v24
-; ZVBB-RV32-NEXT: addi s5, sp, 1184
+; ZVBB-RV32-NEXT: addi s5, sp, 544
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v16, (s5)
; ZVBB-RV32-NEXT: csrr a6, vlenb
@@ -5331,7 +5466,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vslidedown.vx v20, v8, a1
; ZVBB-RV32-NEXT: vmv2r.v v22, v24
-; ZVBB-RV32-NEXT: addi a6, sp, 928
+; ZVBB-RV32-NEXT: addi a6, sp, 1312
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v16, (a6)
; ZVBB-RV32-NEXT: csrr a7, vlenb
@@ -5437,7 +5572,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vslidedown.vx v12, v0, a1
; ZVBB-RV32-NEXT: vmv2r.v v14, v20
-; ZVBB-RV32-NEXT: addi s4, sp, 160
+; ZVBB-RV32-NEXT: addi s4, sp, 1568
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s4)
; ZVBB-RV32-NEXT: csrr a7, vlenb
@@ -5489,7 +5624,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a1
; ZVBB-RV32-NEXT: vmv2r.v v10, v12
-; ZVBB-RV32-NEXT: addi a7, sp, 1952
+; ZVBB-RV32-NEXT: addi a7, sp, 288
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v4, (a7)
; ZVBB-RV32-NEXT: csrr t0, vlenb
@@ -5537,7 +5672,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a1
; ZVBB-RV32-NEXT: vmv2r.v v10, v12
-; ZVBB-RV32-NEXT: addi t0, sp, 1440
+; ZVBB-RV32-NEXT: addi t0, sp, 800
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v4, (t0)
; ZVBB-RV32-NEXT: csrr t1, vlenb
@@ -5589,7 +5724,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t1, t1, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi s3, sp, 544
+; ZVBB-RV32-NEXT: addi s3, sp, 1184
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s3)
; ZVBB-RV32-NEXT: csrr t1, vlenb
; ZVBB-RV32-NEXT: slli t1, t1, 3
@@ -5630,7 +5765,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vslidedown.vx v8, v16, a1
; ZVBB-RV32-NEXT: vmv2r.v v10, v12
-; ZVBB-RV32-NEXT: addi t1, sp, 416
+; ZVBB-RV32-NEXT: addi t1, sp, 1824
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vsseg4e8.v v4, (t1)
; ZVBB-RV32-NEXT: csrr t2, vlenb
@@ -5675,7 +5810,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t2, t2, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi s2, sp, 1568
+; ZVBB-RV32-NEXT: addi s2, sp, 160
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s2)
; ZVBB-RV32-NEXT: csrr t2, vlenb
; ZVBB-RV32-NEXT: slli t2, t2, 4
@@ -5718,7 +5853,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t2, t2, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi t2, sp, 1056
+; ZVBB-RV32-NEXT: addi t2, sp, 672
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t2)
; ZVBB-RV32-NEXT: csrr t3, vlenb
; ZVBB-RV32-NEXT: slli t3, t3, 4
@@ -5773,7 +5908,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t3, t3, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi t3, sp, 800
+; ZVBB-RV32-NEXT: addi t3, sp, 1440
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t3)
; ZVBB-RV32-NEXT: csrr t4, vlenb
; ZVBB-RV32-NEXT: slli t4, t4, 3
@@ -5813,7 +5948,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t4, t4, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi s1, sp, 32
+; ZVBB-RV32-NEXT: addi s1, sp, 1696
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (s1)
; ZVBB-RV32-NEXT: csrr t4, vlenb
; ZVBB-RV32-NEXT: slli t4, t4, 3
@@ -5860,7 +5995,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t4, t4, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi t4, sp, 1824
+; ZVBB-RV32-NEXT: addi t4, sp, 416
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t4)
; ZVBB-RV32-NEXT: csrr t5, vlenb
; ZVBB-RV32-NEXT: slli t5, t5, 4
@@ -5903,7 +6038,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi t5, t5, 33
; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v14, v16
-; ZVBB-RV32-NEXT: addi t6, sp, 1312
+; ZVBB-RV32-NEXT: addi t6, sp, 928
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t6)
; ZVBB-RV32-NEXT: csrr t5, vlenb
; ZVBB-RV32-NEXT: slli t5, t5, 8
@@ -5940,9 +6075,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; ZVBB-RV32-NEXT: vmv2r.v v12, v16
; ZVBB-RV32-NEXT: vmv2r.v v14, v24
-; ZVBB-RV32-NEXT: addi t5, sp, 288
+; ZVBB-RV32-NEXT: addi t5, sp, 1952
; ZVBB-RV32-NEXT: vsseg4e8.v v8, (t5)
-; ZVBB-RV32-NEXT: addi s6, sp, 768
+; ZVBB-RV32-NEXT: addi s6, sp, 1152
; ZVBB-RV32-NEXT: vle8.v v8, (s6)
; ZVBB-RV32-NEXT: csrr s6, vlenb
; ZVBB-RV32-NEXT: slli s6, s6, 4
@@ -5955,7 +6090,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s6, s6, 2047
; ZVBB-RV32-NEXT: addi s6, s6, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s6, sp, 704
+; ZVBB-RV32-NEXT: addi s6, sp, 1088
; ZVBB-RV32-NEXT: vle8.v v8, (s6)
; ZVBB-RV32-NEXT: csrr s6, vlenb
; ZVBB-RV32-NEXT: slli s6, s6, 3
@@ -5968,7 +6103,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s6, s6, 2047
; ZVBB-RV32-NEXT: addi s6, s6, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s6, sp, 1792
+; ZVBB-RV32-NEXT: addi s6, sp, 128
; ZVBB-RV32-NEXT: vle8.v v8, (s6)
; ZVBB-RV32-NEXT: csrr s6, vlenb
; ZVBB-RV32-NEXT: slli s6, s6, 5
@@ -5979,7 +6114,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s6, s6, 2047
; ZVBB-RV32-NEXT: addi s6, s6, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s6, sp, 1728
+; ZVBB-RV32-NEXT: addi s6, sp, 64
; ZVBB-RV32-NEXT: vle8.v v8, (s6)
; ZVBB-RV32-NEXT: csrr s6, vlenb
; ZVBB-RV32-NEXT: slli s6, s6, 3
@@ -5992,13 +6127,13 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s6, s6, 2047
; ZVBB-RV32-NEXT: addi s6, s6, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s6, sp, 1280
+; ZVBB-RV32-NEXT: addi s6, sp, 640
; ZVBB-RV32-NEXT: vle8.v v16, (s6)
-; ZVBB-RV32-NEXT: addi s6, sp, 1248
+; ZVBB-RV32-NEXT: addi s6, sp, 608
; ZVBB-RV32-NEXT: vle8.v v8, (s6)
-; ZVBB-RV32-NEXT: addi s6, sp, 1216
+; ZVBB-RV32-NEXT: addi s6, sp, 576
; ZVBB-RV32-NEXT: vle8.v v12, (s6)
-; ZVBB-RV32-NEXT: addi s6, sp, 1024
+; ZVBB-RV32-NEXT: addi s6, sp, 1408
; ZVBB-RV32-NEXT: vle8.v v20, (s6)
; ZVBB-RV32-NEXT: csrr s6, vlenb
; ZVBB-RV32-NEXT: slli s6, s6, 4
@@ -6013,7 +6148,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vslideup.vx v8, v16, a1
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v16, (s5)
-; ZVBB-RV32-NEXT: addi s5, sp, 960
+; ZVBB-RV32-NEXT: addi s5, sp, 1344
; ZVBB-RV32-NEXT: vle8.v v20, (s5)
; ZVBB-RV32-NEXT: csrr s5, vlenb
; ZVBB-RV32-NEXT: slli s5, s5, 3
@@ -6027,10 +6162,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v16, v12, a1
; ZVBB-RV32-NEXT: vmv.v.v v24, v16
-; ZVBB-RV32-NEXT: addi s5, sp, 256
+; ZVBB-RV32-NEXT: addi s5, sp, 1664
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v20, (s5)
-; ZVBB-RV32-NEXT: addi s5, sp, 192
+; ZVBB-RV32-NEXT: addi s5, sp, 1600
; ZVBB-RV32-NEXT: vle8.v v16, (s5)
; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v24, v8, a4
@@ -6040,8 +6175,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s5, s5, 2047
; ZVBB-RV32-NEXT: addi s5, s5, 33
; ZVBB-RV32-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s5, sp, 2047
-; ZVBB-RV32-NEXT: addi s5, s5, 1
+; ZVBB-RV32-NEXT: addi s5, sp, 384
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v8, (s5)
; ZVBB-RV32-NEXT: csrr s5, vlenb
@@ -6059,7 +6193,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s5, s5, 2047
; ZVBB-RV32-NEXT: addi s5, s5, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s5, sp, 1984
+; ZVBB-RV32-NEXT: addi s5, sp, 320
; ZVBB-RV32-NEXT: vle8.v v8, (s5)
; ZVBB-RV32-NEXT: csrr s5, vlenb
; ZVBB-RV32-NEXT: slli s5, s5, 4
@@ -6074,9 +6208,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s5, s5, 2047
; ZVBB-RV32-NEXT: addi s5, s5, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s5, sp, 224
+; ZVBB-RV32-NEXT: addi s5, sp, 1632
; ZVBB-RV32-NEXT: vle8.v v8, (s5)
-; ZVBB-RV32-NEXT: addi s5, sp, 1536
+; ZVBB-RV32-NEXT: addi s5, sp, 896
; ZVBB-RV32-NEXT: vle8.v v12, (s5)
; ZVBB-RV32-NEXT: csrr s5, vlenb
; ZVBB-RV32-NEXT: slli s5, s5, 3
@@ -6095,7 +6229,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vslideup.vx v8, v20, a1
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v24, (s4)
-; ZVBB-RV32-NEXT: addi s4, sp, 1472
+; ZVBB-RV32-NEXT: addi s4, sp, 832
; ZVBB-RV32-NEXT: vle8.v v12, (s4)
; ZVBB-RV32-NEXT: csrr s4, vlenb
; ZVBB-RV32-NEXT: slli s4, s4, 5
@@ -6111,10 +6245,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v24, v16, a1
; ZVBB-RV32-NEXT: vmv.v.v v0, v24
-; ZVBB-RV32-NEXT: addi s4, sp, 640
+; ZVBB-RV32-NEXT: addi s4, sp, 1280
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v20, (s4)
-; ZVBB-RV32-NEXT: addi s4, sp, 576
+; ZVBB-RV32-NEXT: addi s4, sp, 1216
; ZVBB-RV32-NEXT: vle8.v v24, (s4)
; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v0, v8, a4
@@ -6131,7 +6265,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s4, s4, 2047
; ZVBB-RV32-NEXT: addi s4, s4, 33
; ZVBB-RV32-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s4, sp, 512
+; ZVBB-RV32-NEXT: addi s4, sp, 1920
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v8, (s4)
; ZVBB-RV32-NEXT: csrr s4, vlenb
@@ -6145,7 +6279,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s4, s4, 2047
; ZVBB-RV32-NEXT: addi s4, s4, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s4, sp, 448
+; ZVBB-RV32-NEXT: addi s4, sp, 1856
; ZVBB-RV32-NEXT: vle8.v v8, (s4)
; ZVBB-RV32-NEXT: csrr s4, vlenb
; ZVBB-RV32-NEXT: slli s4, s4, 3
@@ -6158,19 +6292,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s4, s4, 2047
; ZVBB-RV32-NEXT: addi s4, s4, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s4, sp, 608
+; ZVBB-RV32-NEXT: addi s4, sp, 1248
; ZVBB-RV32-NEXT: vle8.v v8, (s4)
-; ZVBB-RV32-NEXT: addi s4, sp, 1664
+; ZVBB-RV32-NEXT: addi s4, sp, 256
; ZVBB-RV32-NEXT: vle8.v v16, (s4)
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v8, v20, a1
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v0, (s3)
-; ZVBB-RV32-NEXT: addi s3, sp, 1600
+; ZVBB-RV32-NEXT: addi s3, sp, 192
; ZVBB-RV32-NEXT: vle8.v v20, (s3)
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v0, v24, a1
-; ZVBB-RV32-NEXT: addi s3, sp, 1152
+; ZVBB-RV32-NEXT: addi s3, sp, 768
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v12, (s3)
; ZVBB-RV32-NEXT: csrr s3, vlenb
@@ -6186,7 +6320,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s3, s3, 2047
; ZVBB-RV32-NEXT: addi s3, s3, 33
; ZVBB-RV32-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s3, sp, 1088
+; ZVBB-RV32-NEXT: addi s3, sp, 704
; ZVBB-RV32-NEXT: vle8.v v24, (s3)
; ZVBB-RV32-NEXT: csrr s3, vlenb
; ZVBB-RV32-NEXT: slli s3, s3, 4
@@ -6210,7 +6344,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s3, s3, 2047
; ZVBB-RV32-NEXT: addi s3, s3, 33
; ZVBB-RV32-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s3, sp, 896
+; ZVBB-RV32-NEXT: addi s3, sp, 1536
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v8, (s3)
; ZVBB-RV32-NEXT: csrr s3, vlenb
@@ -6224,7 +6358,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s3, s3, 2047
; ZVBB-RV32-NEXT: addi s3, s3, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s3, sp, 832
+; ZVBB-RV32-NEXT: addi s3, sp, 1472
; ZVBB-RV32-NEXT: vle8.v v8, (s3)
; ZVBB-RV32-NEXT: csrr s3, vlenb
; ZVBB-RV32-NEXT: slli s3, s3, 3
@@ -6237,19 +6371,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s3, s3, 2047
; ZVBB-RV32-NEXT: addi s3, s3, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s3, sp, 1632
+; ZVBB-RV32-NEXT: addi s3, sp, 224
; ZVBB-RV32-NEXT: vle8.v v8, (s3)
-; ZVBB-RV32-NEXT: addi s3, sp, 128
+; ZVBB-RV32-NEXT: addi s3, sp, 1792
; ZVBB-RV32-NEXT: vle8.v v24, (s3)
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v8, v16, a1
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v16, (s2)
-; ZVBB-RV32-NEXT: addi s2, sp, 64
+; ZVBB-RV32-NEXT: addi s2, sp, 1728
; ZVBB-RV32-NEXT: vle8.v v28, (s2)
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v16, v20, a1
-; ZVBB-RV32-NEXT: addi s2, sp, 1920
+; ZVBB-RV32-NEXT: addi s2, sp, 512
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v12, (s2)
; ZVBB-RV32-NEXT: csrr s2, vlenb
@@ -6261,7 +6395,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s2, s2, 2047
; ZVBB-RV32-NEXT: addi s2, s2, 33
; ZVBB-RV32-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s2, sp, 1856
+; ZVBB-RV32-NEXT: addi s2, sp, 448
; ZVBB-RV32-NEXT: vle8.v v20, (s2)
; ZVBB-RV32-NEXT: csrr s2, vlenb
; ZVBB-RV32-NEXT: slli s2, s2, 3
@@ -6287,10 +6421,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s2, s2, 2047
; ZVBB-RV32-NEXT: addi s2, s2, 33
; ZVBB-RV32-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s2, sp, 1408
+; ZVBB-RV32-NEXT: addi s2, sp, 1024
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v4, (s2)
-; ZVBB-RV32-NEXT: addi s2, sp, 1344
+; ZVBB-RV32-NEXT: addi s2, sp, 960
; ZVBB-RV32-NEXT: vle8.v v8, (s2)
; ZVBB-RV32-NEXT: csrr s2, vlenb
; ZVBB-RV32-NEXT: slli s2, s2, 5
@@ -6301,20 +6435,21 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi s2, s2, 2047
; ZVBB-RV32-NEXT: addi s2, s2, 33
; ZVBB-RV32-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
-; ZVBB-RV32-NEXT: addi s2, sp, 96
+; ZVBB-RV32-NEXT: addi s2, sp, 1760
; ZVBB-RV32-NEXT: vle8.v v8, (s2)
-; ZVBB-RV32-NEXT: addi s2, sp, 384
+; ZVBB-RV32-NEXT: addi s2, sp, 2047
+; ZVBB-RV32-NEXT: addi s2, s2, 1
; ZVBB-RV32-NEXT: vle8.v v0, (s2)
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v8, v24, a1
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v16, (s1)
-; ZVBB-RV32-NEXT: addi s1, sp, 320
+; ZVBB-RV32-NEXT: addi s1, sp, 1984
; ZVBB-RV32-NEXT: vmv2r.v v12, v28
; ZVBB-RV32-NEXT: vle8.v v28, (s1)
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v16, v12, a1
-; ZVBB-RV32-NEXT: addi s1, sp, 736
+; ZVBB-RV32-NEXT: addi s1, sp, 1120
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v24, (s1)
; ZVBB-RV32-NEXT: csrr s1, vlenb
@@ -6344,7 +6479,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi a3, a3, 2047
; ZVBB-RV32-NEXT: addi a3, a3, 33
; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi a3, sp, 1760
+; ZVBB-RV32-NEXT: addi a3, sp, 96
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v8, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
@@ -6370,9 +6505,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi a3, a3, 2047
; ZVBB-RV32-NEXT: addi a3, a3, 33
; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi a3, sp, 1376
-; ZVBB-RV32-NEXT: vle8.v v8, (a3)
; ZVBB-RV32-NEXT: addi a3, sp, 992
+; ZVBB-RV32-NEXT: vle8.v v8, (a3)
+; ZVBB-RV32-NEXT: addi a3, sp, 1376
; ZVBB-RV32-NEXT: vle8.v v24, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
; ZVBB-RV32-NEXT: slli a3, a3, 3
@@ -6410,7 +6545,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v24, v12, a1
-; ZVBB-RV32-NEXT: addi a3, sp, 2016
+; ZVBB-RV32-NEXT: addi a3, sp, 352
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v16, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
@@ -6441,7 +6576,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi a3, a3, 2047
; ZVBB-RV32-NEXT: addi a3, a3, 33
; ZVBB-RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi a3, sp, 1504
+; ZVBB-RV32-NEXT: addi a3, sp, 864
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v8, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
@@ -6465,9 +6600,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: addi a3, a3, 2047
; ZVBB-RV32-NEXT: addi a3, a3, 33
; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi a3, sp, 352
+; ZVBB-RV32-NEXT: addi a3, sp, 2016
; ZVBB-RV32-NEXT: vle8.v v16, (a3)
-; ZVBB-RV32-NEXT: addi a3, sp, 480
+; ZVBB-RV32-NEXT: addi a3, sp, 1888
; ZVBB-RV32-NEXT: vle8.v v8, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
; ZVBB-RV32-NEXT: slli a3, a3, 3
@@ -6491,7 +6626,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVBB-RV32-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v0, v28, a1
-; ZVBB-RV32-NEXT: addi a3, sp, 1120
+; ZVBB-RV32-NEXT: addi a3, sp, 736
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v8, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
@@ -6509,14 +6644,14 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVBB-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; ZVBB-RV32-NEXT: vslideup.vx v0, v16, a4
-; ZVBB-RV32-NEXT: addi a3, sp, 864
+; ZVBB-RV32-NEXT: addi a3, sp, 1504
; ZVBB-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV32-NEXT: vle8.v v24, (a3)
; ZVBB-RV32-NEXT: vle8.v v8, (t3)
; ZVBB-RV32-NEXT: addi a3, sp, 2047
; ZVBB-RV32-NEXT: addi a3, a3, 33
; ZVBB-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV32-NEXT: addi a3, sp, 1888
+; ZVBB-RV32-NEXT: addi a3, sp, 480
; ZVBB-RV32-NEXT: vle8.v v8, (a3)
; ZVBB-RV32-NEXT: csrr a3, vlenb
; ZVBB-RV32-NEXT: slli a3, a3, 4
@@ -7280,7 +7415,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
; ZVBB-RV64-NEXT: vmv2r.v v22, v24
-; ZVBB-RV64-NEXT: addi a3, sp, 672
+; ZVBB-RV64-NEXT: addi a3, sp, 1056
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v16, (a3)
; ZVBB-RV64-NEXT: csrr a5, vlenb
@@ -7380,7 +7515,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vmv2r.v v18, v20
; ZVBB-RV64-NEXT: vslidedown.vx v20, v0, a1
; ZVBB-RV64-NEXT: vmv2r.v v22, v24
-; ZVBB-RV64-NEXT: addi a5, sp, 1696
+; ZVBB-RV64-NEXT: addi a5, sp, 32
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v16, (a5)
; ZVBB-RV64-NEXT: csrr a6, vlenb
@@ -7484,7 +7619,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
; ZVBB-RV64-NEXT: vmv2r.v v22, v24
-; ZVBB-RV64-NEXT: addi s5, sp, 1184
+; ZVBB-RV64-NEXT: addi s5, sp, 544
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v16, (s5)
; ZVBB-RV64-NEXT: csrr a6, vlenb
@@ -7544,7 +7679,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vslidedown.vx v20, v8, a1
; ZVBB-RV64-NEXT: vmv2r.v v22, v24
-; ZVBB-RV64-NEXT: addi a6, sp, 928
+; ZVBB-RV64-NEXT: addi a6, sp, 1312
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v16, (a6)
; ZVBB-RV64-NEXT: csrr a7, vlenb
@@ -7650,7 +7785,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v0, (a7) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vslidedown.vx v12, v0, a1
; ZVBB-RV64-NEXT: vmv2r.v v14, v20
-; ZVBB-RV64-NEXT: addi s4, sp, 160
+; ZVBB-RV64-NEXT: addi s4, sp, 1568
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s4)
; ZVBB-RV64-NEXT: csrr a7, vlenb
@@ -7702,7 +7837,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v16, (a7) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a1
; ZVBB-RV64-NEXT: vmv2r.v v10, v12
-; ZVBB-RV64-NEXT: addi a7, sp, 1952
+; ZVBB-RV64-NEXT: addi a7, sp, 288
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v4, (a7)
; ZVBB-RV64-NEXT: csrr t0, vlenb
@@ -7750,7 +7885,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a1
; ZVBB-RV64-NEXT: vmv2r.v v10, v12
-; ZVBB-RV64-NEXT: addi t0, sp, 1440
+; ZVBB-RV64-NEXT: addi t0, sp, 800
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v4, (t0)
; ZVBB-RV64-NEXT: csrr t1, vlenb
@@ -7802,7 +7937,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t1, t1, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi s3, sp, 544
+; ZVBB-RV64-NEXT: addi s3, sp, 1184
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s3)
; ZVBB-RV64-NEXT: csrr t1, vlenb
; ZVBB-RV64-NEXT: slli t1, t1, 3
@@ -7843,7 +7978,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vslidedown.vx v8, v16, a1
; ZVBB-RV64-NEXT: vmv2r.v v10, v12
-; ZVBB-RV64-NEXT: addi t1, sp, 416
+; ZVBB-RV64-NEXT: addi t1, sp, 1824
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vsseg4e8.v v4, (t1)
; ZVBB-RV64-NEXT: csrr t2, vlenb
@@ -7888,7 +8023,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t2, t2, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi s2, sp, 1568
+; ZVBB-RV64-NEXT: addi s2, sp, 160
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s2)
; ZVBB-RV64-NEXT: csrr t2, vlenb
; ZVBB-RV64-NEXT: slli t2, t2, 4
@@ -7931,7 +8066,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t2, t2, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi t2, sp, 1056
+; ZVBB-RV64-NEXT: addi t2, sp, 672
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t2)
; ZVBB-RV64-NEXT: csrr t3, vlenb
; ZVBB-RV64-NEXT: slli t3, t3, 4
@@ -7986,7 +8121,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t3, t3, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t3) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi t3, sp, 800
+; ZVBB-RV64-NEXT: addi t3, sp, 1440
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t3)
; ZVBB-RV64-NEXT: csrr t4, vlenb
; ZVBB-RV64-NEXT: slli t4, t4, 3
@@ -8026,7 +8161,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t4, t4, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi s1, sp, 32
+; ZVBB-RV64-NEXT: addi s1, sp, 1696
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (s1)
; ZVBB-RV64-NEXT: csrr t4, vlenb
; ZVBB-RV64-NEXT: slli t4, t4, 3
@@ -8073,7 +8208,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t4, t4, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi t4, sp, 1824
+; ZVBB-RV64-NEXT: addi t4, sp, 416
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t4)
; ZVBB-RV64-NEXT: csrr t5, vlenb
; ZVBB-RV64-NEXT: slli t5, t5, 4
@@ -8116,7 +8251,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi t5, t5, 33
; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v14, v16
-; ZVBB-RV64-NEXT: addi t6, sp, 1312
+; ZVBB-RV64-NEXT: addi t6, sp, 928
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t6)
; ZVBB-RV64-NEXT: csrr t5, vlenb
; ZVBB-RV64-NEXT: slli t5, t5, 8
@@ -8153,9 +8288,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vl8r.v v16, (t5) # vscale x 64-byte Folded Reload
; ZVBB-RV64-NEXT: vmv2r.v v12, v16
; ZVBB-RV64-NEXT: vmv2r.v v14, v24
-; ZVBB-RV64-NEXT: addi t5, sp, 288
+; ZVBB-RV64-NEXT: addi t5, sp, 1952
; ZVBB-RV64-NEXT: vsseg4e8.v v8, (t5)
-; ZVBB-RV64-NEXT: addi s6, sp, 768
+; ZVBB-RV64-NEXT: addi s6, sp, 1152
; ZVBB-RV64-NEXT: vle8.v v8, (s6)
; ZVBB-RV64-NEXT: csrr s6, vlenb
; ZVBB-RV64-NEXT: slli s6, s6, 4
@@ -8168,7 +8303,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s6, s6, 2047
; ZVBB-RV64-NEXT: addi s6, s6, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s6, sp, 704
+; ZVBB-RV64-NEXT: addi s6, sp, 1088
; ZVBB-RV64-NEXT: vle8.v v8, (s6)
; ZVBB-RV64-NEXT: csrr s6, vlenb
; ZVBB-RV64-NEXT: slli s6, s6, 3
@@ -8181,7 +8316,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s6, s6, 2047
; ZVBB-RV64-NEXT: addi s6, s6, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s6, sp, 1792
+; ZVBB-RV64-NEXT: addi s6, sp, 128
; ZVBB-RV64-NEXT: vle8.v v8, (s6)
; ZVBB-RV64-NEXT: csrr s6, vlenb
; ZVBB-RV64-NEXT: slli s6, s6, 5
@@ -8192,7 +8327,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s6, s6, 2047
; ZVBB-RV64-NEXT: addi s6, s6, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s6, sp, 1728
+; ZVBB-RV64-NEXT: addi s6, sp, 64
; ZVBB-RV64-NEXT: vle8.v v8, (s6)
; ZVBB-RV64-NEXT: csrr s6, vlenb
; ZVBB-RV64-NEXT: slli s6, s6, 3
@@ -8205,13 +8340,13 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s6, s6, 2047
; ZVBB-RV64-NEXT: addi s6, s6, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s6) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s6, sp, 1280
+; ZVBB-RV64-NEXT: addi s6, sp, 640
; ZVBB-RV64-NEXT: vle8.v v16, (s6)
-; ZVBB-RV64-NEXT: addi s6, sp, 1248
+; ZVBB-RV64-NEXT: addi s6, sp, 608
; ZVBB-RV64-NEXT: vle8.v v8, (s6)
-; ZVBB-RV64-NEXT: addi s6, sp, 1216
+; ZVBB-RV64-NEXT: addi s6, sp, 576
; ZVBB-RV64-NEXT: vle8.v v12, (s6)
-; ZVBB-RV64-NEXT: addi s6, sp, 1024
+; ZVBB-RV64-NEXT: addi s6, sp, 1408
; ZVBB-RV64-NEXT: vle8.v v20, (s6)
; ZVBB-RV64-NEXT: csrr s6, vlenb
; ZVBB-RV64-NEXT: slli s6, s6, 4
@@ -8226,7 +8361,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vslideup.vx v8, v16, a1
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v16, (s5)
-; ZVBB-RV64-NEXT: addi s5, sp, 960
+; ZVBB-RV64-NEXT: addi s5, sp, 1344
; ZVBB-RV64-NEXT: vle8.v v20, (s5)
; ZVBB-RV64-NEXT: csrr s5, vlenb
; ZVBB-RV64-NEXT: slli s5, s5, 3
@@ -8240,10 +8375,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v16, v12, a1
; ZVBB-RV64-NEXT: vmv.v.v v24, v16
-; ZVBB-RV64-NEXT: addi s5, sp, 256
+; ZVBB-RV64-NEXT: addi s5, sp, 1664
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v20, (s5)
-; ZVBB-RV64-NEXT: addi s5, sp, 192
+; ZVBB-RV64-NEXT: addi s5, sp, 1600
; ZVBB-RV64-NEXT: vle8.v v16, (s5)
; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v24, v8, a4
@@ -8253,8 +8388,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s5, s5, 2047
; ZVBB-RV64-NEXT: addi s5, s5, 33
; ZVBB-RV64-NEXT: vs8r.v v24, (s5) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s5, sp, 2047
-; ZVBB-RV64-NEXT: addi s5, s5, 1
+; ZVBB-RV64-NEXT: addi s5, sp, 384
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v8, (s5)
; ZVBB-RV64-NEXT: csrr s5, vlenb
@@ -8272,7 +8406,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s5, s5, 2047
; ZVBB-RV64-NEXT: addi s5, s5, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s5, sp, 1984
+; ZVBB-RV64-NEXT: addi s5, sp, 320
; ZVBB-RV64-NEXT: vle8.v v8, (s5)
; ZVBB-RV64-NEXT: csrr s5, vlenb
; ZVBB-RV64-NEXT: slli s5, s5, 4
@@ -8287,9 +8421,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s5, s5, 2047
; ZVBB-RV64-NEXT: addi s5, s5, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s5) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s5, sp, 224
+; ZVBB-RV64-NEXT: addi s5, sp, 1632
; ZVBB-RV64-NEXT: vle8.v v8, (s5)
-; ZVBB-RV64-NEXT: addi s5, sp, 1536
+; ZVBB-RV64-NEXT: addi s5, sp, 896
; ZVBB-RV64-NEXT: vle8.v v12, (s5)
; ZVBB-RV64-NEXT: csrr s5, vlenb
; ZVBB-RV64-NEXT: slli s5, s5, 3
@@ -8308,7 +8442,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vslideup.vx v8, v20, a1
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v24, (s4)
-; ZVBB-RV64-NEXT: addi s4, sp, 1472
+; ZVBB-RV64-NEXT: addi s4, sp, 832
; ZVBB-RV64-NEXT: vle8.v v12, (s4)
; ZVBB-RV64-NEXT: csrr s4, vlenb
; ZVBB-RV64-NEXT: slli s4, s4, 5
@@ -8324,10 +8458,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v24, v16, a1
; ZVBB-RV64-NEXT: vmv.v.v v0, v24
-; ZVBB-RV64-NEXT: addi s4, sp, 640
+; ZVBB-RV64-NEXT: addi s4, sp, 1280
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v20, (s4)
-; ZVBB-RV64-NEXT: addi s4, sp, 576
+; ZVBB-RV64-NEXT: addi s4, sp, 1216
; ZVBB-RV64-NEXT: vle8.v v24, (s4)
; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v0, v8, a4
@@ -8344,7 +8478,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s4, s4, 2047
; ZVBB-RV64-NEXT: addi s4, s4, 33
; ZVBB-RV64-NEXT: vs8r.v v0, (s4) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s4, sp, 512
+; ZVBB-RV64-NEXT: addi s4, sp, 1920
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v8, (s4)
; ZVBB-RV64-NEXT: csrr s4, vlenb
@@ -8358,7 +8492,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s4, s4, 2047
; ZVBB-RV64-NEXT: addi s4, s4, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s4, sp, 448
+; ZVBB-RV64-NEXT: addi s4, sp, 1856
; ZVBB-RV64-NEXT: vle8.v v8, (s4)
; ZVBB-RV64-NEXT: csrr s4, vlenb
; ZVBB-RV64-NEXT: slli s4, s4, 3
@@ -8371,19 +8505,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s4, s4, 2047
; ZVBB-RV64-NEXT: addi s4, s4, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s4) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s4, sp, 608
+; ZVBB-RV64-NEXT: addi s4, sp, 1248
; ZVBB-RV64-NEXT: vle8.v v8, (s4)
-; ZVBB-RV64-NEXT: addi s4, sp, 1664
+; ZVBB-RV64-NEXT: addi s4, sp, 256
; ZVBB-RV64-NEXT: vle8.v v16, (s4)
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v8, v20, a1
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v0, (s3)
-; ZVBB-RV64-NEXT: addi s3, sp, 1600
+; ZVBB-RV64-NEXT: addi s3, sp, 192
; ZVBB-RV64-NEXT: vle8.v v20, (s3)
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v0, v24, a1
-; ZVBB-RV64-NEXT: addi s3, sp, 1152
+; ZVBB-RV64-NEXT: addi s3, sp, 768
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v12, (s3)
; ZVBB-RV64-NEXT: csrr s3, vlenb
@@ -8399,7 +8533,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s3, s3, 2047
; ZVBB-RV64-NEXT: addi s3, s3, 33
; ZVBB-RV64-NEXT: vs4r.v v12, (s3) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s3, sp, 1088
+; ZVBB-RV64-NEXT: addi s3, sp, 704
; ZVBB-RV64-NEXT: vle8.v v24, (s3)
; ZVBB-RV64-NEXT: csrr s3, vlenb
; ZVBB-RV64-NEXT: slli s3, s3, 4
@@ -8423,7 +8557,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s3, s3, 2047
; ZVBB-RV64-NEXT: addi s3, s3, 33
; ZVBB-RV64-NEXT: vs8r.v v0, (s3) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s3, sp, 896
+; ZVBB-RV64-NEXT: addi s3, sp, 1536
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v8, (s3)
; ZVBB-RV64-NEXT: csrr s3, vlenb
@@ -8437,7 +8571,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s3, s3, 2047
; ZVBB-RV64-NEXT: addi s3, s3, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s3, sp, 832
+; ZVBB-RV64-NEXT: addi s3, sp, 1472
; ZVBB-RV64-NEXT: vle8.v v8, (s3)
; ZVBB-RV64-NEXT: csrr s3, vlenb
; ZVBB-RV64-NEXT: slli s3, s3, 3
@@ -8450,19 +8584,19 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s3, s3, 2047
; ZVBB-RV64-NEXT: addi s3, s3, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s3) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s3, sp, 1632
+; ZVBB-RV64-NEXT: addi s3, sp, 224
; ZVBB-RV64-NEXT: vle8.v v8, (s3)
-; ZVBB-RV64-NEXT: addi s3, sp, 128
+; ZVBB-RV64-NEXT: addi s3, sp, 1792
; ZVBB-RV64-NEXT: vle8.v v24, (s3)
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v8, v16, a1
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v16, (s2)
-; ZVBB-RV64-NEXT: addi s2, sp, 64
+; ZVBB-RV64-NEXT: addi s2, sp, 1728
; ZVBB-RV64-NEXT: vle8.v v28, (s2)
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v16, v20, a1
-; ZVBB-RV64-NEXT: addi s2, sp, 1920
+; ZVBB-RV64-NEXT: addi s2, sp, 512
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v12, (s2)
; ZVBB-RV64-NEXT: csrr s2, vlenb
@@ -8474,7 +8608,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s2, s2, 2047
; ZVBB-RV64-NEXT: addi s2, s2, 33
; ZVBB-RV64-NEXT: vs4r.v v12, (s2) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s2, sp, 1856
+; ZVBB-RV64-NEXT: addi s2, sp, 448
; ZVBB-RV64-NEXT: vle8.v v20, (s2)
; ZVBB-RV64-NEXT: csrr s2, vlenb
; ZVBB-RV64-NEXT: slli s2, s2, 3
@@ -8500,10 +8634,10 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s2, s2, 2047
; ZVBB-RV64-NEXT: addi s2, s2, 33
; ZVBB-RV64-NEXT: vs8r.v v16, (s2) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s2, sp, 1408
+; ZVBB-RV64-NEXT: addi s2, sp, 1024
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v4, (s2)
-; ZVBB-RV64-NEXT: addi s2, sp, 1344
+; ZVBB-RV64-NEXT: addi s2, sp, 960
; ZVBB-RV64-NEXT: vle8.v v8, (s2)
; ZVBB-RV64-NEXT: csrr s2, vlenb
; ZVBB-RV64-NEXT: slli s2, s2, 5
@@ -8514,20 +8648,21 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi s2, s2, 2047
; ZVBB-RV64-NEXT: addi s2, s2, 33
; ZVBB-RV64-NEXT: vs4r.v v8, (s2) # vscale x 32-byte Folded Spill
-; ZVBB-RV64-NEXT: addi s2, sp, 96
+; ZVBB-RV64-NEXT: addi s2, sp, 1760
; ZVBB-RV64-NEXT: vle8.v v8, (s2)
-; ZVBB-RV64-NEXT: addi s2, sp, 384
+; ZVBB-RV64-NEXT: addi s2, sp, 2047
+; ZVBB-RV64-NEXT: addi s2, s2, 1
; ZVBB-RV64-NEXT: vle8.v v0, (s2)
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v8, v24, a1
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v16, (s1)
-; ZVBB-RV64-NEXT: addi s1, sp, 320
+; ZVBB-RV64-NEXT: addi s1, sp, 1984
; ZVBB-RV64-NEXT: vmv2r.v v12, v28
; ZVBB-RV64-NEXT: vle8.v v28, (s1)
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v16, v12, a1
-; ZVBB-RV64-NEXT: addi s1, sp, 736
+; ZVBB-RV64-NEXT: addi s1, sp, 1120
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v24, (s1)
; ZVBB-RV64-NEXT: csrr s1, vlenb
@@ -8557,7 +8692,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi a3, a3, 2047
; ZVBB-RV64-NEXT: addi a3, a3, 33
; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi a3, sp, 1760
+; ZVBB-RV64-NEXT: addi a3, sp, 96
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v8, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
@@ -8583,9 +8718,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi a3, a3, 2047
; ZVBB-RV64-NEXT: addi a3, a3, 33
; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi a3, sp, 1376
-; ZVBB-RV64-NEXT: vle8.v v8, (a3)
; ZVBB-RV64-NEXT: addi a3, sp, 992
+; ZVBB-RV64-NEXT: vle8.v v8, (a3)
+; ZVBB-RV64-NEXT: addi a3, sp, 1376
; ZVBB-RV64-NEXT: vle8.v v24, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
; ZVBB-RV64-NEXT: slli a3, a3, 3
@@ -8623,7 +8758,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v24, v12, a1
-; ZVBB-RV64-NEXT: addi a3, sp, 2016
+; ZVBB-RV64-NEXT: addi a3, sp, 352
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v16, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
@@ -8654,7 +8789,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi a3, a3, 2047
; ZVBB-RV64-NEXT: addi a3, a3, 33
; ZVBB-RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi a3, sp, 1504
+; ZVBB-RV64-NEXT: addi a3, sp, 864
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v8, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
@@ -8678,9 +8813,9 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi a3, a3, 2047
; ZVBB-RV64-NEXT: addi a3, a3, 33
; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi a3, sp, 352
+; ZVBB-RV64-NEXT: addi a3, sp, 2016
; ZVBB-RV64-NEXT: vle8.v v16, (a3)
-; ZVBB-RV64-NEXT: addi a3, sp, 480
+; ZVBB-RV64-NEXT: addi a3, sp, 1888
; ZVBB-RV64-NEXT: vle8.v v8, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
; ZVBB-RV64-NEXT: slli a3, a3, 3
@@ -8704,7 +8839,7 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVBB-RV64-NEXT: vsetvli zero, a4, e8, m4, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v0, v28, a1
-; ZVBB-RV64-NEXT: addi a3, sp, 1120
+; ZVBB-RV64-NEXT: addi a3, sp, 736
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v8, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
@@ -8722,14 +8857,14 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVBB-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; ZVBB-RV64-NEXT: vslideup.vx v0, v16, a4
-; ZVBB-RV64-NEXT: addi a3, sp, 864
+; ZVBB-RV64-NEXT: addi a3, sp, 1504
; ZVBB-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; ZVBB-RV64-NEXT: vle8.v v24, (a3)
; ZVBB-RV64-NEXT: vle8.v v8, (t3)
; ZVBB-RV64-NEXT: addi a3, sp, 2047
; ZVBB-RV64-NEXT: addi a3, a3, 33
; ZVBB-RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVBB-RV64-NEXT: addi a3, sp, 1888
+; ZVBB-RV64-NEXT: addi a3, sp, 480
; ZVBB-RV64-NEXT: vle8.v v8, (a3)
; ZVBB-RV64-NEXT: csrr a3, vlenb
; ZVBB-RV64-NEXT: slli a3, a3, 4
@@ -9211,1044 +9346,2988 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
; ZVBB-RV64-NEXT: addi sp, sp, 2032
; ZVBB-RV64-NEXT: ret
;
-; ZVZIP-LABEL: vector_interleave4_v512i8_v2048i8:
-; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: slli a2, a2, 4
-; ZVZIP-NEXT: mv a4, a2
-; ZVZIP-NEXT: slli a2, a2, 4
-; ZVZIP-NEXT: add a2, a2, a4
-; ZVZIP-NEXT: sub sp, sp, a2
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: slli a2, a2, 6
-; ZVZIP-NEXT: mv a4, a2
-; ZVZIP-NEXT: slli a2, a2, 1
-; ZVZIP-NEXT: add a2, a2, a4
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 16
-; ZVZIP-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: slli a2, a2, 3
-; ZVZIP-NEXT: mv a4, a2
-; ZVZIP-NEXT: slli a2, a2, 5
-; ZVZIP-NEXT: add a2, a2, a4
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 16
-; ZVZIP-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: li a2, 128
-; ZVZIP-NEXT: csrr a4, vlenb
-; ZVZIP-NEXT: slli a4, a4, 4
-; ZVZIP-NEXT: mv a5, a4
-; ZVZIP-NEXT: slli a4, a4, 4
-; ZVZIP-NEXT: add a4, a4, a5
-; ZVZIP-NEXT: add a4, sp, a4
-; ZVZIP-NEXT: addi a4, a4, 528
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a4)
-; ZVZIP-NEXT: csrr a4, vlenb
-; ZVZIP-NEXT: slli a4, a4, 3
-; ZVZIP-NEXT: mv a5, a4
-; ZVZIP-NEXT: slli a4, a4, 3
-; ZVZIP-NEXT: add a5, a5, a4
-; ZVZIP-NEXT: slli a4, a4, 1
-; ZVZIP-NEXT: add a4, a4, a5
-; ZVZIP-NEXT: add a4, sp, a4
-; ZVZIP-NEXT: addi a4, a4, 16
-; ZVZIP-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: li a4, 64
-; ZVZIP-NEXT: addi a5, a3, 128
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v24, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 2
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v24, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v24, v8
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v0, a4
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a5, a7, 128
-; ZVZIP-NEXT: vslidedown.vx v8, v16, a4
-; ZVZIP-NEXT: csrr a6, vlenb
-; ZVZIP-NEXT: slli a6, a6, 3
-; ZVZIP-NEXT: mv t0, a6
-; ZVZIP-NEXT: slli a6, a6, 2
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add a6, a6, t0
-; ZVZIP-NEXT: add a6, sp, a6
-; ZVZIP-NEXT: addi a6, a6, 16
-; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 2
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 656
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: csrr a6, vlenb
-; ZVZIP-NEXT: slli a6, a6, 3
-; ZVZIP-NEXT: mv t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 2
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add a6, a6, t0
-; ZVZIP-NEXT: add a6, sp, a6
-; ZVZIP-NEXT: addi a6, a6, 16
-; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 2
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a5, a3, 256
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v16, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 5
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v16, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v24, v16, v8
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 2
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v24, a4
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 5
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a1)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 2
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a5, a7, 256
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: csrr a6, vlenb
-; ZVZIP-NEXT: slli a6, a6, 3
-; ZVZIP-NEXT: mv t0, a6
-; ZVZIP-NEXT: slli a6, a6, 2
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 2
-; ZVZIP-NEXT: add a6, a6, t0
-; ZVZIP-NEXT: add a6, sp, a6
-; ZVZIP-NEXT: addi a6, a6, 16
-; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 784
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: csrr a6, vlenb
-; ZVZIP-NEXT: slli a6, a6, 5
-; ZVZIP-NEXT: mv t0, a6
-; ZVZIP-NEXT: slli a6, a6, 2
-; ZVZIP-NEXT: add a6, a6, t0
-; ZVZIP-NEXT: add a6, sp, a6
-; ZVZIP-NEXT: addi a6, a6, 16
-; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 2
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a5, a3, 384
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: csrr a6, vlenb
-; ZVZIP-NEXT: slli a6, a6, 4
-; ZVZIP-NEXT: mv t0, a6
-; ZVZIP-NEXT: slli a6, a6, 3
-; ZVZIP-NEXT: add a6, a6, t0
-; ZVZIP-NEXT: add a6, sp, a6
-; ZVZIP-NEXT: addi a6, a6, 16
-; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a5, a7, 384
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: csrr a6, vlenb
-; ZVZIP-NEXT: slli a6, a6, 3
-; ZVZIP-NEXT: mv t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add t0, t0, a6
-; ZVZIP-NEXT: slli a6, a6, 1
-; ZVZIP-NEXT: add a6, a6, t0
-; ZVZIP-NEXT: add a6, sp, a6
-; ZVZIP-NEXT: addi a6, a6, 16
-; ZVZIP-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a5)
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a1, a1, 128
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 3
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v8, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a5, a1
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: add a1, a1, a5
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 400
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v8, a4
-; ZVZIP-NEXT: csrr a5, vlenb
-; ZVZIP-NEXT: slli a5, a5, 4
-; ZVZIP-NEXT: mv a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a6, a6, a5
-; ZVZIP-NEXT: slli a5, a5, 1
-; ZVZIP-NEXT: add a5, a5, a6
-; ZVZIP-NEXT: add a5, sp, a5
-; ZVZIP-NEXT: addi a5, a5, 16
-; ZVZIP-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v16, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v24, (a3)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v24, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v24, v16
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 8
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 8
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v16, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vslidedown.vx v16, v16, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vle8.v v24, (a7)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v24, a4
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v16, v24
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v0, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 7
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v24, v16
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v0, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v16, v24
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v0, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v24, v16
-; ZVZIP-NEXT: addi a1, sp, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v0, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v24, v8, v16
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v24, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v0, v16, v8
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v0, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v16, v24
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v16, v8, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vzip.vv v16, v8, v0
-; ZVZIP-NEXT: addi a1, sp, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v8, v0, v24
-; ZVZIP-NEXT: vse8.v v16, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v16, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a1, a0, 1536
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vse8.v v8, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v8, v0, v24
-; ZVZIP-NEXT: addi a1, a0, 1024
-; ZVZIP-NEXT: vse8.v v8, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v0, v8, v24
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vzip.vv v24, v0, v16
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v8, v0, v16
-; ZVZIP-NEXT: addi a1, a0, 512
-; ZVZIP-NEXT: vse8.v v24, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 8
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v8, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 8
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a1, a0, 256
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: addi a1, a0, 128
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v0, v24, v16
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: vzip.vv v16, v0, v8
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v8, v24, v0
-; ZVZIP-NEXT: addi a1, a0, 1792
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v8, a4
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: addi a1, a0, 1664
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v8, v24
-; ZVZIP-NEXT: addi a1, a0, 1280
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v24, v8
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v8, v0, v24
-; ZVZIP-NEXT: addi a1, a0, 1152
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 4
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v8, v0
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v0, v24, a4
-; ZVZIP-NEXT: addi a1, a0, 768
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: addi a1, a0, 640
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 7
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 6
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v24, v24, a4
-; ZVZIP-NEXT: addi a1, a0, 384
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 8
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v24, v0
-; ZVZIP-NEXT: addi a1, a0, 1920
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 5
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a3, a3, a1
-; ZVZIP-NEXT: slli a1, a1, 2
-; ZVZIP-NEXT: add a1, a1, a3
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v0, v24
-; ZVZIP-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vx v8, v8, a4
-; ZVZIP-NEXT: addi a1, a0, 1408
-; ZVZIP-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; ZVZIP-NEXT: vse8.v v16, (a1)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a1, a1, 3
-; ZVZIP-NEXT: mv a2, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a2, a2, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a2, a2, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a2, a2, a1
-; ZVZIP-NEXT: slli a1, a1, 1
-; ZVZIP-NEXT: add a1, a1, a2
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 16
-; ZVZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vzip.vv v16, v8, v24
-; ZVZIP-NEXT: addi a0, a0, 896
-; ZVZIP-NEXT: vse8.v v16, (a0)
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 4
-; ZVZIP-NEXT: mv a1, a0
-; ZVZIP-NEXT: slli a0, a0, 4
-; ZVZIP-NEXT: add a0, a0, a1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
-; ZVZIP-NEXT: ret
+; ZVZIP-RV32-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP-RV32: # %bb.0:
+; ZVZIP-RV32-NEXT: addi sp, sp, -16
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a4, a2, 8
+; ZVZIP-RV32-NEXT: add a2, a4, a2
+; ZVZIP-RV32-NEXT: sub sp, sp, a2
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 2
+; ZVZIP-RV32-NEXT: add a4, a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a4, a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a4
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a4, a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a4, a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a4, a4, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a4
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: li a2, 128
+; ZVZIP-RV32-NEXT: csrr a4, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a4, 8
+; ZVZIP-RV32-NEXT: add a4, a5, a4
+; ZVZIP-RV32-NEXT: add a4, sp, a4
+; ZVZIP-RV32-NEXT: addi a4, a4, 528
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a4)
+; ZVZIP-RV32-NEXT: csrr a4, vlenb
+; ZVZIP-RV32-NEXT: slli a4, a4, 4
+; ZVZIP-RV32-NEXT: mv a5, a4
+; ZVZIP-RV32-NEXT: slli a4, a4, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a4
+; ZVZIP-RV32-NEXT: slli a4, a4, 2
+; ZVZIP-RV32-NEXT: add a4, a4, a5
+; ZVZIP-RV32-NEXT: add a4, sp, a4
+; ZVZIP-RV32-NEXT: addi a4, a4, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: li a4, 64
+; ZVZIP-RV32-NEXT: addi a5, a3, 128
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v16, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v16, v16, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v24, v16, v12
+; ZVZIP-RV32-NEXT: lui a5, 699051
+; ZVZIP-RV32-NEXT: addi a5, a5, -1366
+; ZVZIP-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-RV32-NEXT: vmv.v.x v0, a5
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 8
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v24, v12, v8, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 5
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a5, a7, 128
+; ZVZIP-RV32-NEXT: csrr a6, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a6, 3
+; ZVZIP-RV32-NEXT: mv t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 2
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add a6, a6, t0
+; ZVZIP-RV32-NEXT: add a6, sp, a6
+; ZVZIP-RV32-NEXT: addi a6, a6, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 5
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v0, v8
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 8
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a5, 8
+; ZVZIP-RV32-NEXT: add a5, a6, a5
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 656
+; ZVZIP-RV32-NEXT: csrr a6, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a6, 4
+; ZVZIP-RV32-NEXT: mv t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add a6, a6, t0
+; ZVZIP-RV32-NEXT: add a6, sp, a6
+; ZVZIP-RV32-NEXT: addi a6, a6, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a5, a3, 256
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: csrr a6, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a6, 3
+; ZVZIP-RV32-NEXT: mv t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 2
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add a6, a6, t0
+; ZVZIP-RV32-NEXT: add a6, sp, a6
+; ZVZIP-RV32-NEXT: addi a6, a6, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 7
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v0, v12
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 8
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 5
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v12, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v12
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 6
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a5, a7, 256
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v0, v8
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 8
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 5
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a5, 8
+; ZVZIP-RV32-NEXT: add a5, a6, a5
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 784
+; ZVZIP-RV32-NEXT: csrr a6, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a6, 5
+; ZVZIP-RV32-NEXT: mv t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add a6, a6, t0
+; ZVZIP-RV32-NEXT: add a6, sp, a6
+; ZVZIP-RV32-NEXT: addi a6, a6, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 5
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a5, a3, 384
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: csrr a6, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a6, 4
+; ZVZIP-RV32-NEXT: mv t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 3
+; ZVZIP-RV32-NEXT: add a6, a6, t0
+; ZVZIP-RV32-NEXT: add a6, sp, a6
+; ZVZIP-RV32-NEXT: addi a6, a6, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v0, v12
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 8
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v12, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v12
+; ZVZIP-RV32-NEXT: vmv1r.v v7, v0
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a5, a7, 384
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV32-NEXT: csrr a6, vlenb
+; ZVZIP-RV32-NEXT: slli a6, a6, 3
+; ZVZIP-RV32-NEXT: mv t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 2
+; ZVZIP-RV32-NEXT: add t0, t0, a6
+; ZVZIP-RV32-NEXT: slli a6, a6, 1
+; ZVZIP-RV32-NEXT: add a6, a6, t0
+; ZVZIP-RV32-NEXT: add a6, sp, a6
+; ZVZIP-RV32-NEXT: addi a6, a6, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a1, a1, 128
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 4
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a5, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a5
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v24, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a5, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, a1, a5
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a5, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a5, a5, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a5
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a1, 8
+; ZVZIP-RV32-NEXT: add a1, a5, a1
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 400
+; ZVZIP-RV32-NEXT: csrr a5, vlenb
+; ZVZIP-RV32-NEXT: slli a5, a5, 3
+; ZVZIP-RV32-NEXT: mv a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 2
+; ZVZIP-RV32-NEXT: add a6, a6, a5
+; ZVZIP-RV32-NEXT: slli a5, a5, 1
+; ZVZIP-RV32-NEXT: add a5, a5, a6
+; ZVZIP-RV32-NEXT: add a5, sp, a5
+; ZVZIP-RV32-NEXT: addi a5, a5, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a5, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a5
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 6
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v8, (a3)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v24, v12
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v12, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v12
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 6
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vle8.v v16, (a7)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v16, v16, a4
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v24, v8, v12
+; ZVZIP-RV32-NEXT: vzip.vv v24, v8, v16, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 6
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 7
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v0, v16, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v0, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v24, v8, v16
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 7
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV32-NEXT: addi a1, sp, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v24, v8, v16
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v16, v0, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vzip.vv v8, v0, v24
+; ZVZIP-RV32-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV32-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV32-NEXT: vzip.vv v16, v24, v0
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v24, v8, v16
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 6
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 8
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v24, v8, v16, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a0)
+; ZVZIP-RV32-NEXT: addi a1, sp, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v0, v24, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a1, a0, 1536
+; ZVZIP-RV32-NEXT: vse8.v v0, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 7
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 8
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v8, v16, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 7
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a1, a0, 1024
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v24, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a1, a0, 512
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v24, v8
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV32-NEXT: addi a1, a0, 256
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 4
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v8, v24, v4
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v8, v4, v24, v0.t
+; ZVZIP-RV32-NEXT: addi a1, a0, 128
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v16, v8, v0
+; ZVZIP-RV32-NEXT: addi a1, a0, 1792
+; ZVZIP-RV32-NEXT: vse8.v v16, (a1)
+; ZVZIP-RV32-NEXT: addi a1, a0, 1664
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 4
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 6
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 5
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v8, v0, v16
+; ZVZIP-RV32-NEXT: addi a1, a0, 1280
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: addi a1, a0, 1152
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 7
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 4
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vzip.vv v8, v0, v16
+; ZVZIP-RV32-NEXT: addi a1, a0, 768
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: addi a1, a0, 640
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: addi a1, a0, 384
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 2
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: addi a1, a0, 1920
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 4
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: addi a1, a0, 1408
+; ZVZIP-RV32-NEXT: csrr a2, vlenb
+; ZVZIP-RV32-NEXT: slli a2, a2, 3
+; ZVZIP-RV32-NEXT: mv a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 1
+; ZVZIP-RV32-NEXT: add a3, a3, a2
+; ZVZIP-RV32-NEXT: slli a2, a2, 2
+; ZVZIP-RV32-NEXT: add a2, a2, a3
+; ZVZIP-RV32-NEXT: add a2, sp, a2
+; ZVZIP-RV32-NEXT: addi a2, a2, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV32-NEXT: addi a0, a0, 896
+; ZVZIP-RV32-NEXT: csrr a1, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: mv a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 3
+; ZVZIP-RV32-NEXT: add a2, a2, a1
+; ZVZIP-RV32-NEXT: slli a1, a1, 1
+; ZVZIP-RV32-NEXT: add a1, a1, a2
+; ZVZIP-RV32-NEXT: add a1, sp, a1
+; ZVZIP-RV32-NEXT: addi a1, a1, 16
+; ZVZIP-RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV32-NEXT: vse8.v v8, (a0)
+; ZVZIP-RV32-NEXT: csrr a0, vlenb
+; ZVZIP-RV32-NEXT: slli a1, a0, 8
+; ZVZIP-RV32-NEXT: add a0, a1, a0
+; ZVZIP-RV32-NEXT: add sp, sp, a0
+; ZVZIP-RV32-NEXT: addi sp, sp, 16
+; ZVZIP-RV32-NEXT: ret
;
-; ZVZIP-ZVL2048-LABEL: vector_interleave4_v512i8_v2048i8:
-; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: li a0, 1024
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v16, v10, v14
-; ZVZIP-ZVL2048-NEXT: li a1, 512
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vx v20, v16, a1
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v24, v8, v12
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vx v28, v24, a1
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v24, v16
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v28, v20
-; ZVZIP-ZVL2048-NEXT: ret
+; ZVZIP-RV64-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP-RV64: # %bb.0:
+; ZVZIP-RV64-NEXT: addi sp, sp, -16
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a4, a2, 8
+; ZVZIP-RV64-NEXT: add a2, a4, a2
+; ZVZIP-RV64-NEXT: sub sp, sp, a2
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 2
+; ZVZIP-RV64-NEXT: add a4, a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a4, a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a4
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a4, a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a4, a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a4, a4, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a4
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: li a2, 128
+; ZVZIP-RV64-NEXT: csrr a4, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a4, 8
+; ZVZIP-RV64-NEXT: add a4, a5, a4
+; ZVZIP-RV64-NEXT: add a4, sp, a4
+; ZVZIP-RV64-NEXT: addi a4, a4, 528
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a4)
+; ZVZIP-RV64-NEXT: csrr a4, vlenb
+; ZVZIP-RV64-NEXT: slli a4, a4, 4
+; ZVZIP-RV64-NEXT: mv a5, a4
+; ZVZIP-RV64-NEXT: slli a4, a4, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a4
+; ZVZIP-RV64-NEXT: slli a4, a4, 2
+; ZVZIP-RV64-NEXT: add a4, a4, a5
+; ZVZIP-RV64-NEXT: add a4, sp, a4
+; ZVZIP-RV64-NEXT: addi a4, a4, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: li a4, 64
+; ZVZIP-RV64-NEXT: addi a5, a3, 128
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v16, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v16, v16, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v24, v16, v12
+; ZVZIP-RV64-NEXT: lui a5, %hi(.LCPI6_0)
+; ZVZIP-RV64-NEXT: ld a5, %lo(.LCPI6_0)(a5)
+; ZVZIP-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-RV64-NEXT: vmv.v.x v0, a5
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 8
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v24, v12, v8, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 5
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a5, a7, 128
+; ZVZIP-RV64-NEXT: csrr a6, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a6, 3
+; ZVZIP-RV64-NEXT: mv t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 2
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add a6, a6, t0
+; ZVZIP-RV64-NEXT: add a6, sp, a6
+; ZVZIP-RV64-NEXT: addi a6, a6, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 5
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v0, v8
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 8
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a5, 8
+; ZVZIP-RV64-NEXT: add a5, a6, a5
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 656
+; ZVZIP-RV64-NEXT: csrr a6, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a6, 4
+; ZVZIP-RV64-NEXT: mv t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add a6, a6, t0
+; ZVZIP-RV64-NEXT: add a6, sp, a6
+; ZVZIP-RV64-NEXT: addi a6, a6, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a5, a3, 256
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: csrr a6, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a6, 3
+; ZVZIP-RV64-NEXT: mv t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 2
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add a6, a6, t0
+; ZVZIP-RV64-NEXT: add a6, sp, a6
+; ZVZIP-RV64-NEXT: addi a6, a6, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 7
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v0, v12
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 8
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 5
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v12, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v12
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 6
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a5, a7, 256
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v0, v8
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 8
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 5
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a5, 8
+; ZVZIP-RV64-NEXT: add a5, a6, a5
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 784
+; ZVZIP-RV64-NEXT: csrr a6, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a6, 5
+; ZVZIP-RV64-NEXT: mv t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add a6, a6, t0
+; ZVZIP-RV64-NEXT: add a6, sp, a6
+; ZVZIP-RV64-NEXT: addi a6, a6, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v0, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 5
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a5, a3, 384
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: csrr a6, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a6, 4
+; ZVZIP-RV64-NEXT: mv t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 3
+; ZVZIP-RV64-NEXT: add a6, a6, t0
+; ZVZIP-RV64-NEXT: add a6, sp, a6
+; ZVZIP-RV64-NEXT: addi a6, a6, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v0, v12
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 8
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v12, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v12
+; ZVZIP-RV64-NEXT: vmv1r.v v7, v0
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a5, a7, 384
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV64-NEXT: csrr a6, vlenb
+; ZVZIP-RV64-NEXT: slli a6, a6, 3
+; ZVZIP-RV64-NEXT: mv t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 2
+; ZVZIP-RV64-NEXT: add t0, t0, a6
+; ZVZIP-RV64-NEXT: slli a6, a6, 1
+; ZVZIP-RV64-NEXT: add a6, a6, t0
+; ZVZIP-RV64-NEXT: add a6, sp, a6
+; ZVZIP-RV64-NEXT: addi a6, a6, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a5)
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a1, a1, 128
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 4
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a5, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a5
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v24, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a5, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, a1, a5
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a5, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a5, a5, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a5
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a1, 8
+; ZVZIP-RV64-NEXT: add a1, a5, a1
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 400
+; ZVZIP-RV64-NEXT: csrr a5, vlenb
+; ZVZIP-RV64-NEXT: slli a5, a5, 3
+; ZVZIP-RV64-NEXT: mv a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 2
+; ZVZIP-RV64-NEXT: add a6, a6, a5
+; ZVZIP-RV64-NEXT: slli a5, a5, 1
+; ZVZIP-RV64-NEXT: add a5, a5, a6
+; ZVZIP-RV64-NEXT: add a5, sp, a5
+; ZVZIP-RV64-NEXT: addi a5, a5, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a5, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a5
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 6
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v8, (a3)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v24, v12
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v12, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v12
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 6
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v8, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vle8.v v16, (a7)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v16, v16, a4
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v24, v8, v12
+; ZVZIP-RV64-NEXT: vzip.vv v24, v8, v16, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 6
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 7
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v0, v16, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v0, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v24, v8, v16
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 7
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV64-NEXT: addi a1, sp, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v24, v8, v16
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v24, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v16, v0, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v8, v16, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vzip.vv v8, v0, v24
+; ZVZIP-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; ZVZIP-RV64-NEXT: vslidedown.vx v24, v8, a4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; ZVZIP-RV64-NEXT: vzip.vv v16, v24, v0
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v24, v8, v16
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 6
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 8
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v24, v8, v16, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a0)
+; ZVZIP-RV64-NEXT: addi a1, sp, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v0, v24, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a1, a0, 1536
+; ZVZIP-RV64-NEXT: vse8.v v0, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 7
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 8
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v8, v16, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 7
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a1, a0, 1024
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v24, v16, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v24, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a1, a0, 512
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v24, v8
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v24, v0.t
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVZIP-RV64-NEXT: addi a1, a0, 256
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 4
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v8, v24, v4
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v8, v4, v24, v0.t
+; ZVZIP-RV64-NEXT: addi a1, a0, 128
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v16, v8, v0
+; ZVZIP-RV64-NEXT: addi a1, a0, 1792
+; ZVZIP-RV64-NEXT: vse8.v v16, (a1)
+; ZVZIP-RV64-NEXT: addi a1, a0, 1664
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 4
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 6
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 5
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v8, v0, v16
+; ZVZIP-RV64-NEXT: addi a1, a0, 1280
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: addi a1, a0, 1152
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 7
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 4
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vzip.vv v8, v0, v16
+; ZVZIP-RV64-NEXT: addi a1, a0, 768
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: addi a1, a0, 640
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: addi a1, a0, 384
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 2
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: addi a1, a0, 1920
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 4
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: addi a1, a0, 1408
+; ZVZIP-RV64-NEXT: csrr a2, vlenb
+; ZVZIP-RV64-NEXT: slli a2, a2, 3
+; ZVZIP-RV64-NEXT: mv a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 1
+; ZVZIP-RV64-NEXT: add a3, a3, a2
+; ZVZIP-RV64-NEXT: slli a2, a2, 2
+; ZVZIP-RV64-NEXT: add a2, a2, a3
+; ZVZIP-RV64-NEXT: add a2, sp, a2
+; ZVZIP-RV64-NEXT: addi a2, a2, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a1)
+; ZVZIP-RV64-NEXT: addi a0, a0, 896
+; ZVZIP-RV64-NEXT: csrr a1, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: mv a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 3
+; ZVZIP-RV64-NEXT: add a2, a2, a1
+; ZVZIP-RV64-NEXT: slli a1, a1, 1
+; ZVZIP-RV64-NEXT: add a1, a1, a2
+; ZVZIP-RV64-NEXT: add a1, sp, a1
+; ZVZIP-RV64-NEXT: addi a1, a1, 16
+; ZVZIP-RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVZIP-RV64-NEXT: vse8.v v8, (a0)
+; ZVZIP-RV64-NEXT: csrr a0, vlenb
+; ZVZIP-RV64-NEXT: slli a1, a0, 8
+; ZVZIP-RV64-NEXT: add a0, a1, a0
+; ZVZIP-RV64-NEXT: add sp, sp, a0
+; ZVZIP-RV64-NEXT: addi sp, sp, 16
+; ZVZIP-RV64-NEXT: ret
+;
+; ZVZIP-ZVL2048-RV32-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP-ZVL2048-RV32: # %bb.0:
+; ZVZIP-ZVL2048-RV32-NEXT: li a2, 256
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v18, v14, a2
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v26, v10, a2
+; ZVZIP-ZVL2048-RV32-NEXT: li a0, 512
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-ZVL2048-RV32-NEXT: lui a1, 699051
+; ZVZIP-ZVL2048-RV32-NEXT: addi a1, a1, -1366
+; ZVZIP-ZVL2048-RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vmv.v.x v0, a1
+; ZVZIP-ZVL2048-RV32-NEXT: vmv4r.v v20, v16
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v24, v26, v10
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v24, v10, v18, v0.t
+; ZVZIP-ZVL2048-RV32-NEXT: li a3, 1024
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslideup.vx v20, v24, a0
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v20, v20, a0
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v14, v12, a2
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v24, v8, v12
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v18, v8, a2
+; ZVZIP-ZVL2048-RV32-NEXT: vmv4r.v v8, v24
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v18, v15
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v15, v14, v0.t
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslideup.vx v8, v12, a0
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v8, v8, a0
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-ZVL2048-RV32-NEXT: li a0, 32
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vmv.v.x v0, a1
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, mu
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v16, v20, v0.t
+; ZVZIP-ZVL2048-RV32-NEXT: ret
+;
+; ZVZIP-ZVL2048-RV64-LABEL: vector_interleave4_v512i8_v2048i8:
+; ZVZIP-ZVL2048-RV64: # %bb.0:
+; ZVZIP-ZVL2048-RV64-NEXT: li a2, 256
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v18, v14, a2
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v26, v10, a2
+; ZVZIP-ZVL2048-RV64-NEXT: lui a0, %hi(.LCPI6_0)
+; ZVZIP-ZVL2048-RV64-NEXT: ld a0, %lo(.LCPI6_0)(a0)
+; ZVZIP-ZVL2048-RV64-NEXT: li a1, 512
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-ZVL2048-RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vmv.v.x v0, a0
+; ZVZIP-ZVL2048-RV64-NEXT: vmv4r.v v20, v16
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v24, v26, v10
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v24, v10, v18, v0.t
+; ZVZIP-ZVL2048-RV64-NEXT: li a3, 1024
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslideup.vx v20, v24, a1
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v20, v20, a1
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v14, v12, a2
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v24, v8, v12
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v18, v8, a2
+; ZVZIP-ZVL2048-RV64-NEXT: vmv4r.v v8, v24
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v18, v15
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v15, v14, v0.t
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslideup.vx v8, v12, a1
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v8, v8, a1
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-ZVL2048-RV64-NEXT: vsetivli zero, 16, e64, m1, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vmv.v.x v0, a0
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, mu
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v8, v24, v16
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v16, v20, v0.t
+; ZVZIP-ZVL2048-RV64-NEXT: ret
%v = call <2048 x i8> @llvm.vector.interleave4(<512 x i8> %v0, <512 x i8> %v1, <512 x i8> %v2, <512 x i8> %v3)
ret <2048 x i8> %v
}
@@ -10653,36 +12732,8 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vsseg8e8.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 10
-; CHECK-NEXT: vle8.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle8.v v10, (a1)
-; CHECK-NEXT: addi a1, sp, 12
-; CHECK-NEXT: vle8.v v11, (a1)
-; CHECK-NEXT: addi a1, sp, 2
-; CHECK-NEXT: vle8.v v12, (a1)
-; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 4
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 2
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 2
-; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vle8.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v11, 4
-; CHECK-NEXT: vslideup.vi v8, v9, 4
-; CHECK-NEXT: addi a0, sp, 6
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT: vle8.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v12, 6
-; CHECK-NEXT: vslideup.vi v8, v9, 6
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -10692,65 +12743,122 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; ZVBB-NEXT: vsseg8e8.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 10
-; ZVBB-NEXT: vle8.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle8.v v10, (a1)
-; ZVBB-NEXT: addi a1, sp, 12
-; ZVBB-NEXT: vle8.v v11, (a1)
-; ZVBB-NEXT: addi a1, sp, 2
-; ZVBB-NEXT: vle8.v v12, (a1)
-; ZVBB-NEXT: vle8.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 4
-; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 2
-; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVBB-NEXT: vle8.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v8, v12, 2
-; ZVBB-NEXT: addi a0, sp, 14
-; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVBB-NEXT: vle8.v v12, (a0)
-; ZVBB-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v11, 4
-; ZVBB-NEXT: vslideup.vi v8, v9, 4
-; ZVBB-NEXT: addi a0, sp, 6
-; ZVBB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVBB-NEXT: vle8.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v12, 6
-; ZVBB-NEXT: vslideup.vi v8, v9, 6
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave8_v16i8_v2i8:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vpairo.vv v16, v11, v15
+; ZVZIP-NEXT: vslideup.vi v11, v15, 1
+; ZVZIP-NEXT: vpairo.vv v15, v9, v13
+; ZVZIP-NEXT: vslideup.vi v9, v13, 1
+; ZVZIP-NEXT: vpairo.vv v13, v10, v14
+; ZVZIP-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-NEXT: vpairo.vv v14, v8, v12
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vslideup.vi v9, v15, 2
+; ZVZIP-NEXT: vzip.vv v15, v8, v10
+; ZVZIP-NEXT: vslideup.vi v11, v16, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v14, 2
+; ZVZIP-NEXT: vslideup.vi v10, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v11, v11, 2
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v16, v11, v15
-; ZVZIP-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vzip.vv v14, v9, v13
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v10, v10, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
+; ZVZIP-NEXT: vzip.vv v14, v9, v11, v0.t
+; ZVZIP-NEXT: vzip.vv v9, v8, v13
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vzip.vv v9, v8, v10, v0.t
+; ZVZIP-NEXT: vmv.s.x v0, a0
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-NEXT: vzip.vv v8, v15, v12
+; ZVZIP-NEXT: vslideup.vi v15, v9, 4
+; ZVZIP-NEXT: vslideup.vi v12, v14, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v15, 4
+; ZVZIP-NEXT: vslidedown.vi v10, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-NEXT: vzip.vv v12, v9, v10, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave8_v16i8_v2i8:
; ZVZIP-ZVL2048: # %bb.0:
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v16, v11, v15
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v15, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v15, v9, v13
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v13, v10, v14
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v14, v8, v12
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v15, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v16, v11, v15
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-ZVL2048-NEXT: vzip.vv v15, v8, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v16, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v14, 2
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v11, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v9, v13
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v10, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v9, v11, v0.t
+; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v13
+; ZVZIP-ZVL2048-NEXT: li a0, 170
+; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v10, v0.t
+; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v10, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v15, v12
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v15, v9, 4
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v12, v14, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v15, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v12, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 10, e8, mf8, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 12, e8, mf8, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 14, e8, mf8, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 12
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 6
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 14
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
ret <16 x i8> %res
@@ -10761,33 +12869,44 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vector_interleave_v4f16_v2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f16_v2f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
-; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vpairo.vv v11, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
ret <4 x half> %res
@@ -10796,33 +12915,44 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v4bf16_v2bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
-; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vpairo.vv v11, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <4 x bfloat> %res
@@ -10831,32 +12961,73 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vector_interleave_v8f16_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsll.vi v11, v12, 16
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 4
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f16_v4f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v10, v8, 2
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v13, v11, 16
; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v10, v9, 4
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v12, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v13, 4
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
@@ -10866,32 +13037,73 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v8bf16_v4bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v8, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v10
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsll.vi v11, v12, 16
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v10, v8, 4
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v10, v8, 2
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v13, v11, 16
; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v10, v9, 4
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v12, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v13, 4
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
@@ -10901,34 +13113,44 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vector_interleave_v4f32_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vmv1r.v v8, v10
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f32_v2f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vx v10, v9, a0
-; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vmv1r.v v8, v10
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vpairo.vv v11, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv.v.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
@@ -10937,35 +13159,77 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: vector_interleave_v16f16_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v10, v13, 16
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16f16_v8f16:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: li a0, 170
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vslidedown.vi v8, v8, 4
+; ZVBB-NEXT: vslidedown.vi v11, v9, 4
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v8, v9, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
-; ZVBB-NEXT: vwsll.vi v8, v10, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v8, v13
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: li a0, 170
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 8
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
@@ -10975,35 +13239,77 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v16bf16_v8bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vslidedown.vi v8, v8, 4
+; CHECK-NEXT: vslidedown.vi v11, v9, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vzext.vf2 v13, v11
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsll.vi v10, v13, 16
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVBB: # %bb.0:
+; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: li a0, 170
+; ZVBB-NEXT: vmv.s.x v0, a0
+; ZVBB-NEXT: vslidedown.vi v8, v8, 4
+; ZVBB-NEXT: vslidedown.vi v11, v9, 4
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vi v8, v9, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
-; ZVBB-NEXT: vwsll.vi v8, v10, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v8, v13
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: li a0, 170
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 4
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 8
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
@@ -11013,37 +13319,76 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: vector_interleave_v8f32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vslidedown.vi v8, v9, 2
+; CHECK-NEXT: vslidedown.vi v11, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vzext.vf2 v12, v8
+; CHECK-NEXT: vmv.v.i v0, 10
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v8, v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vsll.vx v10, v12, a0
+; CHECK-NEXT: vzext.vf2 v12, v11
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vwmaccu.vx v8, a0, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vwmaccu.vx v8, a0, v9
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f32_v4f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v8
+; ZVBB-NEXT: vslidedown.vi v8, v8, 2
+; ZVBB-NEXT: vmv.v.i v0, 10
+; ZVBB-NEXT: vslidedown.vi v11, v9, 2
; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vwsll.vx v8, v10, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v11
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB-NEXT: vzext.vf2 v12, v8
+; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vx v8, v9, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v10
+; ZVBB-NEXT: vwsll.vx v9, v11, a0
+; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
+; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVBB-NEXT: vslideup.vi v8, v10, 4
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v8, v13
+; ZVZIP-NEXT: vzip.vv v8, v10, v9
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv.v.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
@@ -11052,48 +13397,43 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: vector_interleave_v4f64_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 1
; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; CHECK-NEXT: vslideup.vi v8, v9, 1
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: lui a0, 12304
-; CHECK-NEXT: addi a0, a0, 512
-; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vsext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
-; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f64_v2f64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVBB-NEXT: vmv.v.i v0, 1
; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVBB-NEXT: vslideup.vi v8, v9, 1
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: lui a0, 12304
-; ZVBB-NEXT: addi a0, a0, 512
-; ZVBB-NEXT: vmv.s.x v10, a0
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vsext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
-; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v8
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vpairo.vv v12, v10, v9
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vmv1r.v v11, v8
-; ZVZIP-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-NEXT: vslideup.vi v8, v12, 2
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v10, v9
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v11, v8
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v10
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
@@ -11186,20 +13526,8 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 24
-; CHECK-NEXT: vle32.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle32.v v10, (a1)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 2
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
@@ -11209,68 +13537,67 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 24
-; ZVBB-NEXT: vle32.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle32.v v10, (a1)
-; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 2
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vle64.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave4_v8f32_v2f32:
; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v12, v9
+; ZVZIP-NEXT: vmv1r.v v13, v8
+; ZVZIP-NEXT: vslideup.vi v12, v11, 1
+; ZVZIP-NEXT: vslideup.vi v13, v10, 1
+; ZVZIP-NEXT: vpairo.vv v14, v8, v10
+; ZVZIP-NEXT: vpairo.vv v10, v9, v11
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-NEXT: vzip.vv v11, v8, v10
+; ZVZIP-NEXT: vzip.vv v8, v13, v12
+; ZVZIP-NEXT: vslideup.vi v13, v14, 2
+; ZVZIP-NEXT: vslideup.vi v12, v10, 2
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v12, 2
-; ZVZIP-NEXT: vslidedown.vi v9, v11, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v12, v8, 2
-; ZVZIP-NEXT: vslideup.vi v11, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v11, v12
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v10, v8, 4
+; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vzip.vv v10, v9, v12
+; ZVZIP-NEXT: vzip.vv v10, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave4_v8f32_v2f32:
; ZVZIP-ZVL2048: # %bb.0:
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v9, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v12, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v10, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v9, v12
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v11
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v8, 2
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v10, v8
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v10, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 4
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v9, v0.t
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 4
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 6
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 6
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
ret <8 x float> %res
@@ -12069,36 +14396,8 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 10
-; CHECK-NEXT: vle16.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: addi a1, sp, 12
-; CHECK-NEXT: vle16.v v11, (a1)
-; CHECK-NEXT: addi a1, sp, 2
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 4
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 1
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 1
-; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v11, 2
-; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: addi a0, sp, 6
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v12, 3
-; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -12108,123 +14407,86 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 10
-; ZVBB-NEXT: vle16.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle16.v v10, (a1)
-; ZVBB-NEXT: addi a1, sp, 12
-; ZVBB-NEXT: vle16.v v11, (a1)
-; ZVBB-NEXT: addi a1, sp, 2
-; ZVBB-NEXT: vle16.v v12, (a1)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 4
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 1
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v8, v12, 1
-; ZVBB-NEXT: addi a0, sp, 14
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v12, (a0)
-; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v11, 2
-; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: addi a0, sp, 6
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v12, 3
-; ZVBB-NEXT: vslideup.vi v8, v9, 3
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave8_v8f16_v1f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v16, v11, v15
-; ZVZIP-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-NEXT: vzip.vv v10, v8, v12
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v16, 1
-; ZVZIP-NEXT: vslidedown.vi v12, v11, 1
-; ZVZIP-NEXT: vslidedown.vi v13, v9, 1
-; ZVZIP-NEXT: vslidedown.vi v14, v10, 1
-; ZVZIP-NEXT: vslideup.vi v16, v8, 1
-; ZVZIP-NEXT: vslideup.vi v11, v12, 1
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslideup.vi v11, v15, 1
; ZVZIP-NEXT: vslideup.vi v9, v13, 1
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vmv1r.v v12, v9
; ZVZIP-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-NEXT: vmv1r.v v13, v8
+; ZVZIP-NEXT: vslideup.vi v12, v11, 1
+; ZVZIP-NEXT: vslideup.vi v13, v10, 1
+; ZVZIP-NEXT: vpairo.vv v14, v8, v10
+; ZVZIP-NEXT: vpairo.vv v10, v9, v11
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-NEXT: vzip.vv v8, v13, v12
+; ZVZIP-NEXT: vslideup.vi v13, v14, 2
+; ZVZIP-NEXT: vslideup.vi v12, v10, 2
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v12, 2
-; ZVZIP-NEXT: vslidedown.vi v9, v11, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v12, v8, 2
-; ZVZIP-NEXT: vslideup.vi v11, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v9, v10
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v11, v12
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v8, 4
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave8_v8f16_v1f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v16, v11, v15
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v12
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v16, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v11, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v13, v9, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v14, v10, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v16, v8, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v12, 1
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v15, 1
; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 1
; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v10, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v11, 2
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v13, v10
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v12, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v12
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v9, v8
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v8, 2
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v12, v8
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 3
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 1
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 2
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 3
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 5
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v11, 1
+; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v8, v11
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v13, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v11, v9, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 3
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v14, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 6
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v14, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 5
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 5
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 6
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 7
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v9, 6
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v14, 3
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 7
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 7
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)
ret <8 x half> %res
@@ -12237,36 +14499,8 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; CHECK-NEXT: mv a0, sp
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vsseg8e16.v v8, (a0)
-; CHECK-NEXT: addi a1, sp, 10
-; CHECK-NEXT: vle16.v v9, (a1)
-; CHECK-NEXT: addi a1, sp, 8
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: addi a1, sp, 12
-; CHECK-NEXT: vle16.v v11, (a1)
-; CHECK-NEXT: addi a1, sp, 2
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, sp, 4
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v9, 1
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v8, v12, 1
-; CHECK-NEXT: addi a0, sp, 14
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v12, (a0)
-; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v10, v11, 2
-; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: addi a0, sp, 6
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v12, 3
-; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
;
@@ -12276,123 +14510,86 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVBB-NEXT: mv a0, sp
; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
-; ZVBB-NEXT: addi a1, sp, 10
-; ZVBB-NEXT: vle16.v v9, (a1)
-; ZVBB-NEXT: addi a1, sp, 8
-; ZVBB-NEXT: vle16.v v10, (a1)
-; ZVBB-NEXT: addi a1, sp, 12
-; ZVBB-NEXT: vle16.v v11, (a1)
-; ZVBB-NEXT: addi a1, sp, 2
-; ZVBB-NEXT: vle16.v v12, (a1)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: addi a0, sp, 4
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 1
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v8, v12, 1
-; ZVBB-NEXT: addi a0, sp, 14
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v12, (a0)
-; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZVBB-NEXT: vslideup.vi v10, v11, 2
-; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: addi a0, sp, 6
-; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a0)
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v12, 3
-; ZVBB-NEXT: vslideup.vi v8, v9, 3
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v16, v11, v15
-; ZVZIP-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-NEXT: vzip.vv v10, v8, v12
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v16, 1
-; ZVZIP-NEXT: vslidedown.vi v12, v11, 1
-; ZVZIP-NEXT: vslidedown.vi v13, v9, 1
-; ZVZIP-NEXT: vslidedown.vi v14, v10, 1
-; ZVZIP-NEXT: vslideup.vi v16, v8, 1
-; ZVZIP-NEXT: vslideup.vi v11, v12, 1
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslideup.vi v11, v15, 1
; ZVZIP-NEXT: vslideup.vi v9, v13, 1
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vmv1r.v v12, v9
; ZVZIP-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-NEXT: vmv1r.v v13, v8
+; ZVZIP-NEXT: vslideup.vi v12, v11, 1
+; ZVZIP-NEXT: vslideup.vi v13, v10, 1
+; ZVZIP-NEXT: vpairo.vv v14, v8, v10
+; ZVZIP-NEXT: vpairo.vv v10, v9, v11
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-NEXT: vzip.vv v11, v10, v9
+; ZVZIP-NEXT: vzip.vv v8, v13, v12
+; ZVZIP-NEXT: vslideup.vi v13, v14, 2
+; ZVZIP-NEXT: vslideup.vi v12, v10, 2
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v12, 2
-; ZVZIP-NEXT: vslidedown.vi v9, v11, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v12, v8, 2
-; ZVZIP-NEXT: vslideup.vi v11, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-NEXT: vzip.vv v12, v9, v10
+; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v11, v12
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v8, 4
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v9, 4
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave8_v8bf16_v1bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v16, v11, v15
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v12
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v16, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v11, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v13, v9, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v14, v10, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v16, v8, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v12, 1
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v15, 1
; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 1
; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 1
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v10, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v11, 2
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v13, v10
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v12, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v12
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v9, v8
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v8, 2
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v12, v8
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 3
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 1
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 2
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 3
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 5
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v11, 1
+; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v8, v11
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v13, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v11, v9, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 3
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v14, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 6
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v14, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 5
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 5
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 6
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 7
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v9, 6
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v14, 3
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 7
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 7
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave8.v8bf16(<1 x bfloat> %a, <1 x bfloat> %b, <1 x bfloat> %c, <1 x bfloat> %d, <1 x bfloat> %e, <1 x bfloat> %f, <1 x bfloat> %g, <1 x bfloat> %h)
ret <8 x bfloat> %res
@@ -12455,8 +14652,3 @@ define <8 x i16> @interleave4_same_nonconst_splat_v8i16(i16 %a) {
%retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat)
ret <8 x i16> %retval
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; ZVZIP-RV32: {{.*}}
-; ZVZIP-RV64: {{.*}}
-; ZVZIP-ZVL2048-RV32: {{.*}}
-; ZVZIP-ZVL2048-RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 8493eca74d81b8..b752fb61324b34 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -492,13 +492,14 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vsseg3e8.v v14, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vl2r.v v8, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2r.v v8, (a2)
; CHECK-NEXT: vmsne.vi v10, v8, 0
; CHECK-NEXT: vl2r.v v8, (a0)
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: slli a2, a1, 2
+; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vl2r.v v8, (a2)
+; CHECK-NEXT: vl2r.v v8, (a0)
; CHECK-NEXT: vmsne.vi v11, v8, 0
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -533,13 +534,14 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vsseg3e8.v v14, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vl2r.v v8, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2r.v v8, (a2)
; ZVBB-NEXT: vmsne.vi v10, v8, 0
; ZVBB-NEXT: vl2r.v v8, (a0)
-; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a0, a0, a2
; ZVBB-NEXT: vmsne.vi v0, v8, 0
-; ZVBB-NEXT: vl2r.v v8, (a2)
+; ZVBB-NEXT: vl2r.v v8, (a0)
; ZVBB-NEXT: vmsne.vi v11, v8, 0
; ZVBB-NEXT: srli a0, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -571,9 +573,10 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv16i8(<vscale x 16 x i8>
; CHECK-NEXT: vsseg3e8.v v8, (a0)
; CHECK-NEXT: vl2r.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2r.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2r.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2r.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -595,9 +598,10 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-NEXT: vsseg3e8.v v8, (a0)
; ZVBB-NEXT: vl2r.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2r.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2r.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2r.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -624,9 +628,10 @@ define <vscale x 24 x i16> @vector_interleave_nxv24i16_nxv8i16(<vscale x 8 x i16
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re16.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -648,9 +653,10 @@ define <vscale x 24 x i16> @vector_interleave_nxv24i16_nxv8i16(<vscale x 8 x i16
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl2re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re16.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -677,9 +683,10 @@ define <vscale x 12 x i32> @vector_interleave_nxv12i32_nxv4i32(<vscale x 4 x i32
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: vl2re32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re32.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -701,9 +708,10 @@ define <vscale x 12 x i32> @vector_interleave_nxv12i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: vl2re32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re32.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re32.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -730,9 +738,10 @@ define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64>
; CHECK-NEXT: vsseg3e64.v v8, (a0)
; CHECK-NEXT: vl2re64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re64.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re64.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re64.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -754,9 +763,10 @@ define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
; ZVBB-NEXT: vl2re64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re64.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re64.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -791,14 +801,16 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; V-NEXT: vsseg4e8.v v14, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: slli a2, a1, 1
-; V-NEXT: add a3, a0, a2
+; V-NEXT: slli a3, a1, 2
; V-NEXT: add a4, a3, a2
-; V-NEXT: add a2, a4, a2
-; V-NEXT: vl2r.v v8, (a2)
-; V-NEXT: vmsne.vi v10, v8, 0
+; V-NEXT: add a4, a0, a4
; V-NEXT: vl2r.v v8, (a4)
-; V-NEXT: vmsne.vi v11, v8, 0
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vmsne.vi v10, v8, 0
; V-NEXT: vl2r.v v8, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vmsne.vi v11, v8, 0
+; V-NEXT: vl2r.v v8, (a2)
; V-NEXT: vmsne.vi v12, v8, 0
; V-NEXT: vl2r.v v8, (a0)
; V-NEXT: vmsne.vi v0, v8, 0
@@ -836,14 +848,16 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vsseg4e8.v v14, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 2
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vl2r.v v8, (a2)
-; ZVBB-NEXT: vmsne.vi v10, v8, 0
+; ZVBB-NEXT: add a4, a0, a4
; ZVBB-NEXT: vl2r.v v8, (a4)
-; ZVBB-NEXT: vmsne.vi v11, v8, 0
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vmsne.vi v10, v8, 0
; ZVBB-NEXT: vl2r.v v8, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vmsne.vi v11, v8, 0
+; ZVBB-NEXT: vl2r.v v8, (a2)
; ZVBB-NEXT: vmsne.vi v12, v8, 0
; ZVBB-NEXT: vl2r.v v8, (a0)
; ZVBB-NEXT: vmsne.vi v0, v8, 0
@@ -920,14 +934,16 @@ define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8>
; V-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; V-NEXT: vsseg4e8.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2r.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2r.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2r.v v14, (a2)
; V-NEXT: vl2r.v v8, (a0)
-; V-NEXT: vl2r.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2r.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -944,14 +960,16 @@ define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; ZVBB-NEXT: vsseg4e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2r.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2r.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2r.v v14, (a2)
; ZVBB-NEXT: vl2r.v v8, (a0)
-; ZVBB-NEXT: vl2r.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2r.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -981,13 +999,14 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a
; V-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; V-NEXT: vsseg4e8.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1r.v v10, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl1r.v v11, (a1)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1r.v v11, (a2)
; V-NEXT: vl1r.v v8, (a0)
-; V-NEXT: vl1r.v v9, (a2)
+; V-NEXT: vl1r.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 2
; V-NEXT: add sp, sp, a0
@@ -1004,13 +1023,14 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg4e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1r.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1r.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: vl1r.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -1041,14 +1061,16 @@ define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32
; V-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; V-NEXT: vsseg4e32.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2re32.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2re32.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2re32.v v14, (a2)
; V-NEXT: vl2re32.v v8, (a0)
-; V-NEXT: vl2re32.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2re32.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -1065,14 +1087,16 @@ define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re32.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re32.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v14, (a2)
; ZVBB-NEXT: vl2re32.v v8, (a0)
-; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -1103,14 +1127,16 @@ define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64>
; V-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; V-NEXT: vsseg4e64.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2re64.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2re64.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2re64.v v14, (a2)
; V-NEXT: vl2re64.v v8, (a0)
-; V-NEXT: vl2re64.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2re64.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -1127,14 +1153,16 @@ define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; ZVBB-NEXT: vsseg4e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re64.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re64.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v14, (a2)
; ZVBB-NEXT: vl2re64.v v8, (a0)
-; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re64.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -1176,51 +1204,54 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmv1r.v v22, v14
; CHECK-NEXT: vmv1r.v v23, v8
; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg5e8.v v20, (a0)
-; CHECK-NEXT: vmv1r.v v14, v19
-; CHECK-NEXT: vmv1r.v v16, v9
-; CHECK-NEXT: vmv1r.v v17, v25
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 2
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: slli a0, a1, 2
+; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsseg5e8.v v13, (a1)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsseg5e8.v v20, (a1)
+; CHECK-NEXT: vmv1r.v v14, v19
+; CHECK-NEXT: vmv1r.v v16, v9
+; CHECK-NEXT: vmv1r.v v17, v25
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vsseg5e8.v v13, (a2)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a3, a0, 1
+; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a4, a4, a2
-; CHECK-NEXT: vl1r.v v9, (a4)
-; CHECK-NEXT: vl1r.v v10, (a0)
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: add a0, a1, a2
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: add a4, a3, a0
+; CHECK-NEXT: add a5, a1, a4
+; CHECK-NEXT: vl1r.v v9, (a5)
+; CHECK-NEXT: vl1r.v v10, (a1)
+; CHECK-NEXT: add a5, a1, a0
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: add a5, a2, a0
+; CHECK-NEXT: vsetvli a6, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v12, v8, 0
-; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vl1r.v v9, (a0)
+; CHECK-NEXT: vl1r.v v8, (a5)
+; CHECK-NEXT: add a3, a2, a3
+; CHECK-NEXT: vl1r.v v9, (a3)
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: add a4, a4, a2
-; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: slli a3, a0, 2
+; CHECK-NEXT: add a1, a1, a3
+; CHECK-NEXT: vl1r.v v10, (a1)
; CHECK-NEXT: vmsne.vi v13, v8, 0
-; CHECK-NEXT: vl1r.v v11, (a1)
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: vl1r.v v10, (a0)
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: srli a1, a2, 2
-; CHECK-NEXT: vl1r.v v11, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: add a4, a2, a4
+; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: vl1r.v v11, (a2)
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vx v0, v12, a1
; CHECK-NEXT: vslideup.vx v9, v13, a1
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v8, v10, 0
-; CHECK-NEXT: srli a2, a2, 1
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v9, a2
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v0, v9, a0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 10
; CHECK-NEXT: mul a0, a0, a1
@@ -1250,51 +1281,54 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmv1r.v v22, v14
; ZVBB-NEXT: vmv1r.v v23, v8
; ZVBB-NEXT: vmerge.vim v24, v16, 1, v0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg5e8.v v20, (a0)
-; ZVBB-NEXT: vmv1r.v v14, v19
-; ZVBB-NEXT: vmv1r.v v16, v9
-; ZVBB-NEXT: vmv1r.v v17, v25
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a2, a1, 2
-; ZVBB-NEXT: add a1, a2, a1
+; ZVBB-NEXT: slli a0, a1, 2
+; ZVBB-NEXT: add a1, a0, a1
; ZVBB-NEXT: add a1, sp, a1
; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vsseg5e8.v v13, (a1)
-; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg5e8.v v20, (a1)
+; ZVBB-NEXT: vmv1r.v v14, v19
+; ZVBB-NEXT: vmv1r.v v16, v9
+; ZVBB-NEXT: vmv1r.v v17, v25
+; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: vsseg5e8.v v13, (a2)
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a3, a0, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a4, a4, a2
-; ZVBB-NEXT: vl1r.v v9, (a4)
-; ZVBB-NEXT: vl1r.v v10, (a0)
-; ZVBB-NEXT: vl1r.v v11, (a3)
-; ZVBB-NEXT: add a0, a1, a2
-; ZVBB-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; ZVBB-NEXT: add a4, a3, a0
+; ZVBB-NEXT: add a5, a1, a4
+; ZVBB-NEXT: vl1r.v v9, (a5)
+; ZVBB-NEXT: vl1r.v v10, (a1)
+; ZVBB-NEXT: add a5, a1, a0
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: add a5, a2, a0
+; ZVBB-NEXT: vsetvli a6, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v12, v8, 0
-; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: add a0, a0, a2
-; ZVBB-NEXT: vl1r.v v9, (a0)
+; ZVBB-NEXT: vl1r.v v8, (a5)
+; ZVBB-NEXT: add a3, a2, a3
+; ZVBB-NEXT: vl1r.v v9, (a3)
; ZVBB-NEXT: vmsne.vi v0, v10, 0
-; ZVBB-NEXT: add a4, a4, a2
-; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: slli a3, a0, 2
+; ZVBB-NEXT: add a1, a1, a3
+; ZVBB-NEXT: vl1r.v v10, (a1)
; ZVBB-NEXT: vmsne.vi v13, v8, 0
-; ZVBB-NEXT: vl1r.v v11, (a1)
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vmsne.vi v9, v10, 0
-; ZVBB-NEXT: add a0, a0, a2
-; ZVBB-NEXT: vl1r.v v10, (a0)
-; ZVBB-NEXT: add a0, a0, a2
-; ZVBB-NEXT: srli a1, a2, 2
-; ZVBB-NEXT: vl1r.v v11, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: add a4, a2, a4
+; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: add a2, a2, a3
+; ZVBB-NEXT: srli a1, a0, 2
+; ZVBB-NEXT: vl1r.v v11, (a2)
+; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; ZVBB-NEXT: vslideup.vx v0, v12, a1
; ZVBB-NEXT: vslideup.vx v9, v13, a1
-; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v8, v10, 0
-; ZVBB-NEXT: srli a2, a2, 1
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v9, a2
+; ZVBB-NEXT: srli a0, a0, 1
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v9, a0
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: li a1, 10
; ZVBB-NEXT: mul a0, a0, a1
@@ -1328,35 +1362,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e8.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e8.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1r.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1r.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1r.v v11, (a5)
; RV32-NEXT: vl1r.v v8, (a0)
-; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1r.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1r.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1r.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1r.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1r.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1r.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1r.v v12, (a0)
; RV32-NEXT: vl1r.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1r.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1r.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1r.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1r.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -1394,35 +1431,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e8.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e8.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1r.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1r.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1r.v v11, (a5)
; RV64-NEXT: vl1r.v v8, (a0)
-; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1r.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1r.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1r.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1r.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1r.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1r.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1r.v v12, (a0)
; RV64-NEXT: vl1r.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1r.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1r.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1r.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1r.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -1460,35 +1500,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e8.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e8.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1r.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1r.v v11, (a5)
; ZVBB-RV32-NEXT: vl1r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1r.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1r.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1r.v v12, (a0)
; ZVBB-RV32-NEXT: vl1r.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1r.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1r.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -1526,35 +1569,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e8.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e8.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1r.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1r.v v11, (a5)
; ZVBB-RV64-NEXT: vl1r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1r.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1r.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1r.v v12, (a0)
; ZVBB-RV64-NEXT: vl1r.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1r.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1r.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -1592,35 +1638,38 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
-; ZVZIP-NEXT: vsseg5e8.v v22, (a0)
-; ZVZIP-NEXT: vmv1r.v v18, v11
-; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vsseg5e8.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e8.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1r.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1r.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1r.v v11, (a5)
; ZVZIP-NEXT: vl1r.v v8, (a0)
-; ZVZIP-NEXT: vl1r.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1r.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1r.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1r.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1r.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1r.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1r.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1r.v v12, (a0)
; ZVZIP-NEXT: vl1r.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1r.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1r.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1r.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1r.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -1654,15 +1703,17 @@ define <vscale x 40 x i8> @vector_interleave_nxv40i8_nxv8i8(<vscale x 8 x i8> %a
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg5e8.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1r.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1r.v v12, (a1)
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -1681,15 +1732,17 @@ define <vscale x 40 x i8> @vector_interleave_nxv40i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg5e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1r.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1r.v v12, (a1)
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1r.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -1723,35 +1776,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e32.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e32.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
; RV32-NEXT: vl1re32.v v8, (a0)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re32.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re32.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re32.v v12, (a0)
; RV32-NEXT: vl1re32.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -1789,35 +1845,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e32.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e32.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
; RV64-NEXT: vl1re32.v v8, (a0)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re32.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re32.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re32.v v12, (a0)
; RV64-NEXT: vl1re32.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -1855,35 +1914,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -1921,35 +1983,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -1987,35 +2052,38 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e32.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e32.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
; ZVZIP-NEXT: vl1re32.v v8, (a0)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re32.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a0)
; ZVZIP-NEXT: vl1re32.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -2059,35 +2127,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e64.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e64.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
; RV32-NEXT: vl1re64.v v8, (a0)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re64.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re64.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re64.v v12, (a0)
; RV32-NEXT: vl1re64.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -2125,35 +2196,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e64.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e64.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
; RV64-NEXT: vl1re64.v v8, (a0)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re64.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re64.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re64.v v12, (a0)
; RV64-NEXT: vl1re64.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -2191,35 +2265,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -2257,35 +2334,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -2323,35 +2403,38 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e64.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e64.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
; ZVZIP-NEXT: vl1re64.v v8, (a0)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re64.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a0)
; ZVZIP-NEXT: vl1re64.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -2398,60 +2481,64 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmv1r.v v18, v25
; CHECK-NEXT: vmv1r.v v19, v11
; CHECK-NEXT: vmv1r.v v20, v13
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a0, 6
-; CHECK-NEXT: mul a1, a1, a0
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg6e8.v v15, (a1)
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsseg6e8.v v15, (a0)
; CHECK-NEXT: vmv1r.v v15, v22
; CHECK-NEXT: vmv1r.v v16, v8
; CHECK-NEXT: vmv1r.v v17, v24
; CHECK-NEXT: vmv1r.v v18, v10
; CHECK-NEXT: vmv1r.v v19, v12
-; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a1, 6
+; CHECK-NEXT: mul a2, a2, a1
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vsseg6e8.v v14, (a2)
-; CHECK-NEXT: vl1r.v v8, (a1)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: vl1r.v v9, (a1)
-; CHECK-NEXT: add a4, a3, a0
-; CHECK-NEXT: add a5, a4, a0
-; CHECK-NEXT: add a6, a5, a0
-; CHECK-NEXT: vl1r.v v10, (a6)
-; CHECK-NEXT: add a6, a6, a0
-; CHECK-NEXT: vl1r.v v11, (a6)
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vl1r.v v8, (a0)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: add a4, a2, a3
+; CHECK-NEXT: vl1r.v v10, (a4)
+; CHECK-NEXT: add a4, a3, a1
+; CHECK-NEXT: add a5, a2, a4
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: slli a5, a1, 1
+; CHECK-NEXT: add a6, a2, a5
+; CHECK-NEXT: vl1r.v v12, (a6)
+; CHECK-NEXT: add a6, a5, a1
+; CHECK-NEXT: vsetvli a7, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v14, v8, 0
-; CHECK-NEXT: vl1r.v v13, (a5)
+; CHECK-NEXT: add a7, a2, a6
+; CHECK-NEXT: vl1r.v v13, (a7)
; CHECK-NEXT: vmsne.vi v15, v10, 0
; CHECK-NEXT: vl1r.v v8, (a2)
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: vl1r.v v9, (a2)
; CHECK-NEXT: vmsne.vi v16, v12, 0
-; CHECK-NEXT: add a2, a1, a0
-; CHECK-NEXT: add a3, a2, a0
+; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl1r.v v10, (a3)
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vl1r.v v11, (a4)
+; CHECK-NEXT: add a5, a0, a5
; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: vl1r.v v10, (a1)
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vl1r.v v11, (a2)
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v15, v14, a1
-; CHECK-NEXT: vslideup.vx v0, v16, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vl1r.v v10, (a5)
+; CHECK-NEXT: add a0, a0, a6
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: vl1r.v v11, (a0)
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v15, v14, a2
+; CHECK-NEXT: vslideup.vx v0, v16, a2
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v8, v10, 0
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v15, a0
+; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v0, v15, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
+; CHECK-NEXT: vslideup.vx v8, v9, a2
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 12
; CHECK-NEXT: mul a0, a0, a1
@@ -2484,60 +2571,64 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmv1r.v v18, v25
; ZVBB-NEXT: vmv1r.v v19, v11
; ZVBB-NEXT: vmv1r.v v20, v13
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: li a0, 6
-; ZVBB-NEXT: mul a1, a1, a0
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg6e8.v v15, (a1)
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg6e8.v v15, (a0)
; ZVBB-NEXT: vmv1r.v v15, v22
; ZVBB-NEXT: vmv1r.v v16, v8
; ZVBB-NEXT: vmv1r.v v17, v24
; ZVBB-NEXT: vmv1r.v v18, v10
; ZVBB-NEXT: vmv1r.v v19, v12
-; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: csrr a2, vlenb
+; ZVBB-NEXT: li a1, 6
+; ZVBB-NEXT: mul a2, a2, a1
+; ZVBB-NEXT: add a2, sp, a2
+; ZVBB-NEXT: addi a2, a2, 16
; ZVBB-NEXT: vsseg6e8.v v14, (a2)
-; ZVBB-NEXT: vl1r.v v8, (a1)
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: add a1, a1, a0
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: vl1r.v v9, (a1)
-; ZVBB-NEXT: add a4, a3, a0
-; ZVBB-NEXT: add a5, a4, a0
-; ZVBB-NEXT: add a6, a5, a0
-; ZVBB-NEXT: vl1r.v v10, (a6)
-; ZVBB-NEXT: add a6, a6, a0
-; ZVBB-NEXT: vl1r.v v11, (a6)
-; ZVBB-NEXT: vl1r.v v12, (a4)
-; ZVBB-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmsne.vi v14, v8, 0
-; ZVBB-NEXT: vl1r.v v13, (a5)
-; ZVBB-NEXT: vmsne.vi v15, v10, 0
-; ZVBB-NEXT: vl1r.v v8, (a2)
-; ZVBB-NEXT: add a1, a1, a0
+; ZVBB-NEXT: vl1r.v v8, (a0)
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: vl1r.v v9, (a3)
-; ZVBB-NEXT: vmsne.vi v16, v12, 0
-; ZVBB-NEXT: add a2, a1, a0
-; ZVBB-NEXT: add a3, a2, a0
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a2, a3
+; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: add a5, a2, a4
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: slli a5, a1, 1
+; ZVBB-NEXT: add a6, a2, a5
+; ZVBB-NEXT: vl1r.v v12, (a6)
+; ZVBB-NEXT: add a6, a5, a1
+; ZVBB-NEXT: vsetvli a7, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vmsne.vi v14, v8, 0
+; ZVBB-NEXT: add a7, a2, a6
+; ZVBB-NEXT: vl1r.v v13, (a7)
+; ZVBB-NEXT: vmsne.vi v15, v10, 0
+; ZVBB-NEXT: vl1r.v v8, (a2)
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: vmsne.vi v16, v12, 0
+; ZVBB-NEXT: add a3, a0, a3
; ZVBB-NEXT: vl1r.v v10, (a3)
; ZVBB-NEXT: vmsne.vi v0, v8, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1r.v v11, (a4)
+; ZVBB-NEXT: add a5, a0, a5
; ZVBB-NEXT: vmsne.vi v9, v10, 0
-; ZVBB-NEXT: vl1r.v v10, (a1)
-; ZVBB-NEXT: srli a1, a0, 2
-; ZVBB-NEXT: vl1r.v v11, (a2)
-; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v15, v14, a1
-; ZVBB-NEXT: vslideup.vx v0, v16, a1
-; ZVBB-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vl1r.v v10, (a5)
+; ZVBB-NEXT: add a0, a0, a6
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vl1r.v v11, (a0)
+; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vx v15, v14, a2
+; ZVBB-NEXT: vslideup.vx v0, v16, a2
+; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v8, v10, 0
-; ZVBB-NEXT: srli a0, a0, 1
-; ZVBB-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v15, a0
+; ZVBB-NEXT: srli a1, a1, 1
+; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v15, a1
; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: li a1, 12
; ZVBB-NEXT: mul a0, a0, a1
@@ -2568,52 +2659,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e8.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e8.v v20, (a1)
-; RV32-NEXT: vl1r.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1r.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1r.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1r.v v13, (a6)
-; RV32-NEXT: vl1r.v v10, (a4)
-; RV32-NEXT: vl1r.v v11, (a5)
-; RV32-NEXT: vl1r.v v8, (a1)
-; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e8.v v20, (a2)
+; RV32-NEXT: vl1r.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1r.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1r.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1r.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1r.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1r.v v11, (a7)
+; RV32-NEXT: vl1r.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1r.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1r.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1r.v v19, (a3)
-; RV32-NEXT: vl1r.v v16, (a0)
-; RV32-NEXT: vl1r.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1r.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1r.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1r.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8r.v v16, (a2)
+; RV32-NEXT: vl8r.v v16, (a1)
; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -2639,52 +2734,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e8.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e8.v v20, (a1)
-; RV64-NEXT: vl1r.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1r.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1r.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1r.v v13, (a6)
-; RV64-NEXT: vl1r.v v10, (a4)
-; RV64-NEXT: vl1r.v v11, (a5)
-; RV64-NEXT: vl1r.v v8, (a1)
-; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e8.v v20, (a2)
+; RV64-NEXT: vl1r.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1r.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1r.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1r.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1r.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1r.v v11, (a7)
+; RV64-NEXT: vl1r.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1r.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1r.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1r.v v19, (a3)
-; RV64-NEXT: vl1r.v v16, (a0)
-; RV64-NEXT: vl1r.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1r.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1r.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1r.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8r.v v16, (a2)
+; RV64-NEXT: vl8r.v v16, (a1)
; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -2710,52 +2809,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e8.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e8.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1r.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1r.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1r.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e8.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1r.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1r.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1r.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1r.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1r.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1r.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1r.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1r.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8r.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8r.v v16, (a1)
; ZVBB-RV32-NEXT: vl8r.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -2781,52 +2884,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e8.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e8.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1r.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1r.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1r.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1r.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e8.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1r.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1r.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1r.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1r.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1r.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1r.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1r.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1r.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1r.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1r.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1r.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1r.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8r.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8r.v v16, (a1)
; ZVBB-RV64-NEXT: vl8r.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -2852,52 +2959,56 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e8.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e8.v v20, (a1)
-; ZVZIP-NEXT: vl1r.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1r.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1r.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1r.v v13, (a6)
-; ZVZIP-NEXT: vl1r.v v10, (a4)
-; ZVZIP-NEXT: vl1r.v v11, (a5)
-; ZVZIP-NEXT: vl1r.v v8, (a1)
-; ZVZIP-NEXT: vl1r.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e8.v v20, (a2)
+; ZVZIP-NEXT: vl1r.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1r.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1r.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1r.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1r.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1r.v v11, (a7)
+; ZVZIP-NEXT: vl1r.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1r.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1r.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1r.v v19, (a3)
-; ZVZIP-NEXT: vl1r.v v16, (a0)
-; ZVZIP-NEXT: vl1r.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1r.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1r.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1r.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8r.v v16, (a2)
+; ZVZIP-NEXT: vl8r.v v16, (a1)
; ZVZIP-NEXT: vl8r.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -2920,15 +3031,17 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv8i8(<vscale x 8 x i8> %a
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg6e8.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1r.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1r.v v11, (a2)
; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1r.v v12, (a3)
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1r.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1r.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -2949,15 +3062,17 @@ define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv8i8(<vscale x 8 x i8> %a
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg6e8.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1r.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1r.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1r.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -2990,52 +3105,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e32.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e32.v v20, (a1)
-; RV32-NEXT: vl1re32.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re32.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re32.v v13, (a6)
-; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: vl1re32.v v11, (a5)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e32.v v20, (a2)
+; RV32-NEXT: vl1re32.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v11, (a7)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re32.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re32.v v19, (a3)
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re32.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re32.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re32.v v16, (a2)
+; RV32-NEXT: vl8re32.v v16, (a1)
; RV32-NEXT: vl8re32.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3061,52 +3180,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e32.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e32.v v20, (a1)
-; RV64-NEXT: vl1re32.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re32.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re32.v v13, (a6)
-; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: vl1re32.v v11, (a5)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e32.v v20, (a2)
+; RV64-NEXT: vl1re32.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v11, (a7)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re32.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re32.v v19, (a3)
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re32.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re32.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re32.v v16, (a2)
+; RV64-NEXT: vl8re32.v v16, (a1)
; RV64-NEXT: vl8re32.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3132,52 +3255,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3203,52 +3330,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3274,52 +3405,56 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e32.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e32.v v20, (a1)
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re32.v v13, (a6)
-; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: vl1re32.v v11, (a5)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e32.v v20, (a2)
+; ZVZIP-NEXT: vl1re32.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v11, (a7)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re32.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re32.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re32.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v16, (a1)
; ZVZIP-NEXT: vl8re32.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3350,52 +3485,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e64.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e64.v v20, (a1)
-; RV32-NEXT: vl1re64.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re64.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re64.v v13, (a6)
-; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: vl1re64.v v11, (a5)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e64.v v20, (a2)
+; RV32-NEXT: vl1re64.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v11, (a7)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re64.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re64.v v19, (a3)
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re64.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re64.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re64.v v16, (a2)
+; RV32-NEXT: vl8re64.v v16, (a1)
; RV32-NEXT: vl8re64.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3421,52 +3560,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e64.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e64.v v20, (a1)
-; RV64-NEXT: vl1re64.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re64.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re64.v v13, (a6)
-; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: vl1re64.v v11, (a5)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e64.v v20, (a2)
+; RV64-NEXT: vl1re64.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v11, (a7)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re64.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re64.v v19, (a3)
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re64.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re64.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re64.v v16, (a2)
+; RV64-NEXT: vl8re64.v v16, (a1)
; RV64-NEXT: vl8re64.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3492,52 +3635,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -3563,52 +3710,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3634,52 +3785,56 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e64.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e64.v v20, (a1)
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re64.v v13, (a6)
-; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: vl1re64.v v11, (a5)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e64.v v20, (a2)
+; ZVZIP-NEXT: vl1re64.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v11, (a7)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re64.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re64.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re64.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v16, (a1)
; ZVZIP-NEXT: vl8re64.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -3719,53 +3874,58 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: vmv1r.v v24, v18
; CHECK-NEXT: vmv1r.v v25, v10
; CHECK-NEXT: vmerge.vim v26, v30, 1, v0
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a0, a3, 3
+; CHECK-NEXT: sub a3, a0, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg7e8.v v20, (a1)
+; CHECK-NEXT: vsseg7e8.v v20, (a3)
; CHECK-NEXT: vmv1r.v v16, v29
; CHECK-NEXT: vmv1r.v v18, v9
; CHECK-NEXT: vmv1r.v v20, v11
; CHECK-NEXT: vmv1r.v v21, v27
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a0, a2, 3
-; CHECK-NEXT: sub a2, a0, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vsseg7e8.v v15, (a2)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vsseg7e8.v v15, (a1)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: add a4, a3, a0
+; CHECK-NEXT: slli a2, a0, 1
+; CHECK-NEXT: add a4, a3, a2
; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v9, (a4)
-; CHECK-NEXT: vl1r.v v10, (a1)
-; CHECK-NEXT: vl1r.v v11, (a3)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vl1r.v v13, (a4)
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: add a4, a2, a0
+; CHECK-NEXT: add a5, a3, a4
+; CHECK-NEXT: vl1r.v v9, (a5)
+; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a5, a3, a0
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: slli a5, a0, 2
+; CHECK-NEXT: add a6, a3, a5
+; CHECK-NEXT: vl1r.v v12, (a6)
+; CHECK-NEXT: add a6, a5, a0
+; CHECK-NEXT: add a7, a3, a6
+; CHECK-NEXT: vl1r.v v13, (a7)
+; CHECK-NEXT: add a7, a5, a2
+; CHECK-NEXT: add a3, a3, a7
+; CHECK-NEXT: vsetvli t0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v14, v8, 0
-; CHECK-NEXT: vl1r.v v8, (a4)
-; CHECK-NEXT: add a1, a2, a0
-; CHECK-NEXT: vl1r.v v9, (a2)
+; CHECK-NEXT: vl1r.v v8, (a3)
+; CHECK-NEXT: vl1r.v v9, (a1)
; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: add a2, a1, a0
-; CHECK-NEXT: add a3, a2, a0
-; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a4, a1, a4
+; CHECK-NEXT: vl1r.v v10, (a4)
; CHECK-NEXT: vmsne.vi v15, v12, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a5, a1, a5
+; CHECK-NEXT: vl1r.v v11, (a5)
+; CHECK-NEXT: add a3, a1, a0
; CHECK-NEXT: vmsne.vi v16, v8, 0
-; CHECK-NEXT: vl1r.v v12, (a1)
+; CHECK-NEXT: vl1r.v v12, (a3)
+; CHECK-NEXT: add a2, a1, a2
; CHECK-NEXT: vl1r.v v13, (a2)
; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v10, (a3)
+; CHECK-NEXT: add a6, a1, a6
+; CHECK-NEXT: vl1r.v v10, (a6)
; CHECK-NEXT: vmsne.vi v8, v12, 0
-; CHECK-NEXT: add a3, a3, a0
-; CHECK-NEXT: vl1r.v v11, (a3)
+; CHECK-NEXT: add a1, a1, a7
+; CHECK-NEXT: vl1r.v v11, (a1)
; CHECK-NEXT: vmsne.vi v12, v10, 0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -3811,53 +3971,58 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: vmv1r.v v24, v18
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmerge.vim v26, v30, 1, v0
-; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: csrr a3, vlenb
+; ZVBB-NEXT: slli a0, a3, 3
+; ZVBB-NEXT: sub a3, a0, a3
+; ZVBB-NEXT: add a3, sp, a3
+; ZVBB-NEXT: addi a3, a3, 16
; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg7e8.v v20, (a1)
+; ZVBB-NEXT: vsseg7e8.v v20, (a3)
; ZVBB-NEXT: vmv1r.v v16, v29
; ZVBB-NEXT: vmv1r.v v18, v9
; ZVBB-NEXT: vmv1r.v v20, v11
; ZVBB-NEXT: vmv1r.v v21, v27
-; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: slli a0, a2, 3
-; ZVBB-NEXT: sub a2, a0, a2
-; ZVBB-NEXT: add a2, sp, a2
-; ZVBB-NEXT: addi a2, a2, 16
-; ZVBB-NEXT: vsseg7e8.v v15, (a2)
+; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: vsseg7e8.v v15, (a1)
; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: add a4, a3, a0
+; ZVBB-NEXT: slli a2, a0, 1
+; ZVBB-NEXT: add a4, a3, a2
; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v9, (a4)
-; ZVBB-NEXT: vl1r.v v10, (a1)
-; ZVBB-NEXT: vl1r.v v11, (a3)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v12, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v13, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; ZVBB-NEXT: add a4, a2, a0
+; ZVBB-NEXT: add a5, a3, a4
+; ZVBB-NEXT: vl1r.v v9, (a5)
+; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a5, a3, a0
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: slli a5, a0, 2
+; ZVBB-NEXT: add a6, a3, a5
+; ZVBB-NEXT: vl1r.v v12, (a6)
+; ZVBB-NEXT: add a6, a5, a0
+; ZVBB-NEXT: add a7, a3, a6
+; ZVBB-NEXT: vl1r.v v13, (a7)
+; ZVBB-NEXT: add a7, a5, a2
+; ZVBB-NEXT: add a3, a3, a7
+; ZVBB-NEXT: vsetvli t0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v14, v8, 0
-; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a1, a2, a0
-; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: vl1r.v v8, (a3)
+; ZVBB-NEXT: vl1r.v v9, (a1)
; ZVBB-NEXT: vmsne.vi v0, v10, 0
-; ZVBB-NEXT: add a2, a1, a0
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a4, a1, a4
+; ZVBB-NEXT: vl1r.v v10, (a4)
; ZVBB-NEXT: vmsne.vi v15, v12, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a5, a1, a5
+; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: add a3, a1, a0
; ZVBB-NEXT: vmsne.vi v16, v8, 0
-; ZVBB-NEXT: vl1r.v v12, (a1)
+; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: add a2, a1, a2
; ZVBB-NEXT: vl1r.v v13, (a2)
; ZVBB-NEXT: vmsne.vi v9, v10, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a6, a1, a6
+; ZVBB-NEXT: vl1r.v v10, (a6)
; ZVBB-NEXT: vmsne.vi v8, v12, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a1, a1, a7
+; ZVBB-NEXT: vl1r.v v11, (a1)
; ZVBB-NEXT: vmsne.vi v12, v10, 0
; ZVBB-NEXT: srli a1, a0, 2
; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
@@ -3903,59 +4068,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e8.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e8.v v21, (a2)
+; RV32-NEXT: vsseg7e8.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e8.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1r.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v11, (a4)
-; RV32-NEXT: vl1r.v v8, (a1)
-; RV32-NEXT: vl1r.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1r.v v14, (a4)
-; RV32-NEXT: vl1r.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1r.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1r.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1r.v v11, (a5)
+; RV32-NEXT: vl1r.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1r.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1r.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1r.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1r.v v14, (a2)
+; RV32-NEXT: vl1r.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1r.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1r.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1r.v v16, (a2)
-; RV32-NEXT: vl1r.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1r.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1r.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1r.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1r.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1r.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8r.v v16, (a0)
-; RV32-NEXT: vl8r.v v8, (a2)
+; RV32-NEXT: vl8r.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -3984,59 +4153,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e8.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e8.v v21, (a2)
+; RV64-NEXT: vsseg7e8.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e8.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1r.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v11, (a4)
-; RV64-NEXT: vl1r.v v8, (a1)
-; RV64-NEXT: vl1r.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1r.v v14, (a4)
-; RV64-NEXT: vl1r.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1r.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1r.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1r.v v11, (a5)
+; RV64-NEXT: vl1r.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1r.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1r.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1r.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1r.v v14, (a2)
+; RV64-NEXT: vl1r.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1r.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1r.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1r.v v16, (a2)
-; RV64-NEXT: vl1r.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1r.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1r.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1r.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1r.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1r.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8r.v v16, (a0)
-; RV64-NEXT: vl8r.v v8, (a2)
+; RV64-NEXT: vl8r.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4065,59 +4238,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e8.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e8.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e8.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e8.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1r.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1r.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1r.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1r.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1r.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1r.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1r.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1r.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1r.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1r.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1r.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1r.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1r.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1r.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1r.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1r.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8r.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8r.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4146,59 +4323,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e8.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e8.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e8.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e8.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1r.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1r.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1r.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1r.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1r.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1r.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1r.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1r.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1r.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1r.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1r.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1r.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1r.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1r.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1r.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1r.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1r.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1r.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1r.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1r.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1r.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1r.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1r.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8r.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8r.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4227,59 +4408,63 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e8.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e8.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e8.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e8.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1r.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v11, (a4)
-; ZVZIP-NEXT: vl1r.v v8, (a1)
-; ZVZIP-NEXT: vl1r.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1r.v v14, (a4)
-; ZVZIP-NEXT: vl1r.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1r.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1r.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1r.v v11, (a5)
+; ZVZIP-NEXT: vl1r.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1r.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1r.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1r.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1r.v v14, (a2)
+; ZVZIP-NEXT: vl1r.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1r.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1r.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1r.v v16, (a2)
-; ZVZIP-NEXT: vl1r.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1r.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1r.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1r.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1r.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1r.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8r.v v16, (a0)
-; ZVZIP-NEXT: vl8r.v v8, (a2)
+; ZVZIP-NEXT: vl8r.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4314,59 +4499,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e16.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e16.v v21, (a2)
+; RV32-NEXT: vsseg7e16.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e16.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v11, (a4)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v14, (a4)
-; RV32-NEXT: vl1re16.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re16.v v14, (a2)
+; RV32-NEXT: vl1re16.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re16.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re16.v v16, (a2)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re16.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re16.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re16.v v16, (a0)
-; RV32-NEXT: vl8re16.v v8, (a2)
+; RV32-NEXT: vl8re16.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4395,59 +4584,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e16.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e16.v v21, (a2)
+; RV64-NEXT: vsseg7e16.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e16.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v11, (a4)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v14, (a4)
-; RV64-NEXT: vl1re16.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re16.v v14, (a2)
+; RV64-NEXT: vl1re16.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re16.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re16.v v16, (a2)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re16.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re16.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re16.v v16, (a0)
-; RV64-NEXT: vl8re16.v v8, (a2)
+; RV64-NEXT: vl8re16.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4476,59 +4669,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4557,59 +4754,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4638,59 +4839,63 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e16.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e16.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v14, (a4)
-; ZVZIP-NEXT: vl1re16.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re16.v v14, (a2)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re16.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re16.v v16, (a2)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re16.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re16.v v16, (a0)
-; ZVZIP-NEXT: vl8re16.v v8, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4725,59 +4930,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e32.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e32.v v21, (a2)
+; RV32-NEXT: vsseg7e32.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e32.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v11, (a4)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v14, (a4)
-; RV32-NEXT: vl1re32.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re32.v v14, (a2)
+; RV32-NEXT: vl1re32.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re32.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re32.v v16, (a2)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re32.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re32.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re32.v v16, (a0)
-; RV32-NEXT: vl8re32.v v8, (a2)
+; RV32-NEXT: vl8re32.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4806,59 +5015,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e32.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e32.v v21, (a2)
+; RV64-NEXT: vsseg7e32.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e32.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v11, (a4)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v14, (a4)
-; RV64-NEXT: vl1re32.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re32.v v14, (a2)
+; RV64-NEXT: vl1re32.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re32.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re32.v v16, (a2)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re32.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re32.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re32.v v16, (a0)
-; RV64-NEXT: vl8re32.v v8, (a2)
+; RV64-NEXT: vl8re32.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -4887,59 +5100,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -4968,59 +5185,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5049,59 +5270,63 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e32.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e32.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e32.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e32.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v14, (a4)
-; ZVZIP-NEXT: vl1re32.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re32.v v14, (a2)
+; ZVZIP-NEXT: vl1re32.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re32.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re32.v v16, (a2)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re32.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re32.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re32.v v16, (a0)
-; ZVZIP-NEXT: vl8re32.v v8, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5135,59 +5360,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e64.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e64.v v21, (a2)
+; RV32-NEXT: vsseg7e64.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e64.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v11, (a4)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v14, (a4)
-; RV32-NEXT: vl1re64.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re64.v v14, (a2)
+; RV32-NEXT: vl1re64.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re64.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re64.v v16, (a2)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re64.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re64.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re64.v v16, (a0)
-; RV32-NEXT: vl8re64.v v8, (a2)
+; RV32-NEXT: vl8re64.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -5216,59 +5445,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e64.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e64.v v21, (a2)
+; RV64-NEXT: vsseg7e64.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e64.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v11, (a4)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v14, (a4)
-; RV64-NEXT: vl1re64.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re64.v v14, (a2)
+; RV64-NEXT: vl1re64.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re64.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re64.v v16, (a2)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re64.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re64.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re64.v v16, (a0)
-; RV64-NEXT: vl8re64.v v8, (a2)
+; RV64-NEXT: vl8re64.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5297,59 +5530,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -5378,59 +5615,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5459,59 +5700,63 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e64.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e64.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e64.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e64.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v14, (a4)
-; ZVZIP-NEXT: vl1re64.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re64.v v14, (a2)
+; ZVZIP-NEXT: vl1re64.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re64.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re64.v v16, (a2)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re64.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re64.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re64.v v16, (a0)
-; ZVZIP-NEXT: vl8re64.v v8, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -5553,68 +5798,75 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; V-NEXT: vmv1r.v v6, v11
; V-NEXT: vmv1r.v v7, v23
; V-NEXT: vmv1r.v v8, v13
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
-; V-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; V-NEXT: vsseg8e8.v v1, (a1)
+; V-NEXT: addi a0, sp, 16
+; V-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; V-NEXT: vsseg8e8.v v1, (a0)
; V-NEXT: vmv1r.v v17, v24
; V-NEXT: vmv1r.v v19, v28
; V-NEXT: vmv1r.v v21, v10
; V-NEXT: vmv1r.v v23, v12
-; V-NEXT: addi a2, sp, 16
+; V-NEXT: csrr a2, vlenb
+; V-NEXT: slli a2, a2, 3
+; V-NEXT: add a2, sp, a2
+; V-NEXT: addi a2, a2, 16
; V-NEXT: vsseg8e8.v v16, (a2)
-; V-NEXT: csrr a0, vlenb
-; V-NEXT: add a3, a1, a0
-; V-NEXT: add a4, a3, a0
-; V-NEXT: vl1r.v v8, (a4)
-; V-NEXT: add a4, a4, a0
-; V-NEXT: vl1r.v v9, (a4)
-; V-NEXT: vl1r.v v10, (a1)
-; V-NEXT: add a4, a4, a0
-; V-NEXT: vl1r.v v11, (a3)
-; V-NEXT: add a1, a4, a0
-; V-NEXT: add a3, a1, a0
-; V-NEXT: vl1r.v v12, (a3)
-; V-NEXT: add a3, a3, a0
-; V-NEXT: vl1r.v v13, (a3)
-; V-NEXT: add a3, a2, a0
-; V-NEXT: add a5, a3, a0
-; V-NEXT: vl1r.v v14, (a5)
-; V-NEXT: vsetvli a6, zero, e8, m2, ta, ma
+; V-NEXT: csrr a1, vlenb
+; V-NEXT: slli a4, a1, 1
+; V-NEXT: add a3, a0, a4
+; V-NEXT: vl1r.v v8, (a3)
+; V-NEXT: add a5, a4, a1
+; V-NEXT: add a3, a0, a5
+; V-NEXT: vl1r.v v9, (a3)
+; V-NEXT: vl1r.v v10, (a0)
+; V-NEXT: add a6, a0, a1
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: vl1r.v v11, (a6)
+; V-NEXT: add a6, a3, a4
+; V-NEXT: add a7, a0, a6
+; V-NEXT: slli t0, a1, 3
+; V-NEXT: vl1r.v v12, (a7)
+; V-NEXT: sub a7, t0, a1
+; V-NEXT: add t0, a0, a7
+; V-NEXT: vl1r.v v13, (t0)
+; V-NEXT: add a4, a2, a4
+; V-NEXT: vl1r.v v14, (a4)
+; V-NEXT: vsetvli a4, zero, e8, m2, ta, ma
; V-NEXT: vmsne.vi v16, v8, 0
-; V-NEXT: add a5, a5, a0
+; V-NEXT: add a5, a2, a5
; V-NEXT: vl1r.v v15, (a5)
; V-NEXT: vmsne.vi v8, v10, 0
; V-NEXT: vl1r.v v10, (a2)
-; V-NEXT: add a5, a5, a0
-; V-NEXT: vl1r.v v11, (a3)
+; V-NEXT: add a4, a2, a1
+; V-NEXT: vl1r.v v11, (a4)
; V-NEXT: vmsne.vi v9, v12, 0
-; V-NEXT: add a2, a5, a0
-; V-NEXT: add a3, a2, a0
-; V-NEXT: vl1r.v v12, (a3)
+; V-NEXT: add a6, a2, a6
+; V-NEXT: vl1r.v v12, (a6)
; V-NEXT: vmsne.vi v17, v14, 0
-; V-NEXT: add a3, a3, a0
-; V-NEXT: vl1r.v v13, (a3)
+; V-NEXT: add a7, a2, a7
+; V-NEXT: vl1r.v v13, (a7)
+; V-NEXT: add a4, a2, a3
; V-NEXT: vmsne.vi v0, v10, 0
-; V-NEXT: vl1r.v v10, (a5)
+; V-NEXT: vl1r.v v10, (a4)
+; V-NEXT: add a4, a3, a1
+; V-NEXT: add a2, a2, a4
; V-NEXT: vl1r.v v11, (a2)
; V-NEXT: vmsne.vi v14, v12, 0
-; V-NEXT: vl1r.v v12, (a4)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1r.v v12, (a3)
+; V-NEXT: add a0, a0, a4
; V-NEXT: vmsne.vi v15, v10, 0
-; V-NEXT: vl1r.v v13, (a1)
+; V-NEXT: vl1r.v v13, (a0)
; V-NEXT: vmsne.vi v10, v12, 0
-; V-NEXT: srli a1, a0, 2
+; V-NEXT: srli a0, a1, 2
; V-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; V-NEXT: vslideup.vx v15, v14, a1
-; V-NEXT: vslideup.vx v0, v17, a1
-; V-NEXT: vslideup.vx v10, v9, a1
-; V-NEXT: vslideup.vx v8, v16, a1
-; V-NEXT: srli a0, a0, 1
-; V-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; V-NEXT: vslideup.vx v0, v15, a0
-; V-NEXT: vslideup.vx v8, v10, a0
+; V-NEXT: vslideup.vx v15, v14, a0
+; V-NEXT: vslideup.vx v0, v17, a0
+; V-NEXT: vslideup.vx v10, v9, a0
+; V-NEXT: vslideup.vx v8, v16, a0
+; V-NEXT: srli a1, a1, 1
+; V-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; V-NEXT: vslideup.vx v0, v15, a1
+; V-NEXT: vslideup.vx v8, v10, a1
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -5652,68 +5904,75 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: vmv1r.v v6, v11
; ZVBB-NEXT: vmv1r.v v7, v23
; ZVBB-NEXT: vmv1r.v v8, v13
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg8e8.v v1, (a1)
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg8e8.v v1, (a0)
; ZVBB-NEXT: vmv1r.v v17, v24
; ZVBB-NEXT: vmv1r.v v19, v28
; ZVBB-NEXT: vmv1r.v v21, v10
; ZVBB-NEXT: vmv1r.v v23, v12
-; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: csrr a2, vlenb
+; ZVBB-NEXT: slli a2, a2, 3
+; ZVBB-NEXT: add a2, sp, a2
+; ZVBB-NEXT: addi a2, a2, 16
; ZVBB-NEXT: vsseg8e8.v v16, (a2)
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: add a4, a3, a0
-; ZVBB-NEXT: vl1r.v v8, (a4)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v9, (a4)
-; ZVBB-NEXT: vl1r.v v10, (a1)
-; ZVBB-NEXT: add a4, a4, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
-; ZVBB-NEXT: add a1, a4, a0
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: vl1r.v v12, (a3)
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v13, (a3)
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: add a5, a3, a0
-; ZVBB-NEXT: vl1r.v v14, (a5)
-; ZVBB-NEXT: vsetvli a6, zero, e8, m2, ta, ma
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: slli a4, a1, 1
+; ZVBB-NEXT: add a3, a0, a4
+; ZVBB-NEXT: vl1r.v v8, (a3)
+; ZVBB-NEXT: add a5, a4, a1
+; ZVBB-NEXT: add a3, a0, a5
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: vl1r.v v10, (a0)
+; ZVBB-NEXT: add a6, a0, a1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: vl1r.v v11, (a6)
+; ZVBB-NEXT: add a6, a3, a4
+; ZVBB-NEXT: add a7, a0, a6
+; ZVBB-NEXT: slli t0, a1, 3
+; ZVBB-NEXT: vl1r.v v12, (a7)
+; ZVBB-NEXT: sub a7, t0, a1
+; ZVBB-NEXT: add t0, a0, a7
+; ZVBB-NEXT: vl1r.v v13, (t0)
+; ZVBB-NEXT: add a4, a2, a4
+; ZVBB-NEXT: vl1r.v v14, (a4)
+; ZVBB-NEXT: vsetvli a4, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v16, v8, 0
-; ZVBB-NEXT: add a5, a5, a0
+; ZVBB-NEXT: add a5, a2, a5
; ZVBB-NEXT: vl1r.v v15, (a5)
; ZVBB-NEXT: vmsne.vi v8, v10, 0
; ZVBB-NEXT: vl1r.v v10, (a2)
-; ZVBB-NEXT: add a5, a5, a0
-; ZVBB-NEXT: vl1r.v v11, (a3)
+; ZVBB-NEXT: add a4, a2, a1
+; ZVBB-NEXT: vl1r.v v11, (a4)
; ZVBB-NEXT: vmsne.vi v9, v12, 0
-; ZVBB-NEXT: add a2, a5, a0
-; ZVBB-NEXT: add a3, a2, a0
-; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: add a6, a2, a6
+; ZVBB-NEXT: vl1r.v v12, (a6)
; ZVBB-NEXT: vmsne.vi v17, v14, 0
-; ZVBB-NEXT: add a3, a3, a0
-; ZVBB-NEXT: vl1r.v v13, (a3)
+; ZVBB-NEXT: add a7, a2, a7
+; ZVBB-NEXT: vl1r.v v13, (a7)
+; ZVBB-NEXT: add a4, a2, a3
; ZVBB-NEXT: vmsne.vi v0, v10, 0
-; ZVBB-NEXT: vl1r.v v10, (a5)
+; ZVBB-NEXT: vl1r.v v10, (a4)
+; ZVBB-NEXT: add a4, a3, a1
+; ZVBB-NEXT: add a2, a2, a4
; ZVBB-NEXT: vl1r.v v11, (a2)
; ZVBB-NEXT: vmsne.vi v14, v12, 0
-; ZVBB-NEXT: vl1r.v v12, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1r.v v12, (a3)
+; ZVBB-NEXT: add a0, a0, a4
; ZVBB-NEXT: vmsne.vi v15, v10, 0
-; ZVBB-NEXT: vl1r.v v13, (a1)
+; ZVBB-NEXT: vl1r.v v13, (a0)
; ZVBB-NEXT: vmsne.vi v10, v12, 0
-; ZVBB-NEXT: srli a1, a0, 2
+; ZVBB-NEXT: srli a0, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v15, v14, a1
-; ZVBB-NEXT: vslideup.vx v0, v17, a1
-; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vslideup.vx v8, v16, a1
-; ZVBB-NEXT: srli a0, a0, 1
-; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v15, a0
-; ZVBB-NEXT: vslideup.vx v8, v10, a0
+; ZVBB-NEXT: vslideup.vx v15, v14, a0
+; ZVBB-NEXT: vslideup.vx v0, v17, a0
+; ZVBB-NEXT: vslideup.vx v10, v9, a0
+; ZVBB-NEXT: vslideup.vx v8, v16, a0
+; ZVBB-NEXT: srli a1, a1, 1
+; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v15, a1
+; ZVBB-NEXT: vslideup.vx v8, v10, a1
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -5837,48 +6096,55 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e8.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e8.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1r.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1r.v v23, (t0)
-; V-NEXT: vl1r.v v20, (a6)
-; V-NEXT: vl1r.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1r.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1r.v v19, (a5)
; V-NEXT: vl1r.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1r.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1r.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1r.v v15, (a2)
-; V-NEXT: vl1r.v v12, (a3)
-; V-NEXT: vl1r.v v13, (a6)
-; V-NEXT: vl1r.v v10, (a4)
-; V-NEXT: vl1r.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1r.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1r.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1r.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1r.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1r.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1r.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1r.v v11, (a4)
; V-NEXT: vl1r.v v8, (a0)
-; V-NEXT: vl1r.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1r.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1r.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1r.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1r.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1r.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -5902,50 +6168,57 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8
; ZVBB-NEXT: vmv1r.v v4, v15
; ZVBB-NEXT: vmv1r.v v5, v29
; ZVBB-NEXT: vmv1r.v v6, v19
-; ZVBB-NEXT: vmv1r.v v7, v31
-; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: vmv1r.v v7, v31
+; ZVBB-NEXT: vmv1r.v v8, v23
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e8.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e8.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1r.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1r.v v23, (t0)
-; ZVBB-NEXT: vl1r.v v20, (a6)
-; ZVBB-NEXT: vl1r.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1r.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1r.v v19, (a5)
; ZVBB-NEXT: vl1r.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1r.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1r.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1r.v v15, (a2)
-; ZVBB-NEXT: vl1r.v v12, (a3)
-; ZVBB-NEXT: vl1r.v v13, (a6)
-; ZVBB-NEXT: vl1r.v v10, (a4)
-; ZVBB-NEXT: vl1r.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1r.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1r.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1r.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1r.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1r.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1r.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1r.v v11, (a4)
; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: vl1r.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1r.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1r.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1r.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1r.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -5995,48 +6268,55 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e16.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e16.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re16.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re16.v v23, (t0)
-; V-NEXT: vl1re16.v v20, (a6)
-; V-NEXT: vl1re16.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re16.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re16.v v19, (a5)
; V-NEXT: vl1re16.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re16.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re16.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re16.v v15, (a2)
-; V-NEXT: vl1re16.v v12, (a3)
-; V-NEXT: vl1re16.v v13, (a6)
-; V-NEXT: vl1re16.v v10, (a4)
-; V-NEXT: vl1re16.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re16.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re16.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re16.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re16.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re16.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re16.v v11, (a4)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re16.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re16.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re16.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re16.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -6062,48 +6342,55 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e16.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e16.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re16.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re16.v v23, (t0)
-; ZVBB-NEXT: vl1re16.v v20, (a6)
-; ZVBB-NEXT: vl1re16.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re16.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re16.v v19, (a5)
; ZVBB-NEXT: vl1re16.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re16.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re16.v v15, (a2)
-; ZVBB-NEXT: vl1re16.v v12, (a3)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
-; ZVBB-NEXT: vl1re16.v v10, (a4)
-; ZVBB-NEXT: vl1re16.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re16.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re16.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re16.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re16.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re16.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re16.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re16.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re16.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re16.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re16.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -6153,48 +6440,55 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e32.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e32.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re32.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re32.v v23, (t0)
-; V-NEXT: vl1re32.v v20, (a6)
-; V-NEXT: vl1re32.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re32.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re32.v v19, (a5)
; V-NEXT: vl1re32.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re32.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re32.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re32.v v15, (a2)
-; V-NEXT: vl1re32.v v12, (a3)
-; V-NEXT: vl1re32.v v13, (a6)
-; V-NEXT: vl1re32.v v10, (a4)
-; V-NEXT: vl1re32.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re32.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re32.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re32.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re32.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re32.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re32.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re32.v v11, (a4)
; V-NEXT: vl1re32.v v8, (a0)
-; V-NEXT: vl1re32.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re32.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re32.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re32.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re32.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re32.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -6220,48 +6514,55 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e32.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e32.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re32.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re32.v v23, (t0)
-; ZVBB-NEXT: vl1re32.v v20, (a6)
-; ZVBB-NEXT: vl1re32.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re32.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re32.v v19, (a5)
; ZVBB-NEXT: vl1re32.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re32.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re32.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re32.v v15, (a2)
-; ZVBB-NEXT: vl1re32.v v12, (a3)
-; ZVBB-NEXT: vl1re32.v v13, (a6)
-; ZVBB-NEXT: vl1re32.v v10, (a4)
-; ZVBB-NEXT: vl1re32.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re32.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re32.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re32.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re32.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re32.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re32.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re32.v v11, (a4)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re32.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re32.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re32.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re32.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -6310,48 +6611,55 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e64.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e64.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re64.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re64.v v23, (t0)
-; V-NEXT: vl1re64.v v20, (a6)
-; V-NEXT: vl1re64.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re64.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re64.v v19, (a5)
; V-NEXT: vl1re64.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re64.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re64.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re64.v v15, (a2)
-; V-NEXT: vl1re64.v v12, (a3)
-; V-NEXT: vl1re64.v v13, (a6)
-; V-NEXT: vl1re64.v v10, (a4)
-; V-NEXT: vl1re64.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re64.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re64.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re64.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re64.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re64.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re64.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re64.v v11, (a4)
; V-NEXT: vl1re64.v v8, (a0)
-; V-NEXT: vl1re64.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re64.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re64.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re64.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re64.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re64.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -6377,48 +6685,55 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e64.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e64.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re64.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re64.v v23, (t0)
-; ZVBB-NEXT: vl1re64.v v20, (a6)
-; ZVBB-NEXT: vl1re64.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re64.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re64.v v19, (a5)
; ZVBB-NEXT: vl1re64.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re64.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re64.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re64.v v15, (a2)
-; ZVBB-NEXT: vl1re64.v v12, (a3)
-; ZVBB-NEXT: vl1re64.v v13, (a6)
-; ZVBB-NEXT: vl1re64.v v10, (a4)
-; ZVBB-NEXT: vl1re64.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re64.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re64.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re64.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re64.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re64.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re64.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re64.v v11, (a4)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re64.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re64.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re64.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re64.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -6456,9 +6771,11 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; V-NEXT: li a0, -1
; V-NEXT: vwmaccu.vx v10, a0, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v8, v10, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v8, v10, a0
; V-NEXT: vslideup.vx v10, v8, a0
; V-NEXT: vmv.v.v v8, v10
; V-NEXT: ret
@@ -6469,9 +6786,11 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v8, v10, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v8, v10, a0
; ZVBB-NEXT: vslideup.vx v10, v8, a0
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
@@ -6480,6 +6799,10 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vslidedown.vx v8, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v8, a0
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
@@ -6525,9 +6848,11 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; V-NEXT: li a0, -1
; V-NEXT: vwmaccu.vx v10, a0, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v8, v10, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v8, v10, a0
; V-NEXT: vslideup.vx v10, v8, a0
; V-NEXT: vmv.v.v v8, v10
; V-NEXT: ret
@@ -6538,9 +6863,11 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v8, v10, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v8, v10, a0
; ZVBB-NEXT: vslideup.vx v10, v8, a0
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
@@ -6549,6 +6876,10 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vslidedown.vx v8, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v8, a0
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
@@ -6932,15 +7263,15 @@ define <vscale x 6 x half> @vector_interleave_nxv6f16_nxv2f16(<vscale x 2 x half
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vle16.v v9, (a3)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -6958,15 +7289,15 @@ define <vscale x 6 x half> @vector_interleave_nxv6f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vle16.v v9, (a3)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
-; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle16.v v9, (a2)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
@@ -6989,8 +7320,9 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl1re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re16.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7012,8 +7344,9 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl1re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re16.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7039,9 +7372,10 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv8f16(<vscale x 8 x ha
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re16.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7063,9 +7397,10 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl2re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re16.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7090,15 +7425,15 @@ define <vscale x 6 x bfloat> @vector_interleave_nxv6bf16_nxv2bf16(<vscale x 2 x
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vle16.v v9, (a3)
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vle16.v v9, (a2)
+; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -7116,15 +7451,15 @@ define <vscale x 6 x bfloat> @vector_interleave_nxv6bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vle16.v v9, (a3)
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
-; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle16.v v9, (a2)
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
@@ -7147,8 +7482,9 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl1re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re16.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re16.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7170,8 +7506,9 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl1re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re16.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7197,9 +7534,10 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv8bf16(<vscale x 8
; CHECK-NEXT: vsseg3e16.v v8, (a0)
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re16.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7221,9 +7559,10 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vsseg3e16.v v8, (a0)
; ZVBB-NEXT: vl2re16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re16.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7248,15 +7587,15 @@ define <vscale x 3 x float> @vector_interleave_nxv3f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vle32.v v9, (a3)
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v9, a1
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: add a2, a0, a2
; CHECK-NEXT: vle32.v v9, (a2)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v9, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -7274,15 +7613,15 @@ define <vscale x 3 x float> @vector_interleave_nxv3f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vle32.v v9, (a3)
-; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v9, a1
-; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle32.v v9, (a2)
+; ZVBB-NEXT: vle32.v v8, (a0)
+; ZVBB-NEXT: srli a2, a1, 3
+; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v9, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v9, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
@@ -7305,8 +7644,9 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv2f32(<vscale x 2 x flo
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: vl1re32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re32.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re32.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re32.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7328,8 +7668,9 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv2f32(<vscale x 2 x flo
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: vl1re32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re32.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7355,9 +7696,10 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv4f32(<vscale x 4 x f
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: vl2re32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re32.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re32.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re32.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7379,9 +7721,10 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: vl2re32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re32.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re32.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7407,8 +7750,9 @@ define <vscale x 3 x double> @vector_interleave_nxv3f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsseg3e64.v v8, (a0)
; CHECK-NEXT: vl1re64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl1re64.v v9, (a0)
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: vl1re64.v v9, (a2)
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl1re64.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7430,8 +7774,9 @@ define <vscale x 3 x double> @vector_interleave_nxv3f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
; ZVBB-NEXT: vl1re64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl1re64.v v9, (a0)
+; ZVBB-NEXT: add a2, a0, a1
+; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl1re64.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7457,9 +7802,10 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv2f64(<vscale x 2 x do
; CHECK-NEXT: vsseg3e64.v v8, (a0)
; CHECK-NEXT: vl2re64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vl2re64.v v10, (a0)
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vl2re64.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vl2re64.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
@@ -7481,9 +7827,10 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: vsseg3e64.v v8, (a0)
; ZVBB-NEXT: vl2re64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a0, a0, a1
-; ZVBB-NEXT: vl2re64.v v10, (a0)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 2
; ZVBB-NEXT: add a0, a0, a1
; ZVBB-NEXT: vl2re64.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
@@ -7508,12 +7855,12 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half
; V-NEXT: vsseg4e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: srli a2, a1, 1
-; V-NEXT: add a3, a0, a2
+; V-NEXT: add a3, a0, a1
; V-NEXT: add a4, a3, a2
-; V-NEXT: add a2, a4, a2
-; V-NEXT: vle16.v v8, (a2)
-; V-NEXT: vle16.v v9, (a4)
-; V-NEXT: vle16.v v10, (a3)
+; V-NEXT: vle16.v v8, (a4)
+; V-NEXT: vle16.v v9, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vle16.v v10, (a2)
; V-NEXT: srli a1, a1, 2
; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v9, v8, a1
@@ -7538,12 +7885,12 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
@@ -7559,11 +7906,22 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half
;
; ZVZIP-LABEL: vector_interleave_nxv8f16_nxv2f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v9, v11
; ZVZIP-NEXT: vzip.vv v11, v8, v10
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v9, v11, a0
+; ZVZIP-NEXT: vslideup.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v11, v9, a0
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v10, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v10, a0
+; ZVZIP-NEXT: vslidedown.vx v10, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v10, a0
; ZVZIP-NEXT: ret
%res = call <vscale x 8 x half> @llvm.vector.interleave4.nxv8f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3)
ret <vscale x 8 x half> %res
@@ -7580,13 +7938,14 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x ha
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; V-NEXT: vsseg4e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re16.v v10, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl1re16.v v11, (a1)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re16.v v11, (a2)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: vl1re16.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 2
; V-NEXT: add sp, sp, a0
@@ -7603,13 +7962,14 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -7639,14 +7999,16 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x ha
; V-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; V-NEXT: vsseg4e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2re16.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2re16.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2re16.v v14, (a2)
; V-NEXT: vl2re16.v v8, (a0)
-; V-NEXT: vl2re16.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2re16.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -7663,14 +8025,16 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re16.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re16.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v14, (a2)
; ZVBB-NEXT: vl2re16.v v8, (a0)
-; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -7701,12 +8065,12 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x
; V-NEXT: vsseg4e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: srli a2, a1, 1
-; V-NEXT: add a3, a0, a2
+; V-NEXT: add a3, a0, a1
; V-NEXT: add a4, a3, a2
-; V-NEXT: add a2, a4, a2
-; V-NEXT: vle16.v v8, (a2)
-; V-NEXT: vle16.v v9, (a4)
-; V-NEXT: vle16.v v10, (a3)
+; V-NEXT: vle16.v v8, (a4)
+; V-NEXT: vle16.v v9, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vle16.v v10, (a2)
; V-NEXT: srli a1, a1, 2
; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v9, v8, a1
@@ -7731,12 +8095,12 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
@@ -7752,11 +8116,22 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x
;
; ZVZIP-LABEL: vector_interleave_nxv8bf16_nxv2bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v9, v11
; ZVZIP-NEXT: vzip.vv v11, v8, v10
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v9, v11, a0
+; ZVZIP-NEXT: vslideup.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v11, v9, a0
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v10, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v10, a0
+; ZVZIP-NEXT: vslidedown.vx v10, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v10, a0
; ZVZIP-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.vector.interleave4.nxv8bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3)
ret <vscale x 8 x bfloat> %res
@@ -7773,13 +8148,14 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; V-NEXT: vsseg4e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re16.v v10, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl1re16.v v11, (a1)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re16.v v11, (a2)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: vl1re16.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 2
; V-NEXT: add sp, sp, a0
@@ -7796,13 +8172,14 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -7832,14 +8209,16 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8
; V-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; V-NEXT: vsseg4e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2re16.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2re16.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2re16.v v14, (a2)
; V-NEXT: vl2re16.v v8, (a0)
-; V-NEXT: vl2re16.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2re16.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -7856,14 +8235,16 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVBB-NEXT: vsseg4e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re16.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re16.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re16.v v14, (a2)
; ZVBB-NEXT: vl2re16.v v8, (a0)
-; ZVBB-NEXT: vl2re16.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -7894,12 +8275,12 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x flo
; V-NEXT: vsseg4e32.v v8, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: srli a2, a1, 1
-; V-NEXT: add a3, a0, a2
+; V-NEXT: add a3, a0, a1
; V-NEXT: add a4, a3, a2
-; V-NEXT: add a2, a4, a2
-; V-NEXT: vle32.v v8, (a2)
-; V-NEXT: vle32.v v9, (a4)
-; V-NEXT: vle32.v v10, (a3)
+; V-NEXT: vle32.v v8, (a4)
+; V-NEXT: vle32.v v9, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vle32.v v10, (a2)
; V-NEXT: srli a1, a1, 3
; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; V-NEXT: vslideup.vx v9, v8, a1
@@ -7924,12 +8305,12 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vle32.v v8, (a2)
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: vle32.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v10, (a2)
; ZVBB-NEXT: srli a1, a1, 3
; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
@@ -7945,11 +8326,22 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x flo
;
; ZVZIP-LABEL: vector_interleave_nxv4f32_nxv1f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 3
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v9, v11
; ZVZIP-NEXT: vzip.vv v11, v8, v10
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v9, v11, a0
+; ZVZIP-NEXT: vslideup.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v11, v9, a0
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v11, v12
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v10, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v10, a0
+; ZVZIP-NEXT: vslidedown.vx v10, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v10, a0
; ZVZIP-NEXT: ret
%res = call <vscale x 4 x float> @llvm.vector.interleave4.nxv4f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3)
ret <vscale x 4 x float> %res
@@ -7966,13 +8358,14 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x flo
; V-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; V-NEXT: vsseg4e32.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re32.v v10, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl1re32.v v11, (a1)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re32.v v11, (a2)
; V-NEXT: vl1re32.v v8, (a0)
-; V-NEXT: vl1re32.v v9, (a2)
+; V-NEXT: vl1re32.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 2
; V-NEXT: add sp, sp, a0
@@ -7989,13 +8382,14 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x flo
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: vl1re32.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -8025,14 +8419,16 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x f
; V-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; V-NEXT: vsseg4e32.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2re32.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2re32.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2re32.v v14, (a2)
; V-NEXT: vl2re32.v v8, (a0)
-; V-NEXT: vl2re32.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2re32.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -8049,14 +8445,16 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re32.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re32.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re32.v v14, (a2)
; ZVBB-NEXT: vl2re32.v v8, (a0)
-; ZVBB-NEXT: vl2re32.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -8086,13 +8484,14 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x do
; V-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; V-NEXT: vsseg4e64.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re64.v v10, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl1re64.v v11, (a1)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re64.v v11, (a2)
; V-NEXT: vl1re64.v v8, (a0)
-; V-NEXT: vl1re64.v v9, (a2)
+; V-NEXT: vl1re64.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 2
; V-NEXT: add sp, sp, a0
@@ -8109,13 +8508,14 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg4e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a1)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: vl1re64.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -8145,14 +8545,16 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x do
; V-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; V-NEXT: vsseg4e64.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 1
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
+; V-NEXT: slli a2, a1, 2
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl2re64.v v12, (a3)
-; V-NEXT: add a1, a3, a1
-; V-NEXT: vl2re64.v v14, (a1)
+; V-NEXT: slli a1, a1, 1
+; V-NEXT: add a2, a2, a1
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl2re64.v v14, (a2)
; V-NEXT: vl2re64.v v8, (a0)
-; V-NEXT: vl2re64.v v10, (a2)
+; V-NEXT: add a0, a0, a1
+; V-NEXT: vl2re64.v v10, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -8169,14 +8571,16 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; ZVBB-NEXT: vsseg4e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 2
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl2re64.v v12, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl2re64.v v14, (a1)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: add a2, a2, a1
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl2re64.v v14, (a2)
; ZVBB-NEXT: vl2re64.v v8, (a0)
-; ZVBB-NEXT: vl2re64.v v10, (a2)
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl2re64.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -8208,22 +8612,23 @@ define <vscale x 10 x half> @vector_interleave_nxv10f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a2
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: add a2, a5, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
@@ -8243,22 +8648,23 @@ define <vscale x 10 x half> @vector_interleave_nxv10f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
-; ZVBB-NEXT: srli a1, a1, 2
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: srli a2, a1, 2
; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
+; ZVBB-NEXT: vslideup.vx v9, v8, a2
; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
-; ZVBB-NEXT: add a2, a5, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 1
; ZVBB-NEXT: add a0, a1, a0
@@ -8281,15 +8687,17 @@ define <vscale x 20 x half> @vector_interleave_nxv20f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a1)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -8308,15 +8716,17 @@ define <vscale x 20 x half> @vector_interleave_nxv20f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a1)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -8348,35 +8758,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e16.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e16.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
; RV32-NEXT: vl1re16.v v8, (a0)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re16.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re16.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re16.v v12, (a0)
; RV32-NEXT: vl1re16.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -8414,35 +8827,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e16.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e16.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
; RV64-NEXT: vl1re16.v v8, (a0)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re16.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re16.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re16.v v12, (a0)
; RV64-NEXT: vl1re16.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -8480,35 +8896,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -8546,35 +8965,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -8612,35 +9034,38 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e16.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e16.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
; ZVZIP-NEXT: vl1re16.v v8, (a0)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a0)
; ZVZIP-NEXT: vl1re16.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -8674,22 +9099,23 @@ define <vscale x 10 x bfloat> @vector_interleave_nxv10bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 2
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a2
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: add a2, a5, a2
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
@@ -8709,22 +9135,23 @@ define <vscale x 10 x bfloat> @vector_interleave_nxv10bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v10, (a3)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v8, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
-; ZVBB-NEXT: add a2, a5, a2
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
; ZVBB-NEXT: vle16.v v10, (a2)
+; ZVBB-NEXT: srli a2, a1, 2
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a2
+; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v8, (a0)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 1
; ZVBB-NEXT: add a0, a1, a0
@@ -8747,15 +9174,17 @@ define <vscale x 20 x bfloat> @vector_interleave_nxv20bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a1)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -8774,15 +9203,17 @@ define <vscale x 20 x bfloat> @vector_interleave_nxv20bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a1)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -8814,35 +9245,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e16.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e16.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
; RV32-NEXT: vl1re16.v v8, (a0)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re16.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re16.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re16.v v12, (a0)
; RV32-NEXT: vl1re16.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -8880,35 +9314,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e16.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e16.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
; RV64-NEXT: vl1re16.v v8, (a0)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re16.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re16.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re16.v v12, (a0)
; RV64-NEXT: vl1re16.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -8946,35 +9383,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -9012,35 +9452,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e16.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re16.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re16.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -9078,35 +9521,38 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e16.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e16.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
; ZVZIP-NEXT: vl1re16.v v8, (a0)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a0)
; ZVZIP-NEXT: vl1re16.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -9140,22 +9586,23 @@ define <vscale x 5 x float> @vector_interleave_nxv5f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg5e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: vle32.v v8, (a5)
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v10, (a3)
-; CHECK-NEXT: srli a1, a1, 3
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: vle32.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
+; CHECK-NEXT: vslideup.vx v9, v8, a2
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
-; CHECK-NEXT: add a2, a5, a2
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
@@ -9175,22 +9622,23 @@ define <vscale x 5 x float> @vector_interleave_nxv5f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg5e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: add a3, a0, a1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vle32.v v8, (a5)
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v10, (a3)
-; ZVBB-NEXT: srli a1, a1, 3
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: vle32.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v10, (a2)
+; ZVBB-NEXT: srli a2, a1, 3
; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
+; ZVBB-NEXT: vslideup.vx v9, v8, a2
; ZVBB-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
-; ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
-; ZVBB-NEXT: add a2, a5, a2
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a2)
+; ZVBB-NEXT: slli a1, a1, 1
+; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 1
; ZVBB-NEXT: add a0, a1, a0
@@ -9213,15 +9661,17 @@ define <vscale x 10 x float> @vector_interleave_nxv10f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg5e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re32.v v11, (a2)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re32.v v12, (a1)
+; CHECK-NEXT: vl1re32.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re32.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -9240,15 +9690,17 @@ define <vscale x 10 x float> @vector_interleave_nxv10f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg5e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re32.v v12, (a1)
+; ZVBB-NEXT: vl1re32.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re32.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -9280,35 +9732,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e32.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e32.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
; RV32-NEXT: vl1re32.v v8, (a0)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re32.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re32.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re32.v v12, (a0)
; RV32-NEXT: vl1re32.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -9346,35 +9801,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e32.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e32.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
; RV64-NEXT: vl1re32.v v8, (a0)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re32.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re32.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re32.v v12, (a0)
; RV64-NEXT: vl1re32.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -9412,35 +9870,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -9478,35 +9939,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e32.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re32.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re32.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -9544,35 +10008,38 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e32.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e32.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
; ZVZIP-NEXT: vl1re32.v v8, (a0)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re32.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a0)
; ZVZIP-NEXT: vl1re32.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -9605,15 +10072,17 @@ define <vscale x 5 x double> @vector_interleave_nxv5f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg5e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re64.v v11, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re64.v v12, (a1)
+; CHECK-NEXT: vl1re64.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re64.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
; CHECK-NEXT: add a0, a1, a0
@@ -9632,15 +10101,17 @@ define <vscale x 5 x double> @vector_interleave_nxv5f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg5e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re64.v v12, (a1)
+; ZVBB-NEXT: vl1re64.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re64.v v12, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
; ZVBB-NEXT: add a0, a1, a0
@@ -9672,35 +10143,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv1r.v v26, v20
; RV32-NEXT: vmv1r.v v23, v10
; RV32-NEXT: vmv1r.v v25, v14
-; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 64
; RV32-NEXT: vsseg5e64.v v22, (a0)
; RV32-NEXT: vmv1r.v v18, v11
; RV32-NEXT: vmv1r.v v20, v15
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 2
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: addi a1, sp, 64
; RV32-NEXT: vsseg5e64.v v17, (a1)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a3, a0, a2
-; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: slli a3, a2, 1
+; RV32-NEXT: add a4, a0, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v11, (a4)
+; RV32-NEXT: add a4, a3, a2
+; RV32-NEXT: add a5, a0, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
; RV32-NEXT: vl1re64.v v8, (a0)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a1, a2
-; RV32-NEXT: vl1re64.v v14, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a4, a2
-; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a5, a0, a2
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: add a5, a1, a2
+; RV32-NEXT: vl1re64.v v14, (a5)
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a2, 2
+; RV32-NEXT: add a0, a0, a3
+; RV32-NEXT: vl1re64.v v12, (a0)
; RV32-NEXT: vl1re64.v v13, (a1)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v16, (a4)
+; RV32-NEXT: add a1, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a1)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 10
@@ -9738,35 +10212,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv1r.v v26, v20
; RV64-NEXT: vmv1r.v v23, v10
; RV64-NEXT: vmv1r.v v25, v14
-; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: vsseg5e64.v v22, (a0)
; RV64-NEXT: vmv1r.v v18, v11
; RV64-NEXT: vmv1r.v v20, v15
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 2
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: addi a1, sp, 64
; RV64-NEXT: vsseg5e64.v v17, (a1)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a3, a0, a2
-; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: slli a3, a2, 1
+; RV64-NEXT: add a4, a0, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v11, (a4)
+; RV64-NEXT: add a4, a3, a2
+; RV64-NEXT: add a5, a0, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
; RV64-NEXT: vl1re64.v v8, (a0)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a1, a2
-; RV64-NEXT: vl1re64.v v14, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a5, a0, a2
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: add a5, a1, a2
+; RV64-NEXT: vl1re64.v v14, (a5)
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a2, 2
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: vl1re64.v v12, (a0)
; RV64-NEXT: vl1re64.v v13, (a1)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v16, (a4)
+; RV64-NEXT: add a1, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a1)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 10
@@ -9804,35 +10281,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv1r.v v26, v20
; ZVBB-RV32-NEXT: vmv1r.v v23, v10
; ZVBB-RV32-NEXT: vmv1r.v v25, v14
-; ZVBB-RV32-NEXT: addi a0, sp, 64
+; ZVBB-RV32-NEXT: csrr a0, vlenb
+; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a0, a1, a0
+; ZVBB-RV32-NEXT: add a0, sp, a0
+; ZVBB-RV32-NEXT: addi a0, a0, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v18, v11
; ZVBB-RV32-NEXT: vmv1r.v v20, v15
-; ZVBB-RV32-NEXT: csrr a1, vlenb
-; ZVBB-RV32-NEXT: slli a2, a1, 2
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: add a1, sp, a1
-; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: addi a1, sp, 64
; ZVBB-RV32-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a3, a0, a2
-; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: slli a3, a2, 1
+; ZVBB-RV32-NEXT: add a4, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a2
+; ZVBB-RV32-NEXT: add a5, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV32-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a4, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a2
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: add a5, a1, a2
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a2, 2
+; ZVBB-RV32-NEXT: add a0, a0, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV32-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV32-NEXT: add a1, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV32-NEXT: slli a2, a2, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
; ZVBB-RV32-NEXT: li a1, 10
@@ -9870,35 +10350,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv1r.v v26, v20
; ZVBB-RV64-NEXT: vmv1r.v v23, v10
; ZVBB-RV64-NEXT: vmv1r.v v25, v14
-; ZVBB-RV64-NEXT: addi a0, sp, 64
+; ZVBB-RV64-NEXT: csrr a0, vlenb
+; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a0, a1, a0
+; ZVBB-RV64-NEXT: add a0, sp, a0
+; ZVBB-RV64-NEXT: addi a0, a0, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v22, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v18, v11
; ZVBB-RV64-NEXT: vmv1r.v v20, v15
-; ZVBB-RV64-NEXT: csrr a1, vlenb
-; ZVBB-RV64-NEXT: slli a2, a1, 2
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: add a1, sp, a1
-; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: addi a1, sp, 64
; ZVBB-RV64-NEXT: vsseg5e64.v v17, (a1)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a3, a0, a2
-; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: slli a3, a2, 1
+; ZVBB-RV64-NEXT: add a4, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a2
+; ZVBB-RV64-NEXT: add a5, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
; ZVBB-RV64-NEXT: vl1re64.v v8, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a4, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a2
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: add a5, a1, a2
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a5)
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a2, 2
+; ZVBB-RV64-NEXT: add a0, a0, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a0)
; ZVBB-RV64-NEXT: vl1re64.v v13, (a1)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a4)
+; ZVBB-RV64-NEXT: add a1, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
; ZVBB-RV64-NEXT: slli a2, a2, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
; ZVBB-RV64-NEXT: li a1, 10
@@ -9936,35 +10419,38 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: vmv1r.v v26, v20
; ZVZIP-NEXT: vmv1r.v v23, v10
; ZVZIP-NEXT: vmv1r.v v25, v14
-; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a0, a1, a0
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
; ZVZIP-NEXT: vsseg5e64.v v22, (a0)
; ZVZIP-NEXT: vmv1r.v v18, v11
; ZVZIP-NEXT: vmv1r.v v20, v15
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: slli a2, a1, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: add a1, sp, a1
-; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: addi a1, sp, 64
; ZVZIP-NEXT: vsseg5e64.v v17, (a1)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a3, a0, a2
-; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: slli a3, a2, 1
+; ZVZIP-NEXT: add a4, a0, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: add a5, a0, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
; ZVZIP-NEXT: vl1re64.v v8, (a0)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a1, a2
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a4, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a5, a0, a2
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re64.v v14, (a5)
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a0, a0, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a0)
; ZVZIP-NEXT: vl1re64.v v13, (a1)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v16, (a4)
+; ZVZIP-NEXT: add a1, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a1)
; ZVZIP-NEXT: slli a2, a2, 3
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: li a1, 10
@@ -9998,20 +10484,22 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a2, a6, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v11, (a5)
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -10037,20 +10525,22 @@ define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a2, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v11, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -10079,15 +10569,17 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -10108,15 +10600,17 @@ define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -10148,52 +10642,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e16.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e16.v v20, (a1)
-; RV32-NEXT: vl1re16.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re16.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re16.v v13, (a6)
-; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: vl1re16.v v11, (a5)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e16.v v20, (a2)
+; RV32-NEXT: vl1re16.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v11, (a7)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re16.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re16.v v19, (a3)
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re16.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re16.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re16.v v16, (a2)
+; RV32-NEXT: vl8re16.v v16, (a1)
; RV32-NEXT: vl8re16.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10219,52 +10717,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e16.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e16.v v20, (a1)
-; RV64-NEXT: vl1re16.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re16.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re16.v v13, (a6)
-; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: vl1re16.v v11, (a5)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e16.v v20, (a2)
+; RV64-NEXT: vl1re16.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v11, (a7)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re16.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re16.v v19, (a3)
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re16.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re16.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re16.v v16, (a2)
+; RV64-NEXT: vl8re16.v v16, (a1)
; RV64-NEXT: vl8re16.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10290,52 +10792,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10361,52 +10867,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10432,52 +10942,56 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e16.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e16.v v20, (a1)
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re16.v v13, (a6)
-; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: vl1re16.v v11, (a5)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e16.v v20, (a2)
+; ZVZIP-NEXT: vl1re16.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v11, (a7)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re16.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re16.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re16.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v16, (a1)
; ZVZIP-NEXT: vl8re16.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10501,20 +11015,22 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle16.v v10, (a3)
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a2, a6, a2
-; CHECK-NEXT: vle16.v v8, (a2)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: vle16.v v11, (a5)
+; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -10540,20 +11056,22 @@ define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a2, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a4, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v11, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -10582,15 +11100,17 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg6e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a2)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -10611,15 +11131,17 @@ define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg6e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -10651,52 +11173,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e16.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e16.v v20, (a1)
-; RV32-NEXT: vl1re16.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re16.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re16.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re16.v v13, (a6)
-; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: vl1re16.v v11, (a5)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e16.v v20, (a2)
+; RV32-NEXT: vl1re16.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re16.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re16.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v11, (a7)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re16.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re16.v v19, (a3)
-; RV32-NEXT: vl1re16.v v16, (a0)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re16.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re16.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re16.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re16.v v16, (a2)
+; RV32-NEXT: vl8re16.v v16, (a1)
; RV32-NEXT: vl8re16.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10722,52 +11248,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e16.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e16.v v20, (a1)
-; RV64-NEXT: vl1re16.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re16.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re16.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re16.v v13, (a6)
-; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: vl1re16.v v11, (a5)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e16.v v20, (a2)
+; RV64-NEXT: vl1re16.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re16.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re16.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v11, (a7)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re16.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re16.v v19, (a3)
-; RV64-NEXT: vl1re16.v v16, (a0)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re16.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re16.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re16.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re16.v v16, (a2)
+; RV64-NEXT: vl8re16.v v16, (a1)
; RV64-NEXT: vl8re16.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10793,52 +11323,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -10864,52 +11398,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e16.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e16.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re16.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -10935,52 +11473,56 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e16.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e16.v v20, (a1)
-; ZVZIP-NEXT: vl1re16.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re16.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re16.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re16.v v13, (a6)
-; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: vl1re16.v v11, (a5)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e16.v v20, (a2)
+; ZVZIP-NEXT: vl1re16.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re16.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re16.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v11, (a7)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re16.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
-; ZVZIP-NEXT: vl1re16.v v16, (a0)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re16.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re16.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re16.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v16, (a1)
; ZVZIP-NEXT: vl8re16.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11004,20 +11546,22 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg6e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: add a3, a0, a3
+; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: add a3, a0, a1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a2, a6, a2
-; CHECK-NEXT: vle32.v v8, (a2)
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: vle32.v v11, (a5)
+; CHECK-NEXT: vle32.v v11, (a4)
; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v12, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a3)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v12, (a2)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vx v9, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -11043,20 +11587,22 @@ define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg6e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a2, a6, a2
-; ZVBB-NEXT: vle32.v v8, (a2)
-; ZVBB-NEXT: vle32.v v10, (a6)
-; ZVBB-NEXT: vle32.v v11, (a5)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vle32.v v11, (a4)
; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vsetvli a4, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v12, (a3)
+; ZVBB-NEXT: vsetvli a4, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v9, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v11, a1
; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -11085,15 +11631,17 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg6e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re32.v v11, (a2)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v12, (a3)
+; CHECK-NEXT: vl1re32.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re32.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re32.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -11114,15 +11662,17 @@ define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg6e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v12, (a3)
+; ZVBB-NEXT: vl1re32.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re32.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re32.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -11154,52 +11704,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e32.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e32.v v20, (a1)
-; RV32-NEXT: vl1re32.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re32.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re32.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re32.v v13, (a6)
-; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: vl1re32.v v11, (a5)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e32.v v20, (a2)
+; RV32-NEXT: vl1re32.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re32.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re32.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v11, (a7)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re32.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re32.v v19, (a3)
-; RV32-NEXT: vl1re32.v v16, (a0)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re32.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re32.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re32.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re32.v v16, (a2)
+; RV32-NEXT: vl8re32.v v16, (a1)
; RV32-NEXT: vl8re32.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11225,52 +11779,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e32.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e32.v v20, (a1)
-; RV64-NEXT: vl1re32.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re32.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re32.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re32.v v13, (a6)
-; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: vl1re32.v v11, (a5)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e32.v v20, (a2)
+; RV64-NEXT: vl1re32.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re32.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re32.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v11, (a7)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re32.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re32.v v19, (a3)
-; RV64-NEXT: vl1re32.v v16, (a0)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re32.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re32.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re32.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re32.v v16, (a2)
+; RV64-NEXT: vl8re32.v v16, (a1)
; RV64-NEXT: vl8re32.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11296,52 +11854,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11367,52 +11929,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e32.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e32.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re32.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11438,52 +12004,56 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e32.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
-; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e32.v v20, (a1)
-; ZVZIP-NEXT: vl1re32.v v14, (a0)
+; ZVZIP-NEXT: vmv1r.v v25, v18
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re32.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re32.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re32.v v13, (a6)
-; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: vl1re32.v v11, (a5)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e32.v v20, (a2)
+; ZVZIP-NEXT: vl1re32.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re32.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re32.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v11, (a7)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re32.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
-; ZVZIP-NEXT: vl1re32.v v16, (a0)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re32.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re32.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re32.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v16, (a1)
; ZVZIP-NEXT: vl8re32.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11506,15 +12076,17 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg6e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: vl1re64.v v11, (a2)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v12, (a3)
+; CHECK-NEXT: vl1re64.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re64.v v12, (a0)
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: vl1re64.v v13, (a1)
; CHECK-NEXT: csrr a0, vlenb
@@ -11535,15 +12107,17 @@ define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg6e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a2, a3, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v12, (a3)
+; ZVBB-NEXT: vl1re64.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re64.v v12, (a0)
; ZVBB-NEXT: add a1, a3, a1
; ZVBB-NEXT: vl1re64.v v13, (a1)
; ZVBB-NEXT: csrr a0, vlenb
@@ -11575,52 +12149,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv1r.v v24, v15
; RV32-NEXT: vmv1r.v v25, v17
; RV32-NEXT: vmv1r.v v26, v19
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 6
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 64
+; RV32-NEXT: addi a0, sp, 64
; RV32-NEXT: vsseg6e64.v v21, (a0)
; RV32-NEXT: vmv1r.v v21, v10
; RV32-NEXT: vmv1r.v v22, v12
; RV32-NEXT: vmv1r.v v23, v14
; RV32-NEXT: vmv1r.v v24, v16
; RV32-NEXT: vmv1r.v v25, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg6e64.v v20, (a1)
-; RV32-NEXT: vl1re64.v v14, (a0)
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a3, a1, a2
-; RV32-NEXT: vl1re64.v v15, (a0)
-; RV32-NEXT: add a4, a3, a2
-; RV32-NEXT: add a5, a4, a2
-; RV32-NEXT: add a6, a5, a2
-; RV32-NEXT: vl1re64.v v12, (a6)
-; RV32-NEXT: add a6, a6, a2
-; RV32-NEXT: vl1re64.v v13, (a6)
-; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: vl1re64.v v11, (a5)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: add a1, a0, a2
-; RV32-NEXT: add a3, a1, a2
+; RV32-NEXT: li a1, 6
+; RV32-NEXT: mul a2, a2, a1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 64
+; RV32-NEXT: vsseg6e64.v v20, (a2)
+; RV32-NEXT: vl1re64.v v14, (a0)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: add a3, a0, a1
+; RV32-NEXT: vl1re64.v v15, (a3)
+; RV32-NEXT: slli a3, a1, 2
+; RV32-NEXT: add a4, a2, a3
+; RV32-NEXT: vl1re64.v v12, (a4)
+; RV32-NEXT: add a4, a3, a1
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v13, (a5)
+; RV32-NEXT: slli a5, a1, 1
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v10, (a6)
+; RV32-NEXT: add a6, a5, a1
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v11, (a7)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a2, a2, a1
+; RV32-NEXT: vl1re64.v v9, (a2)
+; RV32-NEXT: add a3, a0, a3
; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a2
-; RV32-NEXT: vl1re64.v v19, (a3)
-; RV32-NEXT: vl1re64.v v16, (a0)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a4, a0, a4
+; RV32-NEXT: vl1re64.v v19, (a4)
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: vl1re64.v v16, (a5)
+; RV32-NEXT: add a0, a0, a6
+; RV32-NEXT: vl1re64.v v17, (a0)
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 12
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: li a2, 12
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 64
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs4r.v v16, (a2)
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs4r.v v16, (a1)
; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: vl8re64.v v16, (a2)
+; RV32-NEXT: vl8re64.v v16, (a1)
; RV32-NEXT: vl8re64.v v8, (a0)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11646,52 +12224,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv1r.v v24, v15
; RV64-NEXT: vmv1r.v v25, v17
; RV64-NEXT: vmv1r.v v26, v19
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 6
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 64
+; RV64-NEXT: addi a0, sp, 64
; RV64-NEXT: vsseg6e64.v v21, (a0)
; RV64-NEXT: vmv1r.v v21, v10
; RV64-NEXT: vmv1r.v v22, v12
; RV64-NEXT: vmv1r.v v23, v14
; RV64-NEXT: vmv1r.v v24, v16
; RV64-NEXT: vmv1r.v v25, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg6e64.v v20, (a1)
-; RV64-NEXT: vl1re64.v v14, (a0)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a3, a1, a2
-; RV64-NEXT: vl1re64.v v15, (a0)
-; RV64-NEXT: add a4, a3, a2
-; RV64-NEXT: add a5, a4, a2
-; RV64-NEXT: add a6, a5, a2
-; RV64-NEXT: vl1re64.v v12, (a6)
-; RV64-NEXT: add a6, a6, a2
-; RV64-NEXT: vl1re64.v v13, (a6)
-; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: vl1re64.v v11, (a5)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: add a1, a0, a2
-; RV64-NEXT: add a3, a1, a2
+; RV64-NEXT: li a1, 6
+; RV64-NEXT: mul a2, a2, a1
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 64
+; RV64-NEXT: vsseg6e64.v v20, (a2)
+; RV64-NEXT: vl1re64.v v14, (a0)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: add a3, a0, a1
+; RV64-NEXT: vl1re64.v v15, (a3)
+; RV64-NEXT: slli a3, a1, 2
+; RV64-NEXT: add a4, a2, a3
+; RV64-NEXT: vl1re64.v v12, (a4)
+; RV64-NEXT: add a4, a3, a1
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v13, (a5)
+; RV64-NEXT: slli a5, a1, 1
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v10, (a6)
+; RV64-NEXT: add a6, a5, a1
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v11, (a7)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a2, a2, a1
+; RV64-NEXT: vl1re64.v v9, (a2)
+; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: vl1re64.v v19, (a3)
-; RV64-NEXT: vl1re64.v v16, (a0)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: add a4, a0, a4
+; RV64-NEXT: vl1re64.v v19, (a4)
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: vl1re64.v v16, (a5)
+; RV64-NEXT: add a0, a0, a6
+; RV64-NEXT: vl1re64.v v17, (a0)
+; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 12
-; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: li a2, 12
+; RV64-NEXT: mul a0, a0, a2
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 64
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs4r.v v16, (a2)
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs4r.v v16, (a1)
; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vl8re64.v v16, (a2)
+; RV64-NEXT: vl8re64.v v16, (a1)
; RV64-NEXT: vl8re64.v v8, (a0)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11717,52 +12299,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv1r.v v24, v15
; ZVBB-RV32-NEXT: vmv1r.v v25, v17
; ZVBB-RV32-NEXT: vmv1r.v v26, v19
-; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 6
-; ZVBB-RV32-NEXT: mul a0, a0, a1
-; ZVBB-RV32-NEXT: add a0, sp, a0
-; ZVBB-RV32-NEXT: addi a0, a0, 64
+; ZVBB-RV32-NEXT: addi a0, sp, 64
; ZVBB-RV32-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV32-NEXT: vmv1r.v v21, v10
; ZVBB-RV32-NEXT: vmv1r.v v22, v12
; ZVBB-RV32-NEXT: vmv1r.v v23, v14
; ZVBB-RV32-NEXT: vmv1r.v v24, v16
; ZVBB-RV32-NEXT: vmv1r.v v25, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV32-NEXT: add a4, a3, a2
-; ZVBB-RV32-NEXT: add a5, a4, a2
-; ZVBB-RV32-NEXT: add a6, a5, a2
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV32-NEXT: add a6, a6, a2
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a0, a0, a2
-; ZVBB-RV32-NEXT: add a1, a0, a2
-; ZVBB-RV32-NEXT: add a3, a1, a2
+; ZVBB-RV32-NEXT: li a1, 6
+; ZVBB-RV32-NEXT: mul a2, a2, a1
+; ZVBB-RV32-NEXT: add a2, sp, a2
+; ZVBB-RV32-NEXT: addi a2, a2, 64
+; ZVBB-RV32-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: add a3, a0, a1
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV32-NEXT: slli a3, a1, 2
+; ZVBB-RV32-NEXT: add a4, a2, a3
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV32-NEXT: add a4, a3, a1
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV32-NEXT: slli a5, a1, 1
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a1
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a2, a2, a1
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV32-NEXT: add a3, a0, a3
; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a2
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV32-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: slli a2, a2, 3
+; ZVBB-RV32-NEXT: add a4, a0, a4
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV32-NEXT: add a0, a0, a6
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV32-NEXT: slli a1, a1, 3
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: li a1, 12
-; ZVBB-RV32-NEXT: mul a0, a0, a1
+; ZVBB-RV32-NEXT: li a2, 12
+; ZVBB-RV32-NEXT: mul a0, a0, a2
; ZVBB-RV32-NEXT: add a0, sp, a0
; ZVBB-RV32-NEXT: addi a0, a0, 64
-; ZVBB-RV32-NEXT: add a2, a0, a2
-; ZVBB-RV32-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV32-NEXT: add a1, a0, a1
+; ZVBB-RV32-NEXT: vs4r.v v16, (a1)
; ZVBB-RV32-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -11788,52 +12374,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv1r.v v24, v15
; ZVBB-RV64-NEXT: vmv1r.v v25, v17
; ZVBB-RV64-NEXT: vmv1r.v v26, v19
-; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 6
-; ZVBB-RV64-NEXT: mul a0, a0, a1
-; ZVBB-RV64-NEXT: add a0, sp, a0
-; ZVBB-RV64-NEXT: addi a0, a0, 64
+; ZVBB-RV64-NEXT: addi a0, sp, 64
; ZVBB-RV64-NEXT: vsseg6e64.v v21, (a0)
; ZVBB-RV64-NEXT: vmv1r.v v21, v10
; ZVBB-RV64-NEXT: vmv1r.v v22, v12
; ZVBB-RV64-NEXT: vmv1r.v v23, v14
; ZVBB-RV64-NEXT: vmv1r.v v24, v16
; ZVBB-RV64-NEXT: vmv1r.v v25, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a0)
-; ZVBB-RV64-NEXT: add a4, a3, a2
-; ZVBB-RV64-NEXT: add a5, a4, a2
-; ZVBB-RV64-NEXT: add a6, a5, a2
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
-; ZVBB-RV64-NEXT: add a6, a6, a2
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a6)
-; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a0, a0, a2
-; ZVBB-RV64-NEXT: add a1, a0, a2
-; ZVBB-RV64-NEXT: add a3, a1, a2
+; ZVBB-RV64-NEXT: li a1, 6
+; ZVBB-RV64-NEXT: mul a2, a2, a1
+; ZVBB-RV64-NEXT: add a2, sp, a2
+; ZVBB-RV64-NEXT: addi a2, a2, 64
+; ZVBB-RV64-NEXT: vsseg6e64.v v20, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a0)
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: add a3, a0, a1
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a3)
+; ZVBB-RV64-NEXT: slli a3, a1, 2
+; ZVBB-RV64-NEXT: add a4, a2, a3
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
+; ZVBB-RV64-NEXT: add a4, a3, a1
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a5)
+; ZVBB-RV64-NEXT: slli a5, a1, 1
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v10, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a1
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a7)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a2, a2, a1
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a2)
+; ZVBB-RV64-NEXT: add a3, a0, a3
; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a2
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
-; ZVBB-RV64-NEXT: vl1re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: slli a2, a2, 3
+; ZVBB-RV64-NEXT: add a4, a0, a4
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a4)
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: vl1re64.v v16, (a5)
+; ZVBB-RV64-NEXT: add a0, a0, a6
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a0)
+; ZVBB-RV64-NEXT: slli a1, a1, 3
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: li a1, 12
-; ZVBB-RV64-NEXT: mul a0, a0, a1
+; ZVBB-RV64-NEXT: li a2, 12
+; ZVBB-RV64-NEXT: mul a0, a0, a2
; ZVBB-RV64-NEXT: add a0, sp, a0
; ZVBB-RV64-NEXT: addi a0, a0, 64
-; ZVBB-RV64-NEXT: add a2, a0, a2
-; ZVBB-RV64-NEXT: vs4r.v v16, (a2)
+; ZVBB-RV64-NEXT: add a1, a0, a1
+; ZVBB-RV64-NEXT: vs4r.v v16, (a1)
; ZVBB-RV64-NEXT: vs8r.v v8, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v16, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v16, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v8, (a0)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11859,52 +12449,56 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: vmv1r.v v24, v15
; ZVZIP-NEXT: vmv1r.v v25, v17
; ZVZIP-NEXT: vmv1r.v v26, v19
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 6
-; ZVZIP-NEXT: mul a0, a0, a1
-; ZVZIP-NEXT: add a0, sp, a0
-; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: addi a0, sp, 64
; ZVZIP-NEXT: vsseg6e64.v v21, (a0)
; ZVZIP-NEXT: vmv1r.v v21, v10
; ZVZIP-NEXT: vmv1r.v v22, v12
; ZVZIP-NEXT: vmv1r.v v23, v14
; ZVZIP-NEXT: vmv1r.v v24, v16
; ZVZIP-NEXT: vmv1r.v v25, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg6e64.v v20, (a1)
-; ZVZIP-NEXT: vl1re64.v v14, (a0)
; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
-; ZVZIP-NEXT: vl1re64.v v15, (a0)
-; ZVZIP-NEXT: add a4, a3, a2
-; ZVZIP-NEXT: add a5, a4, a2
-; ZVZIP-NEXT: add a6, a5, a2
-; ZVZIP-NEXT: vl1re64.v v12, (a6)
-; ZVZIP-NEXT: add a6, a6, a2
-; ZVZIP-NEXT: vl1re64.v v13, (a6)
-; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: vl1re64.v v11, (a5)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a0, a0, a2
-; ZVZIP-NEXT: add a1, a0, a2
-; ZVZIP-NEXT: add a3, a1, a2
+; ZVZIP-NEXT: li a1, 6
+; ZVZIP-NEXT: mul a2, a2, a1
+; ZVZIP-NEXT: add a2, sp, a2
+; ZVZIP-NEXT: addi a2, a2, 64
+; ZVZIP-NEXT: vsseg6e64.v v20, (a2)
+; ZVZIP-NEXT: vl1re64.v v14, (a0)
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: add a3, a0, a1
+; ZVZIP-NEXT: vl1re64.v v15, (a3)
+; ZVZIP-NEXT: slli a3, a1, 2
+; ZVZIP-NEXT: add a4, a2, a3
+; ZVZIP-NEXT: vl1re64.v v12, (a4)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v13, (a5)
+; ZVZIP-NEXT: slli a5, a1, 1
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v11, (a7)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vl1re64.v v9, (a2)
+; ZVZIP-NEXT: add a3, a0, a3
; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a2
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
-; ZVZIP-NEXT: vl1re64.v v16, (a0)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a4, a0, a4
+; ZVZIP-NEXT: vl1re64.v v19, (a4)
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: vl1re64.v v16, (a5)
+; ZVZIP-NEXT: add a0, a0, a6
+; ZVZIP-NEXT: vl1re64.v v17, (a0)
+; ZVZIP-NEXT: slli a1, a1, 3
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: li a1, 12
-; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: li a2, 12
+; ZVZIP-NEXT: mul a0, a0, a2
; ZVZIP-NEXT: add a0, sp, a0
; ZVZIP-NEXT: addi a0, a0, 64
-; ZVZIP-NEXT: add a2, a0, a2
-; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: add a1, a0, a1
+; ZVZIP-NEXT: vs4r.v v16, (a1)
; ZVZIP-NEXT: vs8r.v v8, (a0)
-; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v16, (a1)
; ZVZIP-NEXT: vl8re64.v v8, (a0)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
@@ -11927,28 +12521,30 @@ define <vscale x 14 x half> @vector_interleave_nxv14f16_nxv2f16(<vscale x 2 x ha
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vle16.v v8, (a7)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v11, (a2)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vle16.v v10, (a4)
+; CHECK-NEXT: srli a4, a1, 2
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v8, a4
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v11, (a3)
+; CHECK-NEXT: add a3, a1, a2
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v8, a4
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -11966,28 +12562,30 @@ define <vscale x 14 x half> @vector_interleave_nxv14f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a7)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v11, (a2)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a4)
+; ZVBB-NEXT: srli a4, a1, 2
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v10, v8, a4
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v11, (a3)
+; ZVBB-NEXT: add a3, a1, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vle16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
+; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a4
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-NEXT: vslideup.vx v8, v12, a4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -12009,19 +12607,22 @@ define <vscale x 28 x half> @vector_interleave_nxv28f16_nxv4f16(<vscale x 4 x ha
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -12040,19 +12641,22 @@ define <vscale x 28 x half> @vector_interleave_nxv28f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -12086,59 +12690,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e16.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e16.v v21, (a2)
+; RV32-NEXT: vsseg7e16.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e16.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v11, (a4)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v14, (a4)
-; RV32-NEXT: vl1re16.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re16.v v14, (a2)
+; RV32-NEXT: vl1re16.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re16.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re16.v v16, (a2)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re16.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re16.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re16.v v16, (a0)
-; RV32-NEXT: vl8re16.v v8, (a2)
+; RV32-NEXT: vl8re16.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12167,59 +12775,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e16.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e16.v v21, (a2)
+; RV64-NEXT: vsseg7e16.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e16.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v11, (a4)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v14, (a4)
-; RV64-NEXT: vl1re16.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re16.v v14, (a2)
+; RV64-NEXT: vl1re16.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re16.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re16.v v16, (a2)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re16.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re16.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re16.v v16, (a0)
-; RV64-NEXT: vl8re16.v v8, (a2)
+; RV64-NEXT: vl8re16.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12248,59 +12860,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12329,59 +12945,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12410,59 +13030,63 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e16.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e16.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v14, (a4)
-; ZVZIP-NEXT: vl1re16.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re16.v v14, (a2)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re16.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re16.v v16, (a2)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re16.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re16.v v16, (a0)
-; ZVZIP-NEXT: vl8re16.v v8, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12484,28 +13108,30 @@ define <vscale x 14 x bfloat> @vector_interleave_nxv14bf16_nxv2bf16(<vscale x 2
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vle16.v v8, (a7)
-; CHECK-NEXT: vle16.v v10, (a6)
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v11, (a2)
-; CHECK-NEXT: vle16.v v8, (a5)
-; CHECK-NEXT: vle16.v v9, (a4)
-; CHECK-NEXT: vle16.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle16.v v8, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vle16.v v10, (a4)
+; CHECK-NEXT: srli a4, a1, 2
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v8, a4
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vle16.v v11, (a3)
+; CHECK-NEXT: add a3, a1, a2
+; CHECK-NEXT: vle16.v v8, (a3)
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle16.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v8, a4
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -12523,28 +13149,30 @@ define <vscale x 14 x bfloat> @vector_interleave_nxv14bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vle16.v v8, (a7)
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a6, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vsetvli a6, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v11, (a2)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle16.v v8, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vle16.v v10, (a4)
+; ZVBB-NEXT: srli a4, a1, 2
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v10, v8, a4
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v11, (a3)
+; ZVBB-NEXT: add a3, a1, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vle16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
+; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a4
+; ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-NEXT: vslideup.vx v8, v12, a4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -12566,19 +13194,22 @@ define <vscale x 28 x bfloat> @vector_interleave_nxv28bf16_nxv4bf16(<vscale x 4
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re16.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re16.v v11, (a4)
; CHECK-NEXT: vl1re16.v v8, (a0)
-; CHECK-NEXT: vl1re16.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re16.v v12, (a3)
+; CHECK-NEXT: vl1re16.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re16.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re16.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re16.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re16.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -12597,19 +13228,22 @@ define <vscale x 28 x bfloat> @vector_interleave_nxv28bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re16.v v12, (a3)
+; ZVBB-NEXT: vl1re16.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re16.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re16.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re16.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re16.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -12643,59 +13277,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e16.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e16.v v21, (a2)
+; RV32-NEXT: vsseg7e16.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e16.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re16.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v11, (a4)
-; RV32-NEXT: vl1re16.v v8, (a1)
-; RV32-NEXT: vl1re16.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re16.v v14, (a4)
-; RV32-NEXT: vl1re16.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re16.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re16.v v11, (a5)
+; RV32-NEXT: vl1re16.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re16.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re16.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re16.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re16.v v14, (a2)
+; RV32-NEXT: vl1re16.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re16.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re16.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re16.v v16, (a2)
-; RV32-NEXT: vl1re16.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re16.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re16.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re16.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re16.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re16.v v16, (a0)
-; RV32-NEXT: vl8re16.v v8, (a2)
+; RV32-NEXT: vl8re16.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12724,59 +13362,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e16.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e16.v v21, (a2)
+; RV64-NEXT: vsseg7e16.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e16.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re16.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v11, (a4)
-; RV64-NEXT: vl1re16.v v8, (a1)
-; RV64-NEXT: vl1re16.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re16.v v14, (a4)
-; RV64-NEXT: vl1re16.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re16.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re16.v v11, (a5)
+; RV64-NEXT: vl1re16.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re16.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re16.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re16.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re16.v v14, (a2)
+; RV64-NEXT: vl1re16.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re16.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re16.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re16.v v16, (a2)
-; RV64-NEXT: vl1re16.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re16.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re16.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re16.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re16.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re16.v v16, (a0)
-; RV64-NEXT: vl8re16.v v8, (a2)
+; RV64-NEXT: vl8re16.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12805,59 +13447,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -12886,59 +13532,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e16.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e16.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re16.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re16.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re16.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re16.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re16.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re16.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re16.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re16.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re16.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re16.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re16.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re16.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re16.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re16.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re16.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re16.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re16.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re16.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re16.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re16.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re16.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re16.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re16.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -12967,59 +13617,63 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e16.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e16.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e16.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re16.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v11, (a4)
-; ZVZIP-NEXT: vl1re16.v v8, (a1)
-; ZVZIP-NEXT: vl1re16.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re16.v v14, (a4)
-; ZVZIP-NEXT: vl1re16.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re16.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re16.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re16.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re16.v v14, (a2)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re16.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re16.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re16.v v16, (a2)
-; ZVZIP-NEXT: vl1re16.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re16.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re16.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re16.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re16.v v16, (a0)
-; ZVZIP-NEXT: vl8re16.v v8, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13041,28 +13695,30 @@ define <vscale x 7 x float> @vector_interleave_nxv7f32_nxv1f32(<vscale x 1 x flo
; CHECK-NEXT: vsseg7e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: slli a3, a1, 1
; CHECK-NEXT: add a4, a3, a2
-; CHECK-NEXT: add a5, a4, a2
-; CHECK-NEXT: add a6, a5, a2
-; CHECK-NEXT: add a7, a6, a2
-; CHECK-NEXT: vle32.v v8, (a7)
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: srli a1, a1, 3
-; CHECK-NEXT: vsetvli a6, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: add a2, a7, a2
-; CHECK-NEXT: vsetvli a6, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v11, (a2)
-; CHECK-NEXT: vle32.v v8, (a5)
-; CHECK-NEXT: vle32.v v9, (a4)
-; CHECK-NEXT: vle32.v v12, (a3)
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vle32.v v8, (a4)
+; CHECK-NEXT: add a4, a0, a3
+; CHECK-NEXT: vle32.v v10, (a4)
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: add a1, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v10, v8, a4
+; CHECK-NEXT: add a3, a1, a3
+; CHECK-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v11, (a3)
+; CHECK-NEXT: add a3, a1, a2
+; CHECK-NEXT: vle32.v v8, (a3)
+; CHECK-NEXT: vle32.v v9, (a1)
+; CHECK-NEXT: add a2, a0, a2
+; CHECK-NEXT: vle32.v v12, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v8, a4
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v12, a1
+; CHECK-NEXT: vslideup.vx v8, v12, a4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add sp, sp, a0
@@ -13080,28 +13736,30 @@ define <vscale x 7 x float> @vector_interleave_nxv7f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg7e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: slli a3, a1, 1
; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vle32.v v8, (a7)
-; ZVBB-NEXT: vle32.v v10, (a6)
-; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a6, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v10, v8, a1
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vsetvli a6, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v11, (a2)
-; ZVBB-NEXT: vle32.v v8, (a5)
-; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v12, (a3)
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vle32.v v8, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vle32.v v10, (a4)
+; ZVBB-NEXT: srli a4, a1, 3
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: vsetvli a5, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v10, v8, a4
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v11, (a3)
+; ZVBB-NEXT: add a3, a1, a2
+; ZVBB-NEXT: vle32.v v8, (a3)
+; ZVBB-NEXT: vle32.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v12, (a2)
+; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v8, a4
+; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v12, a1
+; ZVBB-NEXT: vslideup.vx v8, v12, a4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 2
; ZVBB-NEXT: add sp, sp, a0
@@ -13123,19 +13781,22 @@ define <vscale x 14 x float> @vector_interleave_nxv14f32_nxv2f32(<vscale x 2 x f
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vsseg7e32.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re32.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re32.v v11, (a4)
; CHECK-NEXT: vl1re32.v v8, (a0)
-; CHECK-NEXT: vl1re32.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re32.v v12, (a3)
+; CHECK-NEXT: vl1re32.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re32.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re32.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re32.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re32.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -13154,19 +13815,22 @@ define <vscale x 14 x float> @vector_interleave_nxv14f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg7e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re32.v v11, (a4)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re32.v v12, (a3)
+; ZVBB-NEXT: vl1re32.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re32.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re32.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re32.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re32.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -13200,59 +13864,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e32.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e32.v v21, (a2)
+; RV32-NEXT: vsseg7e32.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e32.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re32.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v11, (a4)
-; RV32-NEXT: vl1re32.v v8, (a1)
-; RV32-NEXT: vl1re32.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re32.v v14, (a4)
-; RV32-NEXT: vl1re32.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re32.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re32.v v11, (a5)
+; RV32-NEXT: vl1re32.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re32.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re32.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re32.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re32.v v14, (a2)
+; RV32-NEXT: vl1re32.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re32.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re32.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re32.v v16, (a2)
-; RV32-NEXT: vl1re32.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re32.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re32.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re32.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re32.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re32.v v16, (a0)
-; RV32-NEXT: vl8re32.v v8, (a2)
+; RV32-NEXT: vl8re32.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13281,59 +13949,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e32.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e32.v v21, (a2)
+; RV64-NEXT: vsseg7e32.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e32.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re32.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v11, (a4)
-; RV64-NEXT: vl1re32.v v8, (a1)
-; RV64-NEXT: vl1re32.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re32.v v14, (a4)
-; RV64-NEXT: vl1re32.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re32.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re32.v v11, (a5)
+; RV64-NEXT: vl1re32.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re32.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re32.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re32.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re32.v v14, (a2)
+; RV64-NEXT: vl1re32.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re32.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re32.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re32.v v16, (a2)
-; RV64-NEXT: vl1re32.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re32.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re32.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re32.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re32.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re32.v v16, (a0)
-; RV64-NEXT: vl8re32.v v8, (a2)
+; RV64-NEXT: vl8re32.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13362,59 +14034,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13443,59 +14119,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e32.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e32.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re32.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re32.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re32.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re32.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re32.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re32.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re32.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re32.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re32.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re32.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re32.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re32.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re32.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re32.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re32.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re32.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re32.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re32.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re32.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re32.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re32.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re32.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re32.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13524,59 +14204,63 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e32.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e32.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e32.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e32.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re32.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v11, (a4)
-; ZVZIP-NEXT: vl1re32.v v8, (a1)
-; ZVZIP-NEXT: vl1re32.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re32.v v14, (a4)
-; ZVZIP-NEXT: vl1re32.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re32.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
+; ZVZIP-NEXT: vl1re32.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re32.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re32.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re32.v v14, (a2)
+; ZVZIP-NEXT: vl1re32.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re32.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re32.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re32.v v16, (a2)
-; ZVZIP-NEXT: vl1re32.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re32.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re32.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re32.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re32.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re32.v v16, (a0)
-; ZVZIP-NEXT: vl8re32.v v8, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13598,19 +14282,22 @@ define <vscale x 7 x double> @vector_interleave_nxv7f64_nxv1f64(<vscale x 1 x do
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsseg7e64.v v8, (a0)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vl1re64.v v10, (a3)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v11, (a3)
+; CHECK-NEXT: add a3, a0, a1
+; CHECK-NEXT: add a4, a3, a2
+; CHECK-NEXT: vl1re64.v v11, (a4)
; CHECK-NEXT: vl1re64.v v8, (a0)
-; CHECK-NEXT: vl1re64.v v9, (a2)
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: vl1re64.v v12, (a3)
+; CHECK-NEXT: vl1re64.v v9, (a3)
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: vl1re64.v v12, (a4)
; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: vl1re64.v v13, (a3)
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vl1re64.v v14, (a1)
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vl1re64.v v14, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0
@@ -13629,19 +14316,22 @@ define <vscale x 7 x double> @vector_interleave_nxv7f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg7e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v11, (a3)
+; ZVBB-NEXT: add a3, a0, a1
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: vl1re64.v v11, (a4)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
-; ZVBB-NEXT: add a3, a3, a1
-; ZVBB-NEXT: vl1re64.v v12, (a3)
+; ZVBB-NEXT: vl1re64.v v9, (a3)
+; ZVBB-NEXT: slli a1, a1, 2
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: vl1re64.v v12, (a4)
; ZVBB-NEXT: add a3, a3, a1
; ZVBB-NEXT: vl1re64.v v13, (a3)
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vl1re64.v v14, (a1)
+; ZVBB-NEXT: add a1, a1, a2
+; ZVBB-NEXT: add a0, a0, a1
+; ZVBB-NEXT: vl1re64.v v14, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
; ZVBB-NEXT: sub a0, a1, a0
@@ -13675,59 +14365,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV32-NEXT: vmv1r.v v2, v10
; RV32-NEXT: vmv1r.v v4, v14
; RV32-NEXT: vmv1r.v v6, v18
-; RV32-NEXT: addi a1, sp, 64
-; RV32-NEXT: vsseg7e64.v v1, (a1)
-; RV32-NEXT: vmv1r.v v22, v11
-; RV32-NEXT: vmv1r.v v24, v15
-; RV32-NEXT: vmv1r.v v26, v19
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a0, a2, 3
; RV32-NEXT: sub a2, a0, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: vsseg7e64.v v21, (a2)
+; RV32-NEXT: vsseg7e64.v v1, (a2)
+; RV32-NEXT: vmv1r.v v22, v11
+; RV32-NEXT: vmv1r.v v24, v15
+; RV32-NEXT: vmv1r.v v26, v19
+; RV32-NEXT: addi a1, sp, 64
+; RV32-NEXT: vsseg7e64.v v21, (a1)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: slli a3, a0, 1
+; RV32-NEXT: add a4, a2, a3
; RV32-NEXT: vl1re64.v v10, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v11, (a4)
-; RV32-NEXT: vl1re64.v v8, (a1)
-; RV32-NEXT: vl1re64.v v9, (a3)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v12, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v13, (a4)
-; RV32-NEXT: add a4, a4, a0
-; RV32-NEXT: vl1re64.v v14, (a4)
-; RV32-NEXT: vl1re64.v v15, (a2)
-; RV32-NEXT: add a2, a2, a0
-; RV32-NEXT: add a1, a2, a0
-; RV32-NEXT: add a3, a1, a0
-; RV32-NEXT: vl1re64.v v18, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v19, (a3)
+; RV32-NEXT: add a4, a3, a0
+; RV32-NEXT: add a5, a2, a4
+; RV32-NEXT: vl1re64.v v11, (a5)
+; RV32-NEXT: vl1re64.v v8, (a2)
+; RV32-NEXT: add a5, a2, a0
+; RV32-NEXT: vl1re64.v v9, (a5)
+; RV32-NEXT: slli a5, a0, 2
+; RV32-NEXT: add a6, a2, a5
+; RV32-NEXT: vl1re64.v v12, (a6)
+; RV32-NEXT: add a6, a5, a0
+; RV32-NEXT: add a7, a2, a6
+; RV32-NEXT: vl1re64.v v13, (a7)
+; RV32-NEXT: add a7, a5, a3
+; RV32-NEXT: add a2, a2, a7
+; RV32-NEXT: vl1re64.v v14, (a2)
+; RV32-NEXT: vl1re64.v v15, (a1)
+; RV32-NEXT: add a4, a1, a4
+; RV32-NEXT: vl1re64.v v18, (a4)
+; RV32-NEXT: add a2, a1, a5
+; RV32-NEXT: vl1re64.v v19, (a2)
+; RV32-NEXT: add a2, a1, a0
; RV32-NEXT: vl1re64.v v16, (a2)
-; RV32-NEXT: vl1re64.v v17, (a1)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v20, (a3)
-; RV32-NEXT: add a3, a3, a0
-; RV32-NEXT: vl1re64.v v21, (a3)
-; RV32-NEXT: slli a1, a0, 2
+; RV32-NEXT: add a3, a1, a3
+; RV32-NEXT: vl1re64.v v17, (a3)
+; RV32-NEXT: add a6, a1, a6
+; RV32-NEXT: vl1re64.v v20, (a6)
+; RV32-NEXT: add a1, a1, a7
+; RV32-NEXT: vl1re64.v v21, (a1)
; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 14
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 64
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vs2r.v v20, (a1)
-; RV32-NEXT: add a0, a2, a0
+; RV32-NEXT: add a5, a0, a5
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 14
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: add a5, a1, a5
+; RV32-NEXT: vs2r.v v20, (a5)
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs4r.v v16, (a0)
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vs8r.v v8, (a1)
; RV32-NEXT: vl8re64.v v16, (a0)
-; RV32-NEXT: vl8re64.v v8, (a2)
+; RV32-NEXT: vl8re64.v v8, (a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13756,59 +14450,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; RV64-NEXT: vmv1r.v v2, v10
; RV64-NEXT: vmv1r.v v4, v14
; RV64-NEXT: vmv1r.v v6, v18
-; RV64-NEXT: addi a1, sp, 64
-; RV64-NEXT: vsseg7e64.v v1, (a1)
-; RV64-NEXT: vmv1r.v v22, v11
-; RV64-NEXT: vmv1r.v v24, v15
-; RV64-NEXT: vmv1r.v v26, v19
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a0, a2, 3
; RV64-NEXT: sub a2, a0, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: vsseg7e64.v v21, (a2)
+; RV64-NEXT: vsseg7e64.v v1, (a2)
+; RV64-NEXT: vmv1r.v v22, v11
+; RV64-NEXT: vmv1r.v v24, v15
+; RV64-NEXT: vmv1r.v v26, v19
+; RV64-NEXT: addi a1, sp, 64
+; RV64-NEXT: vsseg7e64.v v21, (a1)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: slli a3, a0, 1
+; RV64-NEXT: add a4, a2, a3
; RV64-NEXT: vl1re64.v v10, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v11, (a4)
-; RV64-NEXT: vl1re64.v v8, (a1)
-; RV64-NEXT: vl1re64.v v9, (a3)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v12, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v13, (a4)
-; RV64-NEXT: add a4, a4, a0
-; RV64-NEXT: vl1re64.v v14, (a4)
-; RV64-NEXT: vl1re64.v v15, (a2)
-; RV64-NEXT: add a2, a2, a0
-; RV64-NEXT: add a1, a2, a0
-; RV64-NEXT: add a3, a1, a0
-; RV64-NEXT: vl1re64.v v18, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v19, (a3)
+; RV64-NEXT: add a4, a3, a0
+; RV64-NEXT: add a5, a2, a4
+; RV64-NEXT: vl1re64.v v11, (a5)
+; RV64-NEXT: vl1re64.v v8, (a2)
+; RV64-NEXT: add a5, a2, a0
+; RV64-NEXT: vl1re64.v v9, (a5)
+; RV64-NEXT: slli a5, a0, 2
+; RV64-NEXT: add a6, a2, a5
+; RV64-NEXT: vl1re64.v v12, (a6)
+; RV64-NEXT: add a6, a5, a0
+; RV64-NEXT: add a7, a2, a6
+; RV64-NEXT: vl1re64.v v13, (a7)
+; RV64-NEXT: add a7, a5, a3
+; RV64-NEXT: add a2, a2, a7
+; RV64-NEXT: vl1re64.v v14, (a2)
+; RV64-NEXT: vl1re64.v v15, (a1)
+; RV64-NEXT: add a4, a1, a4
+; RV64-NEXT: vl1re64.v v18, (a4)
+; RV64-NEXT: add a2, a1, a5
+; RV64-NEXT: vl1re64.v v19, (a2)
+; RV64-NEXT: add a2, a1, a0
; RV64-NEXT: vl1re64.v v16, (a2)
-; RV64-NEXT: vl1re64.v v17, (a1)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v20, (a3)
-; RV64-NEXT: add a3, a3, a0
-; RV64-NEXT: vl1re64.v v21, (a3)
-; RV64-NEXT: slli a1, a0, 2
+; RV64-NEXT: add a3, a1, a3
+; RV64-NEXT: vl1re64.v v17, (a3)
+; RV64-NEXT: add a6, a1, a6
+; RV64-NEXT: vl1re64.v v20, (a6)
+; RV64-NEXT: add a1, a1, a7
+; RV64-NEXT: vl1re64.v v21, (a1)
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 64
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vs2r.v v20, (a1)
-; RV64-NEXT: add a0, a2, a0
+; RV64-NEXT: add a5, a0, a5
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 64
+; RV64-NEXT: add a5, a1, a5
+; RV64-NEXT: vs2r.v v20, (a5)
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: vs4r.v v16, (a0)
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vs8r.v v8, (a1)
; RV64-NEXT: vl8re64.v v16, (a0)
-; RV64-NEXT: vl8re64.v v8, (a2)
+; RV64-NEXT: vl8re64.v v8, (a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13837,59 +14535,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV32-NEXT: vmv1r.v v2, v10
; ZVBB-RV32-NEXT: vmv1r.v v4, v14
; ZVBB-RV32-NEXT: vmv1r.v v6, v18
-; ZVBB-RV32-NEXT: addi a1, sp, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV32-NEXT: vmv1r.v v22, v11
-; ZVBB-RV32-NEXT: vmv1r.v v24, v15
-; ZVBB-RV32-NEXT: vmv1r.v v26, v19
; ZVBB-RV32-NEXT: csrr a2, vlenb
; ZVBB-RV32-NEXT: slli a0, a2, 3
; ZVBB-RV32-NEXT: sub a2, a0, a2
; ZVBB-RV32-NEXT: add a2, sp, a2
; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV32-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV32-NEXT: vmv1r.v v22, v11
+; ZVBB-RV32-NEXT: vmv1r.v v24, v15
+; ZVBB-RV32-NEXT: vmv1r.v v26, v19
+; ZVBB-RV32-NEXT: addi a1, sp, 64
+; ZVBB-RV32-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV32-NEXT: csrr a0, vlenb
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: slli a3, a0, 1
+; ZVBB-RV32-NEXT: add a4, a2, a3
; ZVBB-RV32-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV32-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV32-NEXT: add a4, a4, a0
-; ZVBB-RV32-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV32-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV32-NEXT: add a2, a2, a0
-; ZVBB-RV32-NEXT: add a1, a2, a0
-; ZVBB-RV32-NEXT: add a3, a1, a0
-; ZVBB-RV32-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV32-NEXT: add a4, a3, a0
+; ZVBB-RV32-NEXT: add a5, a2, a4
+; ZVBB-RV32-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV32-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV32-NEXT: add a5, a2, a0
+; ZVBB-RV32-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV32-NEXT: slli a5, a0, 2
+; ZVBB-RV32-NEXT: add a6, a2, a5
+; ZVBB-RV32-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV32-NEXT: add a6, a5, a0
+; ZVBB-RV32-NEXT: add a7, a2, a6
+; ZVBB-RV32-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV32-NEXT: add a7, a5, a3
+; ZVBB-RV32-NEXT: add a2, a2, a7
+; ZVBB-RV32-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV32-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV32-NEXT: add a4, a1, a4
+; ZVBB-RV32-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV32-NEXT: add a2, a1, a5
+; ZVBB-RV32-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV32-NEXT: add a2, a1, a0
; ZVBB-RV32-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV32-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV32-NEXT: add a3, a3, a0
-; ZVBB-RV32-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV32-NEXT: slli a1, a0, 2
+; ZVBB-RV32-NEXT: add a3, a1, a3
+; ZVBB-RV32-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV32-NEXT: add a6, a1, a6
+; ZVBB-RV32-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV32-NEXT: add a1, a1, a7
+; ZVBB-RV32-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV32-NEXT: slli a0, a0, 3
-; ZVBB-RV32-NEXT: add a1, a0, a1
-; ZVBB-RV32-NEXT: csrr a2, vlenb
-; ZVBB-RV32-NEXT: li a3, 14
-; ZVBB-RV32-NEXT: mul a2, a2, a3
-; ZVBB-RV32-NEXT: add a2, sp, a2
-; ZVBB-RV32-NEXT: addi a2, a2, 64
-; ZVBB-RV32-NEXT: add a1, a2, a1
-; ZVBB-RV32-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV32-NEXT: add a0, a2, a0
+; ZVBB-RV32-NEXT: add a5, a0, a5
+; ZVBB-RV32-NEXT: csrr a1, vlenb
+; ZVBB-RV32-NEXT: li a2, 14
+; ZVBB-RV32-NEXT: mul a1, a1, a2
+; ZVBB-RV32-NEXT: add a1, sp, a1
+; ZVBB-RV32-NEXT: addi a1, a1, 64
+; ZVBB-RV32-NEXT: add a5, a1, a5
+; ZVBB-RV32-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV32-NEXT: add a0, a1, a0
; ZVBB-RV32-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV32-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV32-NEXT: vs8r.v v8, (a1)
; ZVBB-RV32-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV32-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV32-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV32-NEXT: addi sp, s0, -80
; ZVBB-RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; ZVBB-RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -13918,59 +14620,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: vmv1r.v v2, v10
; ZVBB-RV64-NEXT: vmv1r.v v4, v14
; ZVBB-RV64-NEXT: vmv1r.v v6, v18
-; ZVBB-RV64-NEXT: addi a1, sp, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a1)
-; ZVBB-RV64-NEXT: vmv1r.v v22, v11
-; ZVBB-RV64-NEXT: vmv1r.v v24, v15
-; ZVBB-RV64-NEXT: vmv1r.v v26, v19
; ZVBB-RV64-NEXT: csrr a2, vlenb
; ZVBB-RV64-NEXT: slli a0, a2, 3
; ZVBB-RV64-NEXT: sub a2, a0, a2
; ZVBB-RV64-NEXT: add a2, sp, a2
; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a2)
+; ZVBB-RV64-NEXT: vsseg7e64.v v1, (a2)
+; ZVBB-RV64-NEXT: vmv1r.v v22, v11
+; ZVBB-RV64-NEXT: vmv1r.v v24, v15
+; ZVBB-RV64-NEXT: vmv1r.v v26, v19
+; ZVBB-RV64-NEXT: addi a1, sp, 64
+; ZVBB-RV64-NEXT: vsseg7e64.v v21, (a1)
; ZVBB-RV64-NEXT: csrr a0, vlenb
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: slli a3, a0, 1
+; ZVBB-RV64-NEXT: add a4, a2, a3
; ZVBB-RV64-NEXT: vl1re64.v v10, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v11, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v8, (a1)
-; ZVBB-RV64-NEXT: vl1re64.v v9, (a3)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v12, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v13, (a4)
-; ZVBB-RV64-NEXT: add a4, a4, a0
-; ZVBB-RV64-NEXT: vl1re64.v v14, (a4)
-; ZVBB-RV64-NEXT: vl1re64.v v15, (a2)
-; ZVBB-RV64-NEXT: add a2, a2, a0
-; ZVBB-RV64-NEXT: add a1, a2, a0
-; ZVBB-RV64-NEXT: add a3, a1, a0
-; ZVBB-RV64-NEXT: vl1re64.v v18, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v19, (a3)
+; ZVBB-RV64-NEXT: add a4, a3, a0
+; ZVBB-RV64-NEXT: add a5, a2, a4
+; ZVBB-RV64-NEXT: vl1re64.v v11, (a5)
+; ZVBB-RV64-NEXT: vl1re64.v v8, (a2)
+; ZVBB-RV64-NEXT: add a5, a2, a0
+; ZVBB-RV64-NEXT: vl1re64.v v9, (a5)
+; ZVBB-RV64-NEXT: slli a5, a0, 2
+; ZVBB-RV64-NEXT: add a6, a2, a5
+; ZVBB-RV64-NEXT: vl1re64.v v12, (a6)
+; ZVBB-RV64-NEXT: add a6, a5, a0
+; ZVBB-RV64-NEXT: add a7, a2, a6
+; ZVBB-RV64-NEXT: vl1re64.v v13, (a7)
+; ZVBB-RV64-NEXT: add a7, a5, a3
+; ZVBB-RV64-NEXT: add a2, a2, a7
+; ZVBB-RV64-NEXT: vl1re64.v v14, (a2)
+; ZVBB-RV64-NEXT: vl1re64.v v15, (a1)
+; ZVBB-RV64-NEXT: add a4, a1, a4
+; ZVBB-RV64-NEXT: vl1re64.v v18, (a4)
+; ZVBB-RV64-NEXT: add a2, a1, a5
+; ZVBB-RV64-NEXT: vl1re64.v v19, (a2)
+; ZVBB-RV64-NEXT: add a2, a1, a0
; ZVBB-RV64-NEXT: vl1re64.v v16, (a2)
-; ZVBB-RV64-NEXT: vl1re64.v v17, (a1)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v20, (a3)
-; ZVBB-RV64-NEXT: add a3, a3, a0
-; ZVBB-RV64-NEXT: vl1re64.v v21, (a3)
-; ZVBB-RV64-NEXT: slli a1, a0, 2
+; ZVBB-RV64-NEXT: add a3, a1, a3
+; ZVBB-RV64-NEXT: vl1re64.v v17, (a3)
+; ZVBB-RV64-NEXT: add a6, a1, a6
+; ZVBB-RV64-NEXT: vl1re64.v v20, (a6)
+; ZVBB-RV64-NEXT: add a1, a1, a7
+; ZVBB-RV64-NEXT: vl1re64.v v21, (a1)
; ZVBB-RV64-NEXT: slli a0, a0, 3
-; ZVBB-RV64-NEXT: add a1, a0, a1
-; ZVBB-RV64-NEXT: csrr a2, vlenb
-; ZVBB-RV64-NEXT: li a3, 14
-; ZVBB-RV64-NEXT: mul a2, a2, a3
-; ZVBB-RV64-NEXT: add a2, sp, a2
-; ZVBB-RV64-NEXT: addi a2, a2, 64
-; ZVBB-RV64-NEXT: add a1, a2, a1
-; ZVBB-RV64-NEXT: vs2r.v v20, (a1)
-; ZVBB-RV64-NEXT: add a0, a2, a0
+; ZVBB-RV64-NEXT: add a5, a0, a5
+; ZVBB-RV64-NEXT: csrr a1, vlenb
+; ZVBB-RV64-NEXT: li a2, 14
+; ZVBB-RV64-NEXT: mul a1, a1, a2
+; ZVBB-RV64-NEXT: add a1, sp, a1
+; ZVBB-RV64-NEXT: addi a1, a1, 64
+; ZVBB-RV64-NEXT: add a5, a1, a5
+; ZVBB-RV64-NEXT: vs2r.v v20, (a5)
+; ZVBB-RV64-NEXT: add a0, a1, a0
; ZVBB-RV64-NEXT: vs4r.v v16, (a0)
-; ZVBB-RV64-NEXT: vs8r.v v8, (a2)
+; ZVBB-RV64-NEXT: vs8r.v v8, (a1)
; ZVBB-RV64-NEXT: vl8re64.v v16, (a0)
-; ZVBB-RV64-NEXT: vl8re64.v v8, (a2)
+; ZVBB-RV64-NEXT: vl8re64.v v8, (a1)
; ZVBB-RV64-NEXT: addi sp, s0, -80
; ZVBB-RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVBB-RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -13999,59 +14705,63 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVZIP-NEXT: vmv1r.v v2, v10
; ZVZIP-NEXT: vmv1r.v v4, v14
; ZVZIP-NEXT: vmv1r.v v6, v18
-; ZVZIP-NEXT: addi a1, sp, 64
-; ZVZIP-NEXT: vsseg7e64.v v1, (a1)
-; ZVZIP-NEXT: vmv1r.v v22, v11
-; ZVZIP-NEXT: vmv1r.v v24, v15
-; ZVZIP-NEXT: vmv1r.v v26, v19
; ZVZIP-NEXT: csrr a2, vlenb
; ZVZIP-NEXT: slli a0, a2, 3
; ZVZIP-NEXT: sub a2, a0, a2
; ZVZIP-NEXT: add a2, sp, a2
; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: vsseg7e64.v v21, (a2)
+; ZVZIP-NEXT: vsseg7e64.v v1, (a2)
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: addi a1, sp, 64
+; ZVZIP-NEXT: vsseg7e64.v v21, (a1)
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: slli a3, a0, 1
+; ZVZIP-NEXT: add a4, a2, a3
; ZVZIP-NEXT: vl1re64.v v10, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v11, (a4)
-; ZVZIP-NEXT: vl1re64.v v8, (a1)
-; ZVZIP-NEXT: vl1re64.v v9, (a3)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v12, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v13, (a4)
-; ZVZIP-NEXT: add a4, a4, a0
-; ZVZIP-NEXT: vl1re64.v v14, (a4)
-; ZVZIP-NEXT: vl1re64.v v15, (a2)
-; ZVZIP-NEXT: add a2, a2, a0
-; ZVZIP-NEXT: add a1, a2, a0
-; ZVZIP-NEXT: add a3, a1, a0
-; ZVZIP-NEXT: vl1re64.v v18, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v19, (a3)
+; ZVZIP-NEXT: add a4, a3, a0
+; ZVZIP-NEXT: add a5, a2, a4
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
+; ZVZIP-NEXT: vl1re64.v v8, (a2)
+; ZVZIP-NEXT: add a5, a2, a0
+; ZVZIP-NEXT: vl1re64.v v9, (a5)
+; ZVZIP-NEXT: slli a5, a0, 2
+; ZVZIP-NEXT: add a6, a2, a5
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a5, a0
+; ZVZIP-NEXT: add a7, a2, a6
+; ZVZIP-NEXT: vl1re64.v v13, (a7)
+; ZVZIP-NEXT: add a7, a5, a3
+; ZVZIP-NEXT: add a2, a2, a7
+; ZVZIP-NEXT: vl1re64.v v14, (a2)
+; ZVZIP-NEXT: vl1re64.v v15, (a1)
+; ZVZIP-NEXT: add a4, a1, a4
+; ZVZIP-NEXT: vl1re64.v v18, (a4)
+; ZVZIP-NEXT: add a2, a1, a5
+; ZVZIP-NEXT: vl1re64.v v19, (a2)
+; ZVZIP-NEXT: add a2, a1, a0
; ZVZIP-NEXT: vl1re64.v v16, (a2)
-; ZVZIP-NEXT: vl1re64.v v17, (a1)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v20, (a3)
-; ZVZIP-NEXT: add a3, a3, a0
-; ZVZIP-NEXT: vl1re64.v v21, (a3)
-; ZVZIP-NEXT: slli a1, a0, 2
+; ZVZIP-NEXT: add a3, a1, a3
+; ZVZIP-NEXT: vl1re64.v v17, (a3)
+; ZVZIP-NEXT: add a6, a1, a6
+; ZVZIP-NEXT: vl1re64.v v20, (a6)
+; ZVZIP-NEXT: add a1, a1, a7
+; ZVZIP-NEXT: vl1re64.v v21, (a1)
; ZVZIP-NEXT: slli a0, a0, 3
-; ZVZIP-NEXT: add a1, a0, a1
-; ZVZIP-NEXT: csrr a2, vlenb
-; ZVZIP-NEXT: li a3, 14
-; ZVZIP-NEXT: mul a2, a2, a3
-; ZVZIP-NEXT: add a2, sp, a2
-; ZVZIP-NEXT: addi a2, a2, 64
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vs2r.v v20, (a1)
-; ZVZIP-NEXT: add a0, a2, a0
+; ZVZIP-NEXT: add a5, a0, a5
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a2, 14
+; ZVZIP-NEXT: mul a1, a1, a2
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: add a5, a1, a5
+; ZVZIP-NEXT: vs2r.v v20, (a5)
+; ZVZIP-NEXT: add a0, a1, a0
; ZVZIP-NEXT: vs4r.v v16, (a0)
-; ZVZIP-NEXT: vs8r.v v8, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a1)
; ZVZIP-NEXT: vl8re64.v v16, (a0)
-; ZVZIP-NEXT: vl8re64.v v8, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a1)
; ZVZIP-NEXT: addi sp, s0, -80
; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
@@ -14073,27 +14783,31 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x ha
; V-NEXT: vsseg8e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: srli a2, a1, 1
-; V-NEXT: add a3, a0, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: add a2, t0, a2
-; V-NEXT: vle16.v v8, (a2)
-; V-NEXT: vle16.v v11, (t0)
-; V-NEXT: vle16.v v9, (a7)
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: sub a3, a3, a2
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vle16.v v8, (a3)
+; V-NEXT: slli a3, a1, 1
+; V-NEXT: add a4, a0, a1
+; V-NEXT: add a5, a4, a3
+; V-NEXT: vle16.v v11, (a5)
+; V-NEXT: add a5, a3, a2
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vle16.v v9, (a5)
; V-NEXT: srli a1, a1, 2
-; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v11, v8, a1
-; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; V-NEXT: vle16.v v10, (a6)
-; V-NEXT: vle16.v v8, (a5)
-; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v10, (a3)
+; V-NEXT: add a3, a4, a2
+; V-NEXT: vle16.v v8, (a3)
+; V-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v10, v9, a1
-; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; V-NEXT: vle16.v v9, (a4)
-; V-NEXT: vle16.v v12, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vle16.v v12, (a2)
; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v9, v8, a1
; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -14117,27 +14831,31 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x ha
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: add a2, t0, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v11, (t0)
-; ZVBB-NEXT: vle16.v v9, (a7)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: sub a3, a3, a2
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: slli a3, a1, 1
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a5, a4, a3
+; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a5, a3, a2
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vle16.v v9, (a5)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v11, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a4, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -14152,16 +14870,35 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x ha
;
; ZVZIP-LABEL: vector_interleave_nxv16f16_nxv2f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v16, v11, v15
; ZVZIP-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-NEXT: vzip.vv v10, v8, v12
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v9, v16, a0
+; ZVZIP-NEXT: vzip.vv v17, v10, v14
+; ZVZIP-NEXT: vslidedown.vx v10, v11, a0
+; ZVZIP-NEXT: vzip.vv v18, v8, v12
+; ZVZIP-NEXT: vslidedown.vx v8, v17, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v18, a0
+; ZVZIP-NEXT: vslideup.vx v16, v9, a0
+; ZVZIP-NEXT: vslideup.vx v11, v10, a0
+; ZVZIP-NEXT: vslideup.vx v17, v8, a0
+; ZVZIP-NEXT: vslideup.vx v18, v12, a0
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-NEXT: vzip.vv v14, v10, v9
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v14, v18, v17
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v11, a0
+; ZVZIP-NEXT: vslideup.vx v11, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v12, a0
; ZVZIP-NEXT: ret
%res = call <vscale x 16 x half> @llvm.vector.interleave8.nxv16f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6, <vscale x 2 x half> %v7)
ret <vscale x 16 x half> %res
@@ -14178,21 +14915,26 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x ha
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; V-NEXT: vsseg8e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
-; V-NEXT: add a4, a3, a1
-; V-NEXT: add a5, a4, a1
-; V-NEXT: add a6, a5, a1
-; V-NEXT: add a7, a6, a1
-; V-NEXT: vl1re16.v v14, (a7)
-; V-NEXT: add a1, a7, a1
-; V-NEXT: vl1re16.v v15, (a1)
-; V-NEXT: vl1re16.v v12, (a5)
-; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re16.v v14, (a4)
+; V-NEXT: slli a4, a1, 3
+; V-NEXT: sub a5, a0, a1
+; V-NEXT: add a4, a5, a4
+; V-NEXT: vl1re16.v v15, (a4)
+; V-NEXT: add a4, a0, a3
+; V-NEXT: vl1re16.v v12, (a4)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a3, a1, a3
+; V-NEXT: vl1re16.v v13, (a3)
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re16.v v10, (a3)
-; V-NEXT: vl1re16.v v11, (a4)
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re16.v v11, (a2)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: vl1re16.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -14209,21 +14951,26 @@ define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x ha
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re16.v v15, (a1)
-; ZVBB-NEXT: vl1re16.v v12, (a5)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re16.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re16.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re16.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: vl1re16.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -14269,48 +15016,55 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x ha
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e16.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e16.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re16.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re16.v v23, (t0)
-; V-NEXT: vl1re16.v v20, (a6)
-; V-NEXT: vl1re16.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re16.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re16.v v19, (a5)
; V-NEXT: vl1re16.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re16.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re16.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re16.v v15, (a2)
-; V-NEXT: vl1re16.v v12, (a3)
-; V-NEXT: vl1re16.v v13, (a6)
-; V-NEXT: vl1re16.v v10, (a4)
-; V-NEXT: vl1re16.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re16.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re16.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re16.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re16.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re16.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re16.v v11, (a4)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re16.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re16.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re16.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re16.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -14336,48 +15090,55 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e16.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e16.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re16.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re16.v v23, (t0)
-; ZVBB-NEXT: vl1re16.v v20, (a6)
-; ZVBB-NEXT: vl1re16.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re16.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re16.v v19, (a5)
; ZVBB-NEXT: vl1re16.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re16.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re16.v v15, (a2)
-; ZVBB-NEXT: vl1re16.v v12, (a3)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
-; ZVBB-NEXT: vl1re16.v v10, (a4)
-; ZVBB-NEXT: vl1re16.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re16.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re16.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re16.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re16.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re16.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re16.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re16.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re16.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re16.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re16.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -14417,27 +15178,31 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2
; V-NEXT: vsseg8e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: srli a2, a1, 1
-; V-NEXT: add a3, a0, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: add a2, t0, a2
-; V-NEXT: vle16.v v8, (a2)
-; V-NEXT: vle16.v v11, (t0)
-; V-NEXT: vle16.v v9, (a7)
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: sub a3, a3, a2
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vle16.v v8, (a3)
+; V-NEXT: slli a3, a1, 1
+; V-NEXT: add a4, a0, a1
+; V-NEXT: add a5, a4, a3
+; V-NEXT: vle16.v v11, (a5)
+; V-NEXT: add a5, a3, a2
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vle16.v v9, (a5)
; V-NEXT: srli a1, a1, 2
-; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v11, v8, a1
-; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; V-NEXT: vle16.v v10, (a6)
-; V-NEXT: vle16.v v8, (a5)
-; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; V-NEXT: vle16.v v10, (a3)
+; V-NEXT: add a3, a4, a2
+; V-NEXT: vle16.v v8, (a3)
+; V-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v10, v9, a1
-; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; V-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; V-NEXT: vle16.v v9, (a4)
-; V-NEXT: vle16.v v12, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vle16.v v12, (a2)
; V-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; V-NEXT: vslideup.vx v9, v8, a1
; V-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -14461,27 +15226,31 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: add a2, t0, a2
-; ZVBB-NEXT: vle16.v v8, (a2)
-; ZVBB-NEXT: vle16.v v11, (t0)
-; ZVBB-NEXT: vle16.v v9, (a7)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: sub a3, a3, a2
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: slli a3, a1, 1
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a5, a4, a3
+; ZVBB-NEXT: vle16.v v11, (a5)
+; ZVBB-NEXT: add a5, a3, a2
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vle16.v v9, (a5)
; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: vsetvli a5, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v11, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a6)
-; ZVBB-NEXT: vle16.v v8, (a5)
-; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vsetvli a5, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a3)
+; ZVBB-NEXT: add a3, a4, a2
+; ZVBB-NEXT: vle16.v v8, (a3)
+; ZVBB-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vle16.v v9, (a4)
-; ZVBB-NEXT: vle16.v v12, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle16.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
; ZVBB-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
@@ -14496,16 +15265,35 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2
;
; ZVZIP-LABEL: vector_interleave_nxv16bf16_nxv2bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v16, v11, v15
; ZVZIP-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-NEXT: vzip.vv v10, v8, v12
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v9, v16, a0
+; ZVZIP-NEXT: vzip.vv v17, v10, v14
+; ZVZIP-NEXT: vslidedown.vx v10, v11, a0
+; ZVZIP-NEXT: vzip.vv v18, v8, v12
+; ZVZIP-NEXT: vslidedown.vx v8, v17, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v18, a0
+; ZVZIP-NEXT: vslideup.vx v16, v9, a0
+; ZVZIP-NEXT: vslideup.vx v11, v10, a0
+; ZVZIP-NEXT: vslideup.vx v17, v8, a0
+; ZVZIP-NEXT: vslideup.vx v18, v12, a0
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-NEXT: vzip.vv v14, v10, v9
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v14, v18, v17
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v11, a0
+; ZVZIP-NEXT: vslideup.vx v11, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v12, a0
; ZVZIP-NEXT: ret
%res = call <vscale x 16 x bfloat> @llvm.vector.interleave8.nxv16bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6, <vscale x 2 x bfloat> %v7)
ret <vscale x 16 x bfloat> %res
@@ -14522,21 +15310,26 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; V-NEXT: vsseg8e16.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
-; V-NEXT: add a4, a3, a1
-; V-NEXT: add a5, a4, a1
-; V-NEXT: add a6, a5, a1
-; V-NEXT: add a7, a6, a1
-; V-NEXT: vl1re16.v v14, (a7)
-; V-NEXT: add a1, a7, a1
-; V-NEXT: vl1re16.v v15, (a1)
-; V-NEXT: vl1re16.v v12, (a5)
-; V-NEXT: vl1re16.v v13, (a6)
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re16.v v14, (a4)
+; V-NEXT: slli a4, a1, 3
+; V-NEXT: sub a5, a0, a1
+; V-NEXT: add a4, a5, a4
+; V-NEXT: vl1re16.v v15, (a4)
+; V-NEXT: add a4, a0, a3
+; V-NEXT: vl1re16.v v12, (a4)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a3, a1, a3
+; V-NEXT: vl1re16.v v13, (a3)
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re16.v v10, (a3)
-; V-NEXT: vl1re16.v v11, (a4)
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re16.v v11, (a2)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: vl1re16.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -14553,21 +15346,26 @@ define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVBB-NEXT: vsseg8e16.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re16.v v15, (a1)
-; ZVBB-NEXT: vl1re16.v v12, (a5)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re16.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re16.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re16.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re16.v v10, (a3)
-; ZVBB-NEXT: vl1re16.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re16.v v11, (a2)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: vl1re16.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -14613,48 +15411,55 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e16.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e16.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re16.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re16.v v23, (t0)
-; V-NEXT: vl1re16.v v20, (a6)
-; V-NEXT: vl1re16.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re16.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re16.v v19, (a5)
; V-NEXT: vl1re16.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re16.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re16.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re16.v v15, (a2)
-; V-NEXT: vl1re16.v v12, (a3)
-; V-NEXT: vl1re16.v v13, (a6)
-; V-NEXT: vl1re16.v v10, (a4)
-; V-NEXT: vl1re16.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re16.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re16.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re16.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re16.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re16.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re16.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re16.v v11, (a4)
; V-NEXT: vl1re16.v v8, (a0)
-; V-NEXT: vl1re16.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re16.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re16.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re16.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re16.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re16.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -14680,48 +15485,55 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e16.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e16.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re16.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re16.v v23, (t0)
-; ZVBB-NEXT: vl1re16.v v20, (a6)
-; ZVBB-NEXT: vl1re16.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re16.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re16.v v19, (a5)
; ZVBB-NEXT: vl1re16.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re16.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re16.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re16.v v15, (a2)
-; ZVBB-NEXT: vl1re16.v v12, (a3)
-; ZVBB-NEXT: vl1re16.v v13, (a6)
-; ZVBB-NEXT: vl1re16.v v10, (a4)
-; ZVBB-NEXT: vl1re16.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re16.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re16.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re16.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re16.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re16.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re16.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re16.v v11, (a4)
; ZVBB-NEXT: vl1re16.v v8, (a0)
-; ZVBB-NEXT: vl1re16.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re16.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re16.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re16.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re16.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re16.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -14761,27 +15573,31 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x flo
; V-NEXT: vsseg8e32.v v8, (a0)
; V-NEXT: csrr a1, vlenb
; V-NEXT: srli a2, a1, 1
-; V-NEXT: add a3, a0, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: add a2, t0, a2
-; V-NEXT: vle32.v v8, (a2)
-; V-NEXT: vle32.v v11, (t0)
-; V-NEXT: vle32.v v9, (a7)
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: sub a3, a3, a2
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vle32.v v8, (a3)
+; V-NEXT: slli a3, a1, 1
+; V-NEXT: add a4, a0, a1
+; V-NEXT: add a5, a4, a3
+; V-NEXT: vle32.v v11, (a5)
+; V-NEXT: add a5, a3, a2
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vle32.v v9, (a5)
; V-NEXT: srli a1, a1, 3
-; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; V-NEXT: vsetvli a5, zero, e32, m1, ta, ma
; V-NEXT: vslideup.vx v11, v8, a1
-; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; V-NEXT: vle32.v v10, (a6)
-; V-NEXT: vle32.v v8, (a5)
-; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; V-NEXT: vle32.v v10, (a3)
+; V-NEXT: add a3, a4, a2
+; V-NEXT: vle32.v v8, (a3)
+; V-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; V-NEXT: vslideup.vx v10, v9, a1
-; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; V-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; V-NEXT: vle32.v v9, (a4)
-; V-NEXT: vle32.v v12, (a3)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vle32.v v12, (a2)
; V-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; V-NEXT: vslideup.vx v9, v8, a1
; V-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -14805,27 +15621,31 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x flo
; ZVBB-NEXT: vsseg8e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a2, a1, 1
-; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: add a2, t0, a2
-; ZVBB-NEXT: vle32.v v8, (a2)
-; ZVBB-NEXT: vle32.v v11, (t0)
-; ZVBB-NEXT: vle32.v v9, (a7)
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: sub a3, a3, a2
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vle32.v v8, (a3)
+; ZVBB-NEXT: slli a3, a1, 1
+; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a5, a4, a3
+; ZVBB-NEXT: vle32.v v11, (a5)
+; ZVBB-NEXT: add a5, a3, a2
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vle32.v v9, (a5)
; ZVBB-NEXT: srli a1, a1, 3
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vsetvli a5, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v11, v8, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a6)
-; ZVBB-NEXT: vle32.v v8, (a5)
-; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vsetvli a5, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: add a3, a4, a2
+; ZVBB-NEXT: vle32.v v8, (a3)
+; ZVBB-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v10, v9, a1
-; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vle32.v v9, (a4)
-; ZVBB-NEXT: vle32.v v12, (a3)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vle32.v v12, (a2)
; ZVBB-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vx v9, v8, a1
; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
@@ -14840,16 +15660,35 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x flo
;
; ZVZIP-LABEL: vector_interleave_nxv8f32_nxv1f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 3
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v16, v11, v15
; ZVZIP-NEXT: vzip.vv v11, v9, v13
-; ZVZIP-NEXT: vzip.vv v9, v10, v14
-; ZVZIP-NEXT: vzip.vv v10, v8, v12
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v9, v16, a0
+; ZVZIP-NEXT: vzip.vv v17, v10, v14
+; ZVZIP-NEXT: vslidedown.vx v10, v11, a0
+; ZVZIP-NEXT: vzip.vv v18, v8, v12
+; ZVZIP-NEXT: vslidedown.vx v8, v17, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v18, a0
+; ZVZIP-NEXT: vslideup.vx v16, v9, a0
+; ZVZIP-NEXT: vslideup.vx v11, v10, a0
+; ZVZIP-NEXT: vslideup.vx v17, v8, a0
+; ZVZIP-NEXT: vslideup.vx v18, v12, a0
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v11, v16
-; ZVZIP-NEXT: vzip.vv v14, v10, v9
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vzip.vv v14, v18, v17
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v12, v11, a0
+; ZVZIP-NEXT: vslideup.vx v11, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v9, a0
+; ZVZIP-NEXT: vslideup.vx v9, v12, a0
+; ZVZIP-NEXT: vslidedown.vx v12, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v12, a0
; ZVZIP-NEXT: ret
%res = call <vscale x 8 x float> @llvm.vector.interleave8.nxv8f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6, <vscale x 1 x float> %v8)
ret <vscale x 8 x float> %res
@@ -14866,21 +15705,26 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x f
; V-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; V-NEXT: vsseg8e32.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
-; V-NEXT: add a4, a3, a1
-; V-NEXT: add a5, a4, a1
-; V-NEXT: add a6, a5, a1
-; V-NEXT: add a7, a6, a1
-; V-NEXT: vl1re32.v v14, (a7)
-; V-NEXT: add a1, a7, a1
-; V-NEXT: vl1re32.v v15, (a1)
-; V-NEXT: vl1re32.v v12, (a5)
-; V-NEXT: vl1re32.v v13, (a6)
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re32.v v14, (a4)
+; V-NEXT: slli a4, a1, 3
+; V-NEXT: sub a5, a0, a1
+; V-NEXT: add a4, a5, a4
+; V-NEXT: vl1re32.v v15, (a4)
+; V-NEXT: add a4, a0, a3
+; V-NEXT: vl1re32.v v12, (a4)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a3, a1, a3
+; V-NEXT: vl1re32.v v13, (a3)
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re32.v v10, (a3)
-; V-NEXT: vl1re32.v v11, (a4)
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re32.v v11, (a2)
; V-NEXT: vl1re32.v v8, (a0)
-; V-NEXT: vl1re32.v v9, (a2)
+; V-NEXT: vl1re32.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -14897,21 +15741,26 @@ define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x f
; ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; ZVBB-NEXT: vsseg8e32.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re32.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re32.v v15, (a1)
-; ZVBB-NEXT: vl1re32.v v12, (a5)
-; ZVBB-NEXT: vl1re32.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re32.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re32.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re32.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re32.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re32.v v10, (a3)
-; ZVBB-NEXT: vl1re32.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re32.v v11, (a2)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: vl1re32.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -14957,48 +15806,55 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x f
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e32.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e32.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re32.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re32.v v23, (t0)
-; V-NEXT: vl1re32.v v20, (a6)
-; V-NEXT: vl1re32.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re32.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re32.v v19, (a5)
; V-NEXT: vl1re32.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re32.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re32.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re32.v v15, (a2)
-; V-NEXT: vl1re32.v v12, (a3)
-; V-NEXT: vl1re32.v v13, (a6)
-; V-NEXT: vl1re32.v v10, (a4)
-; V-NEXT: vl1re32.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re32.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re32.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re32.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re32.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re32.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re32.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re32.v v11, (a4)
; V-NEXT: vl1re32.v v8, (a0)
-; V-NEXT: vl1re32.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re32.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re32.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re32.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re32.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re32.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -15024,48 +15880,55 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x f
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e32.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e32.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re32.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re32.v v23, (t0)
-; ZVBB-NEXT: vl1re32.v v20, (a6)
-; ZVBB-NEXT: vl1re32.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re32.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re32.v v19, (a5)
; ZVBB-NEXT: vl1re32.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re32.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re32.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re32.v v15, (a2)
-; ZVBB-NEXT: vl1re32.v v12, (a3)
-; ZVBB-NEXT: vl1re32.v v13, (a6)
-; ZVBB-NEXT: vl1re32.v v10, (a4)
-; ZVBB-NEXT: vl1re32.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re32.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re32.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re32.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re32.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re32.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re32.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re32.v v11, (a4)
; ZVBB-NEXT: vl1re32.v v8, (a0)
-; ZVBB-NEXT: vl1re32.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re32.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re32.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re32.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re32.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re32.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -15104,21 +15967,26 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x do
; V-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; V-NEXT: vsseg8e64.v v8, (a0)
; V-NEXT: csrr a1, vlenb
-; V-NEXT: add a2, a0, a1
-; V-NEXT: add a3, a2, a1
-; V-NEXT: add a4, a3, a1
-; V-NEXT: add a5, a4, a1
-; V-NEXT: add a6, a5, a1
-; V-NEXT: add a7, a6, a1
-; V-NEXT: vl1re64.v v14, (a7)
-; V-NEXT: add a1, a7, a1
-; V-NEXT: vl1re64.v v15, (a1)
-; V-NEXT: vl1re64.v v12, (a5)
-; V-NEXT: vl1re64.v v13, (a6)
+; V-NEXT: slli a2, a1, 1
+; V-NEXT: slli a3, a1, 2
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re64.v v14, (a4)
+; V-NEXT: slli a4, a1, 3
+; V-NEXT: sub a5, a0, a1
+; V-NEXT: add a4, a5, a4
+; V-NEXT: vl1re64.v v15, (a4)
+; V-NEXT: add a4, a0, a3
+; V-NEXT: vl1re64.v v12, (a4)
+; V-NEXT: add a1, a0, a1
+; V-NEXT: add a3, a1, a3
+; V-NEXT: vl1re64.v v13, (a3)
+; V-NEXT: add a3, a0, a2
; V-NEXT: vl1re64.v v10, (a3)
-; V-NEXT: vl1re64.v v11, (a4)
+; V-NEXT: add a2, a1, a2
+; V-NEXT: vl1re64.v v11, (a2)
; V-NEXT: vl1re64.v v8, (a0)
-; V-NEXT: vl1re64.v v9, (a2)
+; V-NEXT: vl1re64.v v9, (a1)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 3
; V-NEXT: add sp, sp, a0
@@ -15135,21 +16003,26 @@ define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x do
; ZVBB-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; ZVBB-NEXT: vsseg8e64.v v8, (a0)
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a4, a3, a1
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1re64.v v14, (a7)
-; ZVBB-NEXT: add a1, a7, a1
-; ZVBB-NEXT: vl1re64.v v15, (a1)
-; ZVBB-NEXT: vl1re64.v v12, (a5)
-; ZVBB-NEXT: vl1re64.v v13, (a6)
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: slli a3, a1, 2
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re64.v v14, (a4)
+; ZVBB-NEXT: slli a4, a1, 3
+; ZVBB-NEXT: sub a5, a0, a1
+; ZVBB-NEXT: add a4, a5, a4
+; ZVBB-NEXT: vl1re64.v v15, (a4)
+; ZVBB-NEXT: add a4, a0, a3
+; ZVBB-NEXT: vl1re64.v v12, (a4)
+; ZVBB-NEXT: add a1, a0, a1
+; ZVBB-NEXT: add a3, a1, a3
+; ZVBB-NEXT: vl1re64.v v13, (a3)
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vl1re64.v v10, (a3)
-; ZVBB-NEXT: vl1re64.v v11, (a4)
+; ZVBB-NEXT: add a2, a1, a2
+; ZVBB-NEXT: vl1re64.v v11, (a2)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: vl1re64.v v9, (a1)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 3
; ZVBB-NEXT: add sp, sp, a0
@@ -15195,48 +16068,55 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x
; V-NEXT: vmv1r.v v6, v19
; V-NEXT: vmv1r.v v7, v31
; V-NEXT: vmv1r.v v8, v23
-; V-NEXT: csrr a1, vlenb
-; V-NEXT: slli a1, a1, 3
-; V-NEXT: add a1, sp, a1
-; V-NEXT: addi a1, a1, 16
+; V-NEXT: addi a1, sp, 16
; V-NEXT: vsseg8e64.v v1, (a1)
; V-NEXT: vmv1r.v v25, v10
; V-NEXT: vmv1r.v v27, v14
; V-NEXT: vmv1r.v v29, v18
; V-NEXT: vmv1r.v v31, v22
-; V-NEXT: addi a0, sp, 16
+; V-NEXT: csrr a0, vlenb
+; V-NEXT: slli a0, a0, 3
+; V-NEXT: add a0, sp, a0
+; V-NEXT: addi a0, a0, 16
; V-NEXT: vsseg8e64.v v24, (a0)
; V-NEXT: csrr a2, vlenb
-; V-NEXT: add a3, a1, a2
-; V-NEXT: add a4, a3, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: add a6, a5, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: add t0, a7, a2
-; V-NEXT: vl1re64.v v22, (t0)
-; V-NEXT: add t0, t0, a2
-; V-NEXT: vl1re64.v v23, (t0)
-; V-NEXT: vl1re64.v v20, (a6)
-; V-NEXT: vl1re64.v v21, (a7)
+; V-NEXT: slli a3, a2, 1
+; V-NEXT: add a4, a1, a3
; V-NEXT: vl1re64.v v18, (a4)
+; V-NEXT: add a4, a3, a2
+; V-NEXT: add a5, a1, a4
; V-NEXT: vl1re64.v v19, (a5)
; V-NEXT: vl1re64.v v16, (a1)
-; V-NEXT: add a1, a0, a2
-; V-NEXT: add a4, a1, a2
-; V-NEXT: add a5, a4, a2
-; V-NEXT: vl1re64.v v17, (a3)
-; V-NEXT: add a3, a5, a2
-; V-NEXT: add a6, a3, a2
-; V-NEXT: add a7, a6, a2
-; V-NEXT: vl1re64.v v14, (a7)
-; V-NEXT: add a2, a7, a2
-; V-NEXT: vl1re64.v v15, (a2)
-; V-NEXT: vl1re64.v v12, (a3)
-; V-NEXT: vl1re64.v v13, (a6)
-; V-NEXT: vl1re64.v v10, (a4)
-; V-NEXT: vl1re64.v v11, (a5)
+; V-NEXT: add a5, a1, a2
+; V-NEXT: vl1re64.v v17, (a5)
+; V-NEXT: slli a5, a2, 2
+; V-NEXT: add a6, a5, a3
+; V-NEXT: add a7, a1, a6
+; V-NEXT: vl1re64.v v22, (a7)
+; V-NEXT: slli a7, a2, 3
+; V-NEXT: sub a7, a7, a2
+; V-NEXT: add t0, a1, a7
+; V-NEXT: vl1re64.v v23, (t0)
+; V-NEXT: add t0, a1, a5
+; V-NEXT: vl1re64.v v20, (t0)
+; V-NEXT: add t0, a5, a2
+; V-NEXT: add a1, a1, t0
+; V-NEXT: vl1re64.v v21, (a1)
+; V-NEXT: add a3, a0, a3
+; V-NEXT: vl1re64.v v10, (a3)
+; V-NEXT: add a4, a0, a4
+; V-NEXT: vl1re64.v v11, (a4)
; V-NEXT: vl1re64.v v8, (a0)
-; V-NEXT: vl1re64.v v9, (a1)
+; V-NEXT: add a2, a0, a2
+; V-NEXT: vl1re64.v v9, (a2)
+; V-NEXT: add a6, a0, a6
+; V-NEXT: vl1re64.v v14, (a6)
+; V-NEXT: add a7, a0, a7
+; V-NEXT: vl1re64.v v15, (a7)
+; V-NEXT: add a5, a0, a5
+; V-NEXT: vl1re64.v v12, (a5)
+; V-NEXT: add a0, a0, t0
+; V-NEXT: vl1re64.v v13, (a0)
; V-NEXT: csrr a0, vlenb
; V-NEXT: slli a0, a0, 4
; V-NEXT: add sp, sp, a0
@@ -15262,48 +16142,55 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x
; ZVBB-NEXT: vmv1r.v v6, v19
; ZVBB-NEXT: vmv1r.v v7, v31
; ZVBB-NEXT: vmv1r.v v8, v23
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: slli a1, a1, 3
-; ZVBB-NEXT: add a1, sp, a1
-; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a1, sp, 16
; ZVBB-NEXT: vsseg8e64.v v1, (a1)
; ZVBB-NEXT: vmv1r.v v25, v10
; ZVBB-NEXT: vmv1r.v v27, v14
; ZVBB-NEXT: vmv1r.v v29, v18
; ZVBB-NEXT: vmv1r.v v31, v22
-; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: slli a0, a0, 3
+; ZVBB-NEXT: add a0, sp, a0
+; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: vsseg8e64.v v24, (a0)
; ZVBB-NEXT: csrr a2, vlenb
-; ZVBB-NEXT: add a3, a1, a2
-; ZVBB-NEXT: add a4, a3, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: add a6, a5, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: add t0, a7, a2
-; ZVBB-NEXT: vl1re64.v v22, (t0)
-; ZVBB-NEXT: add t0, t0, a2
-; ZVBB-NEXT: vl1re64.v v23, (t0)
-; ZVBB-NEXT: vl1re64.v v20, (a6)
-; ZVBB-NEXT: vl1re64.v v21, (a7)
+; ZVBB-NEXT: slli a3, a2, 1
+; ZVBB-NEXT: add a4, a1, a3
; ZVBB-NEXT: vl1re64.v v18, (a4)
+; ZVBB-NEXT: add a4, a3, a2
+; ZVBB-NEXT: add a5, a1, a4
; ZVBB-NEXT: vl1re64.v v19, (a5)
; ZVBB-NEXT: vl1re64.v v16, (a1)
-; ZVBB-NEXT: add a1, a0, a2
-; ZVBB-NEXT: add a4, a1, a2
-; ZVBB-NEXT: add a5, a4, a2
-; ZVBB-NEXT: vl1re64.v v17, (a3)
-; ZVBB-NEXT: add a3, a5, a2
-; ZVBB-NEXT: add a6, a3, a2
-; ZVBB-NEXT: add a7, a6, a2
-; ZVBB-NEXT: vl1re64.v v14, (a7)
-; ZVBB-NEXT: add a2, a7, a2
-; ZVBB-NEXT: vl1re64.v v15, (a2)
-; ZVBB-NEXT: vl1re64.v v12, (a3)
-; ZVBB-NEXT: vl1re64.v v13, (a6)
-; ZVBB-NEXT: vl1re64.v v10, (a4)
-; ZVBB-NEXT: vl1re64.v v11, (a5)
+; ZVBB-NEXT: add a5, a1, a2
+; ZVBB-NEXT: vl1re64.v v17, (a5)
+; ZVBB-NEXT: slli a5, a2, 2
+; ZVBB-NEXT: add a6, a5, a3
+; ZVBB-NEXT: add a7, a1, a6
+; ZVBB-NEXT: vl1re64.v v22, (a7)
+; ZVBB-NEXT: slli a7, a2, 3
+; ZVBB-NEXT: sub a7, a7, a2
+; ZVBB-NEXT: add t0, a1, a7
+; ZVBB-NEXT: vl1re64.v v23, (t0)
+; ZVBB-NEXT: add t0, a1, a5
+; ZVBB-NEXT: vl1re64.v v20, (t0)
+; ZVBB-NEXT: add t0, a5, a2
+; ZVBB-NEXT: add a1, a1, t0
+; ZVBB-NEXT: vl1re64.v v21, (a1)
+; ZVBB-NEXT: add a3, a0, a3
+; ZVBB-NEXT: vl1re64.v v10, (a3)
+; ZVBB-NEXT: add a4, a0, a4
+; ZVBB-NEXT: vl1re64.v v11, (a4)
; ZVBB-NEXT: vl1re64.v v8, (a0)
-; ZVBB-NEXT: vl1re64.v v9, (a1)
+; ZVBB-NEXT: add a2, a0, a2
+; ZVBB-NEXT: vl1re64.v v9, (a2)
+; ZVBB-NEXT: add a6, a0, a6
+; ZVBB-NEXT: vl1re64.v v14, (a6)
+; ZVBB-NEXT: add a7, a0, a7
+; ZVBB-NEXT: vl1re64.v v15, (a7)
+; ZVBB-NEXT: add a5, a0, a5
+; ZVBB-NEXT: vl1re64.v v12, (a5)
+; ZVBB-NEXT: add a0, a0, t0
+; ZVBB-NEXT: vl1re64.v v13, (a0)
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: add sp, sp, a0
@@ -15357,9 +16244,11 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; V-NEXT: vmv.v.i v9, -1
; V-NEXT: vwmaccu.vx v8, a0, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v9, v8, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v9, v8, a0
; V-NEXT: vslideup.vx v8, v9, a0
; V-NEXT: ret
;
@@ -15371,9 +16260,11 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; ZVBB-NEXT: li a0, 3
; ZVBB-NEXT: vwaddu.wx v8, v9, a0
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v9, v8, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v9, v8, a0
; ZVBB-NEXT: vslideup.vx v8, v9, a0
; ZVBB-NEXT: ret
;
@@ -15416,9 +16307,11 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; V-NEXT: vmv.v.i v9, -1
; V-NEXT: vwmaccu.vx v8, a1, v9
; V-NEXT: csrr a0, vlenb
+; V-NEXT: srli a1, a0, 3
+; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; V-NEXT: vslidedown.vx v9, v8, a1
; V-NEXT: srli a0, a0, 2
; V-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; V-NEXT: vslidedown.vx v9, v8, a0
; V-NEXT: vslideup.vx v8, v9, a0
; V-NEXT: ret
;
@@ -15429,9 +16322,11 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; ZVBB-NEXT: vwsll.vi v9, v8, 16
; ZVBB-NEXT: vwaddu.wx v8, v9, a0
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: srli a1, a0, 3
+; ZVBB-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVBB-NEXT: vslidedown.vx v9, v8, a1
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vx v9, v8, a0
; ZVBB-NEXT: vslideup.vx v8, v9, a0
; ZVBB-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
index fd46b99bd98e33..a788376bd26ed2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
@@ -370,12 +370,15 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: srli a2, a2, 2
-; RV32-NEXT: vslidedown.vx v11, v11, a2
+; RV32-NEXT: srli a3, a2, 3
+; RV32-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v11, v11, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
+; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v10, v9, a2
; RV32-NEXT: slli a2, a1, 1
@@ -405,12 +408,15 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vslidedown.vx v11, v11, a2
+; RV64-NEXT: srli a3, a2, 3
+; RV64-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v11, v11, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v11, 0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0
+; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vx v10, v9, a2
; RV64-NEXT: slli a2, a1, 33
@@ -591,12 +597,15 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: srli a2, a2, 2
-; RV32-NEXT: vslidedown.vx v9, v11, a2
+; RV32-NEXT: srli a3, a2, 3
+; RV32-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v9, v11, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v9, 0
; RV32-NEXT: vmerge.vim v9, v10, 1, v0
+; RV32-NEXT: srli a2, a2, 2
; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v8, v9, a2
; RV32-NEXT: slli a1, a1, 1
@@ -625,12 +634,15 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vslidedown.vx v9, v11, a2
+; RV64-NEXT: srli a3, a2, 3
+; RV64-NEXT: vsetvli a4, zero, e16, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v9, v11, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v9, 0
; RV64-NEXT: vmerge.vim v9, v10, 1, v0
+; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vx v8, v9, a2
; RV64-NEXT: slli a1, a1, 33
diff --git a/llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll b/llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll
new file mode 100644
index 00000000000000..ad94331638afd3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-deinterleave-intrinsics.ll
@@ -0,0 +1,386 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @deinterleave2(ptr %src, ptr %dst0, ptr %dst1) {
+; CHECK-LABEL: deinterleave2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps (%rdi), %xmm0
+; CHECK-NEXT: movaps 16(%rdi), %xmm1
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm2, (%rdx)
+; CHECK-NEXT: retq
+ %wide = load <8 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32> } %result, 1
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ ret void
+}
+
+define void @deinterleave3(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2) {
+; CHECK-LABEL: deinterleave3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm1
+; CHECK-NEXT: movdqa 32(%rdi), %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm2[0,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm1[0,1]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movdqa %xmm3, (%rdx)
+; CHECK-NEXT: movaps %xmm5, (%rcx)
+; CHECK-NEXT: retq
+ %wide = load <12 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave3.v12i32(<12 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ ret void
+}
+
+define void @deinterleave4(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3) {
+; CHECK-LABEL: deinterleave4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps (%rdi), %xmm0
+; CHECK-NEXT: movaps 16(%rdi), %xmm1
+; CHECK-NEXT: movaps 32(%rdi), %xmm2
+; CHECK-NEXT: movaps 48(%rdi), %xmm3
+; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm3[1,3]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm1[1,3]
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm4[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm4[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm5, (%rdx)
+; CHECK-NEXT: movaps %xmm1, (%rcx)
+; CHECK-NEXT: movaps %xmm6, (%r8)
+; CHECK-NEXT: retq
+ %wide = load <16 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave4.v16i32(<16 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ ret void
+}
+
+define void @deinterleave5(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4) {
+; CHECK-LABEL: deinterleave5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa 64(%rdi), %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[3,3,3,3]
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm4
+; CHECK-NEXT: movdqa 32(%rdi), %xmm2
+; CHECK-NEXT: movdqa 48(%rdi), %xmm3
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm4[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm6[0],xmm4[1],xmm6[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm1[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm6[0],xmm3[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm3[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm8[0],xmm1[1],xmm8[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm10[0],xmm2[1],xmm10[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm9[0],xmm0[1],xmm9[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movdqa %xmm0, (%rsi)
+; CHECK-NEXT: movdqa %xmm1, (%rdx)
+; CHECK-NEXT: movdqa %xmm6, (%rcx)
+; CHECK-NEXT: movdqa %xmm5, (%r8)
+; CHECK-NEXT: movdqa %xmm4, (%r9)
+; CHECK-NEXT: retq
+ %wide = load <20 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave5.v20i32(<20 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ ret void
+}
+
+define void @deinterleave6(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5) {
+; CHECK-LABEL: deinterleave6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movdqa 80(%rdi), %xmm2
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
+; CHECK-NEXT: movdqa 64(%rdi), %xmm5
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm5[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1]
+; CHECK-NEXT: movdqa (%rdi), %xmm0
+; CHECK-NEXT: movdqa 16(%rdi), %xmm3
+; CHECK-NEXT: movdqa 32(%rdi), %xmm6
+; CHECK-NEXT: movdqa 48(%rdi), %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm5[0],xmm8[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm4[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm6[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm4[0],xmm7[1],xmm4[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm7[0]
+; CHECK-NEXT: movdqa %xmm4, %xmm7
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,3],xmm8[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm8[0,2]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm5[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm1[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm2[0,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm3[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm0[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm8[0],xmm10[1],xmm8[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,1],xmm6[0,3]
+; CHECK-NEXT: movaps %xmm10, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm9[1,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm5[0,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm3[0,1]
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm9[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT: movaps %xmm0, (%rsi)
+; CHECK-NEXT: movaps %xmm4, (%rdx)
+; CHECK-NEXT: movaps %xmm10, (%rcx)
+; CHECK-NEXT: movaps %xmm2, (%r8)
+; CHECK-NEXT: movaps %xmm7, (%r9)
+; CHECK-NEXT: movaps %xmm8, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <24 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave6.v24i32(<24 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ ret void
+}
+
+define void @deinterleave7(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5, ptr %dst6) {
+; CHECK-LABEL: deinterleave7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa 80(%rdi), %xmm6
+; CHECK-NEXT: movdqa 96(%rdi), %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm6[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm6[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1]
+; CHECK-NEXT: movdqa (%rdi), %xmm2
+; CHECK-NEXT: movdqa 16(%rdi), %xmm9
+; CHECK-NEXT: movdqa 32(%rdi), %xmm8
+; CHECK-NEXT: movdqa 48(%rdi), %xmm7
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm7[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm9[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm10[0],xmm1[1],xmm10[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm6[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
+; CHECK-NEXT: movdqa 64(%rdi), %xmm10
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm10[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm11 = xmm11[0],xmm6[0],xmm11[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm9[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm11[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm10[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm8[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm13 = xmm9[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm11[0],xmm9[1],xmm11[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm12[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm10[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm11 = xmm11[0],xmm0[0],xmm11[1],xmm0[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm8[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm2[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm0[0],xmm12[1],xmm0[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm12 = xmm12[0],xmm11[0]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm3[0],xmm10[1],xmm3[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm8[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm10[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm7[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm8[0],xmm4[1],xmm8[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm7[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm13[0],xmm2[1],xmm13[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; CHECK-NEXT: movdqa %xmm2, (%rsi)
+; CHECK-NEXT: movdqa %xmm4, (%rdx)
+; CHECK-NEXT: movdqa %xmm3, (%rcx)
+; CHECK-NEXT: movdqa %xmm12, (%r8)
+; CHECK-NEXT: movdqa %xmm9, (%r9)
+; CHECK-NEXT: movdqa %xmm6, (%rdi)
+; CHECK-NEXT: movdqa %xmm1, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <28 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave7.v28i32(<28 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ %v6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ store <4 x i32> %v6, ptr %dst6
+ ret void
+}
+
+define void @deinterleave8(ptr %src, ptr %dst0, ptr %dst1, ptr %dst2, ptr %dst3, ptr %dst4, ptr %dst5, ptr %dst6, ptr %dst7) {
+; CHECK-LABEL: deinterleave8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r11
+; CHECK-NEXT: movaps 112(%rdi), %xmm10
+; CHECK-NEXT: movaps 96(%rdi), %xmm4
+; CHECK-NEXT: movaps %xmm4, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm10[1,3]
+; CHECK-NEXT: movaps 80(%rdi), %xmm11
+; CHECK-NEXT: movaps 64(%rdi), %xmm0
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm11[1,3]
+; CHECK-NEXT: movaps %xmm1, %xmm5
+; CHECK-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,3],xmm8[1,3]
+; CHECK-NEXT: movaps (%rdi), %xmm2
+; CHECK-NEXT: movaps 16(%rdi), %xmm12
+; CHECK-NEXT: movaps 32(%rdi), %xmm9
+; CHECK-NEXT: movaps 48(%rdi), %xmm13
+; CHECK-NEXT: movaps %xmm9, %xmm14
+; CHECK-NEXT: shufps {{.*#+}} xmm14 = xmm14[1,3],xmm13[1,3]
+; CHECK-NEXT: movaps %xmm2, %xmm6
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm12[1,3]
+; CHECK-NEXT: movaps %xmm6, %xmm7
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[1,3],xmm14[1,3]
+; CHECK-NEXT: movaps %xmm7, %xmm3
+; CHECK-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,3],xmm5[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm10[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm11[0,2]
+; CHECK-NEXT: movaps %xmm0, %xmm10
+; CHECK-NEXT: shufps {{.*#+}} xmm10 = xmm10[1,3],xmm4[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm13[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm12[0,2]
+; CHECK-NEXT: movaps %xmm2, %xmm11
+; CHECK-NEXT: shufps {{.*#+}} xmm11 = xmm11[1,3],xmm9[1,3]
+; CHECK-NEXT: movaps %xmm11, %xmm12
+; CHECK-NEXT: shufps {{.*#+}} xmm12 = xmm12[1,3],xmm10[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm8[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm14[0,2]
+; CHECK-NEXT: movaps %xmm6, %xmm8
+; CHECK-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,3],xmm1[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm4[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm9[0,2]
+; CHECK-NEXT: movaps %xmm2, %xmm4
+; CHECK-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm0[1,3]
+; CHECK-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2],xmm5[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2],xmm10[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm1[0,2]
+; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[0,2]
+; CHECK-NEXT: movaps %xmm2, (%rsi)
+; CHECK-NEXT: movaps %xmm6, (%rdx)
+; CHECK-NEXT: movaps %xmm11, (%rcx)
+; CHECK-NEXT: movaps %xmm7, (%r8)
+; CHECK-NEXT: movaps %xmm4, (%r9)
+; CHECK-NEXT: movaps %xmm8, (%r11)
+; CHECK-NEXT: movaps %xmm12, (%r10)
+; CHECK-NEXT: movaps %xmm3, (%rax)
+; CHECK-NEXT: retq
+ %wide = load <32 x i32>, ptr %src
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave8.v32i32(<32 x i32> %wide)
+ %v0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ %v1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ %v2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ %v3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ %v4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ %v5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ %v6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ %v7 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 7
+ store <4 x i32> %v0, ptr %dst0
+ store <4 x i32> %v1, ptr %dst1
+ store <4 x i32> %v2, ptr %dst2
+ store <4 x i32> %v3, ptr %dst3
+ store <4 x i32> %v4, ptr %dst4
+ store <4 x i32> %v5, ptr %dst5
+ store <4 x i32> %v6, ptr %dst6
+ store <4 x i32> %v7, ptr %dst7
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll b/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
new file mode 100644
index 00000000000000..328886432d07d2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-interleave-intrinsics.ll
@@ -0,0 +1,274 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @interleave2(ptr %dst, <4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: interleave2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 16(%rdi)
+; CHECK-NEXT: movaps %xmm2, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %v0, <4 x i32> %v1)
+ store <8 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave3(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: interleave3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm2[2,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; CHECK-NEXT: movdqa %xmm0, %xmm3
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm0[0]
+; CHECK-NEXT: movdqa %xmm6, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm2, 16(%rdi)
+; CHECK-NEXT: movdqa %xmm3, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <12 x i32> @llvm.vector.interleave3.v12i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2)
+ store <12 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave4(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
+; CHECK-LABEL: interleave4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm1, %xmm4
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
+; CHECK-NEXT: movaps %xmm0, %xmm5
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
+; CHECK-NEXT: movaps %xmm5, %xmm6
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm4[2],xmm5[3],xmm4[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 48(%rdi)
+; CHECK-NEXT: movaps %xmm2, 32(%rdi)
+; CHECK-NEXT: movaps %xmm5, 16(%rdi)
+; CHECK-NEXT: movaps %xmm6, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <16 x i32> @llvm.vector.interleave4.v16i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3)
+ store <16 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave5(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4) {
+; CHECK-LABEL: interleave5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm4[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm6[0]
+; CHECK-NEXT: movdqa %xmm0, %xmm5
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm1[2],xmm5[3],xmm1[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm5[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm3[2],xmm5[3],xmm3[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm8[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm9[0],xmm7[1],xmm9[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm2[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm7[0]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movdqa %xmm0, (%rdi)
+; CHECK-NEXT: movdqa %xmm9, 64(%rdi)
+; CHECK-NEXT: movdqa %xmm5, 48(%rdi)
+; CHECK-NEXT: movdqa %xmm6, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm4, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <20 x i32> @llvm.vector.interleave5.v20i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4)
+ store <20 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave6(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5) {
+; CHECK-LABEL: interleave6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm4, %xmm6
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm1[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm0[1,1,1,1]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm8 = xmm8[2],xmm7[2],xmm8[3],xmm7[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm8[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm5[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm3[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm2[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm9[0],xmm7[1],xmm9[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm8[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm4[3,3,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm1[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm10 = xmm10[2],xmm9[2],xmm10[3],xmm9[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm10[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm5[0],xmm8[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm3[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm2[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm5[0],xmm9[1],xmm5[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm8[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm5
+; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
+; CHECK-NEXT: movdqa %xmm0, %xmm8
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm1[0],xmm8[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm5[0]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT: movdqa %xmm0, 48(%rdi)
+; CHECK-NEXT: movdqa %xmm8, (%rdi)
+; CHECK-NEXT: movdqa %xmm9, 80(%rdi)
+; CHECK-NEXT: movdqa %xmm4, 64(%rdi)
+; CHECK-NEXT: movdqa %xmm7, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm6, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <24 x i32> @llvm.vector.interleave6.v24i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5)
+ store <24 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave7(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6) {
+; CHECK-LABEL: interleave7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa %xmm4, %xmm7
+; CHECK-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm0[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm6[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm8 = xmm6[2,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm6[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm9[0],xmm6[1],xmm9[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm6[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm3[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm6[0],xmm9[1],xmm6[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm2[1,1,1,1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm6 = xmm1[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm12[0],xmm6[1],xmm12[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm9[0]
+; CHECK-NEXT: movdqa %xmm0, %xmm12
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm12 = xmm12[2],xmm1[2],xmm12[3],xmm1[3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm9 = xmm5[1,1,1,1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm9 = xmm9[0],xmm10[0],xmm9[1],xmm10[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm12[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm2[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm1[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm10[0],xmm12[1],xmm10[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm0[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm10[0],xmm8[1],xmm10[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm12[0]
+; CHECK-NEXT: pshufd {{.*#+}} xmm10 = xmm5[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm11 = xmm4[3,3,3,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm12 = xmm3[3,3,3,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm12 = xmm12[0],xmm10[0]
+; CHECK-NEXT: movdqa %xmm2, %xmm10
+; CHECK-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm3[0],xmm10[1],xmm3[1]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm10[0]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
+; CHECK-NEXT: movdqa %xmm2, 64(%rdi)
+; CHECK-NEXT: movdqa %xmm0, (%rdi)
+; CHECK-NEXT: movdqa %xmm12, 96(%rdi)
+; CHECK-NEXT: movdqa %xmm8, 80(%rdi)
+; CHECK-NEXT: movdqa %xmm9, 48(%rdi)
+; CHECK-NEXT: movdqa %xmm6, 32(%rdi)
+; CHECK-NEXT: movdqa %xmm7, 16(%rdi)
+; CHECK-NEXT: retq
+ %result = call <28 x i32> @llvm.vector.interleave7.v28i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6)
+ store <28 x i32> %result, ptr %dst
+ ret void
+}
+
+
+define void @interleave8(ptr %dst, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7) {
+; CHECK-LABEL: interleave8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movaps %xmm3, %xmm11
+; CHECK-NEXT: unpcklps {{.*#+}} xmm11 = xmm11[0],xmm7[0],xmm11[1],xmm7[1]
+; CHECK-NEXT: movaps %xmm1, %xmm12
+; CHECK-NEXT: unpcklps {{.*#+}} xmm12 = xmm12[0],xmm5[0],xmm12[1],xmm5[1]
+; CHECK-NEXT: movaps %xmm12, %xmm13
+; CHECK-NEXT: unpcklps {{.*#+}} xmm13 = xmm13[0],xmm11[0],xmm13[1],xmm11[1]
+; CHECK-NEXT: movaps %xmm2, %xmm14
+; CHECK-NEXT: unpcklps {{.*#+}} xmm14 = xmm14[0],xmm6[0],xmm14[1],xmm6[1]
+; CHECK-NEXT: movaps %xmm0, %xmm9
+; CHECK-NEXT: unpcklps {{.*#+}} xmm9 = xmm9[0],xmm4[0],xmm9[1],xmm4[1]
+; CHECK-NEXT: movaps %xmm9, %xmm8
+; CHECK-NEXT: unpcklps {{.*#+}} xmm8 = xmm8[0],xmm14[0],xmm8[1],xmm14[1]
+; CHECK-NEXT: movaps %xmm8, %xmm10
+; CHECK-NEXT: unpcklps {{.*#+}} xmm10 = xmm10[0],xmm13[0],xmm10[1],xmm13[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm8 = xmm8[2],xmm13[2],xmm8[3],xmm13[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm12 = xmm12[2],xmm11[2],xmm12[3],xmm11[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm9 = xmm9[2],xmm14[2],xmm9[3],xmm14[3]
+; CHECK-NEXT: movaps %xmm9, %xmm11
+; CHECK-NEXT: unpcklps {{.*#+}} xmm11 = xmm11[0],xmm12[0],xmm11[1],xmm12[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm9 = xmm9[2],xmm12[2],xmm9[3],xmm12[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm3 = xmm3[2],xmm7[2],xmm3[3],xmm7[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm5[2],xmm1[3],xmm5[3]
+; CHECK-NEXT: movaps %xmm1, %xmm5
+; CHECK-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm6[2],xmm2[3],xmm6[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm4[2],xmm0[3],xmm4[3]
+; CHECK-NEXT: movaps %xmm0, %xmm4
+; CHECK-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
+; CHECK-NEXT: movaps %xmm4, %xmm6
+; CHECK-NEXT: unpcklps {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm5[2],xmm4[3],xmm5[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; CHECK-NEXT: unpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; CHECK-NEXT: movaps %xmm0, 112(%rdi)
+; CHECK-NEXT: movaps %xmm2, 96(%rdi)
+; CHECK-NEXT: movaps %xmm4, 80(%rdi)
+; CHECK-NEXT: movaps %xmm6, 64(%rdi)
+; CHECK-NEXT: movaps %xmm9, 48(%rdi)
+; CHECK-NEXT: movaps %xmm11, 32(%rdi)
+; CHECK-NEXT: movaps %xmm8, 16(%rdi)
+; CHECK-NEXT: movaps %xmm10, (%rdi)
+; CHECK-NEXT: retq
+ %result = call <32 x i32> @llvm.vector.interleave8.v32i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, <4 x i32> %v4, <4 x i32> %v5, <4 x i32> %v6, <4 x i32> %v7)
+ store <32 x i32> %result, ptr %dst
+ ret void
+}
>From 5ef6bd8dff4ea8f2b81e4f97a9e572060b32fd75 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Mon, 7 Sep 2026 12:15:52 +0000
Subject: [PATCH 2/2] Fix riscv interleave regressions
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 27 +
.../rvv/fixed-vectors-interleave-store.ll | 59 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 31 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 1228 +++++------------
4 files changed, 406 insertions(+), 939 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 97b3c6ca103f35..b24ffd2134e55b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -23676,6 +23676,33 @@ static SDValue performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
if (!TLI.isTypeLegal(VT))
return SDValue();
+ // If inputs of concat_vectors are output of 2 way interleave
+ // transform it to wider shuffle for fixed length vector.
+ // i.e.
+ // concat_vectors((vector_interleave X, Y):0,
+ // (vector_interleave X, Y):1)
+ // --> vector_shuffle(concat_vectors(X, Y), undef,
+ // <0, N, 1, N + 1, ...>)
+ if (N->getNumOperands() == 2) {
+ SDValue Lo = N->getOperand(0);
+ SDValue Hi = N->getOperand(1);
+ SDNode *Interleave = Lo.getNode();
+ EVT PartVT = Lo.getValueType();
+ if (PartVT.isFixedLengthVector() &&
+ Lo.getOpcode() == ISD::VECTOR_INTERLEAVE &&
+ Hi.getNode() == Interleave && Interleave->getNumOperands() == 2 &&
+ Lo.hasOneUse() && Hi.hasOneUse() &&
+ TLI.getVectorInterleaveAction(ISD::VECTOR_INTERLEAVE, 2, PartVT) ==
+ TargetLowering::Expand) {
+ unsigned NumElts = PartVT.getVectorNumElements();
+ SDValue Concat =
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Interleave->getOperand(0),
+ Interleave->getOperand(1));
+ return DAG.getVectorShuffle(VT, DL, Concat, DAG.getUNDEF(VT),
+ createInterleaveMask(NumElts, 2));
+ }
+ }
+
// TODO: Potentially extend this to scalable vectors
if (VT.isScalableVector())
return SDValue();
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
index 34f57538deb41e..a5971fb1f0310c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
@@ -9,39 +9,21 @@
define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: lui a1, 11
-; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
-; CHECK-NEXT: addi a1, a1, -1366
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 8
-; CHECK-NEXT: vslidedown.vi v11, v9, 8
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v11
-; CHECK-NEXT: vsll.vi v11, v12, 8
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v10, a1, v8
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmsne.vi v9, v10, 0
-; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vslideup.vi v9, v8, 2
+; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vsm.v v9, (a0)
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 16
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: li a2, -1
+; CHECK-NEXT: vwmaccu.vx v12, a2, v10
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmsne.vi v8, v12, 0
+; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
store <32 x i1> %res, ptr %p
@@ -52,25 +34,10 @@ define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr
define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v16i16_v8i16_align1:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 170
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a1
-; CHECK-NEXT: vslidedown.vi v10, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v8, v13, 16
; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a1, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vse8.v v10, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 14c5d3da6d23ce..6cd6efef76d3b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -3797,44 +3797,19 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; V-NEXT: vnsrl.wx v12, v8, a0
; V-NEXT: vnsrl.wi v14, v8, 0
-; V-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; V-NEXT: vslidedown.vi v8, v12, 4
-; V-NEXT: vslidedown.vi v10, v14, 4
-; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; V-NEXT: vzext.vf2 v16, v8
-; V-NEXT: vsll.vx v16, v16, a0
-; V-NEXT: li a0, 170
-; V-NEXT: vmv.s.x v0, a0
-; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwaddu.vv v8, v14, v12
-; V-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; V-NEXT: vzext.vf2 v14, v10
; V-NEXT: li a0, -1
-; V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; V-NEXT: vwmaccu.vx v8, a0, v12
-; V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; V-NEXT: vmerge.vvm v12, v14, v16, v0
-; V-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; V-NEXT: vslideup.vi v8, v12, 8
; V-NEXT: ret
;
; ZVZIP-LABEL: deinterleave_interleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a0, 32
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vnsrl.wx v14, v8, a0
-; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v10, v14, 4
-; ZVZIP-NEXT: vslidedown.vi v8, v16, 4
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v8, v9
-; ZVZIP-NEXT: vzip.vv v8, v16, v14
-; ZVZIP-NEXT: vzip.vv v12, v11, v10, v0.t
+; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: vzip.vv v8, v14, v12
; ZVZIP-NEXT: ret
entry:
%0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index a540b7aa3d5196..2c268b389f95b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -13,119 +13,68 @@
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: lui a0, 11
-; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
-; CHECK-NEXT: addi a0, a0, -1366
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 8
-; CHECK-NEXT: vslidedown.vi v11, v9, 8
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v10, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v9, v11
-; CHECK-NEXT: vsll.vi v11, v12, 8
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v10, a0, v8
-; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v8, 16
+; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT: vwaddu.vv v12, v8, v10
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vwmaccu.vx v12, a1, v10
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v32i1_v16i1:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vmv.v.i v9, 0
-; ZVBB-NEXT: vmerge.vim v10, v9, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: lui a0, 11
-; ZVBB-NEXT: vmerge.vim v8, v9, 1, v0
-; ZVBB-NEXT: addi a0, a0, -1366
-; ZVBB-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; ZVBB-NEXT: vslidedown.vi v9, v10, 8
-; ZVBB-NEXT: vslidedown.vi v11, v8, 8
-; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v9
-; ZVBB-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v9, v8, 8
-; ZVBB-NEXT: vwaddu.wv v9, v9, v10
-; ZVBB-NEXT: vwsll.vi v8, v11, 8
-; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVBB-NEXT: vmsne.vi v0, v9, 0
-; ZVBB-NEXT: vmsne.vi v8, v8, 0
; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVBB-NEXT: vslideup.vi v0, v8, 2
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVBB-NEXT: vmv.v.i v8, 0
+; ZVBB-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVBB-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; ZVBB-NEXT: vslidedown.vi v10, v8, 16
+; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVBB-NEXT: vwsll.vi v12, v10, 8
+; ZVBB-NEXT: vwaddu.wv v12, v12, v8
+; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v9, v0
-; ZVZIP-NEXT: vmv.v.i v10, 0
-; ZVZIP-NEXT: vmv1r.v v0, v8
-; ZVZIP-NEXT: vmerge.vim v8, v10, 1, v0
-; ZVZIP-NEXT: vmv1r.v v0, v9
-; ZVZIP-NEXT: lui a0, 11
-; ZVZIP-NEXT: vmerge.vim v9, v10, 1, v0
-; ZVZIP-NEXT: addi a0, a0, -1366
-; ZVZIP-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v10, v9, 8
-; ZVZIP-NEXT: vslidedown.vi v11, v8, 8
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v13, v10, v12
-; ZVZIP-NEXT: vzip.vv v10, v9, v8
-; ZVZIP-NEXT: vzip.vv v13, v8, v11, v0.t
-; ZVZIP-NEXT: vmsne.vi v0, v10, 0
-; ZVZIP-NEXT: vmsne.vi v8, v13, 0
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vslideup.vi v0, v8, 2
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v8, 0
+; ZVZIP-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 16
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v9, v0
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v10, 0
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v0, v8
-; ZVZIP-ZVL2048-NEXT: vmerge.vim v8, v10, 1, v0
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v0, v9
-; ZVZIP-ZVL2048-NEXT: lui a0, 11
-; ZVZIP-ZVL2048-NEXT: addi a0, a0, -1366
-; ZVZIP-ZVL2048-NEXT: vmerge.vim v9, v10, 1, v0
-; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v9, 8
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v10, v11
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 8
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf4, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v9, v8
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v10, v0.t
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmsne.vi v0, v11, 0
-; ZVZIP-ZVL2048-NEXT: vmsne.vi v8, v12, 0
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v0, v8, 2
+; ZVZIP-ZVL2048-NEXT: li a0, 32
+; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v8, 0
+; ZVZIP-ZVL2048-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v8, 16
+; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmsne.vi v0, v10, 0
; ZVZIP-ZVL2048-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
@@ -134,77 +83,35 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vector_interleave_v16i16_v8i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v10, v13, 16
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16i16_v8i16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: li a0, 170
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vslidedown.vi v8, v8, 4
-; ZVBB-NEXT: vslidedown.vi v11, v9, 4
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v9, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 4
-; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v8, v13
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: li a0, 170
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 4
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 8
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
@@ -214,76 +121,37 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vector_interleave_v8i32_v4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vsll.vx v10, v12, a0
-; CHECK-NEXT: vzext.vf2 v12, v11
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8i32_v4i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: vslidedown.vi v8, v8, 2
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vx v8, v9, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vx v9, v11, a0
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vwsll.vx v8, v10, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v11, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v8, v13
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vmv.v.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
@@ -292,42 +160,48 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vector_interleave_v4i64_v2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: lui a0, 12304
+; CHECK-NEXT: addi a0, a0, 512
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4i64_v2i64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: lui a0, 12304
+; ZVBB-NEXT: addi a0, a0, 512
+; ZVBB-NEXT: vmv.s.x v10, a0
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-NEXT: vslideup.vi v8, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v10, v9
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v11, v8
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
@@ -438,22 +312,16 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
;
; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v12, v8
-; ZVZIP-NEXT: vpairo.vv v13, v9, v11
-; ZVZIP-NEXT: vslideup.vi v9, v11, 1
-; ZVZIP-NEXT: vpairo.vv v11, v8, v10
-; ZVZIP-NEXT: vslideup.vi v12, v10, 1
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v12, v9
-; ZVZIP-NEXT: vslideup.vi v12, v11, 2
-; ZVZIP-NEXT: vslideup.vi v9, v13, 2
+; ZVZIP-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-NEXT: vzip.vv v13, v9, v11
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vslidedown.vi v8, v12, 2
; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v10, v11, v12
+; ZVZIP-NEXT: vzip.vv v10, v8, v11
+; ZVZIP-NEXT: vzip.vv v8, v12, v13
; ZVZIP-NEXT: vzip.vv v10, v11, v9, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
@@ -461,30 +329,23 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
;
; ZVZIP-ZVL2048-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v9, v11
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v9, v0.t
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v8, v9
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v12, v10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v9, v11, v0.t
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v13, 4
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v13, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 6
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 6
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
@@ -12240,93 +12101,47 @@ define <2048 x i8> @vector_interleave4_v512i8_v2048i8(<512 x i8> %v0, <512 x i8>
;
; ZVZIP-ZVL2048-RV32-LABEL: vector_interleave4_v512i8_v2048i8:
; ZVZIP-ZVL2048-RV32: # %bb.0:
-; ZVZIP-ZVL2048-RV32-NEXT: li a2, 256
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v18, v14, a2
-; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v26, v10, a2
-; ZVZIP-ZVL2048-RV32-NEXT: li a0, 512
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: li a0, 1024
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-ZVL2048-RV32-NEXT: li a1, 512
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v24, v16, a1
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v20, v8, v12
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v8, v20, a1
; ZVZIP-ZVL2048-RV32-NEXT: lui a1, 699051
; ZVZIP-ZVL2048-RV32-NEXT: addi a1, a1, -1366
-; ZVZIP-ZVL2048-RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: li a2, 32
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e32, mf2, ta, ma
; ZVZIP-ZVL2048-RV32-NEXT: vmv.v.x v0, a1
-; ZVZIP-ZVL2048-RV32-NEXT: vmv4r.v v20, v16
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v24, v26, v10
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v24, v10, v18, v0.t
-; ZVZIP-ZVL2048-RV32-NEXT: li a3, 1024
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslideup.vx v20, v24, a0
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v20, v20, a0
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v14, v12, a2
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v24, v8, v12
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v18, v8, a2
-; ZVZIP-ZVL2048-RV32-NEXT: vmv4r.v v8, v24
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v18, v15
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v15, v14, v0.t
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslideup.vx v8, v12, a0
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vslidedown.vx v8, v8, a0
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, ma
+; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v8, v10
-; ZVZIP-ZVL2048-RV32-NEXT: li a0, 32
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-RV32-NEXT: vmv.v.x v0, a1
-; ZVZIP-ZVL2048-RV32-NEXT: vsetvli zero, a3, e8, m4, ta, mu
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v8, v24, v16
-; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v16, v20, v0.t
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v12, v8, v24, v0.t
+; ZVZIP-ZVL2048-RV32-NEXT: vzip.vv v8, v20, v16
; ZVZIP-ZVL2048-RV32-NEXT: ret
;
; ZVZIP-ZVL2048-RV64-LABEL: vector_interleave4_v512i8_v2048i8:
; ZVZIP-ZVL2048-RV64: # %bb.0:
-; ZVZIP-ZVL2048-RV64-NEXT: li a2, 256
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v18, v14, a2
-; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v26, v10, a2
-; ZVZIP-ZVL2048-RV64-NEXT: lui a0, %hi(.LCPI6_0)
-; ZVZIP-ZVL2048-RV64-NEXT: ld a0, %lo(.LCPI6_0)(a0)
-; ZVZIP-ZVL2048-RV64-NEXT: li a1, 512
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: li a0, 1024
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v16, v10, v14
-; ZVZIP-ZVL2048-RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vmv.v.x v0, a0
-; ZVZIP-ZVL2048-RV64-NEXT: vmv4r.v v20, v16
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v24, v26, v10
-; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v24, v10, v18, v0.t
-; ZVZIP-ZVL2048-RV64-NEXT: li a3, 1024
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslideup.vx v20, v24, a1
+; ZVZIP-ZVL2048-RV64-NEXT: li a1, 512
; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v20, v20, a1
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v14, v12, a2
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v20, v16, a1
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v24, v8, v12
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v18, v8, a2
-; ZVZIP-ZVL2048-RV64-NEXT: vmv4r.v v8, v24
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v18, v15
-; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v15, v14, v0.t
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslideup.vx v8, v12, a1
; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v8, v8, a1
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-ZVL2048-RV64-NEXT: vslidedown.vx v8, v24, a1
+; ZVZIP-ZVL2048-RV64-NEXT: lui a1, %hi(.LCPI6_0)
+; ZVZIP-ZVL2048-RV64-NEXT: ld a1, %lo(.LCPI6_0)(a1)
; ZVZIP-ZVL2048-RV64-NEXT: vsetivli zero, 16, e64, m1, ta, ma
-; ZVZIP-ZVL2048-RV64-NEXT: vmv.v.x v0, a0
-; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a3, e8, m4, ta, mu
+; ZVZIP-ZVL2048-RV64-NEXT: vmv.v.x v0, a1
+; ZVZIP-ZVL2048-RV64-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v8, v20, v0.t
; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v8, v24, v16
-; ZVZIP-ZVL2048-RV64-NEXT: vzip.vv v12, v16, v20, v0.t
; ZVZIP-ZVL2048-RV64-NEXT: ret
%v = call <2048 x i8> @llvm.vector.interleave4(<512 x i8> %v0, <512 x i8> %v1, <512 x i8> %v2, <512 x i8> %v3)
ret <2048 x i8> %v
@@ -12750,113 +12565,57 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
;
; ZVZIP-LABEL: vector_interleave8_v16i8_v2i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vpairo.vv v16, v11, v15
-; ZVZIP-NEXT: vslideup.vi v11, v15, 1
-; ZVZIP-NEXT: vpairo.vv v15, v9, v13
-; ZVZIP-NEXT: vslideup.vi v9, v13, 1
-; ZVZIP-NEXT: vpairo.vv v13, v10, v14
-; ZVZIP-NEXT: vslideup.vi v10, v14, 1
-; ZVZIP-NEXT: vpairo.vv v14, v8, v12
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-NEXT: vslideup.vi v9, v15, 2
-; ZVZIP-NEXT: vzip.vv v15, v8, v10
-; ZVZIP-NEXT: vslideup.vi v11, v16, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v14, 2
-; ZVZIP-NEXT: vslideup.vi v10, v13, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v11, v11, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-NEXT: vzip.vv v14, v9, v13
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-NEXT: vslidedown.vi v10, v10, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; ZVZIP-NEXT: vzip.vv v14, v9, v11, v0.t
-; ZVZIP-NEXT: vzip.vv v9, v8, v13
; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vzip.vv v9, v8, v10, v0.t
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-NEXT: vzip.vv v8, v11, v15
+; ZVZIP-NEXT: vzip.vv v11, v9, v13
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v15, v12
-; ZVZIP-NEXT: vslideup.vi v15, v9, 4
-; ZVZIP-NEXT: vslideup.vi v12, v14, 4
+; ZVZIP-NEXT: vzip.vv v9, v10, v16
+; ZVZIP-NEXT: vzip.vv v10, v11, v8
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v15, 4
-; ZVZIP-NEXT: vslidedown.vi v10, v12, 4
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 4
+; ZVZIP-NEXT: vslidedown.vi v11, v10, 4
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-NEXT: vzip.vv v12, v9, v10, v0.t
+; ZVZIP-NEXT: vzip.vv v13, v8, v12
+; ZVZIP-NEXT: vzip.vv v8, v9, v10
+; ZVZIP-NEXT: vzip.vv v13, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: vslideup.vi v8, v13, 8
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave8_v16i8_v2i8:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v16, v11, v15
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v15, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v15, v9, v13
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v13, v10, v14
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v14, v8, v12
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v15, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v15, v8, v10
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v16, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v14, 2
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v11, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v9, v13
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v10, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v9, v11, v0.t
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v13
; ZVZIP-ZVL2048-NEXT: li a0, 170
-; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v10, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
+; ZVZIP-ZVL2048-NEXT: vzip.vv v16, v10, v14
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v12
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v15
+; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v9, v13
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v15, v12
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v15, v9, 4
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v12, v14, 4
+; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v10, v16
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v11, v8
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v15, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v12, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v9, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 4
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v10
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11, v0.t
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v8, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v9, v10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v11, v12, v0.t
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 10, e8, mf8, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v13, 8
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v13, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v13, 4
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 12, e8, mf8, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 10
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 14, e8, mf8, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 12
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 6
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v13, 6
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 14
; ZVZIP-ZVL2048-NEXT: ret
@@ -12869,44 +12628,33 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vector_interleave_v4f16_v2f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f16_v2f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vpairo.vv v11, v8, v9
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
ret <4 x half> %res
@@ -12915,44 +12663,33 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v4bf16_v2bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
-; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vpairo.vv v11, v8, v9
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x bfloat> @llvm.vector.interleave2.v4bf16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <4 x bfloat> %res
@@ -12961,73 +12698,32 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vector_interleave_v8f16_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: vslidedown.vi v10, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsll.vi v11, v12, 16
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 4
-; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f16_v4f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v10, v8, 2
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v13, v11, 16
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 4
-; ZVBB-NEXT: vmv.v.v v8, v10
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-NEXT: vslidedown.vi v12, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; ZVZIP-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-NEXT: vzip.vv v13, v10, v12, v0.t
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v13, 4
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
@@ -13037,73 +12733,32 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v8bf16_v4bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: vslidedown.vi v10, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v8, 2
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v10
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsll.vi v11, v12, 16
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v13, v11, v0
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v10, v8, 4
-; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v10, v8, 2
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v10
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vwsll.vi v13, v11, 16
-; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVBB-NEXT: vmerge.vvm v9, v12, v13, v0
-; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
-; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v10, v9, 4
-; ZVBB-NEXT: vmv.v.v v8, v10
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-NEXT: vslidedown.vi v12, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; ZVZIP-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-NEXT: vzip.vv v13, v10, v12, v0.t
-; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v13, 4
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
@@ -13113,44 +12768,34 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vector_interleave_v4f32_v2f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v10, a0, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f32_v2f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vwsll.vx v10, v9, a0
+; ZVBB-NEXT: vwaddu.wv v10, v10, v8
+; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vpairo.vv v11, v8, v9
-; ZVZIP-NEXT: vslideup.vi v10, v9, 1
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-ZVL2048-NEXT: vmv.v.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
@@ -13159,77 +12804,35 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: vector_interleave_v16f16_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v10, v13, 16
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16f16_v8f16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: li a0, 170
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vslidedown.vi v8, v8, 4
-; ZVBB-NEXT: vslidedown.vi v11, v9, 4
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v9, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 4
-; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v8, v13
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: li a0, 170
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 4
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 8
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
@@ -13239,77 +12842,35 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; CHECK-LABEL: vector_interleave_v16bf16_v8bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: li a0, 170
-; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vslidedown.vi v8, v8, 4
-; CHECK-NEXT: vslidedown.vi v11, v9, 4
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vzext.vf2 v13, v11
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsll.vi v10, v13, 16
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 8
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: li a0, 170
-; ZVBB-NEXT: vmv.s.x v0, a0
-; ZVBB-NEXT: vslidedown.vi v8, v8, 4
-; ZVBB-NEXT: vslidedown.vi v11, v9, 4
-; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v9, 16
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vi v9, v11, 16
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 8
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: vwsll.vi v8, v10, 16
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: li a0, 170
-; ZVZIP-NEXT: vmv.s.x v0, a0
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 4
-; ZVZIP-NEXT: vslidedown.vi v11, v9, 4
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v8, v13
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: li a0, 170
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.s.x v0, a0
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 4
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf2, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 8
; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x bfloat> @llvm.vector.interleave2.v16bf16(<8 x bfloat> %a, <8 x bfloat> %b)
@@ -13319,76 +12880,37 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: vector_interleave_v8f32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v8
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
-; CHECK-NEXT: vslidedown.vi v11, v10, 2
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v12, v8
-; CHECK-NEXT: vmv.v.i v0, 10
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwaddu.vv v8, v10, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vsll.vx v10, v12, a0
-; CHECK-NEXT: vzext.vf2 v12, v11
-; CHECK-NEXT: li a0, -1
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vwmaccu.vx v8, a0, v9
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v8
+; CHECK-NEXT: vwaddu.vv v8, v11, v10
+; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f32_v4f32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVBB-NEXT: vmv1r.v v10, v8
-; ZVBB-NEXT: vslidedown.vi v8, v8, 2
-; ZVBB-NEXT: vmv.v.i v0, 10
-; ZVBB-NEXT: vslidedown.vi v11, v9, 2
-; ZVBB-NEXT: li a0, 32
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVBB-NEXT: vzext.vf2 v12, v8
-; ZVBB-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vwsll.vx v8, v9, a0
-; ZVBB-NEXT: vwaddu.wv v8, v8, v10
-; ZVBB-NEXT: vwsll.vx v9, v11, a0
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVBB-NEXT: vmerge.vvm v10, v12, v9, v0
-; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVBB-NEXT: vslideup.vi v8, v10, 4
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v11, v8
+; ZVBB-NEXT: li a0, 32
+; ZVBB-NEXT: vwsll.vx v8, v10, a0
+; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v11, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v8, v13
-; ZVZIP-NEXT: vzip.vv v8, v10, v9
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v11
-; ZVZIP-ZVL2048-NEXT: vzip.vv v13, v10, v12, v0.t
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 4
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vmv.v.v v8, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
@@ -13397,43 +12919,48 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: vector_interleave_v4f64_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 1
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vslideup.vi v8, v10, 2
+; CHECK-NEXT: lui a0, 12304
+; CHECK-NEXT: addi a0, a0, 512
+; CHECK-NEXT: vmv.s.x v10, a0
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vsext.vf2 v12, v10
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f64_v2f64:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; ZVBB-NEXT: vmv.v.i v0, 1
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vslidedown.vi v10, v8, 1, v0.t
-; ZVBB-NEXT: vslideup.vi v8, v9, 1
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vslideup.vi v8, v10, 2
+; ZVBB-NEXT: lui a0, 12304
+; ZVBB-NEXT: addi a0, a0, 512
+; ZVBB-NEXT: vmv.s.x v10, a0
+; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVBB-NEXT: vsext.vf2 v12, v10
+; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v8
-; ZVZIP-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-NEXT: vpairo.vv v12, v10, v9
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vzip.vv v8, v11, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 1
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v10, v9
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v11, v8
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v10
; ZVZIP-ZVL2048-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
@@ -13544,60 +13071,45 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
;
; ZVZIP-LABEL: vector_interleave4_v8f32_v2f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v12, v9
-; ZVZIP-NEXT: vmv1r.v v13, v8
-; ZVZIP-NEXT: vslideup.vi v12, v11, 1
-; ZVZIP-NEXT: vslideup.vi v13, v10, 1
-; ZVZIP-NEXT: vpairo.vv v14, v8, v10
-; ZVZIP-NEXT: vpairo.vv v10, v9, v11
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v13, v12
-; ZVZIP-NEXT: vslideup.vi v13, v14, 2
-; ZVZIP-NEXT: vslideup.vi v12, v10, 2
+; ZVZIP-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-NEXT: vzip.vv v13, v9, v11
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
+; ZVZIP-NEXT: vslidedown.vi v8, v12, 2
; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-NEXT: vzip.vv v10, v9, v12
-; ZVZIP-NEXT: vzip.vv v10, v9, v11, v0.t
+; ZVZIP-NEXT: vzip.vv v10, v8, v11
+; ZVZIP-NEXT: vzip.vv v8, v12, v13
+; ZVZIP-NEXT: vzip.vv v10, v11, v9, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave4_v8f32_v2f32:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v9, v11
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v12, v10
+; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v11
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v10, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v10, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 2
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v8, v9, v0.t
+; ZVZIP-ZVL2048-NEXT: vzip.vv v12, v9, v10, v0.t
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 4
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 4
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v8, 6
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v8, v10
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 6
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
ret <8 x float> %res
@@ -14414,63 +13926,56 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
;
; ZVZIP-LABEL: vector_interleave8_v8f16_v1f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslideup.vi v11, v15, 1
-; ZVZIP-NEXT: vslideup.vi v9, v13, 1
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: vmv1r.v v12, v9
-; ZVZIP-NEXT: vslideup.vi v10, v14, 1
-; ZVZIP-NEXT: vmv1r.v v13, v8
-; ZVZIP-NEXT: vslideup.vi v12, v11, 1
-; ZVZIP-NEXT: vslideup.vi v13, v10, 1
-; ZVZIP-NEXT: vpairo.vv v14, v8, v10
-; ZVZIP-NEXT: vpairo.vv v10, v9, v11
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-NEXT: vslideup.vi v9, v13, 2
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v13, v12
-; ZVZIP-NEXT: vslideup.vi v13, v14, 2
-; ZVZIP-NEXT: vslideup.vi v12, v10, 2
+; ZVZIP-NEXT: vslideup.vi v8, v14, 3
+; ZVZIP-NEXT: vslideup.vi v9, v15, 3
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
-; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 2
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v9, v10
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
+; ZVZIP-NEXT: vzip.vv v13, v10, v12
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vzip.vv v13, v8, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vslideup.vi v10, v13, 4
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave8_v8f16_v1f16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v15, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 2
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v15, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v14, 3
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v13, v10
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v11, v10
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 1
; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v13, v10, 2
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v11, 1
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 1
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v8, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v8, v12
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v13, 3
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v11, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v11, v9, v0.t
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
@@ -14517,63 +14022,56 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
;
; ZVZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vslideup.vi v11, v15, 1
-; ZVZIP-NEXT: vslideup.vi v9, v13, 1
-; ZVZIP-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-NEXT: vmv1r.v v12, v9
-; ZVZIP-NEXT: vslideup.vi v10, v14, 1
-; ZVZIP-NEXT: vmv1r.v v13, v8
-; ZVZIP-NEXT: vslideup.vi v12, v11, 1
-; ZVZIP-NEXT: vslideup.vi v13, v10, 1
-; ZVZIP-NEXT: vpairo.vv v14, v8, v10
-; ZVZIP-NEXT: vpairo.vv v10, v9, v11
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-NEXT: vslideup.vi v9, v11, 1
+; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-NEXT: vslideup.vi v9, v13, 2
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-NEXT: vzip.vv v8, v13, v12
-; ZVZIP-NEXT: vslideup.vi v13, v14, 2
-; ZVZIP-NEXT: vslideup.vi v12, v10, 2
+; ZVZIP-NEXT: vslideup.vi v8, v14, 3
+; ZVZIP-NEXT: vslideup.vi v9, v15, 3
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v9, v13, 2
-; ZVZIP-NEXT: vslidedown.vi v11, v12, 2
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v11, v9, 2
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
-; ZVZIP-NEXT: vzip.vv v12, v9, v10
-; ZVZIP-NEXT: vzip.vv v12, v9, v11, v0.t
+; ZVZIP-NEXT: vzip.vv v13, v10, v12
+; ZVZIP-NEXT: vzip.vv v10, v8, v9
+; ZVZIP-NEXT: vzip.vv v13, v8, v11, v0.t
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vslideup.vi v10, v13, 4
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
;
; ZVZIP-ZVL2048-LABEL: vector_interleave8_v8bf16_v1bf16:
; ZVZIP-ZVL2048: # %bb.0:
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vmv.v.i v0, 10
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v11, v15, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v14, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v12, v9, v11
; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v11, 1
-; ZVZIP-ZVL2048-NEXT: vpairo.vv v11, v8, v10
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v13, 2
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v15, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v14, 3
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-ZVL2048-NEXT: vmv1r.v v13, v10
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 1
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v9, v12, 2
+; ZVZIP-ZVL2048-NEXT: vmv1r.v v11, v10
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 1
; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v8, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v12, v10, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v13, v10, 2
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v11, 1
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 1
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v8, v11
+; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v8, v12
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 3, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v13, 3
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v12, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v8, v11, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v10, v13, 2
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; ZVZIP-ZVL2048-NEXT: vzip.vv v14, v11, v9, v0.t
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e16, mf4, tu, ma
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