[llvm] [AMDGPU] Legalize uniform 16-bit loads to match subword load instructions (PR #225097)

[via llvm-commits]

LU-JOHN wrote:

> > > Should uniform 16-bit loads get legalized to extloads, since there are no SMEM load instructions that actually write a 16-bit result?
> > 
> > 
> > Yes, that is how I would expect this to work (easier said than done for SelectionDAG though)
> 
> Legalized uniform 16-bit loads to use extloads. Generated code is better than that generated with tablegen patterns. Redundant AND masks are eliminated and better sign-extension is generated. See constant_zextload_i16_to_i64 and constant_sextload_i16_to_i64 in load-constant-i16.ll for examples.

@jayfoad @arsenm ping

https://github.com/llvm/llvm-project/pull/225097