[llvm] [TableGen][AMDGPU] Introduce register sequences (PR #226106)

[Shilei Tian via llvm-commits]

shiltian wrote:

This probably needs an RFC.

How does it interact with sub register and a tuple? Is this purely an "alias" of the corresponding register tuple? From the PR description, I can't find this sort of information.

Can we have some more positive and negative tests as well in terms of the representation itself, such as`$sgpr_0_3_2`?

https://github.com/llvm/llvm-project/pull/226106