[llvm] [AMDGPU] Correct bidirectional pending-candidate arbitration (PR #226156)

via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 24 06:14:01 PDT 2026


llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Alan Li (lialan)

<details>
<summary>Changes</summary>

## Summary
- Pass the actual opposing candidate (`TryCand`) to `tryPendingCandidate`. The current call compares the top candidate with itself when the bottom candidate is pending, so the bottom candidate cannot win the cross-boundary comparison.
- Refresh queue membership for reused candidates and set `PickedPending` from the selected node, so pending-cycle and hazard handling follow the winner.
- Keep this scheduler correctness fix separate from the occupancy-policy changes in #<!-- -->220975.

## Tests
- Add two MIR regressions: a pending bottom PhysReg COPY must beat the top candidate, and `-verify-misched` must not change the schedule through stale cached pending state. Both fail on the original unmodified base (`03fb86920dc0`) and pass with this fix.
- Update five scheduling-sensitive fixtures for the changed instruction order while retaining their semantic assertions.
- On rebased `upstream/main` (`0d7414aec9d6`), `check-llvm-codegen-amdgpu` passed: 5,081 passed, 6 expected failures, 1 unsupported.

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Full diff: https://github.com/llvm/llvm-project/pull/226156.diff


8 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp (+6-2) 
- (modified) llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll (+5-3) 
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll (+6-476) 
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-mfma-single-exit-copy.ll (+15-527) 
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir (+2) 
- (modified) llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll (+2) 
- (added) llvm/test/CodeGen/AMDGPU/schedule-pending-bidirectional-cache.mir (+32) 
- (added) llvm/test/CodeGen/AMDGPU/schedule-pending-bidirectional-physreg.mir (+33) 


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https://github.com/llvm/llvm-project/pull/226156


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