[llvm] [ARM] Lower vector interleave operations (PR #225670)
Kamlesh Kumar via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 06:12:24 PDT 2026
https://github.com/kamleshbhalui updated https://github.com/llvm/llvm-project/pull/225670
>From 0125d143bf337106f9101c9539b9865e54d28453 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Wed, 23 Sep 2026 10:20:08 +0000
Subject: [PATCH 1/2] [ARM] Lower vector interleave operations
Adding support for lowering of vector_interleave
and vector_deinterleave operations.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 103 +
.../CodeGen/ARM/fixed-vector-deinterleave.ll | 3675 +++++++++++++++++
.../CodeGen/ARM/fixed-vector-interleave.ll | 2444 +++++++++++
3 files changed, 6222 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll
create mode 100644 llvm/test/CodeGen/ARM/fixed-vector-interleave.ll
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 194b597bc77ba..7f5a8d1547703 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -198,6 +198,8 @@ void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
}
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+ setVectorInterleaveAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
+ {2, 3, 4}, VT, Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
setOperationAction(ISD::SELECT, VT, Expand);
@@ -9067,6 +9069,103 @@ static SDValue LowerCONCAT_VECTORS_i1(SDValue Op, SelectionDAG &DAG,
return ConcatOps[0];
}
+static SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) {
+ if (!ST->hasNEON())
+ return SDValue();
+ unsigned Factor = Op->getNumOperands();
+ EVT OpVT = Op.getValueType();
+ SDLoc DL(Op);
+
+ if (Factor == 2) {
+ SDValue Zip = DAG.getNode(ARMISD::VZIP, DL, DAG.getVTList(OpVT, OpVT),
+ Op.getOperand(0), Op.getOperand(1));
+ return DAG.getMergeValues({Zip, Zip.getValue(1)}, DL);
+ }
+
+ if (Op->getNumOperands() == 3) {
+ Align Alignment = DAG.getReducedAlign(OpVT, /*UseABI=*/false);
+ SDValue StackPtr =
+ DAG.CreateStackTemporary(OpVT.getStoreSize() * 3, Alignment);
+ MachinePointerInfo StackPtrInfo = MachinePointerInfo::getFixedStack(
+ DAG.getMachineFunction(), cast<FrameIndexSDNode>(StackPtr)->getIndex());
+ SmallVector<SDValue, 6> Ops;
+ Ops.push_back(DAG.getEntryNode());
+ Ops.push_back(
+ DAG.getTargetConstant(Intrinsic::arm_neon_vst3, DL, MVT::i64));
+ Ops.push_back(StackPtr);
+
+ for (SDValue V : Op->ops())
+ Ops.push_back(V);
+ Ops.push_back(DAG.getConstant(Alignment.value(), DL, MVT::i32));
+ EVT TripleOpVT =
+ EVT::getVectorVT(*DAG.getContext(), OpVT.getVectorElementType(),
+ OpVT.getVectorNumElements() * 3);
+ SDValue Chain = DAG.getMemIntrinsicNode(
+ ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops, TripleOpVT,
+ StackPtrInfo, Alignment, MachineMemOperand::MOStore);
+
+ SmallVector<SDValue, 3> Results;
+ for (unsigned I = 0; I < 3; ++I) {
+ SDValue Ptr =
+ DAG.getMemBasePlusOffset(StackPtr, OpVT.getStoreSize() * I, DL);
+ Results.push_back(
+ DAG.getLoad(OpVT, DL, Chain, Ptr, MachinePointerInfo()));
+ }
+ return DAG.getMergeValues(Results, DL);
+ }
+
+ return SDValue();
+}
+
+static SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) {
+ if (!ST->hasNEON())
+ return SDValue();
+ unsigned Factor = Op->getNumOperands();
+ EVT OpVT = Op.getValueType();
+ SDLoc DL(Op);
+
+ if (Factor == 2) {
+ SDValue Unzip = DAG.getNode(ARMISD::VUZP, DL, DAG.getVTList(OpVT, OpVT),
+ Op.getOperand(0), Op.getOperand(1));
+ return DAG.getMergeValues({Unzip, Unzip.getValue(1)}, DL);
+ }
+
+ if (Op->getNumOperands() == 3) {
+ Align Alignment = DAG.getReducedAlign(OpVT, /*UseABI=*/false);
+ SDValue StackPtr =
+ DAG.CreateStackTemporary(OpVT.getStoreSize() * 3, Alignment);
+
+ SmallVector<SDValue, 3> Chains;
+ for (unsigned I = 0; I < 3; ++I) {
+ SDValue Ptr =
+ DAG.getMemBasePlusOffset(StackPtr, OpVT.getStoreSize() * I, DL);
+ Chains.push_back(DAG.getStore(DAG.getEntryNode(), DL, Op.getOperand(I),
+ Ptr, MachinePointerInfo()));
+ }
+
+ SmallVector<SDValue, 3> Ops;
+ Ops.push_back(DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains));
+ Ops.push_back(
+ DAG.getTargetConstant(Intrinsic::arm_neon_vld3, DL, MVT::i64));
+ Ops.push_back(StackPtr);
+
+ EVT TripleOpVT =
+ EVT::getVectorVT(*DAG.getContext(), OpVT.getVectorElementType(),
+ OpVT.getVectorNumElements() * 3);
+ SDVTList VTs = DAG.getVTList(OpVT, OpVT, OpVT, MVT::Other);
+ SDValue LD3 = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops,
+ TripleOpVT, MachinePointerInfo(),
+ Alignment, MachineMemOperand::MOLoad);
+
+ return DAG.getMergeValues(
+ {LD3.getValue(0), LD3.getValue(1), LD3.getValue(2)}, DL);
+ }
+
+ return SDValue();
+}
+
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
EVT VT = Op->getValueType(0);
@@ -10589,6 +10688,10 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG, Subtarget);
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget);
+ case ISD::VECTOR_INTERLEAVE:
+ return LowerVECTOR_INTERLEAVE(Op, DAG, Subtarget);
+ case ISD::VECTOR_DEINTERLEAVE:
+ return LowerVECTOR_DEINTERLEAVE(Op, DAG, Subtarget);
case ISD::TRUNCATE: return LowerTruncate(Op.getNode(), DAG, Subtarget);
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND: return LowerVectorExtend(Op.getNode(), DAG, Subtarget);
diff --git a/llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll
new file mode 100644
index 0000000000000..ee7da511d1c60
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll
@@ -0,0 +1,3675 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
+; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
+
+define void @deinterleave2_v8i8(<16 x i8> %vec) {
+; CHECK-LABEL: deinterleave2_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vuzp.8 d17, d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i8>, <8 x i8> } @llvm.vector.deinterleave2(<16 x i8> %vec)
+ %result0 = extractvalue { <8 x i8>, <8 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i8> %result0)
+ %result1 = extractvalue { <8 x i8>, <8 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i8> %result1)
+ ret void
+}
+
+define void @deinterleave3_v8i8(<24 x i8> %vec) {
+; CHECK-LABEL: deinterleave3_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: add r12, sp, #72
+; CHECK-NEXT: vmov.8 d18[0], r0
+; CHECK-NEXT: add r0, sp, #80
+; CHECK-NEXT: vld1.8 {d16[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #40
+; CHECK-NEXT: vld1.8 {d17[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #76
+; CHECK-NEXT: vld1.8 {d16[1]}, [r12]
+; CHECK-NEXT: add r12, sp, #44
+; CHECK-NEXT: vld1.8 {d17[1]}, [r12]
+; CHECK-NEXT: vld1.8 {d16[2]}, [r0]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vld1.8 {d17[2]}, [r0]
+; CHECK-NEXT: add r0, sp, #84
+; CHECK-NEXT: vld1.8 {d16[3]}, [r0]
+; CHECK-NEXT: add r0, sp, #52
+; CHECK-NEXT: vld1.8 {d17[3]}, [r0]
+; CHECK-NEXT: add r0, sp, #24
+; CHECK-NEXT: vmov.8 d18[1], r1
+; CHECK-NEXT: vmov.8 d18[2], r2
+; CHECK-NEXT: vmov.8 d18[3], r3
+; CHECK-NEXT: vld1.8 {d18[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #88
+; CHECK-NEXT: vld1.8 {d16[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #56
+; CHECK-NEXT: vld1.8 {d17[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #28
+; CHECK-NEXT: vld1.8 {d18[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #92
+; CHECK-NEXT: vld1.8 {d16[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #60
+; CHECK-NEXT: vld1.8 {d17[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vld1.8 {d18[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #96
+; CHECK-NEXT: vld1.8 {d16[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #64
+; CHECK-NEXT: vld1.8 {d17[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #36
+; CHECK-NEXT: vld1.8 {d18[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #100
+; CHECK-NEXT: vld1.8 {d16[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #68
+; CHECK-NEXT: vld1.8 {d17[7]}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vstr d18, [sp]
+; CHECK-NEXT: vstr d16, [sp, #16]
+; CHECK-NEXT: vstr d17, [sp, #8]
+; CHECK-NEXT: vld3.8 {d16, d17, d18}, [r0:64]
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.vector.deinterleave3(<24 x i8> %vec)
+ %result0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i8> %result0)
+ %result1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i8> %result1)
+ %result2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i8> %result2)
+ ret void
+}
+
+define void @deinterleave4_v8i8(<32 x i8> %vec) {
+; CHECK-LABEL: deinterleave4_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vorr d20, d18, d18
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vuzp.8 d20, d19
+; CHECK-NEXT: vuzp.8 d17, d16
+; CHECK-NEXT: vuzp.8 d16, d19
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: vuzp.8 d17, d20
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.vector.deinterleave4(<32 x i8> %vec)
+ %result0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i8> %result0)
+ %result1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i8> %result1)
+ %result2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i8> %result2)
+ %result3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 3
+ call void (...) @llvm.fake.use(<8 x i8> %result3)
+ ret void
+}
+
+define void @deinterleave6_v8i8(<48 x i8> %vec) {
+; CHECK-LABEL: deinterleave6_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: add r12, sp, #192
+; CHECK-NEXT: vmov.8 d21[0], r0
+; CHECK-NEXT: add r0, sp, #76
+; CHECK-NEXT: vld1.8 {d16[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #160
+; CHECK-NEXT: vld1.8 {d18[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #128
+; CHECK-NEXT: vld1.8 {d20[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #96
+; CHECK-NEXT: vld1.8 {d17[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #64
+; CHECK-NEXT: vld1.8 {d19[0]}, [r12]
+; CHECK-NEXT: add r12, sp, #196
+; CHECK-NEXT: vld1.8 {d16[1]}, [r12]
+; CHECK-NEXT: add r12, sp, #164
+; CHECK-NEXT: vld1.8 {d18[1]}, [r12]
+; CHECK-NEXT: add r12, sp, #132
+; CHECK-NEXT: vld1.8 {d20[1]}, [r12]
+; CHECK-NEXT: add r12, sp, #100
+; CHECK-NEXT: vld1.8 {d17[1]}, [r12]
+; CHECK-NEXT: add r12, sp, #68
+; CHECK-NEXT: vld1.8 {d19[1]}, [r12]
+; CHECK-NEXT: add r12, sp, #200
+; CHECK-NEXT: vld1.8 {d16[2]}, [r12]
+; CHECK-NEXT: add r12, sp, #168
+; CHECK-NEXT: vld1.8 {d18[2]}, [r12]
+; CHECK-NEXT: add r12, sp, #136
+; CHECK-NEXT: vld1.8 {d20[2]}, [r12]
+; CHECK-NEXT: add r12, sp, #104
+; CHECK-NEXT: vld1.8 {d17[2]}, [r12]
+; CHECK-NEXT: add r12, sp, #72
+; CHECK-NEXT: vld1.8 {d19[2]}, [r12]
+; CHECK-NEXT: add r12, sp, #204
+; CHECK-NEXT: vld1.8 {d16[3]}, [r12]
+; CHECK-NEXT: add r12, sp, #172
+; CHECK-NEXT: vld1.8 {d19[3]}, [r0]
+; CHECK-NEXT: add r0, sp, #208
+; CHECK-NEXT: vld1.8 {d18[3]}, [r12]
+; CHECK-NEXT: add r12, sp, #140
+; CHECK-NEXT: vld1.8 {d16[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #176
+; CHECK-NEXT: vld1.8 {d20[3]}, [r12]
+; CHECK-NEXT: add r12, sp, #108
+; CHECK-NEXT: vld1.8 {d18[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #144
+; CHECK-NEXT: vld1.8 {d20[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vld1.8 {d17[3]}, [r12]
+; CHECK-NEXT: vmov.8 d21[1], r1
+; CHECK-NEXT: vmov.8 d21[2], r2
+; CHECK-NEXT: vmov.8 d21[3], r3
+; CHECK-NEXT: vld1.8 {d21[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #112
+; CHECK-NEXT: vld1.8 {d17[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #80
+; CHECK-NEXT: vld1.8 {d19[4]}, [r0]
+; CHECK-NEXT: add r0, sp, #212
+; CHECK-NEXT: vld1.8 {d16[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #180
+; CHECK-NEXT: vld1.8 {d18[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #148
+; CHECK-NEXT: vld1.8 {d20[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #52
+; CHECK-NEXT: vld1.8 {d21[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #116
+; CHECK-NEXT: vld1.8 {d17[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #84
+; CHECK-NEXT: vld1.8 {d19[5]}, [r0]
+; CHECK-NEXT: add r0, sp, #216
+; CHECK-NEXT: vld1.8 {d16[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #184
+; CHECK-NEXT: vld1.8 {d18[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #152
+; CHECK-NEXT: vld1.8 {d20[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #56
+; CHECK-NEXT: vld1.8 {d21[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #120
+; CHECK-NEXT: vld1.8 {d17[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #88
+; CHECK-NEXT: vld1.8 {d19[6]}, [r0]
+; CHECK-NEXT: add r0, sp, #220
+; CHECK-NEXT: vld1.8 {d16[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #188
+; CHECK-NEXT: vld1.8 {d18[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #156
+; CHECK-NEXT: vld1.8 {d20[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #60
+; CHECK-NEXT: vld1.8 {d21[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #124
+; CHECK-NEXT: vld1.8 {d17[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #92
+; CHECK-NEXT: vld1.8 {d19[7]}, [r0]
+; CHECK-NEXT: add r0, sp, #24
+; CHECK-NEXT: vstr d16, [sp, #40]
+; CHECK-NEXT: vstr d18, [sp, #32]
+; CHECK-NEXT: vstr d20, [sp, #24]
+; CHECK-NEXT: vld3.8 {d22, d23, d24}, [r0:64]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vorr d20, d22, d22
+; CHECK-NEXT: vorr d26, d23, d23
+; CHECK-NEXT: vstr d21, [sp]
+; CHECK-NEXT: vstr d17, [sp, #16]
+; CHECK-NEXT: vstr d19, [sp, #8]
+; CHECK-NEXT: vld3.8 {d16, d17, d18}, [r0:64]
+; CHECK-NEXT: vorr d21, d16, d16
+; CHECK-NEXT: vorr d27, d17, d17
+; CHECK-NEXT: vuzp.8 d18, d24
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: vuzp.8 d21, d20
+; CHECK-NEXT: @ fake_use: $d21
+; CHECK-NEXT: vuzp.8 d27, d26
+; CHECK-NEXT: @ fake_use: $d27
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: @ fake_use: $d24 $q11_q12
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.vector.deinterleave6(<48 x i8> %vec)
+ %result0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i8> %result0)
+ %result1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i8> %result1)
+ %result2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i8> %result2)
+ %result3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 3
+ call void (...) @llvm.fake.use(<8 x i8> %result3)
+ %result4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 4
+ call void (...) @llvm.fake.use(<8 x i8> %result4)
+ %result5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 5
+ call void (...) @llvm.fake.use(<8 x i8> %result5)
+ ret void
+}
+
+define void @deinterleave8_v8i8(<64 x i8> %vec) {
+; CHECK-LABEL: deinterleave8_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vorr d25, d16, d16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vorr d26, d18, d18
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: vmov d23, r0, r1
+; CHECK-NEXT: vorr d24, d20, d20
+; CHECK-NEXT: vuzp.8 d25, d17
+; CHECK-NEXT: vuzp.8 d23, d22
+; CHECK-NEXT: vuzp.8 d24, d21
+; CHECK-NEXT: vuzp.8 d26, d19
+; CHECK-NEXT: vuzp.8 d25, d24
+; CHECK-NEXT: vuzp.8 d23, d26
+; CHECK-NEXT: vuzp.8 d17, d21
+; CHECK-NEXT: vuzp.8 d22, d19
+; CHECK-NEXT: vuzp.8 d23, d25
+; CHECK-NEXT: @ fake_use: $d23
+; CHECK-NEXT: vuzp.8 d19, d21
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: vuzp.8 d22, d17
+; CHECK-NEXT: @ fake_use: $d22
+; CHECK-NEXT: vuzp.8 d26, d24
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: @ fake_use: $d25
+; CHECK-NEXT: @ fake_use: $d17 $q8
+; CHECK-NEXT: @ fake_use: $d24
+; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.vector.deinterleave8(<64 x i8> %vec)
+ %result0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i8> %result0)
+ %result1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i8> %result1)
+ %result2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i8> %result2)
+ %result3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 3
+ call void (...) @llvm.fake.use(<8 x i8> %result3)
+ %result4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 4
+ call void (...) @llvm.fake.use(<8 x i8> %result4)
+ %result5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 5
+ call void (...) @llvm.fake.use(<8 x i8> %result5)
+ %result6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 6
+ call void (...) @llvm.fake.use(<8 x i8> %result6)
+ %result7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 7
+ call void (...) @llvm.fake.use(<8 x i8> %result7)
+ ret void
+}
+
+define void @deinterleave2_v4i16(<8 x i16> %vec) {
+; CHECK-LABEL: deinterleave2_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vuzp.16 d17, d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i16>, <4 x i16> } @llvm.vector.deinterleave2(<8 x i16> %vec)
+ %result0 = extractvalue { <4 x i16>, <4 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i16> %result0)
+ %result1 = extractvalue { <4 x i16>, <4 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i16> %result1)
+ ret void
+}
+
+define void @deinterleave3_v4i16(<12 x i16> %vec) {
+; CHECK-LABEL: deinterleave3_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: add r12, sp, #40
+; CHECK-NEXT: vmov.16 d18[0], r0
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vld1.16 {d16[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: vld1.16 {d17[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #44
+; CHECK-NEXT: vld1.16 {d16[1]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #28
+; CHECK-NEXT: vld1.16 {d17[1]}, [r12:16]
+; CHECK-NEXT: vld1.16 {d16[2]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vld1.16 {d17[2]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #52
+; CHECK-NEXT: vld1.16 {d16[3]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #36
+; CHECK-NEXT: vld1.16 {d17[3]}, [r0:16]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov.16 d18[1], r1
+; CHECK-NEXT: vstr d16, [sp, #16]
+; CHECK-NEXT: vmov.16 d18[2], r2
+; CHECK-NEXT: vstr d17, [sp, #8]
+; CHECK-NEXT: vmov.16 d18[3], r3
+; CHECK-NEXT: vstr d18, [sp]
+; CHECK-NEXT: vld3.16 {d16, d17, d18}, [r0:64]
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.vector.deinterleave3(<12 x i16> %vec)
+ %result0 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i16> %result0)
+ %result1 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i16> %result1)
+ %result2 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i16> %result2)
+ ret void
+}
+
+define void @deinterleave4_v4i16(<16 x i16> %vec) {
+; CHECK-LABEL: deinterleave4_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vorr d20, d18, d18
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vuzp.16 d20, d19
+; CHECK-NEXT: vuzp.16 d17, d16
+; CHECK-NEXT: vuzp.16 d16, d19
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: vuzp.16 d17, d20
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.vector.deinterleave4(<16 x i16> %vec)
+ %result0 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i16> %result0)
+ %result1 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i16> %result1)
+ %result2 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i16> %result2)
+ %result3 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 3
+ call void (...) @llvm.fake.use(<4 x i16> %result3)
+ ret void
+}
+
+define void @deinterleave6_v4i16(<24 x i16> %vec) {
+; CHECK-LABEL: deinterleave6_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: add r12, sp, #112
+; CHECK-NEXT: vmov.16 d21[0], r0
+; CHECK-NEXT: add r0, sp, #108
+; CHECK-NEXT: vld1.16 {d16[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #96
+; CHECK-NEXT: vld1.16 {d17[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #80
+; CHECK-NEXT: vld1.16 {d18[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #64
+; CHECK-NEXT: vld1.16 {d19[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: vld1.16 {d20[0]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #116
+; CHECK-NEXT: vld1.16 {d16[1]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #100
+; CHECK-NEXT: vld1.16 {d17[1]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #84
+; CHECK-NEXT: vld1.16 {d18[1]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #68
+; CHECK-NEXT: vld1.16 {d19[1]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #52
+; CHECK-NEXT: vld1.16 {d20[1]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #120
+; CHECK-NEXT: vld1.16 {d16[2]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #104
+; CHECK-NEXT: vld1.16 {d17[2]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #88
+; CHECK-NEXT: vld1.16 {d18[2]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #72
+; CHECK-NEXT: vld1.16 {d17[3]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #92
+; CHECK-NEXT: vld1.16 {d19[2]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #56
+; CHECK-NEXT: vld1.16 {d18[3]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #76
+; CHECK-NEXT: vld1.16 {d20[2]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #124
+; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #60
+; CHECK-NEXT: vld1.16 {d16[3]}, [r12:16]
+; CHECK-NEXT: vld1.16 {d20[3]}, [r0:16]
+; CHECK-NEXT: add r0, sp, #24
+; CHECK-NEXT: vmov.16 d21[1], r1
+; CHECK-NEXT: vstr d16, [sp, #40]
+; CHECK-NEXT: vmov.16 d21[2], r2
+; CHECK-NEXT: vstr d17, [sp, #32]
+; CHECK-NEXT: vmov.16 d21[3], r3
+; CHECK-NEXT: vstr d18, [sp, #24]
+; CHECK-NEXT: vld3.16 {d22, d23, d24}, [r0:64]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vorr d26, d23, d23
+; CHECK-NEXT: vstr d20, [sp, #8]
+; CHECK-NEXT: vorr d20, d22, d22
+; CHECK-NEXT: vstr d21, [sp]
+; CHECK-NEXT: vstr d19, [sp, #16]
+; CHECK-NEXT: vld3.16 {d16, d17, d18}, [r0:64]
+; CHECK-NEXT: vorr d21, d16, d16
+; CHECK-NEXT: vorr d27, d17, d17
+; CHECK-NEXT: vuzp.16 d18, d24
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: vuzp.16 d21, d20
+; CHECK-NEXT: @ fake_use: $d21
+; CHECK-NEXT: vuzp.16 d27, d26
+; CHECK-NEXT: @ fake_use: $d27
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: @ fake_use: $d24 $q11_q12
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.vector.deinterleave6(<24 x i16> %vec)
+ %result0 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i16> %result0)
+ %result1 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i16> %result1)
+ %result2 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i16> %result2)
+ %result3 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 3
+ call void (...) @llvm.fake.use(<4 x i16> %result3)
+ %result4 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 4
+ call void (...) @llvm.fake.use(<4 x i16> %result4)
+ %result5 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 5
+ call void (...) @llvm.fake.use(<4 x i16> %result5)
+ ret void
+}
+
+define void @deinterleave8_v4i16(<32 x i16> %vec) {
+; CHECK-LABEL: deinterleave8_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vorr d25, d16, d16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vorr d26, d18, d18
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: vmov d23, r0, r1
+; CHECK-NEXT: vorr d24, d20, d20
+; CHECK-NEXT: vuzp.16 d25, d17
+; CHECK-NEXT: vuzp.16 d23, d22
+; CHECK-NEXT: vuzp.16 d24, d21
+; CHECK-NEXT: vuzp.16 d26, d19
+; CHECK-NEXT: vuzp.16 d25, d24
+; CHECK-NEXT: vuzp.16 d23, d26
+; CHECK-NEXT: vuzp.16 d17, d21
+; CHECK-NEXT: vuzp.16 d22, d19
+; CHECK-NEXT: vuzp.16 d23, d25
+; CHECK-NEXT: @ fake_use: $d23
+; CHECK-NEXT: vuzp.16 d19, d21
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: vuzp.16 d22, d17
+; CHECK-NEXT: @ fake_use: $d22
+; CHECK-NEXT: vuzp.16 d26, d24
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: @ fake_use: $d25
+; CHECK-NEXT: @ fake_use: $d17 $q8
+; CHECK-NEXT: @ fake_use: $d24
+; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.vector.deinterleave8(<32 x i16> %vec)
+ %result0 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i16> %result0)
+ %result1 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i16> %result1)
+ %result2 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i16> %result2)
+ %result3 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 3
+ call void (...) @llvm.fake.use(<4 x i16> %result3)
+ %result4 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 4
+ call void (...) @llvm.fake.use(<4 x i16> %result4)
+ %result5 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 5
+ call void (...) @llvm.fake.use(<4 x i16> %result5)
+ %result6 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 6
+ call void (...) @llvm.fake.use(<4 x i16> %result6)
+ %result7 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 7
+ call void (...) @llvm.fake.use(<4 x i16> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v2i32(<4 x i32> %vec) {
+; CHECK-LABEL: deinterleave2_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: bx lr
+ %result = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2(<4 x i32> %vec)
+ %result0 = extractvalue { <2 x i32>, <2 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<2 x i32> %result0)
+ %result1 = extractvalue { <2 x i32>, <2 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<2 x i32> %result1)
+ ret void
+}
+
+define void @deinterleave3_v2i32(<6 x i32> %vec) {
+; CHECK-LABEL: deinterleave3_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: vldr s1, [sp, #28]
+; CHECK-NEXT: vmov s3, r1
+; CHECK-NEXT: vldr s0, [sp, #24]
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov s5, r3
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov s4, r2
+; CHECK-NEXT: vstr d0, [sp, #16]
+; CHECK-NEXT: vstmia sp, {d1, d2}
+; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r0:64]
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave3(<6 x i32> %vec)
+ %result0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<2 x i32> %result0)
+ %result1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<2 x i32> %result1)
+ %result2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<2 x i32> %result2)
+ ret void
+}
+
+define void @deinterleave4_v2i32(<8 x i32> %vec) {
+; CHECK-LABEL: deinterleave4_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vorr d20, d18, d18
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vtrn.32 d20, d19
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: vtrn.32 d16, d19
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: vtrn.32 d17, d20
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: bx lr
+ %result = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4(<8 x i32> %vec)
+ %result0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<2 x i32> %result0)
+ %result1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<2 x i32> %result1)
+ %result2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<2 x i32> %result2)
+ %result3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 3
+ call void (...) @llvm.fake.use(<2 x i32> %result3)
+ ret void
+}
+
+define void @deinterleave6_v2i32(<12 x i32> %vec) {
+; CHECK-LABEL: deinterleave6_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vldr s1, [sp, #76]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: vldr s0, [sp, #72]
+; CHECK-NEXT: vldr s3, [sp, #68]
+; CHECK-NEXT: vldr s5, [sp, #60]
+; CHECK-NEXT: vldr s7, [sp, #52]
+; CHECK-NEXT: vldr s2, [sp, #64]
+; CHECK-NEXT: vldr s4, [sp, #56]
+; CHECK-NEXT: vstr d0, [sp, #40]
+; CHECK-NEXT: vmov s1, r1
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vldr s6, [sp, #48]
+; CHECK-NEXT: vstr d1, [sp, #32]
+; CHECK-NEXT: vmov s3, r3
+; CHECK-NEXT: vstr d2, [sp, #24]
+; CHECK-NEXT: vmov s2, r2
+; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r12:64]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vorr d24, d16, d16
+; CHECK-NEXT: vstr d3, [sp, #16]
+; CHECK-NEXT: vstmia sp, {d0, d1}
+; CHECK-NEXT: vld3.32 {d20, d21, d22}, [r0:64]
+; CHECK-NEXT: vorr d26, d21, d21
+; CHECK-NEXT: vorr d25, d20, d20
+; CHECK-NEXT: vorr d20, d22, d22
+; CHECK-NEXT: vtrn.32 d26, d17
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: vtrn.32 d25, d24
+; CHECK-NEXT: @ fake_use: $d25
+; CHECK-NEXT: vtrn.32 d20, d18
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d24
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave6(<12 x i32> %vec)
+ %result0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<2 x i32> %result0)
+ %result1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<2 x i32> %result1)
+ %result2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<2 x i32> %result2)
+ %result3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 3
+ call void (...) @llvm.fake.use(<2 x i32> %result3)
+ %result4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 4
+ call void (...) @llvm.fake.use(<2 x i32> %result4)
+ %result5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 5
+ call void (...) @llvm.fake.use(<2 x i32> %result5)
+ ret void
+}
+
+define void @deinterleave8_v2i32(<16 x i32> %vec) {
+; CHECK-LABEL: deinterleave8_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vorr d25, d16, d16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vorr d26, d18, d18
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: vmov d23, r0, r1
+; CHECK-NEXT: vorr d24, d20, d20
+; CHECK-NEXT: vtrn.32 d25, d17
+; CHECK-NEXT: vtrn.32 d23, d22
+; CHECK-NEXT: vtrn.32 d24, d21
+; CHECK-NEXT: vtrn.32 d26, d19
+; CHECK-NEXT: vtrn.32 d25, d24
+; CHECK-NEXT: vtrn.32 d23, d26
+; CHECK-NEXT: vtrn.32 d17, d21
+; CHECK-NEXT: vtrn.32 d22, d19
+; CHECK-NEXT: vtrn.32 d23, d25
+; CHECK-NEXT: @ fake_use: $d23
+; CHECK-NEXT: vtrn.32 d19, d21
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: vtrn.32 d22, d17
+; CHECK-NEXT: @ fake_use: $d22
+; CHECK-NEXT: vtrn.32 d26, d24
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: @ fake_use: $d25
+; CHECK-NEXT: @ fake_use: $d17 $q8
+; CHECK-NEXT: @ fake_use: $d24
+; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: bx lr
+ %result = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8(<16 x i32> %vec)
+ %result0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<2 x i32> %result0)
+ %result1 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<2 x i32> %result1)
+ %result2 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<2 x i32> %result2)
+ %result3 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 3
+ call void (...) @llvm.fake.use(<2 x i32> %result3)
+ %result4 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 4
+ call void (...) @llvm.fake.use(<2 x i32> %result4)
+ %result5 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 5
+ call void (...) @llvm.fake.use(<2 x i32> %result5)
+ %result6 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 6
+ call void (...) @llvm.fake.use(<2 x i32> %result6)
+ %result7 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 7
+ call void (...) @llvm.fake.use(<2 x i32> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v2f32(<4 x float> %vec) {
+; CHECK-LABEL: deinterleave2_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: bx lr
+ %result = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2(<4 x float> %vec)
+ %result0 = extractvalue { <2 x float>, <2 x float> } %result, 0
+ call void (...) @llvm.fake.use(<2 x float> %result0)
+ %result1 = extractvalue { <2 x float>, <2 x float> } %result, 1
+ call void (...) @llvm.fake.use(<2 x float> %result1)
+ ret void
+}
+
+define void @deinterleave3_v2f32(<6 x float> %vec) {
+; CHECK-LABEL: deinterleave3_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: vldr s1, [sp, #28]
+; CHECK-NEXT: vmov s3, r1
+; CHECK-NEXT: vldr s0, [sp, #24]
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov s5, r3
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov s4, r2
+; CHECK-NEXT: vstr d0, [sp, #16]
+; CHECK-NEXT: vstmia sp, {d1, d2}
+; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r0:64]
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call { <2 x float>, <2 x float>, <2 x float> } @llvm.vector.deinterleave3(<6 x float> %vec)
+ %result0 = extractvalue { <2 x float>, <2 x float>, <2 x float> } %result, 0
+ call void (...) @llvm.fake.use(<2 x float> %result0)
+ %result1 = extractvalue { <2 x float>, <2 x float>, <2 x float> } %result, 1
+ call void (...) @llvm.fake.use(<2 x float> %result1)
+ %result2 = extractvalue { <2 x float>, <2 x float>, <2 x float> } %result, 2
+ call void (...) @llvm.fake.use(<2 x float> %result2)
+ ret void
+}
+
+define void @deinterleave4_v2f32(<8 x float> %vec) {
+; CHECK-LABEL: deinterleave4_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vorr d20, d18, d18
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vtrn.32 d20, d19
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: vtrn.32 d16, d19
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: vtrn.32 d17, d20
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: bx lr
+ %result = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.vector.deinterleave4(<8 x float> %vec)
+ %result0 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 0
+ call void (...) @llvm.fake.use(<2 x float> %result0)
+ %result1 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 1
+ call void (...) @llvm.fake.use(<2 x float> %result1)
+ %result2 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 2
+ call void (...) @llvm.fake.use(<2 x float> %result2)
+ %result3 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 3
+ call void (...) @llvm.fake.use(<2 x float> %result3)
+ ret void
+}
+
+define void @deinterleave6_v2f32(<12 x float> %vec) {
+; CHECK-LABEL: deinterleave6_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vldr s1, [sp, #76]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: vldr s0, [sp, #72]
+; CHECK-NEXT: vldr s3, [sp, #68]
+; CHECK-NEXT: vldr s5, [sp, #60]
+; CHECK-NEXT: vldr s7, [sp, #52]
+; CHECK-NEXT: vldr s2, [sp, #64]
+; CHECK-NEXT: vldr s4, [sp, #56]
+; CHECK-NEXT: vstr d0, [sp, #40]
+; CHECK-NEXT: vmov s1, r1
+; CHECK-NEXT: vmov s0, r0
+; CHECK-NEXT: vldr s6, [sp, #48]
+; CHECK-NEXT: vstr d1, [sp, #32]
+; CHECK-NEXT: vmov s3, r3
+; CHECK-NEXT: vstr d2, [sp, #24]
+; CHECK-NEXT: vmov s2, r2
+; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r12:64]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vorr d24, d16, d16
+; CHECK-NEXT: vstr d3, [sp, #16]
+; CHECK-NEXT: vstmia sp, {d0, d1}
+; CHECK-NEXT: vld3.32 {d20, d21, d22}, [r0:64]
+; CHECK-NEXT: vorr d26, d21, d21
+; CHECK-NEXT: vorr d25, d20, d20
+; CHECK-NEXT: vorr d20, d22, d22
+; CHECK-NEXT: vtrn.32 d26, d17
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: vtrn.32 d25, d24
+; CHECK-NEXT: @ fake_use: $d25
+; CHECK-NEXT: vtrn.32 d20, d18
+; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: @ fake_use: $d24
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d18 $q8_q9
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.vector.deinterleave6(<12 x float> %vec)
+ %result0 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 0
+ call void (...) @llvm.fake.use(<2 x float> %result0)
+ %result1 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 1
+ call void (...) @llvm.fake.use(<2 x float> %result1)
+ %result2 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 2
+ call void (...) @llvm.fake.use(<2 x float> %result2)
+ %result3 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 3
+ call void (...) @llvm.fake.use(<2 x float> %result3)
+ %result4 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 4
+ call void (...) @llvm.fake.use(<2 x float> %result4)
+ %result5 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 5
+ call void (...) @llvm.fake.use(<2 x float> %result5)
+ ret void
+}
+
+define void @deinterleave8_v2f32(<16 x float> %vec) {
+; CHECK-LABEL: deinterleave8_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vorr d25, d16, d16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vorr d26, d18, d18
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: vmov d23, r0, r1
+; CHECK-NEXT: vorr d24, d20, d20
+; CHECK-NEXT: vtrn.32 d25, d17
+; CHECK-NEXT: vtrn.32 d23, d22
+; CHECK-NEXT: vtrn.32 d24, d21
+; CHECK-NEXT: vtrn.32 d26, d19
+; CHECK-NEXT: vtrn.32 d25, d24
+; CHECK-NEXT: vtrn.32 d23, d26
+; CHECK-NEXT: vtrn.32 d17, d21
+; CHECK-NEXT: vtrn.32 d22, d19
+; CHECK-NEXT: vtrn.32 d23, d25
+; CHECK-NEXT: @ fake_use: $d23
+; CHECK-NEXT: vtrn.32 d19, d21
+; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: vtrn.32 d22, d17
+; CHECK-NEXT: @ fake_use: $d22
+; CHECK-NEXT: vtrn.32 d26, d24
+; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: @ fake_use: $d25
+; CHECK-NEXT: @ fake_use: $d17 $q8
+; CHECK-NEXT: @ fake_use: $d24
+; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: bx lr
+ %result = call { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.vector.deinterleave8(<16 x float> %vec)
+ %result0 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 0
+ call void (...) @llvm.fake.use(<2 x float> %result0)
+ %result1 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 1
+ call void (...) @llvm.fake.use(<2 x float> %result1)
+ %result2 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 2
+ call void (...) @llvm.fake.use(<2 x float> %result2)
+ %result3 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 3
+ call void (...) @llvm.fake.use(<2 x float> %result3)
+ %result4 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 4
+ call void (...) @llvm.fake.use(<2 x float> %result4)
+ %result5 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 5
+ call void (...) @llvm.fake.use(<2 x float> %result5)
+ %result6 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 6
+ call void (...) @llvm.fake.use(<2 x float> %result6)
+ %result7 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 7
+ call void (...) @llvm.fake.use(<2 x float> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v16i8(<32 x i8> %vec) {
+; CHECK-LABEL: deinterleave2_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vuzp.8 q8, q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: bx lr
+ %result = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2(<32 x i8> %vec)
+ %result0 = extractvalue { <16 x i8>, <16 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<16 x i8> %result0)
+ %result1 = extractvalue { <16 x i8>, <16 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<16 x i8> %result1)
+ ret void
+}
+
+define void @deinterleave3_v16i8(<48 x i8> %vec) {
+; CHECK-LABEL: deinterleave3_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #116
+; CHECK-NEXT: vld1.8 {d20[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #148
+; CHECK-NEXT: vld1.8 {d21[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #20
+; CHECK-NEXT: vld1.8 {d19[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #52
+; CHECK-NEXT: vld1.8 {d16[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #84
+; CHECK-NEXT: vld1.8 {d17[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #120
+; CHECK-NEXT: vld1.8 {d20[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #152
+; CHECK-NEXT: vld1.8 {d21[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vld1.8 {d19[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #56
+; CHECK-NEXT: vld1.8 {d16[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #88
+; CHECK-NEXT: vld1.8 {d17[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #124
+; CHECK-NEXT: vld1.8 {d20[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #156
+; CHECK-NEXT: vld1.8 {d21[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #28
+; CHECK-NEXT: vld1.8 {d19[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #60
+; CHECK-NEXT: vld1.8 {d16[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #92
+; CHECK-NEXT: vld1.8 {d17[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #128
+; CHECK-NEXT: vld1.8 {d20[3]}, [r12]
+; CHECK-NEXT: vmov.8 d18[0], r0
+; CHECK-NEXT: add r0, r11, #160
+; CHECK-NEXT: vld1.8 {d21[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #32
+; CHECK-NEXT: vmov.8 d18[1], r1
+; CHECK-NEXT: vld1.8 {d19[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #64
+; CHECK-NEXT: vld1.8 {d16[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #96
+; CHECK-NEXT: vld1.8 {d17[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #4
+; CHECK-NEXT: vmov.8 d18[2], r2
+; CHECK-NEXT: vmov.8 d18[3], r3
+; CHECK-NEXT: vld1.8 {d18[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #132
+; CHECK-NEXT: vld1.8 {d20[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #164
+; CHECK-NEXT: vld1.8 {d21[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #36
+; CHECK-NEXT: vld1.8 {d19[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #68
+; CHECK-NEXT: vld1.8 {d16[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #100
+; CHECK-NEXT: vld1.8 {d17[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #8
+; CHECK-NEXT: vld1.8 {d18[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #136
+; CHECK-NEXT: vld1.8 {d20[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #168
+; CHECK-NEXT: vld1.8 {d21[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #40
+; CHECK-NEXT: vld1.8 {d19[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #72
+; CHECK-NEXT: vld1.8 {d16[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #104
+; CHECK-NEXT: vld1.8 {d17[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #12
+; CHECK-NEXT: vld1.8 {d18[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #140
+; CHECK-NEXT: vld1.8 {d20[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #172
+; CHECK-NEXT: vld1.8 {d21[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #44
+; CHECK-NEXT: vld1.8 {d19[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #76
+; CHECK-NEXT: vld1.8 {d16[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #108
+; CHECK-NEXT: vld1.8 {d17[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #16
+; CHECK-NEXT: vld1.8 {d18[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #144
+; CHECK-NEXT: vld1.8 {d20[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #176
+; CHECK-NEXT: vld1.8 {d21[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #48
+; CHECK-NEXT: vld1.8 {d19[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #80
+; CHECK-NEXT: vld1.8 {d16[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #112
+; CHECK-NEXT: vld1.8 {d17[7]}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vst1.64 {d20, d21}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld3.8 {d16, d18, d20}, [r0:64]!
+; CHECK-NEXT: vld3.8 {d17, d19, d21}, [r0:64]
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q10 $q8_q9_q10_q11
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.vector.deinterleave3(<48 x i8> %vec)
+ %result0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<16 x i8> %result0)
+ %result1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<16 x i8> %result1)
+ %result2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<16 x i8> %result2)
+ ret void
+}
+
+define void @deinterleave4_v16i8(<64 x i8> %vec) {
+; CHECK-LABEL: deinterleave4_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: add r12, sp, #40
+; CHECK-NEXT: vmov d21, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: add lr, sp, #8
+; CHECK-NEXT: vmov d20, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: vuzp.8 q10, q9
+; CHECK-NEXT: vuzp.8 q11, q8
+; CHECK-NEXT: vuzp.8 q10, q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.8 q9, q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: pop {r11, pc}
+ %result = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.vector.deinterleave4(<64 x i8> %vec)
+ %result0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<16 x i8> %result0)
+ %result1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<16 x i8> %result1)
+ %result2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<16 x i8> %result2)
+ %result3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 3
+ call void (...) @llvm.fake.use(<16 x i8> %result3)
+ ret void
+}
+
+define void @deinterleave6_v16i8(<96 x i8> %vec) {
+; CHECK-LABEL: deinterleave6_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r11, lr}
+; CHECK-NEXT: push {r4, r5, r11, lr}
+; CHECK-NEXT: .setfp r11, sp, #8
+; CHECK-NEXT: add r11, sp, #8
+; CHECK-NEXT: .pad #96
+; CHECK-NEXT: sub sp, sp, #96
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #312
+; CHECK-NEXT: vld1.8 {d26[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #344
+; CHECK-NEXT: vld1.8 {d27[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #184
+; CHECK-NEXT: vld1.8 {d22[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #216
+; CHECK-NEXT: vld1.8 {d23[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #248
+; CHECK-NEXT: vld1.8 {d24[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #280
+; CHECK-NEXT: vld1.8 {d25[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #316
+; CHECK-NEXT: vld1.8 {d26[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #348
+; CHECK-NEXT: vld1.8 {d27[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #188
+; CHECK-NEXT: vld1.8 {d22[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #220
+; CHECK-NEXT: vld1.8 {d23[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #252
+; CHECK-NEXT: vld1.8 {d24[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #284
+; CHECK-NEXT: vld1.8 {d25[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #320
+; CHECK-NEXT: vld1.8 {d26[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #352
+; CHECK-NEXT: vld1.8 {d27[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #192
+; CHECK-NEXT: vld1.8 {d22[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #224
+; CHECK-NEXT: vld1.8 {d23[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #256
+; CHECK-NEXT: vld1.8 {d24[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #288
+; CHECK-NEXT: vld1.8 {d25[2]}, [r12]
+; CHECK-NEXT: add r12, r11, #324
+; CHECK-NEXT: vld1.8 {d26[3]}, [r12]
+; CHECK-NEXT: add r12, r11, #356
+; CHECK-NEXT: vld1.8 {d27[3]}, [r12]
+; CHECK-NEXT: add r12, r11, #196
+; CHECK-NEXT: vld1.8 {d22[3]}, [r12]
+; CHECK-NEXT: add r12, r11, #228
+; CHECK-NEXT: vld1.8 {d23[3]}, [r12]
+; CHECK-NEXT: add r12, r11, #260
+; CHECK-NEXT: vld1.8 {d24[3]}, [r12]
+; CHECK-NEXT: add r12, r11, #292
+; CHECK-NEXT: vld1.8 {d25[3]}, [r12]
+; CHECK-NEXT: add r12, r11, #328
+; CHECK-NEXT: vld1.8 {d26[4]}, [r12]
+; CHECK-NEXT: add r12, r11, #360
+; CHECK-NEXT: vld1.8 {d27[4]}, [r12]
+; CHECK-NEXT: add r12, r11, #200
+; CHECK-NEXT: vld1.8 {d22[4]}, [r12]
+; CHECK-NEXT: add r12, r11, #232
+; CHECK-NEXT: vld1.8 {d23[4]}, [r12]
+; CHECK-NEXT: add r12, r11, #264
+; CHECK-NEXT: vld1.8 {d24[4]}, [r12]
+; CHECK-NEXT: add r12, r11, #296
+; CHECK-NEXT: vld1.8 {d25[4]}, [r12]
+; CHECK-NEXT: add r12, r11, #332
+; CHECK-NEXT: vld1.8 {d26[5]}, [r12]
+; CHECK-NEXT: add r12, r11, #364
+; CHECK-NEXT: vld1.8 {d27[5]}, [r12]
+; CHECK-NEXT: add r12, r11, #204
+; CHECK-NEXT: vld1.8 {d22[5]}, [r12]
+; CHECK-NEXT: add r12, r11, #236
+; CHECK-NEXT: vld1.8 {d23[5]}, [r12]
+; CHECK-NEXT: add r12, r11, #268
+; CHECK-NEXT: vld1.8 {d24[5]}, [r12]
+; CHECK-NEXT: add r12, r11, #300
+; CHECK-NEXT: vld1.8 {d25[5]}, [r12]
+; CHECK-NEXT: add r12, r11, #120
+; CHECK-NEXT: vld1.8 {d16[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #336
+; CHECK-NEXT: vld1.8 {d26[6]}, [r12]
+; CHECK-NEXT: add r12, r11, #368
+; CHECK-NEXT: vld1.8 {d27[6]}, [r12]
+; CHECK-NEXT: add r12, r11, #208
+; CHECK-NEXT: vld1.8 {d22[6]}, [r12]
+; CHECK-NEXT: add r12, r11, #240
+; CHECK-NEXT: vld1.8 {d23[6]}, [r12]
+; CHECK-NEXT: add r12, r11, #272
+; CHECK-NEXT: vld1.8 {d24[6]}, [r12]
+; CHECK-NEXT: add r12, r11, #304
+; CHECK-NEXT: vld1.8 {d25[6]}, [r12]
+; CHECK-NEXT: add r12, r11, #152
+; CHECK-NEXT: vld1.8 {d17[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vld1.8 {d21[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #56
+; CHECK-NEXT: vld1.8 {d18[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #88
+; CHECK-NEXT: vld1.8 {d19[0]}, [r12]
+; CHECK-NEXT: add r12, r11, #124
+; CHECK-NEXT: vld1.8 {d16[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #340
+; CHECK-NEXT: vld1.8 {d26[7]}, [r12]
+; CHECK-NEXT: add r12, r11, #372
+; CHECK-NEXT: vld1.8 {d27[7]}, [r12]
+; CHECK-NEXT: add r12, r11, #212
+; CHECK-NEXT: vld1.8 {d22[7]}, [r12]
+; CHECK-NEXT: add r12, r11, #244
+; CHECK-NEXT: vld1.8 {d23[7]}, [r12]
+; CHECK-NEXT: add r12, r11, #276
+; CHECK-NEXT: vld1.8 {d24[7]}, [r12]
+; CHECK-NEXT: add r12, r11, #308
+; CHECK-NEXT: vld1.8 {d25[7]}, [r12]
+; CHECK-NEXT: add r12, r11, #156
+; CHECK-NEXT: vld1.8 {d17[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #28
+; CHECK-NEXT: vld1.8 {d21[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #60
+; CHECK-NEXT: vld1.8 {d18[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #92
+; CHECK-NEXT: vld1.8 {d19[1]}, [r12]
+; CHECK-NEXT: add r12, r11, #128
+; CHECK-NEXT: vld1.8 {d16[2]}, [r12]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: add lr, r12, #32
+; CHECK-NEXT: vst1.64 {d26, d27}, [lr:128]
+; CHECK-NEXT: mov lr, r12
+; CHECK-NEXT: vst1.64 {d22, d23}, [lr:128]!
+; CHECK-NEXT: vst1.64 {d24, d25}, [lr]
+; CHECK-NEXT: add lr, r11, #160
+; CHECK-NEXT: vld1.8 {d17[2]}, [lr]
+; CHECK-NEXT: add lr, r11, #32
+; CHECK-NEXT: vld1.8 {d21[2]}, [lr]
+; CHECK-NEXT: add lr, r11, #64
+; CHECK-NEXT: vld1.8 {d18[2]}, [lr]
+; CHECK-NEXT: add lr, r11, #96
+; CHECK-NEXT: vld1.8 {d19[2]}, [lr]
+; CHECK-NEXT: add lr, r11, #132
+; CHECK-NEXT: vld1.8 {d16[3]}, [lr]
+; CHECK-NEXT: vmov.8 d20[0], r0
+; CHECK-NEXT: add r0, r11, #164
+; CHECK-NEXT: vld1.8 {d17[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #36
+; CHECK-NEXT: vmov.8 d20[1], r1
+; CHECK-NEXT: vld1.8 {d21[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #68
+; CHECK-NEXT: vld1.8 {d18[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #100
+; CHECK-NEXT: vld1.8 {d19[3]}, [r0]
+; CHECK-NEXT: add r0, r11, #8
+; CHECK-NEXT: vmov.8 d20[2], r2
+; CHECK-NEXT: vld3.8 {d22, d24, d26}, [r12:64]!
+; CHECK-NEXT: vmov.8 d20[3], r3
+; CHECK-NEXT: vld3.8 {d23, d25, d27}, [r12:64]
+; CHECK-NEXT: vld1.8 {d20[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #136
+; CHECK-NEXT: vld1.8 {d16[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #168
+; CHECK-NEXT: vld1.8 {d17[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #40
+; CHECK-NEXT: vld1.8 {d21[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #72
+; CHECK-NEXT: vld1.8 {d18[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #104
+; CHECK-NEXT: vld1.8 {d19[4]}, [r0]
+; CHECK-NEXT: add r0, r11, #12
+; CHECK-NEXT: vld1.8 {d20[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #140
+; CHECK-NEXT: vld1.8 {d16[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #172
+; CHECK-NEXT: vld1.8 {d17[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #44
+; CHECK-NEXT: vld1.8 {d21[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #76
+; CHECK-NEXT: vld1.8 {d18[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #108
+; CHECK-NEXT: vld1.8 {d19[5]}, [r0]
+; CHECK-NEXT: add r0, r11, #16
+; CHECK-NEXT: vld1.8 {d20[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #144
+; CHECK-NEXT: vld1.8 {d16[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #176
+; CHECK-NEXT: vld1.8 {d17[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #48
+; CHECK-NEXT: vld1.8 {d21[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #80
+; CHECK-NEXT: vld1.8 {d18[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #112
+; CHECK-NEXT: vld1.8 {d19[6]}, [r0]
+; CHECK-NEXT: add r0, r11, #20
+; CHECK-NEXT: vld1.8 {d20[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #148
+; CHECK-NEXT: vld1.8 {d16[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #180
+; CHECK-NEXT: vld1.8 {d17[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #52
+; CHECK-NEXT: vld1.8 {d21[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #84
+; CHECK-NEXT: vld1.8 {d18[7]}, [r0]
+; CHECK-NEXT: add r0, r11, #116
+; CHECK-NEXT: vld1.8 {d19[7]}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vld3.8 {d0, d2, d4}, [r0:64]!
+; CHECK-NEXT: vld3.8 {d1, d3, d5}, [r0:64]
+; CHECK-NEXT: vorr q8, q0, q0
+; CHECK-NEXT: vorr q9, q1, q1
+; CHECK-NEXT: vorr q15, q2, q2
+; CHECK-NEXT: vuzp.8 q8, q11
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: vuzp.8 q9, q12
+; CHECK-NEXT: vorr q10, q13, q13
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: @ fake_use: $q12 $q11_q12_q13_q14
+; CHECK-NEXT: vuzp.8 q15, q10
+; CHECK-NEXT: @ fake_use: $q15
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: sub sp, r11, #8
+; CHECK-NEXT: pop {r4, r5, r11, pc}
+ %result = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.vector.deinterleave6(<96 x i8> %vec)
+ %result0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<16 x i8> %result0)
+ %result1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<16 x i8> %result1)
+ %result2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<16 x i8> %result2)
+ %result3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 3
+ call void (...) @llvm.fake.use(<16 x i8> %result3)
+ %result4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 4
+ call void (...) @llvm.fake.use(<16 x i8> %result4)
+ %result5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 5
+ call void (...) @llvm.fake.use(<16 x i8> %result5)
+ ret void
+}
+
+define void @deinterleave8_v16i8(<128 x i8> %vec) {
+; CHECK-LABEL: deinterleave8_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #96
+; CHECK-NEXT: vmov d31, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #80
+; CHECK-NEXT: vmov d30, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #64
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: vuzp.8 q9, q8
+; CHECK-NEXT: vuzp.8 q14, q10
+; CHECK-NEXT: vuzp.8 q15, q11
+; CHECK-NEXT: vuzp.8 q13, q12
+; CHECK-NEXT: vuzp.8 q14, q9
+; CHECK-NEXT: vuzp.8 q15, q13
+; CHECK-NEXT: vuzp.8 q10, q8
+; CHECK-NEXT: vuzp.8 q11, q12
+; CHECK-NEXT: vuzp.8 q15, q14
+; CHECK-NEXT: @ fake_use: $q15
+; CHECK-NEXT: @ fake_use: $q14
+; CHECK-NEXT: vuzp.8 q11, q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: vuzp.8 q13, q9
+; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.8 q12, q8
+; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: bx lr
+ %result = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.vector.deinterleave8(<128 x i8> %vec)
+ %result0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 0
+ call void (...) @llvm.fake.use(<16 x i8> %result0)
+ %result1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 1
+ call void (...) @llvm.fake.use(<16 x i8> %result1)
+ %result2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 2
+ call void (...) @llvm.fake.use(<16 x i8> %result2)
+ %result3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 3
+ call void (...) @llvm.fake.use(<16 x i8> %result3)
+ %result4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 4
+ call void (...) @llvm.fake.use(<16 x i8> %result4)
+ %result5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 5
+ call void (...) @llvm.fake.use(<16 x i8> %result5)
+ %result6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 6
+ call void (...) @llvm.fake.use(<16 x i8> %result6)
+ %result7 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 7
+ call void (...) @llvm.fake.use(<16 x i8> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v8i16(<16 x i16> %vec) {
+; CHECK-LABEL: deinterleave2_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vuzp.16 q8, q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2(<16 x i16> %vec)
+ %result0 = extractvalue { <8 x i16>, <8 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i16> %result0)
+ %result1 = extractvalue { <8 x i16>, <8 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i16> %result1)
+ ret void
+}
+
+define void @deinterleave3_v8i16(<24 x i16> %vec) {
+; CHECK-LABEL: deinterleave3_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #52
+; CHECK-NEXT: vld1.16 {d20[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #68
+; CHECK-NEXT: vld1.16 {d21[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #4
+; CHECK-NEXT: vld1.16 {d19[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #20
+; CHECK-NEXT: vld1.16 {d16[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #36
+; CHECK-NEXT: vld1.16 {d17[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #56
+; CHECK-NEXT: vld1.16 {d20[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #72
+; CHECK-NEXT: vld1.16 {d21[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #8
+; CHECK-NEXT: vld1.16 {d19[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vld1.16 {d16[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #40
+; CHECK-NEXT: vld1.16 {d17[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #60
+; CHECK-NEXT: vld1.16 {d20[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #76
+; CHECK-NEXT: vld1.16 {d21[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #12
+; CHECK-NEXT: vld1.16 {d19[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #28
+; CHECK-NEXT: vld1.16 {d16[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #44
+; CHECK-NEXT: vld1.16 {d17[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #64
+; CHECK-NEXT: vld1.16 {d20[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #80
+; CHECK-NEXT: vld1.16 {d21[3]}, [r12:16]
+; CHECK-NEXT: vmov.16 d18[0], r0
+; CHECK-NEXT: add r0, r11, #16
+; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16]
+; CHECK-NEXT: add r0, r11, #32
+; CHECK-NEXT: vld1.16 {d16[3]}, [r0:16]
+; CHECK-NEXT: add r0, r11, #48
+; CHECK-NEXT: vld1.16 {d17[3]}, [r0:16]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov.16 d18[1], r1
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vst1.64 {d20, d21}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vmov.16 d18[2], r2
+; CHECK-NEXT: vmov.16 d18[3], r3
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
+; CHECK-NEXT: vld3.16 {d16, d18, d20}, [r0:64]!
+; CHECK-NEXT: vld3.16 {d17, d19, d21}, [r0:64]
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q10 $q8_q9_q10_q11
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.vector.deinterleave3(<24 x i16> %vec)
+ %result0 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i16> %result0)
+ %result1 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i16> %result1)
+ %result2 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i16> %result2)
+ ret void
+}
+
+define void @deinterleave4_v8i16(<32 x i16> %vec) {
+; CHECK-LABEL: deinterleave4_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: add r12, sp, #40
+; CHECK-NEXT: vmov d21, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: add lr, sp, #8
+; CHECK-NEXT: vmov d20, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: vuzp.16 q10, q9
+; CHECK-NEXT: vuzp.16 q11, q8
+; CHECK-NEXT: vuzp.16 q10, q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.16 q9, q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: pop {r11, pc}
+ %result = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.vector.deinterleave4(<32 x i16> %vec)
+ %result0 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i16> %result0)
+ %result1 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i16> %result1)
+ %result2 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i16> %result2)
+ %result3 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 3
+ call void (...) @llvm.fake.use(<8 x i16> %result3)
+ ret void
+}
+
+define void @deinterleave6_v8i16(<48 x i16> %vec) {
+; CHECK-LABEL: deinterleave6_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #104
+; CHECK-NEXT: sub sp, sp, #104
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #152
+; CHECK-NEXT: vld1.16 {d26[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #168
+; CHECK-NEXT: vld1.16 {d27[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #88
+; CHECK-NEXT: vld1.16 {d22[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #104
+; CHECK-NEXT: vld1.16 {d23[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #120
+; CHECK-NEXT: vld1.16 {d24[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #136
+; CHECK-NEXT: vld1.16 {d25[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #156
+; CHECK-NEXT: vld1.16 {d26[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #172
+; CHECK-NEXT: vld1.16 {d27[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #92
+; CHECK-NEXT: vld1.16 {d22[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #108
+; CHECK-NEXT: vld1.16 {d23[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #124
+; CHECK-NEXT: vld1.16 {d24[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #140
+; CHECK-NEXT: vld1.16 {d25[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #56
+; CHECK-NEXT: vld1.16 {d16[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #72
+; CHECK-NEXT: vld1.16 {d17[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #160
+; CHECK-NEXT: vld1.16 {d26[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #176
+; CHECK-NEXT: vld1.16 {d27[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #96
+; CHECK-NEXT: vld1.16 {d22[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #112
+; CHECK-NEXT: vld1.16 {d23[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #128
+; CHECK-NEXT: vld1.16 {d24[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #144
+; CHECK-NEXT: vld1.16 {d25[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #8
+; CHECK-NEXT: vld1.16 {d21[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vld1.16 {d18[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #40
+; CHECK-NEXT: vld1.16 {d19[0]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #60
+; CHECK-NEXT: vld1.16 {d16[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #76
+; CHECK-NEXT: vld1.16 {d17[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #164
+; CHECK-NEXT: vld1.16 {d26[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #180
+; CHECK-NEXT: vld1.16 {d27[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #100
+; CHECK-NEXT: vld1.16 {d22[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #116
+; CHECK-NEXT: vld1.16 {d23[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #132
+; CHECK-NEXT: vld1.16 {d24[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #148
+; CHECK-NEXT: vld1.16 {d25[3]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #12
+; CHECK-NEXT: vld1.16 {d21[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #28
+; CHECK-NEXT: vld1.16 {d18[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #44
+; CHECK-NEXT: vld1.16 {d19[1]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #64
+; CHECK-NEXT: vld1.16 {d16[2]}, [r12:16]
+; CHECK-NEXT: add r12, r11, #80
+; CHECK-NEXT: vld1.16 {d17[2]}, [r12:16]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: add lr, r12, #32
+; CHECK-NEXT: vst1.64 {d26, d27}, [lr:128]
+; CHECK-NEXT: mov lr, r12
+; CHECK-NEXT: vst1.64 {d22, d23}, [lr:128]!
+; CHECK-NEXT: vst1.64 {d24, d25}, [lr]
+; CHECK-NEXT: add lr, r11, #16
+; CHECK-NEXT: vld1.16 {d21[2]}, [lr:16]
+; CHECK-NEXT: add lr, r11, #32
+; CHECK-NEXT: vld1.16 {d18[2]}, [lr:16]
+; CHECK-NEXT: add lr, r11, #48
+; CHECK-NEXT: vld1.16 {d19[2]}, [lr:16]
+; CHECK-NEXT: add lr, r11, #68
+; CHECK-NEXT: vld1.16 {d16[3]}, [lr:16]
+; CHECK-NEXT: add lr, r11, #84
+; CHECK-NEXT: vld1.16 {d17[3]}, [lr:16]
+; CHECK-NEXT: vmov.16 d20[0], r0
+; CHECK-NEXT: add r0, r11, #20
+; CHECK-NEXT: vld1.16 {d21[3]}, [r0:16]
+; CHECK-NEXT: add r0, r11, #36
+; CHECK-NEXT: vld1.16 {d18[3]}, [r0:16]
+; CHECK-NEXT: add r0, r11, #52
+; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov.16 d20[1], r1
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vld3.16 {d22, d24, d26}, [r12:64]!
+; CHECK-NEXT: vmov.16 d20[2], r2
+; CHECK-NEXT: vld3.16 {d23, d25, d27}, [r12:64]
+; CHECK-NEXT: vorr q15, q12, q12
+; CHECK-NEXT: vmov.16 d20[3], r3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vorr q8, q11, q11
+; CHECK-NEXT: vst1.64 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vorr q11, q13, q13
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vld3.16 {d0, d2, d4}, [r0:64]!
+; CHECK-NEXT: vld3.16 {d1, d3, d5}, [r0:64]
+; CHECK-NEXT: vorr q9, q0, q0
+; CHECK-NEXT: vorr q10, q1, q1
+; CHECK-NEXT: vorr q0, q2, q2
+; CHECK-NEXT: vuzp.16 q9, q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: vuzp.16 q10, q15
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: @ fake_use: $q15
+; CHECK-NEXT: vuzp.16 q0, q11
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11, pc}
+ %result = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.vector.deinterleave6(<48 x i16> %vec)
+ %result0 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i16> %result0)
+ %result1 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i16> %result1)
+ %result2 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i16> %result2)
+ %result3 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 3
+ call void (...) @llvm.fake.use(<8 x i16> %result3)
+ %result4 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 4
+ call void (...) @llvm.fake.use(<8 x i16> %result4)
+ %result5 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 5
+ call void (...) @llvm.fake.use(<8 x i16> %result5)
+ ret void
+}
+
+define void @deinterleave8_v8i16(<64 x i16> %vec) {
+; CHECK-LABEL: deinterleave8_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #96
+; CHECK-NEXT: vmov d31, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #80
+; CHECK-NEXT: vmov d30, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #64
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: vuzp.16 q9, q8
+; CHECK-NEXT: vuzp.16 q14, q10
+; CHECK-NEXT: vuzp.16 q15, q11
+; CHECK-NEXT: vuzp.16 q13, q12
+; CHECK-NEXT: vuzp.16 q14, q9
+; CHECK-NEXT: vuzp.16 q15, q13
+; CHECK-NEXT: vuzp.16 q10, q8
+; CHECK-NEXT: vuzp.16 q11, q12
+; CHECK-NEXT: vuzp.16 q15, q14
+; CHECK-NEXT: @ fake_use: $q15
+; CHECK-NEXT: @ fake_use: $q14
+; CHECK-NEXT: vuzp.16 q11, q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: vuzp.16 q13, q9
+; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.16 q12, q8
+; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: bx lr
+ %result = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.vector.deinterleave8(<64 x i16> %vec)
+ %result0 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 0
+ call void (...) @llvm.fake.use(<8 x i16> %result0)
+ %result1 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 1
+ call void (...) @llvm.fake.use(<8 x i16> %result1)
+ %result2 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 2
+ call void (...) @llvm.fake.use(<8 x i16> %result2)
+ %result3 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 3
+ call void (...) @llvm.fake.use(<8 x i16> %result3)
+ %result4 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 4
+ call void (...) @llvm.fake.use(<8 x i16> %result4)
+ %result5 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 5
+ call void (...) @llvm.fake.use(<8 x i16> %result5)
+ %result6 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 6
+ call void (...) @llvm.fake.use(<8 x i16> %result6)
+ %result7 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 7
+ call void (...) @llvm.fake.use(<8 x i16> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v4i32(<8 x i32> %vec) {
+; CHECK-LABEL: deinterleave2_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vuzp.32 q8, q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2(<8 x i32> %vec)
+ %result0 = extractvalue { <4 x i32>, <4 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i32> %result0)
+ %result1 = extractvalue { <4 x i32>, <4 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i32> %result1)
+ ret void
+}
+
+define void @deinterleave3_v4i32(<12 x i32> %vec) {
+; CHECK-LABEL: deinterleave3_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #20
+; CHECK-NEXT: vmov.32 d21[0], r2
+; CHECK-NEXT: add r2, r11, #32
+; CHECK-NEXT: vld1.32 {d16[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #28
+; CHECK-NEXT: vld1.32 {d17[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #4
+; CHECK-NEXT: vld1.32 {d18[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #12
+; CHECK-NEXT: vld1.32 {d19[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vld1.32 {d16[1]}, [r12:32]
+; CHECK-NEXT: vld1.32 {d17[1]}, [r2:32]
+; CHECK-NEXT: vmov.32 d20[0], r0
+; CHECK-NEXT: add r0, r11, #8
+; CHECK-NEXT: vld1.32 {d18[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #16
+; CHECK-NEXT: vld1.32 {d19[1]}, [r0:32]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov.32 d20[1], r1
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vmov.32 d21[1], r3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r0:64]!
+; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r0:64]
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q10 $q8_q9_q10_q11
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave3(<12 x i32> %vec)
+ %result0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i32> %result0)
+ %result1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i32> %result1)
+ %result2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i32> %result2)
+ ret void
+}
+
+define void @deinterleave4_v4i32(<16 x i32> %vec) {
+; CHECK-LABEL: deinterleave4_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: add r12, sp, #40
+; CHECK-NEXT: vmov d21, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: add lr, sp, #8
+; CHECK-NEXT: vmov d20, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: vuzp.32 q10, q9
+; CHECK-NEXT: vuzp.32 q11, q8
+; CHECK-NEXT: vuzp.32 q10, q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.32 q9, q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: pop {r11, pc}
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave4(<16 x i32> %vec)
+ %result0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i32> %result0)
+ %result1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i32> %result1)
+ %result2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i32> %result2)
+ %result3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ call void (...) @llvm.fake.use(<4 x i32> %result3)
+ ret void
+}
+
+define void @deinterleave6_v4i32(<24 x i32> %vec) {
+; CHECK-LABEL: deinterleave6_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #20
+; CHECK-NEXT: vmov.32 d21[0], r2
+; CHECK-NEXT: add r2, r11, #32
+; CHECK-NEXT: vld1.32 {d16[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #28
+; CHECK-NEXT: vld1.32 {d17[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #4
+; CHECK-NEXT: vld1.32 {d18[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #12
+; CHECK-NEXT: vld1.32 {d19[0]}, [r12:32]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vld1.32 {d16[1]}, [r12:32]
+; CHECK-NEXT: vld1.32 {d17[1]}, [r2:32]
+; CHECK-NEXT: vmov.32 d20[0], r0
+; CHECK-NEXT: add r0, r11, #8
+; CHECK-NEXT: vld1.32 {d18[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #16
+; CHECK-NEXT: vld1.32 {d19[1]}, [r0:32]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vmov.32 d20[1], r1
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vmov.32 d21[1], r3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, r11, #68
+; CHECK-NEXT: vld1.32 {d24[0]}, [r1:32]
+; CHECK-NEXT: add r1, r11, #76
+; CHECK-NEXT: vld1.32 {d25[0]}, [r1:32]
+; CHECK-NEXT: add r1, r11, #36
+; CHECK-NEXT: vld1.32 {d26[0]}, [r1:32]
+; CHECK-NEXT: add r1, r11, #44
+; CHECK-NEXT: vld1.32 {d27[0]}, [r1:32]
+; CHECK-NEXT: add r1, r11, #52
+; CHECK-NEXT: vld1.32 {d28[0]}, [r1:32]
+; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r0:64]!
+; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r0:64]
+; CHECK-NEXT: add r0, r11, #60
+; CHECK-NEXT: vorr q0, q8, q8
+; CHECK-NEXT: vld1.32 {d29[0]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #72
+; CHECK-NEXT: vorr q3, q9, q9
+; CHECK-NEXT: vorr q8, q10, q10
+; CHECK-NEXT: vld1.32 {d24[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #80
+; CHECK-NEXT: vld1.32 {d25[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #40
+; CHECK-NEXT: vld1.32 {d26[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #48
+; CHECK-NEXT: vld1.32 {d27[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #56
+; CHECK-NEXT: vld1.32 {d28[1]}, [r0:32]
+; CHECK-NEXT: add r0, r11, #64
+; CHECK-NEXT: vld1.32 {d29[1]}, [r0:32]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: vst1.64 {d24, d25}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d26, d27}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d28, d29}, [r1]
+; CHECK-NEXT: vld3.32 {d24, d26, d28}, [r0:64]!
+; CHECK-NEXT: vld3.32 {d25, d27, d29}, [r0:64]
+; CHECK-NEXT: vorr q1, q12, q12
+; CHECK-NEXT: vorr q2, q13, q13
+; CHECK-NEXT: vorr q12, q14, q14
+; CHECK-NEXT: vuzp.32 q0, q1
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q1
+; CHECK-NEXT: vuzp.32 q3, q2
+; CHECK-NEXT: @ fake_use: $q3
+; CHECK-NEXT: @ fake_use: $q2
+; CHECK-NEXT: vuzp.32 q8, q12
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave6(<24 x i32> %vec)
+ %result0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i32> %result0)
+ %result1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i32> %result1)
+ %result2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i32> %result2)
+ %result3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ call void (...) @llvm.fake.use(<4 x i32> %result3)
+ %result4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ call void (...) @llvm.fake.use(<4 x i32> %result4)
+ %result5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ call void (...) @llvm.fake.use(<4 x i32> %result5)
+ ret void
+}
+
+define void @deinterleave8_v4i32(<32 x i32> %vec) {
+; CHECK-LABEL: deinterleave8_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #96
+; CHECK-NEXT: vmov d31, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #80
+; CHECK-NEXT: vmov d30, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #64
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: vuzp.32 q9, q8
+; CHECK-NEXT: vuzp.32 q14, q10
+; CHECK-NEXT: vuzp.32 q15, q11
+; CHECK-NEXT: vuzp.32 q13, q12
+; CHECK-NEXT: vuzp.32 q14, q9
+; CHECK-NEXT: vuzp.32 q15, q13
+; CHECK-NEXT: vuzp.32 q10, q8
+; CHECK-NEXT: vuzp.32 q11, q12
+; CHECK-NEXT: vuzp.32 q15, q14
+; CHECK-NEXT: @ fake_use: $q15
+; CHECK-NEXT: @ fake_use: $q14
+; CHECK-NEXT: vuzp.32 q11, q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: vuzp.32 q13, q9
+; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.32 q12, q8
+; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: bx lr
+ %result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave8(<32 x i32> %vec)
+ %result0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
+ call void (...) @llvm.fake.use(<4 x i32> %result0)
+ %result1 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 1
+ call void (...) @llvm.fake.use(<4 x i32> %result1)
+ %result2 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 2
+ call void (...) @llvm.fake.use(<4 x i32> %result2)
+ %result3 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 3
+ call void (...) @llvm.fake.use(<4 x i32> %result3)
+ %result4 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 4
+ call void (...) @llvm.fake.use(<4 x i32> %result4)
+ %result5 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 5
+ call void (...) @llvm.fake.use(<4 x i32> %result5)
+ %result6 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 6
+ call void (...) @llvm.fake.use(<4 x i32> %result6)
+ %result7 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 7
+ call void (...) @llvm.fake.use(<4 x i32> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v4f32(<8 x float> %vec) {
+; CHECK-LABEL: deinterleave2_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d17, r2, r3
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: vmov d16, r0, r1
+; CHECK-NEXT: vuzp.32 q8, q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: bx lr
+ %result = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2(<8 x float> %vec)
+ %result0 = extractvalue { <4 x float>, <4 x float> } %result, 0
+ call void (...) @llvm.fake.use(<4 x float> %result0)
+ %result1 = extractvalue { <4 x float>, <4 x float> } %result, 1
+ call void (...) @llvm.fake.use(<4 x float> %result1)
+ ret void
+}
+
+define void @deinterleave3_v4f32(<12 x float> %vec) {
+; CHECK-LABEL: deinterleave3_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #4
+; CHECK-NEXT: vmov s7, r3
+; CHECK-NEXT: vmov s6, r2
+; CHECK-NEXT: vldmia r12, {s0, s1, s2, s3}
+; CHECK-NEXT: add r12, r11, #20
+; CHECK-NEXT: vmov s5, r1
+; CHECK-NEXT: vldmia r12, {s8, s9, s10, s11}
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vmov s4, r0
+; CHECK-NEXT: add r0, r12, #32
+; CHECK-NEXT: vst1.64 {d4, d5}, [r0:128]
+; CHECK-NEXT: mov r0, r12
+; CHECK-NEXT: vst1.64 {d2, d3}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d0, d1}, [r0]
+; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r12:64]!
+; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r12:64]
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q10 $q8_q9_q10_q11
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call { <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave3(<12 x float> %vec)
+ %result0 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %result, 0
+ call void (...) @llvm.fake.use(<4 x float> %result0)
+ %result1 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %result, 1
+ call void (...) @llvm.fake.use(<4 x float> %result1)
+ %result2 = extractvalue { <4 x float>, <4 x float>, <4 x float> } %result, 2
+ call void (...) @llvm.fake.use(<4 x float> %result2)
+ ret void
+}
+
+define void @deinterleave4_v4f32(<16 x float> %vec) {
+; CHECK-LABEL: deinterleave4_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: add r12, sp, #40
+; CHECK-NEXT: vmov d21, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #24
+; CHECK-NEXT: add lr, sp, #8
+; CHECK-NEXT: vmov d20, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: vuzp.32 q10, q9
+; CHECK-NEXT: vuzp.32 q11, q8
+; CHECK-NEXT: vuzp.32 q10, q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.32 q9, q8
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: pop {r11, pc}
+ %result = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave4(<16 x float> %vec)
+ %result0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 0
+ call void (...) @llvm.fake.use(<4 x float> %result0)
+ %result1 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 1
+ call void (...) @llvm.fake.use(<4 x float> %result1)
+ %result2 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 2
+ call void (...) @llvm.fake.use(<4 x float> %result2)
+ %result3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 3
+ call void (...) @llvm.fake.use(<4 x float> %result3)
+ ret void
+}
+
+define void @deinterleave6_v4f32(<24 x float> %vec) {
+; CHECK-LABEL: deinterleave6_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #104
+; CHECK-NEXT: sub sp, sp, #104
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r12, r11, #40
+; CHECK-NEXT: vldmia r12, {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11}
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: add lr, r12, #32
+; CHECK-NEXT: vst1.64 {d4, d5}, [lr:128]
+; CHECK-NEXT: mov lr, r12
+; CHECK-NEXT: vmov s11, r3
+; CHECK-NEXT: vst1.64 {d0, d1}, [lr:128]!
+; CHECK-NEXT: vmov s10, r2
+; CHECK-NEXT: vmov s9, r1
+; CHECK-NEXT: vst1.64 {d2, d3}, [lr]
+; CHECK-NEXT: add lr, r11, #8
+; CHECK-NEXT: vmov s8, r0
+; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r12:64]!
+; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r12:64]
+; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: vorr q3, q9, q9
+; CHECK-NEXT: vldr s7, [r11, #36]
+; CHECK-NEXT: vldmia r12, {s4, s5, s6}
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: add r0, r12, #32
+; CHECK-NEXT: vldmia lr, {s0, s1, s2, s3}
+; CHECK-NEXT: vst1.64 {d2, d3}, [r0:128]
+; CHECK-NEXT: mov r0, r12
+; CHECK-NEXT: vst1.64 {d4, d5}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d0, d1}, [r0]
+; CHECK-NEXT: vorr q0, q8, q8
+; CHECK-NEXT: vorr q8, q10, q10
+; CHECK-NEXT: vld3.32 {d24, d26, d28}, [r12:64]!
+; CHECK-NEXT: vld3.32 {d25, d27, d29}, [r12:64]
+; CHECK-NEXT: vorr q1, q12, q12
+; CHECK-NEXT: vorr q2, q13, q13
+; CHECK-NEXT: vorr q12, q14, q14
+; CHECK-NEXT: vuzp.32 q1, q0
+; CHECK-NEXT: @ fake_use: $q1
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: vuzp.32 q2, q3
+; CHECK-NEXT: @ fake_use: $q2
+; CHECK-NEXT: @ fake_use: $q3
+; CHECK-NEXT: vuzp.32 q12, q8
+; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11, pc}
+ %result = call { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave6(<24 x float> %vec)
+ %result0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 0
+ call void (...) @llvm.fake.use(<4 x float> %result0)
+ %result1 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 1
+ call void (...) @llvm.fake.use(<4 x float> %result1)
+ %result2 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 2
+ call void (...) @llvm.fake.use(<4 x float> %result2)
+ %result3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 3
+ call void (...) @llvm.fake.use(<4 x float> %result3)
+ %result4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 4
+ call void (...) @llvm.fake.use(<4 x float> %result4)
+ %result5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 5
+ call void (...) @llvm.fake.use(<4 x float> %result5)
+ ret void
+}
+
+define void @deinterleave8_v4f32(<32 x float> %vec) {
+; CHECK-LABEL: deinterleave8_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r12, sp, #96
+; CHECK-NEXT: vmov d31, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
+; CHECK-NEXT: add r12, sp, #80
+; CHECK-NEXT: vmov d30, r0, r1
+; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
+; CHECK-NEXT: add r12, sp, #64
+; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
+; CHECK-NEXT: add r12, sp, #32
+; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
+; CHECK-NEXT: add r12, sp, #16
+; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
+; CHECK-NEXT: add r12, sp, #48
+; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: vuzp.32 q9, q8
+; CHECK-NEXT: vuzp.32 q14, q10
+; CHECK-NEXT: vuzp.32 q15, q11
+; CHECK-NEXT: vuzp.32 q13, q12
+; CHECK-NEXT: vuzp.32 q14, q9
+; CHECK-NEXT: vuzp.32 q15, q13
+; CHECK-NEXT: vuzp.32 q10, q8
+; CHECK-NEXT: vuzp.32 q11, q12
+; CHECK-NEXT: vuzp.32 q15, q14
+; CHECK-NEXT: @ fake_use: $q15
+; CHECK-NEXT: @ fake_use: $q14
+; CHECK-NEXT: vuzp.32 q11, q10
+; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: @ fake_use: $q10
+; CHECK-NEXT: vuzp.32 q13, q9
+; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.32 q12, q8
+; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: @ fake_use: $q8
+; CHECK-NEXT: bx lr
+ %result = call { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave8(<32 x float> %vec)
+ %result0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 0
+ call void (...) @llvm.fake.use(<4 x float> %result0)
+ %result1 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 1
+ call void (...) @llvm.fake.use(<4 x float> %result1)
+ %result2 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 2
+ call void (...) @llvm.fake.use(<4 x float> %result2)
+ %result3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 3
+ call void (...) @llvm.fake.use(<4 x float> %result3)
+ %result4 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 4
+ call void (...) @llvm.fake.use(<4 x float> %result4)
+ %result5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 5
+ call void (...) @llvm.fake.use(<4 x float> %result5)
+ %result6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 6
+ call void (...) @llvm.fake.use(<4 x float> %result6)
+ %result7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 7
+ call void (...) @llvm.fake.use(<4 x float> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v4f16(<8 x half> %vec) {
+; CHECK-LABEL: deinterleave2_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r11, lr}
+; CHECK-NEXT: push {r4, r5, r11, lr}
+; CHECK-NEXT: ldrh r12, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh lr, [sp, #20]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r5, [sp, #16]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: pop {r4, r5, r11, pc}
+ %result = call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2(<8 x half> %vec)
+ %result0 = extractvalue { <4 x half>, <4 x half> } %result, 0
+ call void (...) @llvm.fake.use(<4 x half> %result0)
+ %result1 = extractvalue { <4 x half>, <4 x half> } %result, 1
+ call void (...) @llvm.fake.use(<4 x half> %result1)
+ ret void
+}
+
+define void @deinterleave3_v4f16(<12 x half> %vec) {
+; CHECK-LABEL: deinterleave3_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r12, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh lr, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r8, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave3(<12 x half> %vec)
+ %result0 = extractvalue { <4 x half>, <4 x half>, <4 x half> } %result, 0
+ call void (...) @llvm.fake.use(<4 x half> %result0)
+ %result1 = extractvalue { <4 x half>, <4 x half>, <4 x half> } %result, 1
+ call void (...) @llvm.fake.use(<4 x half> %result1)
+ %result2 = extractvalue { <4 x half>, <4 x half>, <4 x half> } %result, 2
+ call void (...) @llvm.fake.use(<4 x half> %result2)
+ ret void
+}
+
+define void @deinterleave4_v4f16(<16 x half> %vec) {
+; CHECK-LABEL: deinterleave4_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh lr, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r8, [sp, #44]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r5, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r1, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r9
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave4(<16 x half> %vec)
+ %result0 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 0
+ call void (...) @llvm.fake.use(<4 x half> %result0)
+ %result1 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 1
+ call void (...) @llvm.fake.use(<4 x half> %result1)
+ %result2 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 2
+ call void (...) @llvm.fake.use(<4 x half> %result2)
+ %result3 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 3
+ call void (...) @llvm.fake.use(<4 x half> %result3)
+ ret void
+}
+
+define void @deinterleave6_v4f16(<24 x half> %vec) {
+; CHECK-LABEL: deinterleave6_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave6(<24 x half> %vec)
+ %result0 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 0
+ call void (...) @llvm.fake.use(<4 x half> %result0)
+ %result1 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 1
+ call void (...) @llvm.fake.use(<4 x half> %result1)
+ %result2 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 2
+ call void (...) @llvm.fake.use(<4 x half> %result2)
+ %result3 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 3
+ call void (...) @llvm.fake.use(<4 x half> %result3)
+ %result4 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 4
+ call void (...) @llvm.fake.use(<4 x half> %result4)
+ %result5 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 5
+ call void (...) @llvm.fake.use(<4 x half> %result5)
+ ret void
+}
+
+define void @deinterleave8_v4f16(<32 x half> %vec) {
+; CHECK-LABEL: deinterleave8_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #108]
+; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #116]
+; CHECK-NEXT: ldrh r2, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh lr, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r8, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave8(<32 x half> %vec)
+ %result0 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 0
+ call void (...) @llvm.fake.use(<4 x half> %result0)
+ %result1 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 1
+ call void (...) @llvm.fake.use(<4 x half> %result1)
+ %result2 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 2
+ call void (...) @llvm.fake.use(<4 x half> %result2)
+ %result3 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 3
+ call void (...) @llvm.fake.use(<4 x half> %result3)
+ %result4 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 4
+ call void (...) @llvm.fake.use(<4 x half> %result4)
+ %result5 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 5
+ call void (...) @llvm.fake.use(<4 x half> %result5)
+ %result6 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 6
+ call void (...) @llvm.fake.use(<4 x half> %result6)
+ %result7 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 7
+ call void (...) @llvm.fake.use(<4 x half> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v8f16(<16 x half> %vec) {
+; CHECK-LABEL: deinterleave2_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r12, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh lr, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r8, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r5, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r9
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2(<16 x half> %vec)
+ %result0 = extractvalue { <8 x half>, <8 x half> } %result, 0
+ call void (...) @llvm.fake.use(<8 x half> %result0)
+ %result1 = extractvalue { <8 x half>, <8 x half> } %result, 1
+ call void (...) @llvm.fake.use(<8 x half> %result1)
+ ret void
+}
+
+define void @deinterleave3_v8f16(<24 x half> %vec) {
+; CHECK-LABEL: deinterleave3_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r3, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r3, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r12, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave3(<24 x half> %vec)
+ %result0 = extractvalue { <8 x half>, <8 x half>, <8 x half> } %result, 0
+ call void (...) @llvm.fake.use(<8 x half> %result0)
+ %result1 = extractvalue { <8 x half>, <8 x half>, <8 x half> } %result, 1
+ call void (...) @llvm.fake.use(<8 x half> %result1)
+ %result2 = extractvalue { <8 x half>, <8 x half>, <8 x half> } %result, 2
+ call void (...) @llvm.fake.use(<8 x half> %result2)
+ ret void
+}
+
+define void @deinterleave4_v8f16(<32 x half> %vec) {
+; CHECK-LABEL: deinterleave4_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r1, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r2, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh lr, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r7, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r1, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave4(<32 x half> %vec)
+ %result0 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 0
+ call void (...) @llvm.fake.use(<8 x half> %result0)
+ %result1 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 1
+ call void (...) @llvm.fake.use(<8 x half> %result1)
+ %result2 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 2
+ call void (...) @llvm.fake.use(<8 x half> %result2)
+ %result3 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 3
+ call void (...) @llvm.fake.use(<8 x half> %result3)
+ ret void
+}
+
+define void @deinterleave6_v8f16(<48 x half> %vec) {
+; CHECK-LABEL: deinterleave6_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #84]
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #180]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #152]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #112]
+; CHECK-NEXT: ldrh r2, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r1, [sp, #184]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #156]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #164]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #188]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #160]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r2, [sp, #144]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r3, [sp, #168]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #192]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r12, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh lr, [sp, #148]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #172]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r5, [sp, #196]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r7, [sp, #176]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave6(<48 x half> %vec)
+ %result0 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 0
+ call void (...) @llvm.fake.use(<8 x half> %result0)
+ %result1 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 1
+ call void (...) @llvm.fake.use(<8 x half> %result1)
+ %result2 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 2
+ call void (...) @llvm.fake.use(<8 x half> %result2)
+ %result3 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 3
+ call void (...) @llvm.fake.use(<8 x half> %result3)
+ %result4 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 4
+ call void (...) @llvm.fake.use(<8 x half> %result4)
+ %result5 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 5
+ call void (...) @llvm.fake.use(<8 x half> %result5)
+ ret void
+}
+
+define void @deinterleave8_v8f16(<64 x half> %vec) {
+; CHECK-LABEL: deinterleave8_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #144]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #244]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #152]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #252]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: add r0, sp, #256
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #148]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #184]
+; CHECK-NEXT: ldrh r0, [r0]
+; CHECK-NEXT: add r4, sp, #256
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #248]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #156]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #188]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: add r0, sp, #256
+; CHECK-NEXT: ldrh r3, [sp, #220]
+; CHECK-NEXT: ldrh r5, [r4, #12]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #208]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #160]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #192]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #224]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [r0, #4]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r2, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r6, [sp, #176]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #212]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: add r0, sp, #256
+; CHECK-NEXT: ldrh r1, [sp, #164]
+; CHECK-NEXT: ldrh r2, [sp, #196]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r3, [sp, #228]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r3, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #180]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #216]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #168]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r2, [sp, #200]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r3, [sp, #232]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [r0, #8]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #172]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh lr, [sp, #204]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r8, [sp, #236]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r7, [sp, #240]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+ %result = call { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave8(<64 x half> %vec)
+ %result0 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 0
+ call void (...) @llvm.fake.use(<8 x half> %result0)
+ %result1 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 1
+ call void (...) @llvm.fake.use(<8 x half> %result1)
+ %result2 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 2
+ call void (...) @llvm.fake.use(<8 x half> %result2)
+ %result3 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 3
+ call void (...) @llvm.fake.use(<8 x half> %result3)
+ %result4 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 4
+ call void (...) @llvm.fake.use(<8 x half> %result4)
+ %result5 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 5
+ call void (...) @llvm.fake.use(<8 x half> %result5)
+ %result6 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 6
+ call void (...) @llvm.fake.use(<8 x half> %result6)
+ %result7 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 7
+ call void (...) @llvm.fake.use(<8 x half> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v4bf16(<8 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave2_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r11, lr}
+; CHECK-NEXT: push {r4, r5, r11, lr}
+; CHECK-NEXT: ldrh r12, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh lr, [sp, #20]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r5, [sp, #16]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: pop {r4, r5, r11, pc}
+ %result = call { <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave2(<8 x bfloat> %vec)
+ %result0 = extractvalue { <4 x bfloat>, <4 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<4 x bfloat> %result0)
+ %result1 = extractvalue { <4 x bfloat>, <4 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<4 x bfloat> %result1)
+ ret void
+}
+
+define void @deinterleave3_v4bf16(<12 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave3_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r12, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh lr, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r8, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave3(<12 x bfloat> %vec)
+ %result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<4 x bfloat> %result0)
+ %result1 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<4 x bfloat> %result1)
+ %result2 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<4 x bfloat> %result2)
+ ret void
+}
+
+define void @deinterleave4_v4bf16(<16 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave4_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh lr, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r8, [sp, #44]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r5, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r1, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r9
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave4(<16 x bfloat> %vec)
+ %result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<4 x bfloat> %result0)
+ %result1 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<4 x bfloat> %result1)
+ %result2 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<4 x bfloat> %result2)
+ %result3 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 3
+ call void (...) @llvm.fake.use(<4 x bfloat> %result3)
+ ret void
+}
+
+define void @deinterleave6_v4bf16(<24 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave6_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave6(<24 x bfloat> %vec)
+ %result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<4 x bfloat> %result0)
+ %result1 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<4 x bfloat> %result1)
+ %result2 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<4 x bfloat> %result2)
+ %result3 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 3
+ call void (...) @llvm.fake.use(<4 x bfloat> %result3)
+ %result4 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 4
+ call void (...) @llvm.fake.use(<4 x bfloat> %result4)
+ %result5 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 5
+ call void (...) @llvm.fake.use(<4 x bfloat> %result5)
+ ret void
+}
+
+define void @deinterleave8_v4bf16(<32 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave8_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #108]
+; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #116]
+; CHECK-NEXT: ldrh r2, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh lr, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r8, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave8(<32 x bfloat> %vec)
+ %result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<4 x bfloat> %result0)
+ %result1 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<4 x bfloat> %result1)
+ %result2 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<4 x bfloat> %result2)
+ %result3 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 3
+ call void (...) @llvm.fake.use(<4 x bfloat> %result3)
+ %result4 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 4
+ call void (...) @llvm.fake.use(<4 x bfloat> %result4)
+ %result5 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 5
+ call void (...) @llvm.fake.use(<4 x bfloat> %result5)
+ %result6 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 6
+ call void (...) @llvm.fake.use(<4 x bfloat> %result6)
+ %result7 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 7
+ call void (...) @llvm.fake.use(<4 x bfloat> %result7)
+ ret void
+}
+
+
+define void @deinterleave2_v8bf16(<16 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave2_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r12, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh lr, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r8, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r5, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r9
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call { <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave2(<16 x bfloat> %vec)
+ %result0 = extractvalue { <8 x bfloat>, <8 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<8 x bfloat> %result0)
+ %result1 = extractvalue { <8 x bfloat>, <8 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<8 x bfloat> %result1)
+ ret void
+}
+
+define void @deinterleave3_v8bf16(<24 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave3_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r3, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r3, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r12, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave3(<24 x bfloat> %vec)
+ %result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<8 x bfloat> %result0)
+ %result1 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<8 x bfloat> %result1)
+ %result2 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<8 x bfloat> %result2)
+ ret void
+}
+
+define void @deinterleave4_v8bf16(<32 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave4_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r1, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r6, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r2, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh lr, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r7, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r1, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave4(<32 x bfloat> %vec)
+ %result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<8 x bfloat> %result0)
+ %result1 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<8 x bfloat> %result1)
+ %result2 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<8 x bfloat> %result2)
+ %result3 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 3
+ call void (...) @llvm.fake.use(<8 x bfloat> %result3)
+ ret void
+}
+
+define void @deinterleave6_v8bf16(<48 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave6_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #84]
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #180]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #152]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #112]
+; CHECK-NEXT: ldrh r2, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r1, [sp, #184]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r0, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #156]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #164]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #188]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #160]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r2, [sp, #144]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r3, [sp, #168]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r0, [sp, #192]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r12, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh lr, [sp, #148]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r8, [sp, #172]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r5, [sp, #196]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r7, [sp, #176]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave6(<48 x bfloat> %vec)
+ %result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<8 x bfloat> %result0)
+ %result1 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<8 x bfloat> %result1)
+ %result2 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<8 x bfloat> %result2)
+ %result3 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 3
+ call void (...) @llvm.fake.use(<8 x bfloat> %result3)
+ %result4 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 4
+ call void (...) @llvm.fake.use(<8 x bfloat> %result4)
+ %result5 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 5
+ call void (...) @llvm.fake.use(<8 x bfloat> %result5)
+ ret void
+}
+
+define void @deinterleave8_v8bf16(<64 x bfloat> %vec) {
+; CHECK-LABEL: deinterleave8_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #144]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #244]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #152]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #252]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: add r0, sp, #256
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #148]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #184]
+; CHECK-NEXT: ldrh r0, [r0]
+; CHECK-NEXT: add r4, sp, #256
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #248]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #156]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #188]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: add r0, sp, #256
+; CHECK-NEXT: ldrh r3, [sp, #220]
+; CHECK-NEXT: ldrh r5, [r4, #12]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #96]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #208]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #160]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #192]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #224]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [r0, #4]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r2, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #100]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r0, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r6, [sp, #176]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r4, [sp, #212]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: add r0, sp, #256
+; CHECK-NEXT: ldrh r1, [sp, #164]
+; CHECK-NEXT: ldrh r2, [sp, #196]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r3, [sp, #228]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r6, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r1, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r2, [sp, #72]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r3, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r7, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r6, [sp, #180]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r4, [sp, #216]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r1, [sp, #168]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r2, [sp, #200]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r3, [sp, #232]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r0, [r0, #8]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r12, [sp, #172]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh lr, [sp, #204]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r8, [sp, #236]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r7, [sp, #240]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r6, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r3, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+ %result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave8(<64 x bfloat> %vec)
+ %result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
+ call void (...) @llvm.fake.use(<8 x bfloat> %result0)
+ %result1 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 1
+ call void (...) @llvm.fake.use(<8 x bfloat> %result1)
+ %result2 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 2
+ call void (...) @llvm.fake.use(<8 x bfloat> %result2)
+ %result3 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 3
+ call void (...) @llvm.fake.use(<8 x bfloat> %result3)
+ %result4 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 4
+ call void (...) @llvm.fake.use(<8 x bfloat> %result4)
+ %result5 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 5
+ call void (...) @llvm.fake.use(<8 x bfloat> %result5)
+ %result6 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 6
+ call void (...) @llvm.fake.use(<8 x bfloat> %result6)
+ %result7 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 7
+ call void (...) @llvm.fake.use(<8 x bfloat> %result7)
+ ret void
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/fixed-vector-interleave.ll b/llvm/test/CodeGen/ARM/fixed-vector-interleave.ll
new file mode 100644
index 0000000000000..67138f8a21607
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fixed-vector-interleave.ll
@@ -0,0 +1,2444 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
+; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
+
+define <16 x i8> @interleave2_v8i8(<8 x i8> %vec0, <8 x i8> %vec1) {
+; CHECK-LABEL: interleave2_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vzip.8 d17, d16
+; CHECK-NEXT: vmov r0, r1, d17
+; CHECK-NEXT: vmov r2, r3, d16
+; CHECK-NEXT: bx lr
+ %result = call <16 x i8> @llvm.vector.interleave2(<8 x i8> %vec0, <8 x i8> %vec1)
+ ret <16 x i8> %result
+}
+
+define <24 x i8> @interleave3_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2) {
+; CHECK-LABEL: interleave3_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: vldr d18, [sp, #32]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <24 x i8> @llvm.vector.interleave3(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2)
+ ret <24 x i8> %result
+}
+
+define <32 x i8> @interleave4_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3) {
+; CHECK-LABEL: interleave4_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp, #16]
+; CHECK-NEXT: vldr d19, [sp]
+; CHECK-NEXT: vldr d16, [sp, #8]
+; CHECK-NEXT: vmov d18, r2, r3
+; CHECK-NEXT: vzip.8 d19, d17
+; CHECK-NEXT: vzip.8 d18, d16
+; CHECK-NEXT: vzip.8 d18, d19
+; CHECK-NEXT: vzip.8 d16, d17
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x i8> @llvm.vector.interleave4(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3)
+ ret <32 x i8> %result
+}
+
+define <48 x i8> @interleave6_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5) {
+; CHECK-LABEL: interleave6_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vldr d22, [sp, #56]
+; CHECK-NEXT: add r1, sp, #64
+; CHECK-NEXT: vldr d21, [sp, #48]
+; CHECK-NEXT: vmov d20, r2, r3
+; CHECK-NEXT: vldmia r1, {d16, d17, d18}
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vzip.8 d22, d18
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vzip.8 d21, d17
+; CHECK-NEXT: vzip.8 d20, d16
+; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.8 {d20, d21, d22}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <48 x i8> @llvm.vector.interleave6(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5)
+ ret <48 x i8> %result
+}
+
+define <64 x i8> @interleave8_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5, <8 x i8> %vec6, <8 x i8> %vec7) {
+; CHECK-LABEL: interleave8_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vldr d17, [sp, #48]
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vldr d16, [sp, #40]
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
+; CHECK-NEXT: vzip.8 d19, d17
+; CHECK-NEXT: vzip.8 d23, d21
+; CHECK-NEXT: vzip.8 d18, d16
+; CHECK-NEXT: vzip.8 d22, d20
+; CHECK-NEXT: vzip.8 d23, d19
+; CHECK-NEXT: vzip.8 d22, d18
+; CHECK-NEXT: vzip.8 d21, d17
+; CHECK-NEXT: vzip.8 d20, d16
+; CHECK-NEXT: vzip.8 d22, d23
+; CHECK-NEXT: vzip.8 d18, d19
+; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vzip.8 d20, d21
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vzip.8 d16, d17
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <64 x i8> @llvm.vector.interleave8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5, <8 x i8> %vec6, <8 x i8> %vec7)
+ ret <64 x i8> %result
+}
+
+
+define <8 x i16> @interleave2_v4i16(<4 x i16> %vec0, <4 x i16> %vec1) {
+; CHECK-LABEL: interleave2_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vzip.16 d17, d16
+; CHECK-NEXT: vmov r0, r1, d17
+; CHECK-NEXT: vmov r2, r3, d16
+; CHECK-NEXT: bx lr
+ %result = call <8 x i16> @llvm.vector.interleave2(<4 x i16> %vec0, <4 x i16> %vec1)
+ ret <8 x i16> %result
+}
+
+define <12 x i16> @interleave3_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
+; CHECK-LABEL: interleave3_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: vldr d18, [sp, #32]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vst3.16 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <12 x i16> @llvm.vector.interleave3(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2)
+ ret <12 x i16> %result
+}
+
+define <16 x i16> @interleave4_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3) {
+; CHECK-LABEL: interleave4_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp, #16]
+; CHECK-NEXT: vldr d19, [sp]
+; CHECK-NEXT: vldr d16, [sp, #8]
+; CHECK-NEXT: vmov d18, r2, r3
+; CHECK-NEXT: vzip.16 d19, d17
+; CHECK-NEXT: vzip.16 d18, d16
+; CHECK-NEXT: vzip.16 d18, d19
+; CHECK-NEXT: vzip.16 d16, d17
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <16 x i16> @llvm.vector.interleave4(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3)
+ ret <16 x i16> %result
+}
+
+define <24 x i16> @interleave6_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5) {
+; CHECK-LABEL: interleave6_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vldr d22, [sp, #56]
+; CHECK-NEXT: add r1, sp, #64
+; CHECK-NEXT: vldr d21, [sp, #48]
+; CHECK-NEXT: vmov d20, r2, r3
+; CHECK-NEXT: vldmia r1, {d16, d17, d18}
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vzip.16 d22, d18
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vzip.16 d21, d17
+; CHECK-NEXT: vzip.16 d20, d16
+; CHECK-NEXT: vst3.16 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.16 {d20, d21, d22}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <24 x i16> @llvm.vector.interleave6(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5)
+ ret <24 x i16> %result
+}
+
+define <32 x i16> @interleave8_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5, <4 x i16> %vec6, <4 x i16> %vec7) {
+; CHECK-LABEL: interleave8_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vldr d17, [sp, #48]
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vldr d16, [sp, #40]
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
+; CHECK-NEXT: vzip.16 d19, d17
+; CHECK-NEXT: vzip.16 d23, d21
+; CHECK-NEXT: vzip.16 d18, d16
+; CHECK-NEXT: vzip.16 d22, d20
+; CHECK-NEXT: vzip.16 d23, d19
+; CHECK-NEXT: vzip.16 d22, d18
+; CHECK-NEXT: vzip.16 d21, d17
+; CHECK-NEXT: vzip.16 d20, d16
+; CHECK-NEXT: vzip.16 d22, d23
+; CHECK-NEXT: vzip.16 d18, d19
+; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vzip.16 d20, d21
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vzip.16 d16, d17
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x i16> @llvm.vector.interleave8(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5, <4 x i16> %vec6, <4 x i16> %vec7)
+ ret <32 x i16> %result
+}
+
+
+define <4 x i32> @interleave2_v2i32(<2 x i32> %vec0, <2 x i32> %vec1) {
+; CHECK-LABEL: interleave2_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: vmov r0, r1, d17
+; CHECK-NEXT: vmov r2, r3, d16
+; CHECK-NEXT: bx lr
+ %result = call <4 x i32> @llvm.vector.interleave2(<2 x i32> %vec0, <2 x i32> %vec1)
+ ret <4 x i32> %result
+}
+
+define <6 x i32> @interleave3_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) {
+; CHECK-LABEL: interleave3_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: vldr d18, [sp, #32]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <6 x i32> @llvm.vector.interleave3(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2)
+ ret <6 x i32> %result
+}
+
+define <8 x i32> @interleave4_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3) {
+; CHECK-LABEL: interleave4_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp, #16]
+; CHECK-NEXT: vldr d19, [sp]
+; CHECK-NEXT: vldr d16, [sp, #8]
+; CHECK-NEXT: vmov d18, r2, r3
+; CHECK-NEXT: vtrn.32 d19, d17
+; CHECK-NEXT: vtrn.32 d18, d16
+; CHECK-NEXT: vtrn.32 d18, d19
+; CHECK-NEXT: vtrn.32 d16, d17
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <8 x i32> @llvm.vector.interleave4(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3)
+ ret <8 x i32> %result
+}
+
+define <12 x i32> @interleave6_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5) {
+; CHECK-LABEL: interleave6_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vldr d22, [sp, #56]
+; CHECK-NEXT: add r1, sp, #64
+; CHECK-NEXT: vldr d21, [sp, #48]
+; CHECK-NEXT: vmov d20, r2, r3
+; CHECK-NEXT: vldmia r1, {d16, d17, d18}
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vtrn.32 d22, d18
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vtrn.32 d21, d17
+; CHECK-NEXT: vtrn.32 d20, d16
+; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.32 {d20, d21, d22}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <12 x i32> @llvm.vector.interleave6(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5)
+ ret <12 x i32> %result
+}
+
+define <16 x i32> @interleave8_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5, <2 x i32> %vec6, <2 x i32> %vec7) {
+; CHECK-LABEL: interleave8_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vldr d17, [sp, #48]
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vldr d16, [sp, #40]
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
+; CHECK-NEXT: vtrn.32 d19, d17
+; CHECK-NEXT: vtrn.32 d23, d21
+; CHECK-NEXT: vtrn.32 d18, d16
+; CHECK-NEXT: vtrn.32 d22, d20
+; CHECK-NEXT: vtrn.32 d23, d19
+; CHECK-NEXT: vtrn.32 d22, d18
+; CHECK-NEXT: vtrn.32 d21, d17
+; CHECK-NEXT: vtrn.32 d20, d16
+; CHECK-NEXT: vtrn.32 d22, d23
+; CHECK-NEXT: vtrn.32 d18, d19
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vtrn.32 d20, d21
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vtrn.32 d16, d17
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <16 x i32> @llvm.vector.interleave8(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5, <2 x i32> %vec6, <2 x i32> %vec7)
+ ret <16 x i32> %result
+}
+
+
+define <4 x float> @interleave2_v2f32(<2 x float> %vec0, <2 x float> %vec1) {
+; CHECK-LABEL: interleave2_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vmov d17, r0, r1
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: vmov r0, r1, d17
+; CHECK-NEXT: vmov r2, r3, d16
+; CHECK-NEXT: bx lr
+ %result = call <4 x float> @llvm.vector.interleave2(<2 x float> %vec0, <2 x float> %vec1)
+ ret <4 x float> %result
+}
+
+define <6 x float> @interleave3_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2) {
+; CHECK-LABEL: interleave3_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: vldr d18, [sp, #32]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <6 x float> @llvm.vector.interleave3(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2)
+ ret <6 x float> %result
+}
+
+define <8 x float> @interleave4_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3) {
+; CHECK-LABEL: interleave4_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp, #16]
+; CHECK-NEXT: vldr d19, [sp]
+; CHECK-NEXT: vldr d16, [sp, #8]
+; CHECK-NEXT: vmov d18, r2, r3
+; CHECK-NEXT: vtrn.32 d19, d17
+; CHECK-NEXT: vtrn.32 d18, d16
+; CHECK-NEXT: vtrn.32 d18, d19
+; CHECK-NEXT: vtrn.32 d16, d17
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <8 x float> @llvm.vector.interleave4(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3)
+ ret <8 x float> %result
+}
+
+define <12 x float> @interleave6_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5) {
+; CHECK-LABEL: interleave6_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vldr d22, [sp, #56]
+; CHECK-NEXT: add r1, sp, #64
+; CHECK-NEXT: vldr d21, [sp, #48]
+; CHECK-NEXT: vmov d20, r2, r3
+; CHECK-NEXT: vldmia r1, {d16, d17, d18}
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: vtrn.32 d22, d18
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vtrn.32 d21, d17
+; CHECK-NEXT: vtrn.32 d20, d16
+; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.32 {d20, d21, d22}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <12 x float> @llvm.vector.interleave6(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5)
+ ret <12 x float> %result
+}
+
+define <16 x float> @interleave8_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5, <2 x float> %vec6, <2 x float> %vec7) {
+; CHECK-LABEL: interleave8_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vldr d17, [sp, #48]
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vldr d16, [sp, #40]
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
+; CHECK-NEXT: vtrn.32 d19, d17
+; CHECK-NEXT: vtrn.32 d23, d21
+; CHECK-NEXT: vtrn.32 d18, d16
+; CHECK-NEXT: vtrn.32 d22, d20
+; CHECK-NEXT: vtrn.32 d23, d19
+; CHECK-NEXT: vtrn.32 d22, d18
+; CHECK-NEXT: vtrn.32 d21, d17
+; CHECK-NEXT: vtrn.32 d20, d16
+; CHECK-NEXT: vtrn.32 d22, d23
+; CHECK-NEXT: vtrn.32 d18, d19
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vtrn.32 d20, d21
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vtrn.32 d16, d17
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <16 x float> @llvm.vector.interleave8(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5, <2 x float> %vec6, <2 x float> %vec7)
+ ret <16 x float> %result
+}
+
+
+define <32 x i8> @interleave2_v16i8(<16 x i8> %vec0, <16 x i8> %vec1) {
+; CHECK-LABEL: interleave2_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vzip.8 q8, q9
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x i8> @llvm.vector.interleave2(<16 x i8> %vec0, <16 x i8> %vec1)
+ ret <32 x i8> %result
+}
+
+define <48 x i8> @interleave3_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2) {
+; CHECK-LABEL: interleave3_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vst3.8 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.8 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <48 x i8> @llvm.vector.interleave3(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2)
+ ret <48 x i8> %result
+}
+
+define <64 x i8> @interleave4_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3) {
+; CHECK-LABEL: interleave4_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vzip.8 q9, q8
+; CHECK-NEXT: vzip.8 q11, q10
+; CHECK-NEXT: vzip.8 q11, q9
+; CHECK-NEXT: vzip.8 q10, q8
+; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <64 x i8> @llvm.vector.interleave4(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3)
+ ret <64 x i8> %result
+}
+
+define <96 x i8> @interleave6_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5) {
+; CHECK-LABEL: interleave6_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #76
+; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #60
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, r11, #44
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.8 q10, q14
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.8 q9, q13
+; CHECK-NEXT: vzip.8 q8, q12
+; CHECK-NEXT: vst3.8 {d24, d26, d28}, [r2:64]!
+; CHECK-NEXT: vst3.8 {d25, d27, d29}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst3.8 {d16, d18, d20}, [r3:64]!
+; CHECK-NEXT: vst3.8 {d17, d19, d21}, [r3:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d24, d25}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <96 x i8> @llvm.vector.interleave6(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5)
+ ret <96 x i8> %result
+}
+
+define <128 x i8> @interleave8_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5, <16 x i8> %vec6, <16 x i8> %vec7) {
+; CHECK-LABEL: interleave8_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #104
+; CHECK-NEXT: vldr d29, [sp]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vmov d28, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #72
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, sp, #88
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, sp, #56
+; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.8 q8, q9
+; CHECK-NEXT: vzip.8 q10, q12
+; CHECK-NEXT: vzip.8 q11, q13
+; CHECK-NEXT: vzip.8 q14, q15
+; CHECK-NEXT: vzip.8 q12, q9
+; CHECK-NEXT: vzip.8 q15, q13
+; CHECK-NEXT: vzip.8 q10, q8
+; CHECK-NEXT: vzip.8 q14, q11
+; CHECK-NEXT: vzip.8 q15, q12
+; CHECK-NEXT: vzip.8 q13, q9
+; CHECK-NEXT: vst1.8 {d30, d31}, [r1:128]!
+; CHECK-NEXT: vzip.8 q14, q10
+; CHECK-NEXT: vst1.8 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst1.8 {d26, d27}, [r1:128]!
+; CHECK-NEXT: vzip.8 q11, q8
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
+; CHECK-NEXT: vst1.8 {d28, d29}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <128 x i8> @llvm.vector.interleave8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5, <16 x i8> %vec6, <16 x i8> %vec7)
+ ret <128 x i8> %result
+}
+
+
+define <16 x i16> @interleave2_v8i16(<8 x i16> %vec0, <8 x i16> %vec1) {
+; CHECK-LABEL: interleave2_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vzip.16 q8, q9
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <16 x i16> @llvm.vector.interleave2(<8 x i16> %vec0, <8 x i16> %vec1)
+ ret <16 x i16> %result
+}
+
+define <24 x i16> @interleave3_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2) {
+; CHECK-LABEL: interleave3_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vst3.16 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.16 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <24 x i16> @llvm.vector.interleave3(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2)
+ ret <24 x i16> %result
+}
+
+define <32 x i16> @interleave4_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3) {
+; CHECK-LABEL: interleave4_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vzip.16 q9, q8
+; CHECK-NEXT: vzip.16 q11, q10
+; CHECK-NEXT: vzip.16 q11, q9
+; CHECK-NEXT: vzip.16 q10, q8
+; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x i16> @llvm.vector.interleave4(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3)
+ ret <32 x i16> %result
+}
+
+define <48 x i16> @interleave6_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5) {
+; CHECK-LABEL: interleave6_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #76
+; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #60
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, r11, #44
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.16 q10, q14
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.16 q9, q13
+; CHECK-NEXT: vzip.16 q8, q12
+; CHECK-NEXT: vst3.16 {d24, d26, d28}, [r2:64]!
+; CHECK-NEXT: vst3.16 {d25, d27, d29}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst3.16 {d16, d18, d20}, [r3:64]!
+; CHECK-NEXT: vst3.16 {d17, d19, d21}, [r3:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d24, d25}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <48 x i16> @llvm.vector.interleave6(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5)
+ ret <48 x i16> %result
+}
+
+define <64 x i16> @interleave8_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5, <8 x i16> %vec6, <8 x i16> %vec7) {
+; CHECK-LABEL: interleave8_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #104
+; CHECK-NEXT: vldr d29, [sp]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vmov d28, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #72
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, sp, #88
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, sp, #56
+; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.16 q8, q9
+; CHECK-NEXT: vzip.16 q10, q12
+; CHECK-NEXT: vzip.16 q11, q13
+; CHECK-NEXT: vzip.16 q14, q15
+; CHECK-NEXT: vzip.16 q12, q9
+; CHECK-NEXT: vzip.16 q15, q13
+; CHECK-NEXT: vzip.16 q10, q8
+; CHECK-NEXT: vzip.16 q14, q11
+; CHECK-NEXT: vzip.16 q15, q12
+; CHECK-NEXT: vzip.16 q13, q9
+; CHECK-NEXT: vst1.16 {d30, d31}, [r1:128]!
+; CHECK-NEXT: vzip.16 q14, q10
+; CHECK-NEXT: vst1.16 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst1.16 {d26, d27}, [r1:128]!
+; CHECK-NEXT: vzip.16 q11, q8
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
+; CHECK-NEXT: vst1.16 {d28, d29}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <64 x i16> @llvm.vector.interleave8(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5, <8 x i16> %vec6, <8 x i16> %vec7)
+ ret <64 x i16> %result
+}
+
+define <8 x i32> @interleave2_v4i32(<4 x i32> %vec0, <4 x i32> %vec1) {
+; CHECK-LABEL: interleave2_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vzip.32 q8, q9
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <8 x i32> @llvm.vector.interleave2(<4 x i32> %vec0, <4 x i32> %vec1)
+ ret <8 x i32> %result
+}
+
+define <12 x i32> @interleave3_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2) {
+; CHECK-LABEL: interleave3_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <12 x i32> @llvm.vector.interleave3(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2)
+ ret <12 x i32> %result
+}
+
+define <16 x i32> @interleave4_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3) {
+; CHECK-LABEL: interleave4_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vzip.32 q9, q8
+; CHECK-NEXT: vzip.32 q11, q10
+; CHECK-NEXT: vzip.32 q11, q9
+; CHECK-NEXT: vzip.32 q10, q8
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <16 x i32> @llvm.vector.interleave4(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3)
+ ret <16 x i32> %result
+}
+
+define <24 x i32> @interleave6_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5) {
+; CHECK-LABEL: interleave6_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #76
+; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #60
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, r11, #44
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.32 q10, q14
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.32 q9, q13
+; CHECK-NEXT: vzip.32 q8, q12
+; CHECK-NEXT: vst3.32 {d24, d26, d28}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d25, d27, d29}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r3:64]!
+; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r3:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d24, d25}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <24 x i32> @llvm.vector.interleave6(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5)
+ ret <24 x i32> %result
+}
+
+define <32 x i32> @interleave8_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7) {
+; CHECK-LABEL: interleave8_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #104
+; CHECK-NEXT: vldr d29, [sp]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vmov d28, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #72
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, sp, #88
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, sp, #56
+; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.32 q8, q9
+; CHECK-NEXT: vzip.32 q10, q12
+; CHECK-NEXT: vzip.32 q11, q13
+; CHECK-NEXT: vzip.32 q14, q15
+; CHECK-NEXT: vzip.32 q12, q9
+; CHECK-NEXT: vzip.32 q15, q13
+; CHECK-NEXT: vzip.32 q10, q8
+; CHECK-NEXT: vzip.32 q14, q11
+; CHECK-NEXT: vzip.32 q15, q12
+; CHECK-NEXT: vzip.32 q13, q9
+; CHECK-NEXT: vst1.32 {d30, d31}, [r1:128]!
+; CHECK-NEXT: vzip.32 q14, q10
+; CHECK-NEXT: vst1.32 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst1.32 {d26, d27}, [r1:128]!
+; CHECK-NEXT: vzip.32 q11, q8
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
+; CHECK-NEXT: vst1.32 {d28, d29}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x i32> @llvm.vector.interleave8(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7)
+ ret <32 x i32> %result
+}
+
+
+define <8 x float> @interleave2_v4f32(<4 x float> %vec0, <4 x float> %vec1) {
+; CHECK-LABEL: interleave2_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vldr d17, [sp]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: vzip.32 q8, q9
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <8 x float> @llvm.vector.interleave2(<4 x float> %vec0, <4 x float> %vec1)
+ ret <8 x float> %result
+}
+
+define <12 x float> @interleave3_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2) {
+; CHECK-LABEL: interleave3_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <12 x float> @llvm.vector.interleave3(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2)
+ ret <12 x float> %result
+}
+
+define <16 x float> @interleave4_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3) {
+; CHECK-LABEL: interleave4_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vldr d23, [sp]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vmov d22, r2, r3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vzip.32 q9, q8
+; CHECK-NEXT: vzip.32 q11, q10
+; CHECK-NEXT: vzip.32 q11, q9
+; CHECK-NEXT: vzip.32 q10, q8
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <16 x float> @llvm.vector.interleave4(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3)
+ ret <16 x float> %result
+}
+
+define <24 x float> @interleave6_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5) {
+; CHECK-LABEL: interleave6_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: add r1, r11, #76
+; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
+; CHECK-NEXT: add r1, r11, #28
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #60
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, r11, #12
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, r11, #44
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.32 q10, q14
+; CHECK-NEXT: vldr d17, [r11, #4]
+; CHECK-NEXT: vmov d16, r2, r3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.32 q9, q13
+; CHECK-NEXT: vzip.32 q8, q12
+; CHECK-NEXT: vst3.32 {d24, d26, d28}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d25, d27, d29}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r3:64]!
+; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r3:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d24, d25}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <24 x float> @llvm.vector.interleave6(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5)
+ ret <24 x float> %result
+}
+
+define <32 x float> @interleave8_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5, <4 x float> %vec6, <4 x float> %vec7) {
+; CHECK-LABEL: interleave8_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #104
+; CHECK-NEXT: vldr d29, [sp]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #40
+; CHECK-NEXT: vmov d28, r2, r3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #72
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: add r1, sp, #8
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, sp, #88
+; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, sp, #56
+; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.32 q8, q9
+; CHECK-NEXT: vzip.32 q10, q12
+; CHECK-NEXT: vzip.32 q11, q13
+; CHECK-NEXT: vzip.32 q14, q15
+; CHECK-NEXT: vzip.32 q12, q9
+; CHECK-NEXT: vzip.32 q15, q13
+; CHECK-NEXT: vzip.32 q10, q8
+; CHECK-NEXT: vzip.32 q14, q11
+; CHECK-NEXT: vzip.32 q15, q12
+; CHECK-NEXT: vzip.32 q13, q9
+; CHECK-NEXT: vst1.32 {d30, d31}, [r1:128]!
+; CHECK-NEXT: vzip.32 q14, q10
+; CHECK-NEXT: vst1.32 {d24, d25}, [r1:128]!
+; CHECK-NEXT: vst1.32 {d26, d27}, [r1:128]!
+; CHECK-NEXT: vzip.32 q11, q8
+; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
+; CHECK-NEXT: vst1.32 {d28, d29}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x float> @llvm.vector.interleave8(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5, <4 x float> %vec6, <4 x float> %vec7)
+ ret <32 x float> %result
+}
+
+
+define <8 x half> @interleave2_v4f16(<4 x half> %vec0, <4 x half> %vec1) {
+; CHECK-LABEL: interleave2_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: ldrh r1, [sp, #20]
+; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: ldrh lr, [sp, #16]
+; CHECK-NEXT: ldrh r4, [sp, #28]
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: strh r6, [r0, #14]
+; CHECK-NEXT: strh r1, [r0, #12]
+; CHECK-NEXT: strh r12, [r0, #10]
+; CHECK-NEXT: strh lr, [r0, #8]
+; CHECK-NEXT: strh r4, [r0, #6]
+; CHECK-NEXT: strh r3, [r0, #4]
+; CHECK-NEXT: strh r5, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <8 x half> @llvm.vector.interleave2(<4 x half> %vec0, <4 x half> %vec1)
+ ret <8 x half> %result
+}
+
+define <12 x half> @interleave3_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2) {
+; CHECK-LABEL: interleave3_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r12, [sp, #60]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh lr, [sp, #40]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #28]
+; CHECK-NEXT: ldrh r6, [sp, #56]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: ldrh r4, [sp, #52]
+; CHECK-NEXT: ldrh r5, [sp, #36]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r8, [sp, #32]
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: str r7, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r5, r4, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r6, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r8, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call <12 x half> @llvm.vector.interleave3(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2)
+ ret <12 x half> %result
+}
+
+define <16 x half> @interleave4_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3) {
+; CHECK-LABEL: interleave4_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: ldrh r7, [sp, #92]
+; CHECK-NEXT: ldrh r1, [sp, #76]
+; CHECK-NEXT: ldrh r12, [sp, #60]
+; CHECK-NEXT: ldrh lr, [sp, #44]
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: strh r7, [r0, #30]
+; CHECK-NEXT: strh r1, [r0, #28]
+; CHECK-NEXT: strh r12, [r0, #26]
+; CHECK-NEXT: strh lr, [r0, #24]
+; CHECK-NEXT: strh r4, [r0, #22]
+; CHECK-NEXT: ldrh r9, [sp, #72]
+; CHECK-NEXT: ldrh r8, [sp, #56]
+; CHECK-NEXT: ldrh r10, [sp, #40]
+; CHECK-NEXT: ldrh r11, [sp, #84]
+; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: ldrh r5, [sp, #52]
+; CHECK-NEXT: ldrh r4, [sp, #80]
+; CHECK-NEXT: ldrh r7, [sp, #64]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: strh r9, [r0, #20]
+; CHECK-NEXT: strh r8, [r0, #18]
+; CHECK-NEXT: strh r10, [r0, #16]
+; CHECK-NEXT: strh r11, [r0, #14]
+; CHECK-NEXT: strh r6, [r0, #12]
+; CHECK-NEXT: strh r5, [r0, #10]
+; CHECK-NEXT: strh r3, [r0, #8]
+; CHECK-NEXT: strh r4, [r0, #6]
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: strh r1, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: add sp, sp, #4
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+ %result = call <16 x half> @llvm.vector.interleave4(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3)
+ ret <16 x half> %result
+}
+
+define <24 x half> @interleave6_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5) {
+; CHECK-LABEL: interleave6_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r12, [sp, #116]
+; CHECK-NEXT: ldrh r1, [sp, #100]
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: ldrh r7, [sp, #84]
+; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r9, [sp, #80]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #40]
+; CHECK-NEXT: str r1, [r0, #36]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: ldrh r4, [sp, #112]
+; CHECK-NEXT: ldrh r7, [sp, #96]
+; CHECK-NEXT: orr r1, r1, r9, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #108]
+; CHECK-NEXT: orr r7, r7, r4, lsl #16
+; CHECK-NEXT: str r7, [r0, #32]
+; CHECK-NEXT: str r1, [r0, #28]
+; CHECK-NEXT: ldrh r1, [sp, #92]
+; CHECK-NEXT: ldrh r8, [sp, #48]
+; CHECK-NEXT: ldrh r7, [sp, #32]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: orr r7, r7, r8, lsl #16
+; CHECK-NEXT: str r7, [r0, #24]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r12, [sp, #104]
+; CHECK-NEXT: ldrh r7, [sp, #60]
+; CHECK-NEXT: ldrh r9, [sp, #72]
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #88]
+; CHECK-NEXT: orr r7, r7, lr, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: str r7, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r5, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r4, r9, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r6, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <24 x half> @llvm.vector.interleave6(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5)
+ ret <24 x half> %result
+}
+
+define <32 x half> @interleave8_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5, <4 x half> %vec6, <4 x half> %vec7) {
+; CHECK-LABEL: interleave8_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r7, [sp, #148]
+; CHECK-NEXT: strh r7, [r0, #62]
+; CHECK-NEXT: ldrh r1, [sp, #132]
+; CHECK-NEXT: ldrh r12, [sp, #116]
+; CHECK-NEXT: ldrh lr, [sp, #100]
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: ldrh r9, [sp, #68]
+; CHECK-NEXT: ldrh r8, [sp, #52]
+; CHECK-NEXT: ldrh r7, [sp, #36]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r12, [r0, #58]
+; CHECK-NEXT: strh lr, [r0, #56]
+; CHECK-NEXT: strh r4, [r0, #54]
+; CHECK-NEXT: strh r9, [r0, #52]
+; CHECK-NEXT: strh r8, [r0, #50]
+; CHECK-NEXT: strh r7, [r0, #48]
+; CHECK-NEXT: ldrh r1, [sp, #144]
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: ldrh r5, [sp, #112]
+; CHECK-NEXT: ldrh r4, [sp, #96]
+; CHECK-NEXT: ldrh r12, [sp, #80]
+; CHECK-NEXT: ldrh lr, [sp, #64]
+; CHECK-NEXT: ldrh r7, [sp, #48]
+; CHECK-NEXT: strh r1, [r0, #46]
+; CHECK-NEXT: strh r6, [r0, #44]
+; CHECK-NEXT: strh r5, [r0, #42]
+; CHECK-NEXT: strh r4, [r0, #40]
+; CHECK-NEXT: strh r12, [r0, #38]
+; CHECK-NEXT: strh lr, [r0, #36]
+; CHECK-NEXT: strh r7, [r0, #34]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: ldrh r6, [sp, #140]
+; CHECK-NEXT: ldrh r5, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #108]
+; CHECK-NEXT: ldrh r12, [sp, #92]
+; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: ldrh r7, [sp, #60]
+; CHECK-NEXT: ldrh r9, [sp, #44]
+; CHECK-NEXT: strh r1, [r0, #32]
+; CHECK-NEXT: strh r6, [r0, #30]
+; CHECK-NEXT: strh r5, [r0, #28]
+; CHECK-NEXT: strh r4, [r0, #26]
+; CHECK-NEXT: strh r12, [r0, #24]
+; CHECK-NEXT: strh lr, [r0, #22]
+; CHECK-NEXT: strh r7, [r0, #20]
+; CHECK-NEXT: strh r9, [r0, #18]
+; CHECK-NEXT: strh r3, [r0, #16]
+; CHECK-NEXT: ldrh r8, [sp, #136]
+; CHECK-NEXT: ldrh r5, [sp, #120]
+; CHECK-NEXT: ldrh r4, [sp, #104]
+; CHECK-NEXT: ldrh r6, [sp, #88]
+; CHECK-NEXT: ldrh r1, [sp, #72]
+; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: strh r8, [r0, #14]
+; CHECK-NEXT: strh r5, [r0, #12]
+; CHECK-NEXT: strh r4, [r0, #10]
+; CHECK-NEXT: strh r6, [r0, #8]
+; CHECK-NEXT: strh r1, [r0, #6]
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: strh r3, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <32 x half> @llvm.vector.interleave8(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5, <4 x half> %vec6, <4 x half> %vec7)
+ ret <32 x half> %result
+}
+
+
+define <16 x half> @interleave2_v8f16(<8 x half> %vec0, <8 x half> %vec1) {
+; CHECK-LABEL: interleave2_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: ldrh r7, [sp, #92]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r12, [sp, #88]
+; CHECK-NEXT: ldrh lr, [sp, #56]
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: strh r7, [r0, #30]
+; CHECK-NEXT: strh r1, [r0, #28]
+; CHECK-NEXT: strh r12, [r0, #26]
+; CHECK-NEXT: strh lr, [r0, #24]
+; CHECK-NEXT: strh r4, [r0, #22]
+; CHECK-NEXT: ldrh r9, [sp, #52]
+; CHECK-NEXT: ldrh r8, [sp, #80]
+; CHECK-NEXT: ldrh r10, [sp, #48]
+; CHECK-NEXT: ldrh r11, [sp, #76]
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: ldrh r5, [sp, #72]
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: ldrh r7, [sp, #68]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: strh r9, [r0, #20]
+; CHECK-NEXT: strh r8, [r0, #18]
+; CHECK-NEXT: strh r10, [r0, #16]
+; CHECK-NEXT: strh r11, [r0, #14]
+; CHECK-NEXT: strh r6, [r0, #12]
+; CHECK-NEXT: strh r5, [r0, #10]
+; CHECK-NEXT: strh r4, [r0, #8]
+; CHECK-NEXT: strh r7, [r0, #6]
+; CHECK-NEXT: strh r3, [r0, #4]
+; CHECK-NEXT: strh r1, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: add sp, sp, #4
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+ %result = call <16 x half> @llvm.vector.interleave2(<8 x half> %vec0, <8 x half> %vec1)
+ ret <16 x half> %result
+}
+
+define <24 x half> @interleave3_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2) {
+; CHECK-LABEL: interleave3_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: ldrh r12, [sp, #116]
+; CHECK-NEXT: ldrh r1, [sp, #84]
+; CHECK-NEXT: ldrh lr, [sp, #80]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: ldrh r6, [sp, #112]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r9, [sp, #44]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #40]
+; CHECK-NEXT: str r1, [r0, #36]
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r4, [sp, #108]
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: orr r1, r1, r9, lsl #16
+; CHECK-NEXT: ldrh r10, [sp, #100]
+; CHECK-NEXT: orr r7, r7, r4, lsl #16
+; CHECK-NEXT: str r7, [r0, #32]
+; CHECK-NEXT: str r1, [r0, #28]
+; CHECK-NEXT: ldrh r1, [sp, #68]
+; CHECK-NEXT: ldrh r8, [sp, #72]
+; CHECK-NEXT: ldrh r7, [sp, #40]
+; CHECK-NEXT: orr r1, r1, r10, lsl #16
+; CHECK-NEXT: ldrh lr, [sp, #64]
+; CHECK-NEXT: orr r7, r7, r8, lsl #16
+; CHECK-NEXT: str r7, [r0, #24]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: ldrh r9, [sp, #92]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #96]
+; CHECK-NEXT: ldrh r6, [sp, #60]
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: orr r7, r7, r12, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #88]
+; CHECK-NEXT: str r7, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r6, r9, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r5, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r4, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+ %result = call <24 x half> @llvm.vector.interleave3(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2)
+ ret <24 x half> %result
+}
+
+define <32 x half> @interleave4_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3) {
+; CHECK-LABEL: interleave4_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: ldrh r7, [sp, #148]
+; CHECK-NEXT: strh r7, [r0, #62]
+; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: ldrh r12, [sp, #84]
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: ldrh r4, [sp, #144]
+; CHECK-NEXT: ldrh r9, [sp, #112]
+; CHECK-NEXT: ldrh r8, [sp, #80]
+; CHECK-NEXT: ldrh r7, [sp, #48]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r12, [r0, #58]
+; CHECK-NEXT: strh lr, [r0, #56]
+; CHECK-NEXT: strh r4, [r0, #54]
+; CHECK-NEXT: strh r9, [r0, #52]
+; CHECK-NEXT: strh r8, [r0, #50]
+; CHECK-NEXT: strh r7, [r0, #48]
+; CHECK-NEXT: ldrh r1, [sp, #140]
+; CHECK-NEXT: ldrh r6, [sp, #108]
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r4, [sp, #44]
+; CHECK-NEXT: ldrh r12, [sp, #136]
+; CHECK-NEXT: ldrh lr, [sp, #104]
+; CHECK-NEXT: ldrh r7, [sp, #72]
+; CHECK-NEXT: strh r1, [r0, #46]
+; CHECK-NEXT: strh r6, [r0, #44]
+; CHECK-NEXT: strh r5, [r0, #42]
+; CHECK-NEXT: strh r4, [r0, #40]
+; CHECK-NEXT: strh r12, [r0, #38]
+; CHECK-NEXT: strh lr, [r0, #36]
+; CHECK-NEXT: strh r7, [r0, #34]
+; CHECK-NEXT: ldrh r1, [sp, #40]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: ldrh lr, [sp, #128]
+; CHECK-NEXT: ldrh r7, [sp, #96]
+; CHECK-NEXT: strh r1, [r0, #32]
+; CHECK-NEXT: strh r6, [r0, #30]
+; CHECK-NEXT: strh r5, [r0, #28]
+; CHECK-NEXT: strh r4, [r0, #26]
+; CHECK-NEXT: strh r12, [r0, #24]
+; CHECK-NEXT: strh lr, [r0, #22]
+; CHECK-NEXT: strh r7, [r0, #20]
+; CHECK-NEXT: ldrh r8, [sp, #64]
+; CHECK-NEXT: ldrh r9, [sp, #32]
+; CHECK-NEXT: ldrh r10, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r6, [sp, #120]
+; CHECK-NEXT: ldrh r7, [sp, #88]
+; CHECK-NEXT: ldrh r5, [sp, #56]
+; CHECK-NEXT: strh r8, [r0, #18]
+; CHECK-NEXT: strh r9, [r0, #16]
+; CHECK-NEXT: strh r10, [r0, #14]
+; CHECK-NEXT: strh r4, [r0, #12]
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: strh r3, [r0, #8]
+; CHECK-NEXT: strh r6, [r0, #6]
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: strh r5, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+ %result = call <32 x half> @llvm.vector.interleave4(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3)
+ ret <32 x half> %result
+}
+
+define <48 x half> @interleave6_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5) {
+; CHECK-LABEL: interleave6_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r12, [sp, #212]
+; CHECK-NEXT: ldrh r1, [sp, #180]
+; CHECK-NEXT: ldrh lr, [sp, #84]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #92]
+; CHECK-NEXT: ldrh r1, [sp, #52]
+; CHECK-NEXT: ldrh r7, [sp, #148]
+; CHECK-NEXT: ldrh r6, [sp, #116]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r9, [sp, #144]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #88]
+; CHECK-NEXT: str r1, [r0, #84]
+; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: ldrh r4, [sp, #208]
+; CHECK-NEXT: ldrh r7, [sp, #176]
+; CHECK-NEXT: orr r1, r1, r9, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #204]
+; CHECK-NEXT: orr r7, r7, r4, lsl #16
+; CHECK-NEXT: str r7, [r0, #80]
+; CHECK-NEXT: str r1, [r0, #76]
+; CHECK-NEXT: ldrh r1, [sp, #172]
+; CHECK-NEXT: ldrh r8, [sp, #80]
+; CHECK-NEXT: ldrh r7, [sp, #48]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r4, [sp, #76]
+; CHECK-NEXT: orr r7, r7, r8, lsl #16
+; CHECK-NEXT: str r7, [r0, #72]
+; CHECK-NEXT: str r1, [r0, #68]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r5, [sp, #140]
+; CHECK-NEXT: ldrh r7, [sp, #108]
+; CHECK-NEXT: orr r1, r1, r4, lsl #16
+; CHECK-NEXT: ldrh lr, [sp, #136]
+; CHECK-NEXT: orr r5, r7, r5, lsl #16
+; CHECK-NEXT: str r5, [r0, #64]
+; CHECK-NEXT: str r1, [r0, #60]
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r12, [sp, #200]
+; CHECK-NEXT: ldrh r5, [sp, #168]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #196]
+; CHECK-NEXT: orr r5, r5, r12, lsl #16
+; CHECK-NEXT: str r5, [r0, #56]
+; CHECK-NEXT: str r1, [r0, #52]
+; CHECK-NEXT: ldrh r1, [sp, #164]
+; CHECK-NEXT: ldrh r6, [sp, #72]
+; CHECK-NEXT: ldrh r5, [sp, #40]
+; CHECK-NEXT: orr r1, r1, r7, lsl #16
+; CHECK-NEXT: ldrh r12, [sp, #68]
+; CHECK-NEXT: orr r5, r5, r6, lsl #16
+; CHECK-NEXT: str r5, [r0, #48]
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: ldrh r4, [sp, #132]
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: orr r4, r5, r4, lsl #16
+; CHECK-NEXT: str r4, [r0, #40]
+; CHECK-NEXT: str r1, [r0, #36]
+; CHECK-NEXT: ldrh r1, [sp, #96]
+; CHECK-NEXT: ldrh lr, [sp, #192]
+; CHECK-NEXT: ldrh r4, [sp, #160]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #188]
+; CHECK-NEXT: orr r4, r4, lr, lsl #16
+; CHECK-NEXT: str r4, [r0, #32]
+; CHECK-NEXT: str r1, [r0, #28]
+; CHECK-NEXT: ldrh r1, [sp, #156]
+; CHECK-NEXT: ldrh r7, [sp, #64]
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: orr r1, r1, r5, lsl #16
+; CHECK-NEXT: ldrh r12, [sp, #124]
+; CHECK-NEXT: orr r4, r4, r7, lsl #16
+; CHECK-NEXT: str r4, [r0, #24]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh lr, [sp, #184]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r8, [sp, #120]
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #152]
+; CHECK-NEXT: orr r4, r4, r12, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #56]
+; CHECK-NEXT: ldrh r6, [sp, #88]
+; CHECK-NEXT: str r4, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r7, lr, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r6, r8, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r5, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <48 x half> @llvm.vector.interleave6(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5)
+ ret <48 x half> %result
+}
+
+define <64 x half> @interleave8_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5, <8 x half> %vec6, <8 x half> %vec7) {
+; CHECK-LABEL: interleave8_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: add r5, sp, #256
+; CHECK-NEXT: ldrh r1, [sp, #244]
+; CHECK-NEXT: ldrh r12, [sp, #212]
+; CHECK-NEXT: ldrh r7, [r5, #20]
+; CHECK-NEXT: strh r7, [r0, #126]
+; CHECK-NEXT: strh r1, [r0, #124]
+; CHECK-NEXT: add r1, sp, #256
+; CHECK-NEXT: ldrh lr, [sp, #180]
+; CHECK-NEXT: ldrh r4, [sp, #148]
+; CHECK-NEXT: ldrh r9, [sp, #116]
+; CHECK-NEXT: ldrh r8, [sp, #84]
+; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: ldrh r1, [r1, #16]
+; CHECK-NEXT: ldrh r6, [sp, #240]
+; CHECK-NEXT: strh r12, [r0, #122]
+; CHECK-NEXT: strh lr, [r0, #120]
+; CHECK-NEXT: strh r4, [r0, #118]
+; CHECK-NEXT: strh r9, [r0, #116]
+; CHECK-NEXT: strh r8, [r0, #114]
+; CHECK-NEXT: add r8, sp, #256
+; CHECK-NEXT: strh r7, [r0, #112]
+; CHECK-NEXT: strh r1, [r0, #110]
+; CHECK-NEXT: strh r6, [r0, #108]
+; CHECK-NEXT: add r6, sp, #256
+; CHECK-NEXT: ldrh r5, [sp, #208]
+; CHECK-NEXT: strh r5, [r0, #106]
+; CHECK-NEXT: ldrh r4, [sp, #176]
+; CHECK-NEXT: ldrh r12, [sp, #144]
+; CHECK-NEXT: ldrh lr, [sp, #112]
+; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: ldrh r6, [r6, #12]
+; CHECK-NEXT: ldrh r5, [sp, #236]
+; CHECK-NEXT: strh r4, [r0, #104]
+; CHECK-NEXT: strh r12, [r0, #102]
+; CHECK-NEXT: strh lr, [r0, #100]
+; CHECK-NEXT: strh r7, [r0, #98]
+; CHECK-NEXT: strh r1, [r0, #96]
+; CHECK-NEXT: strh r6, [r0, #94]
+; CHECK-NEXT: strh r5, [r0, #92]
+; CHECK-NEXT: add r5, sp, #256
+; CHECK-NEXT: ldrh r4, [sp, #204]
+; CHECK-NEXT: strh r4, [r0, #90]
+; CHECK-NEXT: ldrh r12, [sp, #172]
+; CHECK-NEXT: ldrh lr, [sp, #140]
+; CHECK-NEXT: ldrh r7, [sp, #108]
+; CHECK-NEXT: ldrh r1, [sp, #76]
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: ldrh r5, [r5, #8]
+; CHECK-NEXT: ldrh r4, [sp, #232]
+; CHECK-NEXT: strh r12, [r0, #88]
+; CHECK-NEXT: strh lr, [r0, #86]
+; CHECK-NEXT: strh r7, [r0, #84]
+; CHECK-NEXT: strh r1, [r0, #82]
+; CHECK-NEXT: strh r6, [r0, #80]
+; CHECK-NEXT: strh r5, [r0, #78]
+; CHECK-NEXT: strh r4, [r0, #76]
+; CHECK-NEXT: add r4, sp, #256
+; CHECK-NEXT: ldrh r12, [sp, #200]
+; CHECK-NEXT: strh r12, [r0, #74]
+; CHECK-NEXT: ldrh lr, [sp, #168]
+; CHECK-NEXT: ldrh r7, [sp, #136]
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r6, [sp, #72]
+; CHECK-NEXT: ldrh r5, [sp, #40]
+; CHECK-NEXT: ldrh r4, [r4, #4]
+; CHECK-NEXT: ldrh r12, [sp, #228]
+; CHECK-NEXT: strh lr, [r0, #72]
+; CHECK-NEXT: strh r7, [r0, #70]
+; CHECK-NEXT: strh r1, [r0, #68]
+; CHECK-NEXT: strh r6, [r0, #66]
+; CHECK-NEXT: strh r5, [r0, #64]
+; CHECK-NEXT: strh r4, [r0, #62]
+; CHECK-NEXT: strh r12, [r0, #60]
+; CHECK-NEXT: ldrh lr, [sp, #196]
+; CHECK-NEXT: ldrh r7, [sp, #164]
+; CHECK-NEXT: ldrh r1, [sp, #132]
+; CHECK-NEXT: ldrh r6, [sp, #100]
+; CHECK-NEXT: ldrh r5, [sp, #68]
+; CHECK-NEXT: ldrh r4, [sp, #36]
+; CHECK-NEXT: ldrh r12, [r8]
+; CHECK-NEXT: strh lr, [r0, #58]
+; CHECK-NEXT: strh r7, [r0, #56]
+; CHECK-NEXT: strh r1, [r0, #54]
+; CHECK-NEXT: strh r6, [r0, #52]
+; CHECK-NEXT: strh r5, [r0, #50]
+; CHECK-NEXT: strh r4, [r0, #48]
+; CHECK-NEXT: strh r12, [r0, #46]
+; CHECK-NEXT: ldrh lr, [sp, #224]
+; CHECK-NEXT: ldrh r7, [sp, #192]
+; CHECK-NEXT: ldrh r1, [sp, #160]
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: ldrh r5, [sp, #96]
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: strh lr, [r0, #44]
+; CHECK-NEXT: strh r7, [r0, #42]
+; CHECK-NEXT: strh r1, [r0, #40]
+; CHECK-NEXT: strh r6, [r0, #38]
+; CHECK-NEXT: strh r5, [r0, #36]
+; CHECK-NEXT: strh r4, [r0, #34]
+; CHECK-NEXT: strh r12, [r0, #32]
+; CHECK-NEXT: ldrh lr, [sp, #252]
+; CHECK-NEXT: ldrh r7, [sp, #220]
+; CHECK-NEXT: ldrh r1, [sp, #188]
+; CHECK-NEXT: ldrh r6, [sp, #156]
+; CHECK-NEXT: ldrh r5, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r12, [sp, #60]
+; CHECK-NEXT: strh lr, [r0, #30]
+; CHECK-NEXT: strh r7, [r0, #28]
+; CHECK-NEXT: strh r1, [r0, #26]
+; CHECK-NEXT: strh r6, [r0, #24]
+; CHECK-NEXT: strh r5, [r0, #22]
+; CHECK-NEXT: strh r4, [r0, #20]
+; CHECK-NEXT: strh r12, [r0, #18]
+; CHECK-NEXT: strh r3, [r0, #16]
+; CHECK-NEXT: ldrh lr, [sp, #248]
+; CHECK-NEXT: ldrh r7, [sp, #216]
+; CHECK-NEXT: ldrh r1, [sp, #184]
+; CHECK-NEXT: ldrh r6, [sp, #152]
+; CHECK-NEXT: ldrh r5, [sp, #120]
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: strh lr, [r0, #14]
+; CHECK-NEXT: strh r7, [r0, #12]
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: strh r6, [r0, #8]
+; CHECK-NEXT: strh r5, [r0, #6]
+; CHECK-NEXT: strh r4, [r0, #4]
+; CHECK-NEXT: strh r3, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <64 x half> @llvm.vector.interleave8(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5, <8 x half> %vec6, <8 x half> %vec7)
+ ret <64 x half> %result
+}
+
+define <8 x bfloat> @interleave2_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1) {
+; CHECK-LABEL: interleave2_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: ldrh r1, [sp, #20]
+; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: ldrh lr, [sp, #16]
+; CHECK-NEXT: ldrh r4, [sp, #28]
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: strh r6, [r0, #14]
+; CHECK-NEXT: strh r1, [r0, #12]
+; CHECK-NEXT: strh r12, [r0, #10]
+; CHECK-NEXT: strh lr, [r0, #8]
+; CHECK-NEXT: strh r4, [r0, #6]
+; CHECK-NEXT: strh r3, [r0, #4]
+; CHECK-NEXT: strh r5, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <8 x bfloat> @llvm.vector.interleave2(<4 x bfloat> %vec0, <4 x bfloat> %vec1)
+ ret <8 x bfloat> %result
+}
+
+define <12 x bfloat> @interleave3_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2) {
+; CHECK-LABEL: interleave3_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: ldrh r12, [sp, #60]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh lr, [sp, #40]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #28]
+; CHECK-NEXT: ldrh r6, [sp, #56]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: ldrh r4, [sp, #52]
+; CHECK-NEXT: ldrh r5, [sp, #36]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r8, [sp, #32]
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: str r7, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r5, r4, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r6, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r8, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call <12 x bfloat> @llvm.vector.interleave3(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2)
+ ret <12 x bfloat> %result
+}
+
+define <16 x bfloat> @interleave4_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3) {
+; CHECK-LABEL: interleave4_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: ldrh r7, [sp, #92]
+; CHECK-NEXT: ldrh r1, [sp, #76]
+; CHECK-NEXT: ldrh r12, [sp, #60]
+; CHECK-NEXT: ldrh lr, [sp, #44]
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: strh r7, [r0, #30]
+; CHECK-NEXT: strh r1, [r0, #28]
+; CHECK-NEXT: strh r12, [r0, #26]
+; CHECK-NEXT: strh lr, [r0, #24]
+; CHECK-NEXT: strh r4, [r0, #22]
+; CHECK-NEXT: ldrh r9, [sp, #72]
+; CHECK-NEXT: ldrh r8, [sp, #56]
+; CHECK-NEXT: ldrh r10, [sp, #40]
+; CHECK-NEXT: ldrh r11, [sp, #84]
+; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: ldrh r5, [sp, #52]
+; CHECK-NEXT: ldrh r4, [sp, #80]
+; CHECK-NEXT: ldrh r7, [sp, #64]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: strh r9, [r0, #20]
+; CHECK-NEXT: strh r8, [r0, #18]
+; CHECK-NEXT: strh r10, [r0, #16]
+; CHECK-NEXT: strh r11, [r0, #14]
+; CHECK-NEXT: strh r6, [r0, #12]
+; CHECK-NEXT: strh r5, [r0, #10]
+; CHECK-NEXT: strh r3, [r0, #8]
+; CHECK-NEXT: strh r4, [r0, #6]
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: strh r1, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: add sp, sp, #4
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+ %result = call <16 x bfloat> @llvm.vector.interleave4(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3)
+ ret <16 x bfloat> %result
+}
+
+define <24 x bfloat> @interleave6_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5) {
+; CHECK-LABEL: interleave6_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r12, [sp, #116]
+; CHECK-NEXT: ldrh r1, [sp, #100]
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: ldrh r7, [sp, #84]
+; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r9, [sp, #80]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #40]
+; CHECK-NEXT: str r1, [r0, #36]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: ldrh r4, [sp, #112]
+; CHECK-NEXT: ldrh r7, [sp, #96]
+; CHECK-NEXT: orr r1, r1, r9, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #108]
+; CHECK-NEXT: orr r7, r7, r4, lsl #16
+; CHECK-NEXT: str r7, [r0, #32]
+; CHECK-NEXT: str r1, [r0, #28]
+; CHECK-NEXT: ldrh r1, [sp, #92]
+; CHECK-NEXT: ldrh r8, [sp, #48]
+; CHECK-NEXT: ldrh r7, [sp, #32]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: orr r7, r7, r8, lsl #16
+; CHECK-NEXT: str r7, [r0, #24]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r12, [sp, #104]
+; CHECK-NEXT: ldrh r7, [sp, #60]
+; CHECK-NEXT: ldrh r9, [sp, #72]
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #88]
+; CHECK-NEXT: orr r7, r7, lr, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: str r7, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r5, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r4, r9, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r6, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <24 x bfloat> @llvm.vector.interleave6(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5)
+ ret <24 x bfloat> %result
+}
+
+define <32 x bfloat> @interleave8_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5, <4 x bfloat> %vec6, <4 x bfloat> %vec7) {
+; CHECK-LABEL: interleave8_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r7, [sp, #148]
+; CHECK-NEXT: strh r7, [r0, #62]
+; CHECK-NEXT: ldrh r1, [sp, #132]
+; CHECK-NEXT: ldrh r12, [sp, #116]
+; CHECK-NEXT: ldrh lr, [sp, #100]
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: ldrh r9, [sp, #68]
+; CHECK-NEXT: ldrh r8, [sp, #52]
+; CHECK-NEXT: ldrh r7, [sp, #36]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r12, [r0, #58]
+; CHECK-NEXT: strh lr, [r0, #56]
+; CHECK-NEXT: strh r4, [r0, #54]
+; CHECK-NEXT: strh r9, [r0, #52]
+; CHECK-NEXT: strh r8, [r0, #50]
+; CHECK-NEXT: strh r7, [r0, #48]
+; CHECK-NEXT: ldrh r1, [sp, #144]
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: ldrh r5, [sp, #112]
+; CHECK-NEXT: ldrh r4, [sp, #96]
+; CHECK-NEXT: ldrh r12, [sp, #80]
+; CHECK-NEXT: ldrh lr, [sp, #64]
+; CHECK-NEXT: ldrh r7, [sp, #48]
+; CHECK-NEXT: strh r1, [r0, #46]
+; CHECK-NEXT: strh r6, [r0, #44]
+; CHECK-NEXT: strh r5, [r0, #42]
+; CHECK-NEXT: strh r4, [r0, #40]
+; CHECK-NEXT: strh r12, [r0, #38]
+; CHECK-NEXT: strh lr, [r0, #36]
+; CHECK-NEXT: strh r7, [r0, #34]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: ldrh r6, [sp, #140]
+; CHECK-NEXT: ldrh r5, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #108]
+; CHECK-NEXT: ldrh r12, [sp, #92]
+; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: ldrh r7, [sp, #60]
+; CHECK-NEXT: ldrh r9, [sp, #44]
+; CHECK-NEXT: strh r1, [r0, #32]
+; CHECK-NEXT: strh r6, [r0, #30]
+; CHECK-NEXT: strh r5, [r0, #28]
+; CHECK-NEXT: strh r4, [r0, #26]
+; CHECK-NEXT: strh r12, [r0, #24]
+; CHECK-NEXT: strh lr, [r0, #22]
+; CHECK-NEXT: strh r7, [r0, #20]
+; CHECK-NEXT: strh r9, [r0, #18]
+; CHECK-NEXT: strh r3, [r0, #16]
+; CHECK-NEXT: ldrh r8, [sp, #136]
+; CHECK-NEXT: ldrh r5, [sp, #120]
+; CHECK-NEXT: ldrh r4, [sp, #104]
+; CHECK-NEXT: ldrh r6, [sp, #88]
+; CHECK-NEXT: ldrh r1, [sp, #72]
+; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: strh r8, [r0, #14]
+; CHECK-NEXT: strh r5, [r0, #12]
+; CHECK-NEXT: strh r4, [r0, #10]
+; CHECK-NEXT: strh r6, [r0, #8]
+; CHECK-NEXT: strh r1, [r0, #6]
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: strh r3, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <32 x bfloat> @llvm.vector.interleave8(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5, <4 x bfloat> %vec6, <4 x bfloat> %vec7)
+ ret <32 x bfloat> %result
+}
+
+define <16 x bfloat> @interleave2_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1) {
+; CHECK-LABEL: interleave2_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: ldrh r7, [sp, #92]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r12, [sp, #88]
+; CHECK-NEXT: ldrh lr, [sp, #56]
+; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: strh r7, [r0, #30]
+; CHECK-NEXT: strh r1, [r0, #28]
+; CHECK-NEXT: strh r12, [r0, #26]
+; CHECK-NEXT: strh lr, [r0, #24]
+; CHECK-NEXT: strh r4, [r0, #22]
+; CHECK-NEXT: ldrh r9, [sp, #52]
+; CHECK-NEXT: ldrh r8, [sp, #80]
+; CHECK-NEXT: ldrh r10, [sp, #48]
+; CHECK-NEXT: ldrh r11, [sp, #76]
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: ldrh r5, [sp, #72]
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: ldrh r7, [sp, #68]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: strh r9, [r0, #20]
+; CHECK-NEXT: strh r8, [r0, #18]
+; CHECK-NEXT: strh r10, [r0, #16]
+; CHECK-NEXT: strh r11, [r0, #14]
+; CHECK-NEXT: strh r6, [r0, #12]
+; CHECK-NEXT: strh r5, [r0, #10]
+; CHECK-NEXT: strh r4, [r0, #8]
+; CHECK-NEXT: strh r7, [r0, #6]
+; CHECK-NEXT: strh r3, [r0, #4]
+; CHECK-NEXT: strh r1, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: add sp, sp, #4
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+ %result = call <16 x bfloat> @llvm.vector.interleave2(<8 x bfloat> %vec0, <8 x bfloat> %vec1)
+ ret <16 x bfloat> %result
+}
+
+define <24 x bfloat> @interleave3_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2) {
+; CHECK-LABEL: interleave3_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: ldrh r12, [sp, #116]
+; CHECK-NEXT: ldrh r1, [sp, #84]
+; CHECK-NEXT: ldrh lr, [sp, #80]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: ldrh r6, [sp, #112]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r9, [sp, #44]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #40]
+; CHECK-NEXT: str r1, [r0, #36]
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r4, [sp, #108]
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: orr r1, r1, r9, lsl #16
+; CHECK-NEXT: ldrh r10, [sp, #100]
+; CHECK-NEXT: orr r7, r7, r4, lsl #16
+; CHECK-NEXT: str r7, [r0, #32]
+; CHECK-NEXT: str r1, [r0, #28]
+; CHECK-NEXT: ldrh r1, [sp, #68]
+; CHECK-NEXT: ldrh r8, [sp, #72]
+; CHECK-NEXT: ldrh r7, [sp, #40]
+; CHECK-NEXT: orr r1, r1, r10, lsl #16
+; CHECK-NEXT: ldrh lr, [sp, #64]
+; CHECK-NEXT: orr r7, r7, r8, lsl #16
+; CHECK-NEXT: str r7, [r0, #24]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: ldrh r9, [sp, #92]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #96]
+; CHECK-NEXT: ldrh r6, [sp, #60]
+; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: orr r7, r7, r12, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #88]
+; CHECK-NEXT: str r7, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r6, r9, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r5, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r4, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+ %result = call <24 x bfloat> @llvm.vector.interleave3(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2)
+ ret <24 x bfloat> %result
+}
+
+define <32 x bfloat> @interleave4_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3) {
+; CHECK-LABEL: interleave4_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: ldrh r7, [sp, #148]
+; CHECK-NEXT: strh r7, [r0, #62]
+; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: ldrh r12, [sp, #84]
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: ldrh r4, [sp, #144]
+; CHECK-NEXT: ldrh r9, [sp, #112]
+; CHECK-NEXT: ldrh r8, [sp, #80]
+; CHECK-NEXT: ldrh r7, [sp, #48]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r12, [r0, #58]
+; CHECK-NEXT: strh lr, [r0, #56]
+; CHECK-NEXT: strh r4, [r0, #54]
+; CHECK-NEXT: strh r9, [r0, #52]
+; CHECK-NEXT: strh r8, [r0, #50]
+; CHECK-NEXT: strh r7, [r0, #48]
+; CHECK-NEXT: ldrh r1, [sp, #140]
+; CHECK-NEXT: ldrh r6, [sp, #108]
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r4, [sp, #44]
+; CHECK-NEXT: ldrh r12, [sp, #136]
+; CHECK-NEXT: ldrh lr, [sp, #104]
+; CHECK-NEXT: ldrh r7, [sp, #72]
+; CHECK-NEXT: strh r1, [r0, #46]
+; CHECK-NEXT: strh r6, [r0, #44]
+; CHECK-NEXT: strh r5, [r0, #42]
+; CHECK-NEXT: strh r4, [r0, #40]
+; CHECK-NEXT: strh r12, [r0, #38]
+; CHECK-NEXT: strh lr, [r0, #36]
+; CHECK-NEXT: strh r7, [r0, #34]
+; CHECK-NEXT: ldrh r1, [sp, #40]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: ldrh lr, [sp, #128]
+; CHECK-NEXT: ldrh r7, [sp, #96]
+; CHECK-NEXT: strh r1, [r0, #32]
+; CHECK-NEXT: strh r6, [r0, #30]
+; CHECK-NEXT: strh r5, [r0, #28]
+; CHECK-NEXT: strh r4, [r0, #26]
+; CHECK-NEXT: strh r12, [r0, #24]
+; CHECK-NEXT: strh lr, [r0, #22]
+; CHECK-NEXT: strh r7, [r0, #20]
+; CHECK-NEXT: ldrh r8, [sp, #64]
+; CHECK-NEXT: ldrh r9, [sp, #32]
+; CHECK-NEXT: ldrh r10, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r6, [sp, #120]
+; CHECK-NEXT: ldrh r7, [sp, #88]
+; CHECK-NEXT: ldrh r5, [sp, #56]
+; CHECK-NEXT: strh r8, [r0, #18]
+; CHECK-NEXT: strh r9, [r0, #16]
+; CHECK-NEXT: strh r10, [r0, #14]
+; CHECK-NEXT: strh r4, [r0, #12]
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: strh r3, [r0, #8]
+; CHECK-NEXT: strh r6, [r0, #6]
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: strh r5, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+ %result = call <32 x bfloat> @llvm.vector.interleave4(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3)
+ ret <32 x bfloat> %result
+}
+
+
+define <48 x bfloat> @interleave6_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5) {
+; CHECK-LABEL: interleave6_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: ldrh r12, [sp, #212]
+; CHECK-NEXT: ldrh r1, [sp, #180]
+; CHECK-NEXT: ldrh lr, [sp, #84]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #92]
+; CHECK-NEXT: ldrh r1, [sp, #52]
+; CHECK-NEXT: ldrh r7, [sp, #148]
+; CHECK-NEXT: ldrh r6, [sp, #116]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r9, [sp, #144]
+; CHECK-NEXT: orr r7, r6, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #88]
+; CHECK-NEXT: str r1, [r0, #84]
+; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: ldrh r4, [sp, #208]
+; CHECK-NEXT: ldrh r7, [sp, #176]
+; CHECK-NEXT: orr r1, r1, r9, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #204]
+; CHECK-NEXT: orr r7, r7, r4, lsl #16
+; CHECK-NEXT: str r7, [r0, #80]
+; CHECK-NEXT: str r1, [r0, #76]
+; CHECK-NEXT: ldrh r1, [sp, #172]
+; CHECK-NEXT: ldrh r8, [sp, #80]
+; CHECK-NEXT: ldrh r7, [sp, #48]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r4, [sp, #76]
+; CHECK-NEXT: orr r7, r7, r8, lsl #16
+; CHECK-NEXT: str r7, [r0, #72]
+; CHECK-NEXT: str r1, [r0, #68]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r5, [sp, #140]
+; CHECK-NEXT: ldrh r7, [sp, #108]
+; CHECK-NEXT: orr r1, r1, r4, lsl #16
+; CHECK-NEXT: ldrh lr, [sp, #136]
+; CHECK-NEXT: orr r5, r7, r5, lsl #16
+; CHECK-NEXT: str r5, [r0, #64]
+; CHECK-NEXT: str r1, [r0, #60]
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r12, [sp, #200]
+; CHECK-NEXT: ldrh r5, [sp, #168]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #196]
+; CHECK-NEXT: orr r5, r5, r12, lsl #16
+; CHECK-NEXT: str r5, [r0, #56]
+; CHECK-NEXT: str r1, [r0, #52]
+; CHECK-NEXT: ldrh r1, [sp, #164]
+; CHECK-NEXT: ldrh r6, [sp, #72]
+; CHECK-NEXT: ldrh r5, [sp, #40]
+; CHECK-NEXT: orr r1, r1, r7, lsl #16
+; CHECK-NEXT: ldrh r12, [sp, #68]
+; CHECK-NEXT: orr r5, r5, r6, lsl #16
+; CHECK-NEXT: str r5, [r0, #48]
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: ldrh r4, [sp, #132]
+; CHECK-NEXT: ldrh r5, [sp, #100]
+; CHECK-NEXT: orr r1, r1, r12, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: orr r4, r5, r4, lsl #16
+; CHECK-NEXT: str r4, [r0, #40]
+; CHECK-NEXT: str r1, [r0, #36]
+; CHECK-NEXT: ldrh r1, [sp, #96]
+; CHECK-NEXT: ldrh lr, [sp, #192]
+; CHECK-NEXT: ldrh r4, [sp, #160]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #188]
+; CHECK-NEXT: orr r4, r4, lr, lsl #16
+; CHECK-NEXT: str r4, [r0, #32]
+; CHECK-NEXT: str r1, [r0, #28]
+; CHECK-NEXT: ldrh r1, [sp, #156]
+; CHECK-NEXT: ldrh r7, [sp, #64]
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: orr r1, r1, r5, lsl #16
+; CHECK-NEXT: ldrh r12, [sp, #124]
+; CHECK-NEXT: orr r4, r4, r7, lsl #16
+; CHECK-NEXT: str r4, [r0, #24]
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh lr, [sp, #184]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r8, [sp, #120]
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: ldrh r7, [sp, #152]
+; CHECK-NEXT: orr r4, r4, r12, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #56]
+; CHECK-NEXT: ldrh r6, [sp, #88]
+; CHECK-NEXT: str r4, [r0, #16]
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r7, lr, lsl #16
+; CHECK-NEXT: str r1, [r0, #8]
+; CHECK-NEXT: orr r1, r6, r8, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r2, r5, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <48 x bfloat> @llvm.vector.interleave6(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5)
+ ret <48 x bfloat> %result
+}
+
+define <64 x bfloat> @interleave8_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5, <8 x bfloat> %vec6, <8 x bfloat> %vec7) {
+; CHECK-LABEL: interleave8_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: add r5, sp, #256
+; CHECK-NEXT: ldrh r1, [sp, #244]
+; CHECK-NEXT: ldrh r12, [sp, #212]
+; CHECK-NEXT: ldrh r7, [r5, #20]
+; CHECK-NEXT: strh r7, [r0, #126]
+; CHECK-NEXT: strh r1, [r0, #124]
+; CHECK-NEXT: add r1, sp, #256
+; CHECK-NEXT: ldrh lr, [sp, #180]
+; CHECK-NEXT: ldrh r4, [sp, #148]
+; CHECK-NEXT: ldrh r9, [sp, #116]
+; CHECK-NEXT: ldrh r8, [sp, #84]
+; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: ldrh r1, [r1, #16]
+; CHECK-NEXT: ldrh r6, [sp, #240]
+; CHECK-NEXT: strh r12, [r0, #122]
+; CHECK-NEXT: strh lr, [r0, #120]
+; CHECK-NEXT: strh r4, [r0, #118]
+; CHECK-NEXT: strh r9, [r0, #116]
+; CHECK-NEXT: strh r8, [r0, #114]
+; CHECK-NEXT: add r8, sp, #256
+; CHECK-NEXT: strh r7, [r0, #112]
+; CHECK-NEXT: strh r1, [r0, #110]
+; CHECK-NEXT: strh r6, [r0, #108]
+; CHECK-NEXT: add r6, sp, #256
+; CHECK-NEXT: ldrh r5, [sp, #208]
+; CHECK-NEXT: strh r5, [r0, #106]
+; CHECK-NEXT: ldrh r4, [sp, #176]
+; CHECK-NEXT: ldrh r12, [sp, #144]
+; CHECK-NEXT: ldrh lr, [sp, #112]
+; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: ldrh r6, [r6, #12]
+; CHECK-NEXT: ldrh r5, [sp, #236]
+; CHECK-NEXT: strh r4, [r0, #104]
+; CHECK-NEXT: strh r12, [r0, #102]
+; CHECK-NEXT: strh lr, [r0, #100]
+; CHECK-NEXT: strh r7, [r0, #98]
+; CHECK-NEXT: strh r1, [r0, #96]
+; CHECK-NEXT: strh r6, [r0, #94]
+; CHECK-NEXT: strh r5, [r0, #92]
+; CHECK-NEXT: add r5, sp, #256
+; CHECK-NEXT: ldrh r4, [sp, #204]
+; CHECK-NEXT: strh r4, [r0, #90]
+; CHECK-NEXT: ldrh r12, [sp, #172]
+; CHECK-NEXT: ldrh lr, [sp, #140]
+; CHECK-NEXT: ldrh r7, [sp, #108]
+; CHECK-NEXT: ldrh r1, [sp, #76]
+; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: ldrh r5, [r5, #8]
+; CHECK-NEXT: ldrh r4, [sp, #232]
+; CHECK-NEXT: strh r12, [r0, #88]
+; CHECK-NEXT: strh lr, [r0, #86]
+; CHECK-NEXT: strh r7, [r0, #84]
+; CHECK-NEXT: strh r1, [r0, #82]
+; CHECK-NEXT: strh r6, [r0, #80]
+; CHECK-NEXT: strh r5, [r0, #78]
+; CHECK-NEXT: strh r4, [r0, #76]
+; CHECK-NEXT: add r4, sp, #256
+; CHECK-NEXT: ldrh r12, [sp, #200]
+; CHECK-NEXT: strh r12, [r0, #74]
+; CHECK-NEXT: ldrh lr, [sp, #168]
+; CHECK-NEXT: ldrh r7, [sp, #136]
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r6, [sp, #72]
+; CHECK-NEXT: ldrh r5, [sp, #40]
+; CHECK-NEXT: ldrh r4, [r4, #4]
+; CHECK-NEXT: ldrh r12, [sp, #228]
+; CHECK-NEXT: strh lr, [r0, #72]
+; CHECK-NEXT: strh r7, [r0, #70]
+; CHECK-NEXT: strh r1, [r0, #68]
+; CHECK-NEXT: strh r6, [r0, #66]
+; CHECK-NEXT: strh r5, [r0, #64]
+; CHECK-NEXT: strh r4, [r0, #62]
+; CHECK-NEXT: strh r12, [r0, #60]
+; CHECK-NEXT: ldrh lr, [sp, #196]
+; CHECK-NEXT: ldrh r7, [sp, #164]
+; CHECK-NEXT: ldrh r1, [sp, #132]
+; CHECK-NEXT: ldrh r6, [sp, #100]
+; CHECK-NEXT: ldrh r5, [sp, #68]
+; CHECK-NEXT: ldrh r4, [sp, #36]
+; CHECK-NEXT: ldrh r12, [r8]
+; CHECK-NEXT: strh lr, [r0, #58]
+; CHECK-NEXT: strh r7, [r0, #56]
+; CHECK-NEXT: strh r1, [r0, #54]
+; CHECK-NEXT: strh r6, [r0, #52]
+; CHECK-NEXT: strh r5, [r0, #50]
+; CHECK-NEXT: strh r4, [r0, #48]
+; CHECK-NEXT: strh r12, [r0, #46]
+; CHECK-NEXT: ldrh lr, [sp, #224]
+; CHECK-NEXT: ldrh r7, [sp, #192]
+; CHECK-NEXT: ldrh r1, [sp, #160]
+; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: ldrh r5, [sp, #96]
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: strh lr, [r0, #44]
+; CHECK-NEXT: strh r7, [r0, #42]
+; CHECK-NEXT: strh r1, [r0, #40]
+; CHECK-NEXT: strh r6, [r0, #38]
+; CHECK-NEXT: strh r5, [r0, #36]
+; CHECK-NEXT: strh r4, [r0, #34]
+; CHECK-NEXT: strh r12, [r0, #32]
+; CHECK-NEXT: ldrh lr, [sp, #252]
+; CHECK-NEXT: ldrh r7, [sp, #220]
+; CHECK-NEXT: ldrh r1, [sp, #188]
+; CHECK-NEXT: ldrh r6, [sp, #156]
+; CHECK-NEXT: ldrh r5, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r12, [sp, #60]
+; CHECK-NEXT: strh lr, [r0, #30]
+; CHECK-NEXT: strh r7, [r0, #28]
+; CHECK-NEXT: strh r1, [r0, #26]
+; CHECK-NEXT: strh r6, [r0, #24]
+; CHECK-NEXT: strh r5, [r0, #22]
+; CHECK-NEXT: strh r4, [r0, #20]
+; CHECK-NEXT: strh r12, [r0, #18]
+; CHECK-NEXT: strh r3, [r0, #16]
+; CHECK-NEXT: ldrh lr, [sp, #248]
+; CHECK-NEXT: ldrh r7, [sp, #216]
+; CHECK-NEXT: ldrh r1, [sp, #184]
+; CHECK-NEXT: ldrh r6, [sp, #152]
+; CHECK-NEXT: ldrh r5, [sp, #120]
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: strh lr, [r0, #14]
+; CHECK-NEXT: strh r7, [r0, #12]
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: strh r6, [r0, #8]
+; CHECK-NEXT: strh r5, [r0, #6]
+; CHECK-NEXT: strh r4, [r0, #4]
+; CHECK-NEXT: strh r3, [r0, #2]
+; CHECK-NEXT: strh r2, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+ %result = call <64 x bfloat> @llvm.vector.interleave8(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5, <8 x bfloat> %vec6, <8 x bfloat> %vec7)
+ ret <64 x bfloat> %result
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
>From 690a3d86755961343aa745b030bfd6e4865d5e80 Mon Sep 17 00:00:00 2001
From: Kamlesh Kumar <kamlesh.kumar at arm.com>
Date: Thu, 24 Sep 2026 13:11:33 +0000
Subject: [PATCH 2/2] address comments
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 +-
.../CodeGen/ARM/fixed-vector-interleave.ll | 2444 ----------------
...deinterleave.ll => vector-deinterleave.ll} | 2519 ++++++++---------
llvm/test/CodeGen/ARM/vector-interleave.ll | 2352 +++++++++++++++
4 files changed, 3592 insertions(+), 3729 deletions(-)
delete mode 100644 llvm/test/CodeGen/ARM/fixed-vector-interleave.ll
rename llvm/test/CodeGen/ARM/{fixed-vector-deinterleave.ll => vector-deinterleave.ll} (77%)
create mode 100644 llvm/test/CodeGen/ARM/vector-interleave.ll
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 7f5a8d1547703..30ab8ffcef29e 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -199,7 +199,7 @@ void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT) {
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setVectorInterleaveAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE},
- {2, 3, 4}, VT, Custom);
+ {2, 3}, VT, Custom);
setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
setOperationAction(ISD::SELECT, VT, Expand);
@@ -9083,7 +9083,7 @@ static SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG,
return DAG.getMergeValues({Zip, Zip.getValue(1)}, DL);
}
- if (Op->getNumOperands() == 3) {
+ if (Factor == 3) {
Align Alignment = DAG.getReducedAlign(OpVT, /*UseABI=*/false);
SDValue StackPtr =
DAG.CreateStackTemporary(OpVT.getStoreSize() * 3, Alignment);
@@ -9132,7 +9132,7 @@ static SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG,
return DAG.getMergeValues({Unzip, Unzip.getValue(1)}, DL);
}
- if (Op->getNumOperands() == 3) {
+ if (Factor == 3) {
Align Alignment = DAG.getReducedAlign(OpVT, /*UseABI=*/false);
SDValue StackPtr =
DAG.CreateStackTemporary(OpVT.getStoreSize() * 3, Alignment);
diff --git a/llvm/test/CodeGen/ARM/fixed-vector-interleave.ll b/llvm/test/CodeGen/ARM/fixed-vector-interleave.ll
deleted file mode 100644
index 67138f8a21607..0000000000000
--- a/llvm/test/CodeGen/ARM/fixed-vector-interleave.ll
+++ /dev/null
@@ -1,2444 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
-; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
-
-define <16 x i8> @interleave2_v8i8(<8 x i8> %vec0, <8 x i8> %vec1) {
-; CHECK-LABEL: interleave2_v8i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vzip.8 d17, d16
-; CHECK-NEXT: vmov r0, r1, d17
-; CHECK-NEXT: vmov r2, r3, d16
-; CHECK-NEXT: bx lr
- %result = call <16 x i8> @llvm.vector.interleave2(<8 x i8> %vec0, <8 x i8> %vec1)
- ret <16 x i8> %result
-}
-
-define <24 x i8> @interleave3_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2) {
-; CHECK-LABEL: interleave3_v8i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #24
-; CHECK-NEXT: sub sp, sp, #24
-; CHECK-NEXT: vldr d18, [sp, #32]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vldr d18, [sp, #16]
-; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vstr d18, [r0]
-; CHECK-NEXT: add sp, sp, #24
-; CHECK-NEXT: bx lr
- %result = call <24 x i8> @llvm.vector.interleave3(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2)
- ret <24 x i8> %result
-}
-
-define <32 x i8> @interleave4_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3) {
-; CHECK-LABEL: interleave4_v8i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp, #16]
-; CHECK-NEXT: vldr d19, [sp]
-; CHECK-NEXT: vldr d16, [sp, #8]
-; CHECK-NEXT: vmov d18, r2, r3
-; CHECK-NEXT: vzip.8 d19, d17
-; CHECK-NEXT: vzip.8 d18, d16
-; CHECK-NEXT: vzip.8 d18, d19
-; CHECK-NEXT: vzip.8 d16, d17
-; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <32 x i8> @llvm.vector.interleave4(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3)
- ret <32 x i8> %result
-}
-
-define <48 x i8> @interleave6_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5) {
-; CHECK-LABEL: interleave6_v8i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #48
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: vldr d22, [sp, #56]
-; CHECK-NEXT: add r1, sp, #64
-; CHECK-NEXT: vldr d21, [sp, #48]
-; CHECK-NEXT: vmov d20, r2, r3
-; CHECK-NEXT: vldmia r1, {d16, d17, d18}
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vzip.8 d22, d18
-; CHECK-NEXT: mov r3, sp
-; CHECK-NEXT: vzip.8 d21, d17
-; CHECK-NEXT: vzip.8 d20, d16
-; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vldr d19, [sp, #40]
-; CHECK-NEXT: vst3.8 {d20, d21, d22}, [r3:64], r2
-; CHECK-NEXT: vldr d20, [sp]
-; CHECK-NEXT: vldr d21, [r3]
-; CHECK-NEXT: vldr d16, [sp, #16]
-; CHECK-NEXT: vldr d18, [r1]
-; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: bx lr
- %result = call <48 x i8> @llvm.vector.interleave6(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5)
- ret <48 x i8> %result
-}
-
-define <64 x i8> @interleave8_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5, <8 x i8> %vec6, <8 x i8> %vec7) {
-; CHECK-LABEL: interleave8_v8i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vldr d17, [sp, #48]
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vldr d16, [sp, #40]
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
-; CHECK-NEXT: vzip.8 d19, d17
-; CHECK-NEXT: vzip.8 d23, d21
-; CHECK-NEXT: vzip.8 d18, d16
-; CHECK-NEXT: vzip.8 d22, d20
-; CHECK-NEXT: vzip.8 d23, d19
-; CHECK-NEXT: vzip.8 d22, d18
-; CHECK-NEXT: vzip.8 d21, d17
-; CHECK-NEXT: vzip.8 d20, d16
-; CHECK-NEXT: vzip.8 d22, d23
-; CHECK-NEXT: vzip.8 d18, d19
-; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vzip.8 d20, d21
-; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vzip.8 d16, d17
-; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <64 x i8> @llvm.vector.interleave8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5, <8 x i8> %vec6, <8 x i8> %vec7)
- ret <64 x i8> %result
-}
-
-
-define <8 x i16> @interleave2_v4i16(<4 x i16> %vec0, <4 x i16> %vec1) {
-; CHECK-LABEL: interleave2_v4i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vzip.16 d17, d16
-; CHECK-NEXT: vmov r0, r1, d17
-; CHECK-NEXT: vmov r2, r3, d16
-; CHECK-NEXT: bx lr
- %result = call <8 x i16> @llvm.vector.interleave2(<4 x i16> %vec0, <4 x i16> %vec1)
- ret <8 x i16> %result
-}
-
-define <12 x i16> @interleave3_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
-; CHECK-LABEL: interleave3_v4i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #24
-; CHECK-NEXT: sub sp, sp, #24
-; CHECK-NEXT: vldr d18, [sp, #32]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vst3.16 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vldr d18, [sp, #16]
-; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vstr d18, [r0]
-; CHECK-NEXT: add sp, sp, #24
-; CHECK-NEXT: bx lr
- %result = call <12 x i16> @llvm.vector.interleave3(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2)
- ret <12 x i16> %result
-}
-
-define <16 x i16> @interleave4_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3) {
-; CHECK-LABEL: interleave4_v4i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp, #16]
-; CHECK-NEXT: vldr d19, [sp]
-; CHECK-NEXT: vldr d16, [sp, #8]
-; CHECK-NEXT: vmov d18, r2, r3
-; CHECK-NEXT: vzip.16 d19, d17
-; CHECK-NEXT: vzip.16 d18, d16
-; CHECK-NEXT: vzip.16 d18, d19
-; CHECK-NEXT: vzip.16 d16, d17
-; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <16 x i16> @llvm.vector.interleave4(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3)
- ret <16 x i16> %result
-}
-
-define <24 x i16> @interleave6_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5) {
-; CHECK-LABEL: interleave6_v4i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #48
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: vldr d22, [sp, #56]
-; CHECK-NEXT: add r1, sp, #64
-; CHECK-NEXT: vldr d21, [sp, #48]
-; CHECK-NEXT: vmov d20, r2, r3
-; CHECK-NEXT: vldmia r1, {d16, d17, d18}
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vzip.16 d22, d18
-; CHECK-NEXT: mov r3, sp
-; CHECK-NEXT: vzip.16 d21, d17
-; CHECK-NEXT: vzip.16 d20, d16
-; CHECK-NEXT: vst3.16 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vldr d19, [sp, #40]
-; CHECK-NEXT: vst3.16 {d20, d21, d22}, [r3:64], r2
-; CHECK-NEXT: vldr d20, [sp]
-; CHECK-NEXT: vldr d21, [r3]
-; CHECK-NEXT: vldr d16, [sp, #16]
-; CHECK-NEXT: vldr d18, [r1]
-; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: bx lr
- %result = call <24 x i16> @llvm.vector.interleave6(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5)
- ret <24 x i16> %result
-}
-
-define <32 x i16> @interleave8_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5, <4 x i16> %vec6, <4 x i16> %vec7) {
-; CHECK-LABEL: interleave8_v4i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vldr d17, [sp, #48]
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vldr d16, [sp, #40]
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
-; CHECK-NEXT: vzip.16 d19, d17
-; CHECK-NEXT: vzip.16 d23, d21
-; CHECK-NEXT: vzip.16 d18, d16
-; CHECK-NEXT: vzip.16 d22, d20
-; CHECK-NEXT: vzip.16 d23, d19
-; CHECK-NEXT: vzip.16 d22, d18
-; CHECK-NEXT: vzip.16 d21, d17
-; CHECK-NEXT: vzip.16 d20, d16
-; CHECK-NEXT: vzip.16 d22, d23
-; CHECK-NEXT: vzip.16 d18, d19
-; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vzip.16 d20, d21
-; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vzip.16 d16, d17
-; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <32 x i16> @llvm.vector.interleave8(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5, <4 x i16> %vec6, <4 x i16> %vec7)
- ret <32 x i16> %result
-}
-
-
-define <4 x i32> @interleave2_v2i32(<2 x i32> %vec0, <2 x i32> %vec1) {
-; CHECK-LABEL: interleave2_v2i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vtrn.32 d17, d16
-; CHECK-NEXT: vmov r0, r1, d17
-; CHECK-NEXT: vmov r2, r3, d16
-; CHECK-NEXT: bx lr
- %result = call <4 x i32> @llvm.vector.interleave2(<2 x i32> %vec0, <2 x i32> %vec1)
- ret <4 x i32> %result
-}
-
-define <6 x i32> @interleave3_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) {
-; CHECK-LABEL: interleave3_v2i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #24
-; CHECK-NEXT: sub sp, sp, #24
-; CHECK-NEXT: vldr d18, [sp, #32]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vldr d18, [sp, #16]
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vstr d18, [r0]
-; CHECK-NEXT: add sp, sp, #24
-; CHECK-NEXT: bx lr
- %result = call <6 x i32> @llvm.vector.interleave3(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2)
- ret <6 x i32> %result
-}
-
-define <8 x i32> @interleave4_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3) {
-; CHECK-LABEL: interleave4_v2i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp, #16]
-; CHECK-NEXT: vldr d19, [sp]
-; CHECK-NEXT: vldr d16, [sp, #8]
-; CHECK-NEXT: vmov d18, r2, r3
-; CHECK-NEXT: vtrn.32 d19, d17
-; CHECK-NEXT: vtrn.32 d18, d16
-; CHECK-NEXT: vtrn.32 d18, d19
-; CHECK-NEXT: vtrn.32 d16, d17
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <8 x i32> @llvm.vector.interleave4(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3)
- ret <8 x i32> %result
-}
-
-define <12 x i32> @interleave6_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5) {
-; CHECK-LABEL: interleave6_v2i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #48
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: vldr d22, [sp, #56]
-; CHECK-NEXT: add r1, sp, #64
-; CHECK-NEXT: vldr d21, [sp, #48]
-; CHECK-NEXT: vmov d20, r2, r3
-; CHECK-NEXT: vldmia r1, {d16, d17, d18}
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vtrn.32 d22, d18
-; CHECK-NEXT: mov r3, sp
-; CHECK-NEXT: vtrn.32 d21, d17
-; CHECK-NEXT: vtrn.32 d20, d16
-; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vldr d19, [sp, #40]
-; CHECK-NEXT: vst3.32 {d20, d21, d22}, [r3:64], r2
-; CHECK-NEXT: vldr d20, [sp]
-; CHECK-NEXT: vldr d21, [r3]
-; CHECK-NEXT: vldr d16, [sp, #16]
-; CHECK-NEXT: vldr d18, [r1]
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: bx lr
- %result = call <12 x i32> @llvm.vector.interleave6(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5)
- ret <12 x i32> %result
-}
-
-define <16 x i32> @interleave8_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5, <2 x i32> %vec6, <2 x i32> %vec7) {
-; CHECK-LABEL: interleave8_v2i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vldr d17, [sp, #48]
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vldr d16, [sp, #40]
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
-; CHECK-NEXT: vtrn.32 d19, d17
-; CHECK-NEXT: vtrn.32 d23, d21
-; CHECK-NEXT: vtrn.32 d18, d16
-; CHECK-NEXT: vtrn.32 d22, d20
-; CHECK-NEXT: vtrn.32 d23, d19
-; CHECK-NEXT: vtrn.32 d22, d18
-; CHECK-NEXT: vtrn.32 d21, d17
-; CHECK-NEXT: vtrn.32 d20, d16
-; CHECK-NEXT: vtrn.32 d22, d23
-; CHECK-NEXT: vtrn.32 d18, d19
-; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vtrn.32 d20, d21
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vtrn.32 d16, d17
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <16 x i32> @llvm.vector.interleave8(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5, <2 x i32> %vec6, <2 x i32> %vec7)
- ret <16 x i32> %result
-}
-
-
-define <4 x float> @interleave2_v2f32(<2 x float> %vec0, <2 x float> %vec1) {
-; CHECK-LABEL: interleave2_v2f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vtrn.32 d17, d16
-; CHECK-NEXT: vmov r0, r1, d17
-; CHECK-NEXT: vmov r2, r3, d16
-; CHECK-NEXT: bx lr
- %result = call <4 x float> @llvm.vector.interleave2(<2 x float> %vec0, <2 x float> %vec1)
- ret <4 x float> %result
-}
-
-define <6 x float> @interleave3_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2) {
-; CHECK-LABEL: interleave3_v2f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #24
-; CHECK-NEXT: sub sp, sp, #24
-; CHECK-NEXT: vldr d18, [sp, #32]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d16, [sp]
-; CHECK-NEXT: vldr d17, [r1]
-; CHECK-NEXT: vldr d18, [sp, #16]
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vstr d18, [r0]
-; CHECK-NEXT: add sp, sp, #24
-; CHECK-NEXT: bx lr
- %result = call <6 x float> @llvm.vector.interleave3(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2)
- ret <6 x float> %result
-}
-
-define <8 x float> @interleave4_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3) {
-; CHECK-LABEL: interleave4_v2f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp, #16]
-; CHECK-NEXT: vldr d19, [sp]
-; CHECK-NEXT: vldr d16, [sp, #8]
-; CHECK-NEXT: vmov d18, r2, r3
-; CHECK-NEXT: vtrn.32 d19, d17
-; CHECK-NEXT: vtrn.32 d18, d16
-; CHECK-NEXT: vtrn.32 d18, d19
-; CHECK-NEXT: vtrn.32 d16, d17
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <8 x float> @llvm.vector.interleave4(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3)
- ret <8 x float> %result
-}
-
-define <12 x float> @interleave6_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5) {
-; CHECK-LABEL: interleave6_v2f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .pad #48
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: vldr d22, [sp, #56]
-; CHECK-NEXT: add r1, sp, #64
-; CHECK-NEXT: vldr d21, [sp, #48]
-; CHECK-NEXT: vmov d20, r2, r3
-; CHECK-NEXT: vldmia r1, {d16, d17, d18}
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: mov r2, #8
-; CHECK-NEXT: vtrn.32 d22, d18
-; CHECK-NEXT: mov r3, sp
-; CHECK-NEXT: vtrn.32 d21, d17
-; CHECK-NEXT: vtrn.32 d20, d16
-; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
-; CHECK-NEXT: vldr d17, [sp, #24]
-; CHECK-NEXT: vldr d19, [sp, #40]
-; CHECK-NEXT: vst3.32 {d20, d21, d22}, [r3:64], r2
-; CHECK-NEXT: vldr d20, [sp]
-; CHECK-NEXT: vldr d21, [r3]
-; CHECK-NEXT: vldr d16, [sp, #16]
-; CHECK-NEXT: vldr d18, [r1]
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: bx lr
- %result = call <12 x float> @llvm.vector.interleave6(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5)
- ret <12 x float> %result
-}
-
-define <16 x float> @interleave8_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5, <2 x float> %vec6, <2 x float> %vec7) {
-; CHECK-LABEL: interleave8_v2f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vldr d17, [sp, #48]
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vldr d16, [sp, #40]
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vldmia r1, {d18, d19, d20, d21}
-; CHECK-NEXT: vtrn.32 d19, d17
-; CHECK-NEXT: vtrn.32 d23, d21
-; CHECK-NEXT: vtrn.32 d18, d16
-; CHECK-NEXT: vtrn.32 d22, d20
-; CHECK-NEXT: vtrn.32 d23, d19
-; CHECK-NEXT: vtrn.32 d22, d18
-; CHECK-NEXT: vtrn.32 d21, d17
-; CHECK-NEXT: vtrn.32 d20, d16
-; CHECK-NEXT: vtrn.32 d22, d23
-; CHECK-NEXT: vtrn.32 d18, d19
-; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vtrn.32 d20, d21
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vtrn.32 d16, d17
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <16 x float> @llvm.vector.interleave8(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5, <2 x float> %vec6, <2 x float> %vec7)
- ret <16 x float> %result
-}
-
-
-define <32 x i8> @interleave2_v16i8(<16 x i8> %vec0, <16 x i8> %vec1) {
-; CHECK-LABEL: interleave2_v16i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vzip.8 q8, q9
-; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <32 x i8> @llvm.vector.interleave2(<16 x i8> %vec0, <16 x i8> %vec1)
- ret <32 x i8> %result
-}
-
-define <48 x i8> @interleave3_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2) {
-; CHECK-LABEL: interleave3_v16i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #60
-; CHECK-NEXT: sub sp, sp, #60
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vst3.8 {d16, d18, d20}, [r2:64]!
-; CHECK-NEXT: vst3.8 {d17, d19, d21}, [r2:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <48 x i8> @llvm.vector.interleave3(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2)
- ret <48 x i8> %result
-}
-
-define <64 x i8> @interleave4_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3) {
-; CHECK-LABEL: interleave4_v16i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vzip.8 q9, q8
-; CHECK-NEXT: vzip.8 q11, q10
-; CHECK-NEXT: vzip.8 q11, q9
-; CHECK-NEXT: vzip.8 q10, q8
-; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <64 x i8> @llvm.vector.interleave4(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3)
- ret <64 x i8> %result
-}
-
-define <96 x i8> @interleave6_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5) {
-; CHECK-LABEL: interleave6_v16i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #108
-; CHECK-NEXT: sub sp, sp, #108
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #76
-; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #60
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, r11, #44
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #48
-; CHECK-NEXT: vzip.8 q10, q14
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vzip.8 q9, q13
-; CHECK-NEXT: vzip.8 q8, q12
-; CHECK-NEXT: vst3.8 {d24, d26, d28}, [r2:64]!
-; CHECK-NEXT: vst3.8 {d25, d27, d29}, [r2:64]
-; CHECK-NEXT: mov r2, sp
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst3.8 {d16, d18, d20}, [r3:64]!
-; CHECK-NEXT: vst3.8 {d17, d19, d21}, [r3:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
-; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d26, d27}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d24, d25}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <96 x i8> @llvm.vector.interleave6(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5)
- ret <96 x i8> %result
-}
-
-define <128 x i8> @interleave8_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5, <16 x i8> %vec6, <16 x i8> %vec7) {
-; CHECK-LABEL: interleave8_v16i8:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #104
-; CHECK-NEXT: vldr d29, [sp]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vmov d28, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #72
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, sp, #88
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: add r1, sp, #56
-; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
-; CHECK-NEXT: add r1, r0, #64
-; CHECK-NEXT: vzip.8 q8, q9
-; CHECK-NEXT: vzip.8 q10, q12
-; CHECK-NEXT: vzip.8 q11, q13
-; CHECK-NEXT: vzip.8 q14, q15
-; CHECK-NEXT: vzip.8 q12, q9
-; CHECK-NEXT: vzip.8 q15, q13
-; CHECK-NEXT: vzip.8 q10, q8
-; CHECK-NEXT: vzip.8 q14, q11
-; CHECK-NEXT: vzip.8 q15, q12
-; CHECK-NEXT: vzip.8 q13, q9
-; CHECK-NEXT: vst1.8 {d30, d31}, [r1:128]!
-; CHECK-NEXT: vzip.8 q14, q10
-; CHECK-NEXT: vst1.8 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst1.8 {d26, d27}, [r1:128]!
-; CHECK-NEXT: vzip.8 q11, q8
-; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
-; CHECK-NEXT: vst1.8 {d28, d29}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <128 x i8> @llvm.vector.interleave8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5, <16 x i8> %vec6, <16 x i8> %vec7)
- ret <128 x i8> %result
-}
-
-
-define <16 x i16> @interleave2_v8i16(<8 x i16> %vec0, <8 x i16> %vec1) {
-; CHECK-LABEL: interleave2_v8i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vzip.16 q8, q9
-; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <16 x i16> @llvm.vector.interleave2(<8 x i16> %vec0, <8 x i16> %vec1)
- ret <16 x i16> %result
-}
-
-define <24 x i16> @interleave3_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2) {
-; CHECK-LABEL: interleave3_v8i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #60
-; CHECK-NEXT: sub sp, sp, #60
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vst3.16 {d16, d18, d20}, [r2:64]!
-; CHECK-NEXT: vst3.16 {d17, d19, d21}, [r2:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <24 x i16> @llvm.vector.interleave3(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2)
- ret <24 x i16> %result
-}
-
-define <32 x i16> @interleave4_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3) {
-; CHECK-LABEL: interleave4_v8i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vzip.16 q9, q8
-; CHECK-NEXT: vzip.16 q11, q10
-; CHECK-NEXT: vzip.16 q11, q9
-; CHECK-NEXT: vzip.16 q10, q8
-; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <32 x i16> @llvm.vector.interleave4(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3)
- ret <32 x i16> %result
-}
-
-define <48 x i16> @interleave6_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5) {
-; CHECK-LABEL: interleave6_v8i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #108
-; CHECK-NEXT: sub sp, sp, #108
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #76
-; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #60
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, r11, #44
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #48
-; CHECK-NEXT: vzip.16 q10, q14
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vzip.16 q9, q13
-; CHECK-NEXT: vzip.16 q8, q12
-; CHECK-NEXT: vst3.16 {d24, d26, d28}, [r2:64]!
-; CHECK-NEXT: vst3.16 {d25, d27, d29}, [r2:64]
-; CHECK-NEXT: mov r2, sp
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst3.16 {d16, d18, d20}, [r3:64]!
-; CHECK-NEXT: vst3.16 {d17, d19, d21}, [r3:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
-; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d26, d27}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d24, d25}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <48 x i16> @llvm.vector.interleave6(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5)
- ret <48 x i16> %result
-}
-
-define <64 x i16> @interleave8_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5, <8 x i16> %vec6, <8 x i16> %vec7) {
-; CHECK-LABEL: interleave8_v8i16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #104
-; CHECK-NEXT: vldr d29, [sp]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vmov d28, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #72
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, sp, #88
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: add r1, sp, #56
-; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
-; CHECK-NEXT: add r1, r0, #64
-; CHECK-NEXT: vzip.16 q8, q9
-; CHECK-NEXT: vzip.16 q10, q12
-; CHECK-NEXT: vzip.16 q11, q13
-; CHECK-NEXT: vzip.16 q14, q15
-; CHECK-NEXT: vzip.16 q12, q9
-; CHECK-NEXT: vzip.16 q15, q13
-; CHECK-NEXT: vzip.16 q10, q8
-; CHECK-NEXT: vzip.16 q14, q11
-; CHECK-NEXT: vzip.16 q15, q12
-; CHECK-NEXT: vzip.16 q13, q9
-; CHECK-NEXT: vst1.16 {d30, d31}, [r1:128]!
-; CHECK-NEXT: vzip.16 q14, q10
-; CHECK-NEXT: vst1.16 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst1.16 {d26, d27}, [r1:128]!
-; CHECK-NEXT: vzip.16 q11, q8
-; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
-; CHECK-NEXT: vst1.16 {d28, d29}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <64 x i16> @llvm.vector.interleave8(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5, <8 x i16> %vec6, <8 x i16> %vec7)
- ret <64 x i16> %result
-}
-
-define <8 x i32> @interleave2_v4i32(<4 x i32> %vec0, <4 x i32> %vec1) {
-; CHECK-LABEL: interleave2_v4i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vzip.32 q8, q9
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <8 x i32> @llvm.vector.interleave2(<4 x i32> %vec0, <4 x i32> %vec1)
- ret <8 x i32> %result
-}
-
-define <12 x i32> @interleave3_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2) {
-; CHECK-LABEL: interleave3_v4i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #60
-; CHECK-NEXT: sub sp, sp, #60
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r2:64]!
-; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r2:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <12 x i32> @llvm.vector.interleave3(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2)
- ret <12 x i32> %result
-}
-
-define <16 x i32> @interleave4_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3) {
-; CHECK-LABEL: interleave4_v4i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vzip.32 q9, q8
-; CHECK-NEXT: vzip.32 q11, q10
-; CHECK-NEXT: vzip.32 q11, q9
-; CHECK-NEXT: vzip.32 q10, q8
-; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <16 x i32> @llvm.vector.interleave4(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3)
- ret <16 x i32> %result
-}
-
-define <24 x i32> @interleave6_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5) {
-; CHECK-LABEL: interleave6_v4i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #108
-; CHECK-NEXT: sub sp, sp, #108
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #76
-; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #60
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, r11, #44
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #48
-; CHECK-NEXT: vzip.32 q10, q14
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vzip.32 q9, q13
-; CHECK-NEXT: vzip.32 q8, q12
-; CHECK-NEXT: vst3.32 {d24, d26, d28}, [r2:64]!
-; CHECK-NEXT: vst3.32 {d25, d27, d29}, [r2:64]
-; CHECK-NEXT: mov r2, sp
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r3:64]!
-; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r3:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d26, d27}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d24, d25}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <24 x i32> @llvm.vector.interleave6(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5)
- ret <24 x i32> %result
-}
-
-define <32 x i32> @interleave8_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7) {
-; CHECK-LABEL: interleave8_v4i32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #104
-; CHECK-NEXT: vldr d29, [sp]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vmov d28, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #72
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, sp, #88
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: add r1, sp, #56
-; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
-; CHECK-NEXT: add r1, r0, #64
-; CHECK-NEXT: vzip.32 q8, q9
-; CHECK-NEXT: vzip.32 q10, q12
-; CHECK-NEXT: vzip.32 q11, q13
-; CHECK-NEXT: vzip.32 q14, q15
-; CHECK-NEXT: vzip.32 q12, q9
-; CHECK-NEXT: vzip.32 q15, q13
-; CHECK-NEXT: vzip.32 q10, q8
-; CHECK-NEXT: vzip.32 q14, q11
-; CHECK-NEXT: vzip.32 q15, q12
-; CHECK-NEXT: vzip.32 q13, q9
-; CHECK-NEXT: vst1.32 {d30, d31}, [r1:128]!
-; CHECK-NEXT: vzip.32 q14, q10
-; CHECK-NEXT: vst1.32 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst1.32 {d26, d27}, [r1:128]!
-; CHECK-NEXT: vzip.32 q11, q8
-; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
-; CHECK-NEXT: vst1.32 {d28, d29}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <32 x i32> @llvm.vector.interleave8(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7)
- ret <32 x i32> %result
-}
-
-
-define <8 x float> @interleave2_v4f32(<4 x float> %vec0, <4 x float> %vec1) {
-; CHECK-LABEL: interleave2_v4f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d17, [sp]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vzip.32 q8, q9
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <8 x float> @llvm.vector.interleave2(<4 x float> %vec0, <4 x float> %vec1)
- ret <8 x float> %result
-}
-
-define <12 x float> @interleave3_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2) {
-; CHECK-LABEL: interleave3_v4f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #60
-; CHECK-NEXT: sub sp, sp, #60
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: mov r1, sp
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r2:64]!
-; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r2:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <12 x float> @llvm.vector.interleave3(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2)
- ret <12 x float> %result
-}
-
-define <16 x float> @interleave4_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3) {
-; CHECK-LABEL: interleave4_v4f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vldr d23, [sp]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: vzip.32 q9, q8
-; CHECK-NEXT: vzip.32 q11, q10
-; CHECK-NEXT: vzip.32 q11, q9
-; CHECK-NEXT: vzip.32 q10, q8
-; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <16 x float> @llvm.vector.interleave4(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3)
- ret <16 x float> %result
-}
-
-define <24 x float> @interleave6_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5) {
-; CHECK-LABEL: interleave6_v4f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11}
-; CHECK-NEXT: push {r11}
-; CHECK-NEXT: .setfp r11, sp
-; CHECK-NEXT: mov r11, sp
-; CHECK-NEXT: .pad #108
-; CHECK-NEXT: sub sp, sp, #108
-; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r1, r11, #76
-; CHECK-NEXT: vld1.64 {d28, d29}, [r1]
-; CHECK-NEXT: add r1, r11, #28
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, r11, #60
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, r11, #12
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, r11, #44
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #48
-; CHECK-NEXT: vzip.32 q10, q14
-; CHECK-NEXT: vldr d17, [r11, #4]
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: mov r2, r1
-; CHECK-NEXT: vzip.32 q9, q13
-; CHECK-NEXT: vzip.32 q8, q12
-; CHECK-NEXT: vst3.32 {d24, d26, d28}, [r2:64]!
-; CHECK-NEXT: vst3.32 {d25, d27, d29}, [r2:64]
-; CHECK-NEXT: mov r2, sp
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r3:64]!
-; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r3:64]
-; CHECK-NEXT: vld1.64 {d16, d17}, [r2:128]!
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
-; CHECK-NEXT: vld1.64 {d20, d21}, [r2]!
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
-; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d26, d27}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d24, d25}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11}
-; CHECK-NEXT: bx lr
- %result = call <24 x float> @llvm.vector.interleave6(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5)
- ret <24 x float> %result
-}
-
-define <32 x float> @interleave8_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5, <4 x float> %vec6, <4 x float> %vec7) {
-; CHECK-LABEL: interleave8_v4f32:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: add r1, sp, #104
-; CHECK-NEXT: vldr d29, [sp]
-; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
-; CHECK-NEXT: add r1, sp, #40
-; CHECK-NEXT: vmov d28, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT: add r1, sp, #72
-; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
-; CHECK-NEXT: add r1, sp, #8
-; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
-; CHECK-NEXT: add r1, sp, #88
-; CHECK-NEXT: vld1.64 {d26, d27}, [r1]
-; CHECK-NEXT: add r1, sp, #24
-; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
-; CHECK-NEXT: add r1, sp, #56
-; CHECK-NEXT: vld1.64 {d30, d31}, [r1]
-; CHECK-NEXT: add r1, r0, #64
-; CHECK-NEXT: vzip.32 q8, q9
-; CHECK-NEXT: vzip.32 q10, q12
-; CHECK-NEXT: vzip.32 q11, q13
-; CHECK-NEXT: vzip.32 q14, q15
-; CHECK-NEXT: vzip.32 q12, q9
-; CHECK-NEXT: vzip.32 q15, q13
-; CHECK-NEXT: vzip.32 q10, q8
-; CHECK-NEXT: vzip.32 q14, q11
-; CHECK-NEXT: vzip.32 q15, q12
-; CHECK-NEXT: vzip.32 q13, q9
-; CHECK-NEXT: vst1.32 {d30, d31}, [r1:128]!
-; CHECK-NEXT: vzip.32 q14, q10
-; CHECK-NEXT: vst1.32 {d24, d25}, [r1:128]!
-; CHECK-NEXT: vst1.32 {d26, d27}, [r1:128]!
-; CHECK-NEXT: vzip.32 q11, q8
-; CHECK-NEXT: vst1.64 {d18, d19}, [r1:128]
-; CHECK-NEXT: vst1.32 {d28, d29}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
-; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
-; CHECK-NEXT: bx lr
- %result = call <32 x float> @llvm.vector.interleave8(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5, <4 x float> %vec6, <4 x float> %vec7)
- ret <32 x float> %result
-}
-
-
-define <8 x half> @interleave2_v4f16(<4 x half> %vec0, <4 x half> %vec1) {
-; CHECK-LABEL: interleave2_v4f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: ldrh r1, [sp, #20]
-; CHECK-NEXT: ldrh r12, [sp, #32]
-; CHECK-NEXT: ldrh lr, [sp, #16]
-; CHECK-NEXT: ldrh r4, [sp, #28]
-; CHECK-NEXT: ldrh r5, [sp, #24]
-; CHECK-NEXT: strh r6, [r0, #14]
-; CHECK-NEXT: strh r1, [r0, #12]
-; CHECK-NEXT: strh r12, [r0, #10]
-; CHECK-NEXT: strh lr, [r0, #8]
-; CHECK-NEXT: strh r4, [r0, #6]
-; CHECK-NEXT: strh r3, [r0, #4]
-; CHECK-NEXT: strh r5, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, pc}
- %result = call <8 x half> @llvm.vector.interleave2(<4 x half> %vec0, <4 x half> %vec1)
- ret <8 x half> %result
-}
-
-define <12 x half> @interleave3_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2) {
-; CHECK-LABEL: interleave3_v4f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r12, [sp, #60]
-; CHECK-NEXT: ldrh r1, [sp, #44]
-; CHECK-NEXT: ldrh lr, [sp, #40]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #28]
-; CHECK-NEXT: ldrh r6, [sp, #56]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #24]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: ldrh r4, [sp, #52]
-; CHECK-NEXT: ldrh r5, [sp, #36]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r8, [sp, #32]
-; CHECK-NEXT: ldrh r6, [sp, #48]
-; CHECK-NEXT: str r7, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r5, r4, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r6, r3, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r8, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
- %result = call <12 x half> @llvm.vector.interleave3(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2)
- ret <12 x half> %result
-}
-
-define <16 x half> @interleave4_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3) {
-; CHECK-LABEL: interleave4_v4f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, sp, #4
-; CHECK-NEXT: ldrh r7, [sp, #92]
-; CHECK-NEXT: ldrh r1, [sp, #76]
-; CHECK-NEXT: ldrh r12, [sp, #60]
-; CHECK-NEXT: ldrh lr, [sp, #44]
-; CHECK-NEXT: ldrh r4, [sp, #88]
-; CHECK-NEXT: strh r7, [r0, #30]
-; CHECK-NEXT: strh r1, [r0, #28]
-; CHECK-NEXT: strh r12, [r0, #26]
-; CHECK-NEXT: strh lr, [r0, #24]
-; CHECK-NEXT: strh r4, [r0, #22]
-; CHECK-NEXT: ldrh r9, [sp, #72]
-; CHECK-NEXT: ldrh r8, [sp, #56]
-; CHECK-NEXT: ldrh r10, [sp, #40]
-; CHECK-NEXT: ldrh r11, [sp, #84]
-; CHECK-NEXT: ldrh r6, [sp, #68]
-; CHECK-NEXT: ldrh r5, [sp, #52]
-; CHECK-NEXT: ldrh r4, [sp, #80]
-; CHECK-NEXT: ldrh r7, [sp, #64]
-; CHECK-NEXT: ldrh r1, [sp, #48]
-; CHECK-NEXT: strh r9, [r0, #20]
-; CHECK-NEXT: strh r8, [r0, #18]
-; CHECK-NEXT: strh r10, [r0, #16]
-; CHECK-NEXT: strh r11, [r0, #14]
-; CHECK-NEXT: strh r6, [r0, #12]
-; CHECK-NEXT: strh r5, [r0, #10]
-; CHECK-NEXT: strh r3, [r0, #8]
-; CHECK-NEXT: strh r4, [r0, #6]
-; CHECK-NEXT: strh r7, [r0, #4]
-; CHECK-NEXT: strh r1, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: add sp, sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
- %result = call <16 x half> @llvm.vector.interleave4(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3)
- ret <16 x half> %result
-}
-
-define <24 x half> @interleave6_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5) {
-; CHECK-LABEL: interleave6_v4f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r12, [sp, #116]
-; CHECK-NEXT: ldrh r1, [sp, #100]
-; CHECK-NEXT: ldrh lr, [sp, #52]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #44]
-; CHECK-NEXT: ldrh r1, [sp, #36]
-; CHECK-NEXT: ldrh r7, [sp, #84]
-; CHECK-NEXT: ldrh r6, [sp, #68]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r9, [sp, #80]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: str r7, [r0, #40]
-; CHECK-NEXT: str r1, [r0, #36]
-; CHECK-NEXT: ldrh r1, [sp, #64]
-; CHECK-NEXT: ldrh r4, [sp, #112]
-; CHECK-NEXT: ldrh r7, [sp, #96]
-; CHECK-NEXT: orr r1, r1, r9, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #108]
-; CHECK-NEXT: orr r7, r7, r4, lsl #16
-; CHECK-NEXT: str r7, [r0, #32]
-; CHECK-NEXT: str r1, [r0, #28]
-; CHECK-NEXT: ldrh r1, [sp, #92]
-; CHECK-NEXT: ldrh r8, [sp, #48]
-; CHECK-NEXT: ldrh r7, [sp, #32]
-; CHECK-NEXT: orr r1, r1, r6, lsl #16
-; CHECK-NEXT: ldrh lr, [sp, #76]
-; CHECK-NEXT: orr r7, r7, r8, lsl #16
-; CHECK-NEXT: str r7, [r0, #24]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #44]
-; CHECK-NEXT: ldrh r12, [sp, #104]
-; CHECK-NEXT: ldrh r7, [sp, #60]
-; CHECK-NEXT: ldrh r9, [sp, #72]
-; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #88]
-; CHECK-NEXT: orr r7, r7, lr, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #40]
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: str r7, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r5, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r4, r9, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r6, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <24 x half> @llvm.vector.interleave6(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5)
- ret <24 x half> %result
-}
-
-define <32 x half> @interleave8_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5, <4 x half> %vec6, <4 x half> %vec7) {
-; CHECK-LABEL: interleave8_v4f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r7, [sp, #148]
-; CHECK-NEXT: strh r7, [r0, #62]
-; CHECK-NEXT: ldrh r1, [sp, #132]
-; CHECK-NEXT: ldrh r12, [sp, #116]
-; CHECK-NEXT: ldrh lr, [sp, #100]
-; CHECK-NEXT: ldrh r4, [sp, #84]
-; CHECK-NEXT: ldrh r9, [sp, #68]
-; CHECK-NEXT: ldrh r8, [sp, #52]
-; CHECK-NEXT: ldrh r7, [sp, #36]
-; CHECK-NEXT: strh r1, [r0, #60]
-; CHECK-NEXT: strh r12, [r0, #58]
-; CHECK-NEXT: strh lr, [r0, #56]
-; CHECK-NEXT: strh r4, [r0, #54]
-; CHECK-NEXT: strh r9, [r0, #52]
-; CHECK-NEXT: strh r8, [r0, #50]
-; CHECK-NEXT: strh r7, [r0, #48]
-; CHECK-NEXT: ldrh r1, [sp, #144]
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: ldrh r5, [sp, #112]
-; CHECK-NEXT: ldrh r4, [sp, #96]
-; CHECK-NEXT: ldrh r12, [sp, #80]
-; CHECK-NEXT: ldrh lr, [sp, #64]
-; CHECK-NEXT: ldrh r7, [sp, #48]
-; CHECK-NEXT: strh r1, [r0, #46]
-; CHECK-NEXT: strh r6, [r0, #44]
-; CHECK-NEXT: strh r5, [r0, #42]
-; CHECK-NEXT: strh r4, [r0, #40]
-; CHECK-NEXT: strh r12, [r0, #38]
-; CHECK-NEXT: strh lr, [r0, #36]
-; CHECK-NEXT: strh r7, [r0, #34]
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: ldrh r6, [sp, #140]
-; CHECK-NEXT: ldrh r5, [sp, #124]
-; CHECK-NEXT: ldrh r4, [sp, #108]
-; CHECK-NEXT: ldrh r12, [sp, #92]
-; CHECK-NEXT: ldrh lr, [sp, #76]
-; CHECK-NEXT: ldrh r7, [sp, #60]
-; CHECK-NEXT: ldrh r9, [sp, #44]
-; CHECK-NEXT: strh r1, [r0, #32]
-; CHECK-NEXT: strh r6, [r0, #30]
-; CHECK-NEXT: strh r5, [r0, #28]
-; CHECK-NEXT: strh r4, [r0, #26]
-; CHECK-NEXT: strh r12, [r0, #24]
-; CHECK-NEXT: strh lr, [r0, #22]
-; CHECK-NEXT: strh r7, [r0, #20]
-; CHECK-NEXT: strh r9, [r0, #18]
-; CHECK-NEXT: strh r3, [r0, #16]
-; CHECK-NEXT: ldrh r8, [sp, #136]
-; CHECK-NEXT: ldrh r5, [sp, #120]
-; CHECK-NEXT: ldrh r4, [sp, #104]
-; CHECK-NEXT: ldrh r6, [sp, #88]
-; CHECK-NEXT: ldrh r1, [sp, #72]
-; CHECK-NEXT: ldrh r7, [sp, #56]
-; CHECK-NEXT: ldrh r3, [sp, #40]
-; CHECK-NEXT: strh r8, [r0, #14]
-; CHECK-NEXT: strh r5, [r0, #12]
-; CHECK-NEXT: strh r4, [r0, #10]
-; CHECK-NEXT: strh r6, [r0, #8]
-; CHECK-NEXT: strh r1, [r0, #6]
-; CHECK-NEXT: strh r7, [r0, #4]
-; CHECK-NEXT: strh r3, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <32 x half> @llvm.vector.interleave8(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5, <4 x half> %vec6, <4 x half> %vec7)
- ret <32 x half> %result
-}
-
-
-define <16 x half> @interleave2_v8f16(<8 x half> %vec0, <8 x half> %vec1) {
-; CHECK-LABEL: interleave2_v8f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, sp, #4
-; CHECK-NEXT: ldrh r7, [sp, #92]
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: ldrh r12, [sp, #88]
-; CHECK-NEXT: ldrh lr, [sp, #56]
-; CHECK-NEXT: ldrh r4, [sp, #84]
-; CHECK-NEXT: strh r7, [r0, #30]
-; CHECK-NEXT: strh r1, [r0, #28]
-; CHECK-NEXT: strh r12, [r0, #26]
-; CHECK-NEXT: strh lr, [r0, #24]
-; CHECK-NEXT: strh r4, [r0, #22]
-; CHECK-NEXT: ldrh r9, [sp, #52]
-; CHECK-NEXT: ldrh r8, [sp, #80]
-; CHECK-NEXT: ldrh r10, [sp, #48]
-; CHECK-NEXT: ldrh r11, [sp, #76]
-; CHECK-NEXT: ldrh r6, [sp, #44]
-; CHECK-NEXT: ldrh r5, [sp, #72]
-; CHECK-NEXT: ldrh r4, [sp, #40]
-; CHECK-NEXT: ldrh r7, [sp, #68]
-; CHECK-NEXT: ldrh r1, [sp, #64]
-; CHECK-NEXT: strh r9, [r0, #20]
-; CHECK-NEXT: strh r8, [r0, #18]
-; CHECK-NEXT: strh r10, [r0, #16]
-; CHECK-NEXT: strh r11, [r0, #14]
-; CHECK-NEXT: strh r6, [r0, #12]
-; CHECK-NEXT: strh r5, [r0, #10]
-; CHECK-NEXT: strh r4, [r0, #8]
-; CHECK-NEXT: strh r7, [r0, #6]
-; CHECK-NEXT: strh r3, [r0, #4]
-; CHECK-NEXT: strh r1, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: add sp, sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
- %result = call <16 x half> @llvm.vector.interleave2(<8 x half> %vec0, <8 x half> %vec1)
- ret <16 x half> %result
-}
-
-define <24 x half> @interleave3_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2) {
-; CHECK-LABEL: interleave3_v8f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: ldrh r12, [sp, #116]
-; CHECK-NEXT: ldrh r1, [sp, #84]
-; CHECK-NEXT: ldrh lr, [sp, #80]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #44]
-; CHECK-NEXT: ldrh r1, [sp, #48]
-; CHECK-NEXT: ldrh r7, [sp, #52]
-; CHECK-NEXT: ldrh r6, [sp, #112]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r9, [sp, #44]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: str r7, [r0, #40]
-; CHECK-NEXT: str r1, [r0, #36]
-; CHECK-NEXT: ldrh r1, [sp, #104]
-; CHECK-NEXT: ldrh r4, [sp, #108]
-; CHECK-NEXT: ldrh r7, [sp, #76]
-; CHECK-NEXT: orr r1, r1, r9, lsl #16
-; CHECK-NEXT: ldrh r10, [sp, #100]
-; CHECK-NEXT: orr r7, r7, r4, lsl #16
-; CHECK-NEXT: str r7, [r0, #32]
-; CHECK-NEXT: str r1, [r0, #28]
-; CHECK-NEXT: ldrh r1, [sp, #68]
-; CHECK-NEXT: ldrh r8, [sp, #72]
-; CHECK-NEXT: ldrh r7, [sp, #40]
-; CHECK-NEXT: orr r1, r1, r10, lsl #16
-; CHECK-NEXT: ldrh lr, [sp, #64]
-; CHECK-NEXT: orr r7, r7, r8, lsl #16
-; CHECK-NEXT: str r7, [r0, #24]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: ldrh r12, [sp, #36]
-; CHECK-NEXT: ldrh r9, [sp, #92]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #96]
-; CHECK-NEXT: ldrh r6, [sp, #60]
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: orr r7, r7, r12, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #88]
-; CHECK-NEXT: str r7, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r6, r9, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r5, r3, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r4, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
- %result = call <24 x half> @llvm.vector.interleave3(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2)
- ret <24 x half> %result
-}
-
-define <32 x half> @interleave4_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3) {
-; CHECK-LABEL: interleave4_v8f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: ldrh r7, [sp, #148]
-; CHECK-NEXT: strh r7, [r0, #62]
-; CHECK-NEXT: ldrh r1, [sp, #116]
-; CHECK-NEXT: ldrh r12, [sp, #84]
-; CHECK-NEXT: ldrh lr, [sp, #52]
-; CHECK-NEXT: ldrh r4, [sp, #144]
-; CHECK-NEXT: ldrh r9, [sp, #112]
-; CHECK-NEXT: ldrh r8, [sp, #80]
-; CHECK-NEXT: ldrh r7, [sp, #48]
-; CHECK-NEXT: strh r1, [r0, #60]
-; CHECK-NEXT: strh r12, [r0, #58]
-; CHECK-NEXT: strh lr, [r0, #56]
-; CHECK-NEXT: strh r4, [r0, #54]
-; CHECK-NEXT: strh r9, [r0, #52]
-; CHECK-NEXT: strh r8, [r0, #50]
-; CHECK-NEXT: strh r7, [r0, #48]
-; CHECK-NEXT: ldrh r1, [sp, #140]
-; CHECK-NEXT: ldrh r6, [sp, #108]
-; CHECK-NEXT: ldrh r5, [sp, #76]
-; CHECK-NEXT: ldrh r4, [sp, #44]
-; CHECK-NEXT: ldrh r12, [sp, #136]
-; CHECK-NEXT: ldrh lr, [sp, #104]
-; CHECK-NEXT: ldrh r7, [sp, #72]
-; CHECK-NEXT: strh r1, [r0, #46]
-; CHECK-NEXT: strh r6, [r0, #44]
-; CHECK-NEXT: strh r5, [r0, #42]
-; CHECK-NEXT: strh r4, [r0, #40]
-; CHECK-NEXT: strh r12, [r0, #38]
-; CHECK-NEXT: strh lr, [r0, #36]
-; CHECK-NEXT: strh r7, [r0, #34]
-; CHECK-NEXT: ldrh r1, [sp, #40]
-; CHECK-NEXT: ldrh r6, [sp, #132]
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: ldrh r4, [sp, #68]
-; CHECK-NEXT: ldrh r12, [sp, #36]
-; CHECK-NEXT: ldrh lr, [sp, #128]
-; CHECK-NEXT: ldrh r7, [sp, #96]
-; CHECK-NEXT: strh r1, [r0, #32]
-; CHECK-NEXT: strh r6, [r0, #30]
-; CHECK-NEXT: strh r5, [r0, #28]
-; CHECK-NEXT: strh r4, [r0, #26]
-; CHECK-NEXT: strh r12, [r0, #24]
-; CHECK-NEXT: strh lr, [r0, #22]
-; CHECK-NEXT: strh r7, [r0, #20]
-; CHECK-NEXT: ldrh r8, [sp, #64]
-; CHECK-NEXT: ldrh r9, [sp, #32]
-; CHECK-NEXT: ldrh r10, [sp, #124]
-; CHECK-NEXT: ldrh r4, [sp, #92]
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: ldrh r6, [sp, #120]
-; CHECK-NEXT: ldrh r7, [sp, #88]
-; CHECK-NEXT: ldrh r5, [sp, #56]
-; CHECK-NEXT: strh r8, [r0, #18]
-; CHECK-NEXT: strh r9, [r0, #16]
-; CHECK-NEXT: strh r10, [r0, #14]
-; CHECK-NEXT: strh r4, [r0, #12]
-; CHECK-NEXT: strh r1, [r0, #10]
-; CHECK-NEXT: strh r3, [r0, #8]
-; CHECK-NEXT: strh r6, [r0, #6]
-; CHECK-NEXT: strh r7, [r0, #4]
-; CHECK-NEXT: strh r5, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
- %result = call <32 x half> @llvm.vector.interleave4(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3)
- ret <32 x half> %result
-}
-
-define <48 x half> @interleave6_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5) {
-; CHECK-LABEL: interleave6_v8f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r12, [sp, #212]
-; CHECK-NEXT: ldrh r1, [sp, #180]
-; CHECK-NEXT: ldrh lr, [sp, #84]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #92]
-; CHECK-NEXT: ldrh r1, [sp, #52]
-; CHECK-NEXT: ldrh r7, [sp, #148]
-; CHECK-NEXT: ldrh r6, [sp, #116]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r9, [sp, #144]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: str r7, [r0, #88]
-; CHECK-NEXT: str r1, [r0, #84]
-; CHECK-NEXT: ldrh r1, [sp, #112]
-; CHECK-NEXT: ldrh r4, [sp, #208]
-; CHECK-NEXT: ldrh r7, [sp, #176]
-; CHECK-NEXT: orr r1, r1, r9, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #204]
-; CHECK-NEXT: orr r7, r7, r4, lsl #16
-; CHECK-NEXT: str r7, [r0, #80]
-; CHECK-NEXT: str r1, [r0, #76]
-; CHECK-NEXT: ldrh r1, [sp, #172]
-; CHECK-NEXT: ldrh r8, [sp, #80]
-; CHECK-NEXT: ldrh r7, [sp, #48]
-; CHECK-NEXT: orr r1, r1, r6, lsl #16
-; CHECK-NEXT: ldrh r4, [sp, #76]
-; CHECK-NEXT: orr r7, r7, r8, lsl #16
-; CHECK-NEXT: str r7, [r0, #72]
-; CHECK-NEXT: str r1, [r0, #68]
-; CHECK-NEXT: ldrh r1, [sp, #44]
-; CHECK-NEXT: ldrh r5, [sp, #140]
-; CHECK-NEXT: ldrh r7, [sp, #108]
-; CHECK-NEXT: orr r1, r1, r4, lsl #16
-; CHECK-NEXT: ldrh lr, [sp, #136]
-; CHECK-NEXT: orr r5, r7, r5, lsl #16
-; CHECK-NEXT: str r5, [r0, #64]
-; CHECK-NEXT: str r1, [r0, #60]
-; CHECK-NEXT: ldrh r1, [sp, #104]
-; CHECK-NEXT: ldrh r12, [sp, #200]
-; CHECK-NEXT: ldrh r5, [sp, #168]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #196]
-; CHECK-NEXT: orr r5, r5, r12, lsl #16
-; CHECK-NEXT: str r5, [r0, #56]
-; CHECK-NEXT: str r1, [r0, #52]
-; CHECK-NEXT: ldrh r1, [sp, #164]
-; CHECK-NEXT: ldrh r6, [sp, #72]
-; CHECK-NEXT: ldrh r5, [sp, #40]
-; CHECK-NEXT: orr r1, r1, r7, lsl #16
-; CHECK-NEXT: ldrh r12, [sp, #68]
-; CHECK-NEXT: orr r5, r5, r6, lsl #16
-; CHECK-NEXT: str r5, [r0, #48]
-; CHECK-NEXT: str r1, [r0, #44]
-; CHECK-NEXT: ldrh r1, [sp, #36]
-; CHECK-NEXT: ldrh r4, [sp, #132]
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: orr r4, r5, r4, lsl #16
-; CHECK-NEXT: str r4, [r0, #40]
-; CHECK-NEXT: str r1, [r0, #36]
-; CHECK-NEXT: ldrh r1, [sp, #96]
-; CHECK-NEXT: ldrh lr, [sp, #192]
-; CHECK-NEXT: ldrh r4, [sp, #160]
-; CHECK-NEXT: orr r1, r1, r6, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #188]
-; CHECK-NEXT: orr r4, r4, lr, lsl #16
-; CHECK-NEXT: str r4, [r0, #32]
-; CHECK-NEXT: str r1, [r0, #28]
-; CHECK-NEXT: ldrh r1, [sp, #156]
-; CHECK-NEXT: ldrh r7, [sp, #64]
-; CHECK-NEXT: ldrh r4, [sp, #32]
-; CHECK-NEXT: orr r1, r1, r5, lsl #16
-; CHECK-NEXT: ldrh r12, [sp, #124]
-; CHECK-NEXT: orr r4, r4, r7, lsl #16
-; CHECK-NEXT: str r4, [r0, #24]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: ldrh lr, [sp, #184]
-; CHECK-NEXT: ldrh r4, [sp, #92]
-; CHECK-NEXT: ldrh r8, [sp, #120]
-; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #152]
-; CHECK-NEXT: orr r4, r4, r12, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #56]
-; CHECK-NEXT: ldrh r6, [sp, #88]
-; CHECK-NEXT: str r4, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r7, lr, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r6, r8, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r5, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <48 x half> @llvm.vector.interleave6(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5)
- ret <48 x half> %result
-}
-
-define <64 x half> @interleave8_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5, <8 x half> %vec6, <8 x half> %vec7) {
-; CHECK-LABEL: interleave8_v8f16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: add r5, sp, #256
-; CHECK-NEXT: ldrh r1, [sp, #244]
-; CHECK-NEXT: ldrh r12, [sp, #212]
-; CHECK-NEXT: ldrh r7, [r5, #20]
-; CHECK-NEXT: strh r7, [r0, #126]
-; CHECK-NEXT: strh r1, [r0, #124]
-; CHECK-NEXT: add r1, sp, #256
-; CHECK-NEXT: ldrh lr, [sp, #180]
-; CHECK-NEXT: ldrh r4, [sp, #148]
-; CHECK-NEXT: ldrh r9, [sp, #116]
-; CHECK-NEXT: ldrh r8, [sp, #84]
-; CHECK-NEXT: ldrh r7, [sp, #52]
-; CHECK-NEXT: ldrh r1, [r1, #16]
-; CHECK-NEXT: ldrh r6, [sp, #240]
-; CHECK-NEXT: strh r12, [r0, #122]
-; CHECK-NEXT: strh lr, [r0, #120]
-; CHECK-NEXT: strh r4, [r0, #118]
-; CHECK-NEXT: strh r9, [r0, #116]
-; CHECK-NEXT: strh r8, [r0, #114]
-; CHECK-NEXT: add r8, sp, #256
-; CHECK-NEXT: strh r7, [r0, #112]
-; CHECK-NEXT: strh r1, [r0, #110]
-; CHECK-NEXT: strh r6, [r0, #108]
-; CHECK-NEXT: add r6, sp, #256
-; CHECK-NEXT: ldrh r5, [sp, #208]
-; CHECK-NEXT: strh r5, [r0, #106]
-; CHECK-NEXT: ldrh r4, [sp, #176]
-; CHECK-NEXT: ldrh r12, [sp, #144]
-; CHECK-NEXT: ldrh lr, [sp, #112]
-; CHECK-NEXT: ldrh r7, [sp, #80]
-; CHECK-NEXT: ldrh r1, [sp, #48]
-; CHECK-NEXT: ldrh r6, [r6, #12]
-; CHECK-NEXT: ldrh r5, [sp, #236]
-; CHECK-NEXT: strh r4, [r0, #104]
-; CHECK-NEXT: strh r12, [r0, #102]
-; CHECK-NEXT: strh lr, [r0, #100]
-; CHECK-NEXT: strh r7, [r0, #98]
-; CHECK-NEXT: strh r1, [r0, #96]
-; CHECK-NEXT: strh r6, [r0, #94]
-; CHECK-NEXT: strh r5, [r0, #92]
-; CHECK-NEXT: add r5, sp, #256
-; CHECK-NEXT: ldrh r4, [sp, #204]
-; CHECK-NEXT: strh r4, [r0, #90]
-; CHECK-NEXT: ldrh r12, [sp, #172]
-; CHECK-NEXT: ldrh lr, [sp, #140]
-; CHECK-NEXT: ldrh r7, [sp, #108]
-; CHECK-NEXT: ldrh r1, [sp, #76]
-; CHECK-NEXT: ldrh r6, [sp, #44]
-; CHECK-NEXT: ldrh r5, [r5, #8]
-; CHECK-NEXT: ldrh r4, [sp, #232]
-; CHECK-NEXT: strh r12, [r0, #88]
-; CHECK-NEXT: strh lr, [r0, #86]
-; CHECK-NEXT: strh r7, [r0, #84]
-; CHECK-NEXT: strh r1, [r0, #82]
-; CHECK-NEXT: strh r6, [r0, #80]
-; CHECK-NEXT: strh r5, [r0, #78]
-; CHECK-NEXT: strh r4, [r0, #76]
-; CHECK-NEXT: add r4, sp, #256
-; CHECK-NEXT: ldrh r12, [sp, #200]
-; CHECK-NEXT: strh r12, [r0, #74]
-; CHECK-NEXT: ldrh lr, [sp, #168]
-; CHECK-NEXT: ldrh r7, [sp, #136]
-; CHECK-NEXT: ldrh r1, [sp, #104]
-; CHECK-NEXT: ldrh r6, [sp, #72]
-; CHECK-NEXT: ldrh r5, [sp, #40]
-; CHECK-NEXT: ldrh r4, [r4, #4]
-; CHECK-NEXT: ldrh r12, [sp, #228]
-; CHECK-NEXT: strh lr, [r0, #72]
-; CHECK-NEXT: strh r7, [r0, #70]
-; CHECK-NEXT: strh r1, [r0, #68]
-; CHECK-NEXT: strh r6, [r0, #66]
-; CHECK-NEXT: strh r5, [r0, #64]
-; CHECK-NEXT: strh r4, [r0, #62]
-; CHECK-NEXT: strh r12, [r0, #60]
-; CHECK-NEXT: ldrh lr, [sp, #196]
-; CHECK-NEXT: ldrh r7, [sp, #164]
-; CHECK-NEXT: ldrh r1, [sp, #132]
-; CHECK-NEXT: ldrh r6, [sp, #100]
-; CHECK-NEXT: ldrh r5, [sp, #68]
-; CHECK-NEXT: ldrh r4, [sp, #36]
-; CHECK-NEXT: ldrh r12, [r8]
-; CHECK-NEXT: strh lr, [r0, #58]
-; CHECK-NEXT: strh r7, [r0, #56]
-; CHECK-NEXT: strh r1, [r0, #54]
-; CHECK-NEXT: strh r6, [r0, #52]
-; CHECK-NEXT: strh r5, [r0, #50]
-; CHECK-NEXT: strh r4, [r0, #48]
-; CHECK-NEXT: strh r12, [r0, #46]
-; CHECK-NEXT: ldrh lr, [sp, #224]
-; CHECK-NEXT: ldrh r7, [sp, #192]
-; CHECK-NEXT: ldrh r1, [sp, #160]
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: ldrh r5, [sp, #96]
-; CHECK-NEXT: ldrh r4, [sp, #64]
-; CHECK-NEXT: ldrh r12, [sp, #32]
-; CHECK-NEXT: strh lr, [r0, #44]
-; CHECK-NEXT: strh r7, [r0, #42]
-; CHECK-NEXT: strh r1, [r0, #40]
-; CHECK-NEXT: strh r6, [r0, #38]
-; CHECK-NEXT: strh r5, [r0, #36]
-; CHECK-NEXT: strh r4, [r0, #34]
-; CHECK-NEXT: strh r12, [r0, #32]
-; CHECK-NEXT: ldrh lr, [sp, #252]
-; CHECK-NEXT: ldrh r7, [sp, #220]
-; CHECK-NEXT: ldrh r1, [sp, #188]
-; CHECK-NEXT: ldrh r6, [sp, #156]
-; CHECK-NEXT: ldrh r5, [sp, #124]
-; CHECK-NEXT: ldrh r4, [sp, #92]
-; CHECK-NEXT: ldrh r12, [sp, #60]
-; CHECK-NEXT: strh lr, [r0, #30]
-; CHECK-NEXT: strh r7, [r0, #28]
-; CHECK-NEXT: strh r1, [r0, #26]
-; CHECK-NEXT: strh r6, [r0, #24]
-; CHECK-NEXT: strh r5, [r0, #22]
-; CHECK-NEXT: strh r4, [r0, #20]
-; CHECK-NEXT: strh r12, [r0, #18]
-; CHECK-NEXT: strh r3, [r0, #16]
-; CHECK-NEXT: ldrh lr, [sp, #248]
-; CHECK-NEXT: ldrh r7, [sp, #216]
-; CHECK-NEXT: ldrh r1, [sp, #184]
-; CHECK-NEXT: ldrh r6, [sp, #152]
-; CHECK-NEXT: ldrh r5, [sp, #120]
-; CHECK-NEXT: ldrh r4, [sp, #88]
-; CHECK-NEXT: ldrh r3, [sp, #56]
-; CHECK-NEXT: strh lr, [r0, #14]
-; CHECK-NEXT: strh r7, [r0, #12]
-; CHECK-NEXT: strh r1, [r0, #10]
-; CHECK-NEXT: strh r6, [r0, #8]
-; CHECK-NEXT: strh r5, [r0, #6]
-; CHECK-NEXT: strh r4, [r0, #4]
-; CHECK-NEXT: strh r3, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <64 x half> @llvm.vector.interleave8(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5, <8 x half> %vec6, <8 x half> %vec7)
- ret <64 x half> %result
-}
-
-define <8 x bfloat> @interleave2_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1) {
-; CHECK-LABEL: interleave2_v4bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: ldrh r1, [sp, #20]
-; CHECK-NEXT: ldrh r12, [sp, #32]
-; CHECK-NEXT: ldrh lr, [sp, #16]
-; CHECK-NEXT: ldrh r4, [sp, #28]
-; CHECK-NEXT: ldrh r5, [sp, #24]
-; CHECK-NEXT: strh r6, [r0, #14]
-; CHECK-NEXT: strh r1, [r0, #12]
-; CHECK-NEXT: strh r12, [r0, #10]
-; CHECK-NEXT: strh lr, [r0, #8]
-; CHECK-NEXT: strh r4, [r0, #6]
-; CHECK-NEXT: strh r3, [r0, #4]
-; CHECK-NEXT: strh r5, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, pc}
- %result = call <8 x bfloat> @llvm.vector.interleave2(<4 x bfloat> %vec0, <4 x bfloat> %vec1)
- ret <8 x bfloat> %result
-}
-
-define <12 x bfloat> @interleave3_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2) {
-; CHECK-LABEL: interleave3_v4bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r12, [sp, #60]
-; CHECK-NEXT: ldrh r1, [sp, #44]
-; CHECK-NEXT: ldrh lr, [sp, #40]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #28]
-; CHECK-NEXT: ldrh r6, [sp, #56]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #24]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: ldrh r4, [sp, #52]
-; CHECK-NEXT: ldrh r5, [sp, #36]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r8, [sp, #32]
-; CHECK-NEXT: ldrh r6, [sp, #48]
-; CHECK-NEXT: str r7, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r5, r4, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r6, r3, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r8, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
- %result = call <12 x bfloat> @llvm.vector.interleave3(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2)
- ret <12 x bfloat> %result
-}
-
-define <16 x bfloat> @interleave4_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3) {
-; CHECK-LABEL: interleave4_v4bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, sp, #4
-; CHECK-NEXT: ldrh r7, [sp, #92]
-; CHECK-NEXT: ldrh r1, [sp, #76]
-; CHECK-NEXT: ldrh r12, [sp, #60]
-; CHECK-NEXT: ldrh lr, [sp, #44]
-; CHECK-NEXT: ldrh r4, [sp, #88]
-; CHECK-NEXT: strh r7, [r0, #30]
-; CHECK-NEXT: strh r1, [r0, #28]
-; CHECK-NEXT: strh r12, [r0, #26]
-; CHECK-NEXT: strh lr, [r0, #24]
-; CHECK-NEXT: strh r4, [r0, #22]
-; CHECK-NEXT: ldrh r9, [sp, #72]
-; CHECK-NEXT: ldrh r8, [sp, #56]
-; CHECK-NEXT: ldrh r10, [sp, #40]
-; CHECK-NEXT: ldrh r11, [sp, #84]
-; CHECK-NEXT: ldrh r6, [sp, #68]
-; CHECK-NEXT: ldrh r5, [sp, #52]
-; CHECK-NEXT: ldrh r4, [sp, #80]
-; CHECK-NEXT: ldrh r7, [sp, #64]
-; CHECK-NEXT: ldrh r1, [sp, #48]
-; CHECK-NEXT: strh r9, [r0, #20]
-; CHECK-NEXT: strh r8, [r0, #18]
-; CHECK-NEXT: strh r10, [r0, #16]
-; CHECK-NEXT: strh r11, [r0, #14]
-; CHECK-NEXT: strh r6, [r0, #12]
-; CHECK-NEXT: strh r5, [r0, #10]
-; CHECK-NEXT: strh r3, [r0, #8]
-; CHECK-NEXT: strh r4, [r0, #6]
-; CHECK-NEXT: strh r7, [r0, #4]
-; CHECK-NEXT: strh r1, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: add sp, sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
- %result = call <16 x bfloat> @llvm.vector.interleave4(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3)
- ret <16 x bfloat> %result
-}
-
-define <24 x bfloat> @interleave6_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5) {
-; CHECK-LABEL: interleave6_v4bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r12, [sp, #116]
-; CHECK-NEXT: ldrh r1, [sp, #100]
-; CHECK-NEXT: ldrh lr, [sp, #52]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #44]
-; CHECK-NEXT: ldrh r1, [sp, #36]
-; CHECK-NEXT: ldrh r7, [sp, #84]
-; CHECK-NEXT: ldrh r6, [sp, #68]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r9, [sp, #80]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: str r7, [r0, #40]
-; CHECK-NEXT: str r1, [r0, #36]
-; CHECK-NEXT: ldrh r1, [sp, #64]
-; CHECK-NEXT: ldrh r4, [sp, #112]
-; CHECK-NEXT: ldrh r7, [sp, #96]
-; CHECK-NEXT: orr r1, r1, r9, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #108]
-; CHECK-NEXT: orr r7, r7, r4, lsl #16
-; CHECK-NEXT: str r7, [r0, #32]
-; CHECK-NEXT: str r1, [r0, #28]
-; CHECK-NEXT: ldrh r1, [sp, #92]
-; CHECK-NEXT: ldrh r8, [sp, #48]
-; CHECK-NEXT: ldrh r7, [sp, #32]
-; CHECK-NEXT: orr r1, r1, r6, lsl #16
-; CHECK-NEXT: ldrh lr, [sp, #76]
-; CHECK-NEXT: orr r7, r7, r8, lsl #16
-; CHECK-NEXT: str r7, [r0, #24]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #44]
-; CHECK-NEXT: ldrh r12, [sp, #104]
-; CHECK-NEXT: ldrh r7, [sp, #60]
-; CHECK-NEXT: ldrh r9, [sp, #72]
-; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #88]
-; CHECK-NEXT: orr r7, r7, lr, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #40]
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: str r7, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r5, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r4, r9, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r6, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <24 x bfloat> @llvm.vector.interleave6(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5)
- ret <24 x bfloat> %result
-}
-
-define <32 x bfloat> @interleave8_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5, <4 x bfloat> %vec6, <4 x bfloat> %vec7) {
-; CHECK-LABEL: interleave8_v4bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r7, [sp, #148]
-; CHECK-NEXT: strh r7, [r0, #62]
-; CHECK-NEXT: ldrh r1, [sp, #132]
-; CHECK-NEXT: ldrh r12, [sp, #116]
-; CHECK-NEXT: ldrh lr, [sp, #100]
-; CHECK-NEXT: ldrh r4, [sp, #84]
-; CHECK-NEXT: ldrh r9, [sp, #68]
-; CHECK-NEXT: ldrh r8, [sp, #52]
-; CHECK-NEXT: ldrh r7, [sp, #36]
-; CHECK-NEXT: strh r1, [r0, #60]
-; CHECK-NEXT: strh r12, [r0, #58]
-; CHECK-NEXT: strh lr, [r0, #56]
-; CHECK-NEXT: strh r4, [r0, #54]
-; CHECK-NEXT: strh r9, [r0, #52]
-; CHECK-NEXT: strh r8, [r0, #50]
-; CHECK-NEXT: strh r7, [r0, #48]
-; CHECK-NEXT: ldrh r1, [sp, #144]
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: ldrh r5, [sp, #112]
-; CHECK-NEXT: ldrh r4, [sp, #96]
-; CHECK-NEXT: ldrh r12, [sp, #80]
-; CHECK-NEXT: ldrh lr, [sp, #64]
-; CHECK-NEXT: ldrh r7, [sp, #48]
-; CHECK-NEXT: strh r1, [r0, #46]
-; CHECK-NEXT: strh r6, [r0, #44]
-; CHECK-NEXT: strh r5, [r0, #42]
-; CHECK-NEXT: strh r4, [r0, #40]
-; CHECK-NEXT: strh r12, [r0, #38]
-; CHECK-NEXT: strh lr, [r0, #36]
-; CHECK-NEXT: strh r7, [r0, #34]
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: ldrh r6, [sp, #140]
-; CHECK-NEXT: ldrh r5, [sp, #124]
-; CHECK-NEXT: ldrh r4, [sp, #108]
-; CHECK-NEXT: ldrh r12, [sp, #92]
-; CHECK-NEXT: ldrh lr, [sp, #76]
-; CHECK-NEXT: ldrh r7, [sp, #60]
-; CHECK-NEXT: ldrh r9, [sp, #44]
-; CHECK-NEXT: strh r1, [r0, #32]
-; CHECK-NEXT: strh r6, [r0, #30]
-; CHECK-NEXT: strh r5, [r0, #28]
-; CHECK-NEXT: strh r4, [r0, #26]
-; CHECK-NEXT: strh r12, [r0, #24]
-; CHECK-NEXT: strh lr, [r0, #22]
-; CHECK-NEXT: strh r7, [r0, #20]
-; CHECK-NEXT: strh r9, [r0, #18]
-; CHECK-NEXT: strh r3, [r0, #16]
-; CHECK-NEXT: ldrh r8, [sp, #136]
-; CHECK-NEXT: ldrh r5, [sp, #120]
-; CHECK-NEXT: ldrh r4, [sp, #104]
-; CHECK-NEXT: ldrh r6, [sp, #88]
-; CHECK-NEXT: ldrh r1, [sp, #72]
-; CHECK-NEXT: ldrh r7, [sp, #56]
-; CHECK-NEXT: ldrh r3, [sp, #40]
-; CHECK-NEXT: strh r8, [r0, #14]
-; CHECK-NEXT: strh r5, [r0, #12]
-; CHECK-NEXT: strh r4, [r0, #10]
-; CHECK-NEXT: strh r6, [r0, #8]
-; CHECK-NEXT: strh r1, [r0, #6]
-; CHECK-NEXT: strh r7, [r0, #4]
-; CHECK-NEXT: strh r3, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <32 x bfloat> @llvm.vector.interleave8(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5, <4 x bfloat> %vec6, <4 x bfloat> %vec7)
- ret <32 x bfloat> %result
-}
-
-define <16 x bfloat> @interleave2_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1) {
-; CHECK-LABEL: interleave2_v8bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, sp, #4
-; CHECK-NEXT: ldrh r7, [sp, #92]
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: ldrh r12, [sp, #88]
-; CHECK-NEXT: ldrh lr, [sp, #56]
-; CHECK-NEXT: ldrh r4, [sp, #84]
-; CHECK-NEXT: strh r7, [r0, #30]
-; CHECK-NEXT: strh r1, [r0, #28]
-; CHECK-NEXT: strh r12, [r0, #26]
-; CHECK-NEXT: strh lr, [r0, #24]
-; CHECK-NEXT: strh r4, [r0, #22]
-; CHECK-NEXT: ldrh r9, [sp, #52]
-; CHECK-NEXT: ldrh r8, [sp, #80]
-; CHECK-NEXT: ldrh r10, [sp, #48]
-; CHECK-NEXT: ldrh r11, [sp, #76]
-; CHECK-NEXT: ldrh r6, [sp, #44]
-; CHECK-NEXT: ldrh r5, [sp, #72]
-; CHECK-NEXT: ldrh r4, [sp, #40]
-; CHECK-NEXT: ldrh r7, [sp, #68]
-; CHECK-NEXT: ldrh r1, [sp, #64]
-; CHECK-NEXT: strh r9, [r0, #20]
-; CHECK-NEXT: strh r8, [r0, #18]
-; CHECK-NEXT: strh r10, [r0, #16]
-; CHECK-NEXT: strh r11, [r0, #14]
-; CHECK-NEXT: strh r6, [r0, #12]
-; CHECK-NEXT: strh r5, [r0, #10]
-; CHECK-NEXT: strh r4, [r0, #8]
-; CHECK-NEXT: strh r7, [r0, #6]
-; CHECK-NEXT: strh r3, [r0, #4]
-; CHECK-NEXT: strh r1, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: add sp, sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
- %result = call <16 x bfloat> @llvm.vector.interleave2(<8 x bfloat> %vec0, <8 x bfloat> %vec1)
- ret <16 x bfloat> %result
-}
-
-define <24 x bfloat> @interleave3_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2) {
-; CHECK-LABEL: interleave3_v8bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: ldrh r12, [sp, #116]
-; CHECK-NEXT: ldrh r1, [sp, #84]
-; CHECK-NEXT: ldrh lr, [sp, #80]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #44]
-; CHECK-NEXT: ldrh r1, [sp, #48]
-; CHECK-NEXT: ldrh r7, [sp, #52]
-; CHECK-NEXT: ldrh r6, [sp, #112]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r9, [sp, #44]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: str r7, [r0, #40]
-; CHECK-NEXT: str r1, [r0, #36]
-; CHECK-NEXT: ldrh r1, [sp, #104]
-; CHECK-NEXT: ldrh r4, [sp, #108]
-; CHECK-NEXT: ldrh r7, [sp, #76]
-; CHECK-NEXT: orr r1, r1, r9, lsl #16
-; CHECK-NEXT: ldrh r10, [sp, #100]
-; CHECK-NEXT: orr r7, r7, r4, lsl #16
-; CHECK-NEXT: str r7, [r0, #32]
-; CHECK-NEXT: str r1, [r0, #28]
-; CHECK-NEXT: ldrh r1, [sp, #68]
-; CHECK-NEXT: ldrh r8, [sp, #72]
-; CHECK-NEXT: ldrh r7, [sp, #40]
-; CHECK-NEXT: orr r1, r1, r10, lsl #16
-; CHECK-NEXT: ldrh lr, [sp, #64]
-; CHECK-NEXT: orr r7, r7, r8, lsl #16
-; CHECK-NEXT: str r7, [r0, #24]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: ldrh r12, [sp, #36]
-; CHECK-NEXT: ldrh r9, [sp, #92]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #96]
-; CHECK-NEXT: ldrh r6, [sp, #60]
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: orr r7, r7, r12, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #88]
-; CHECK-NEXT: str r7, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r6, r9, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r5, r3, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r4, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
- %result = call <24 x bfloat> @llvm.vector.interleave3(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2)
- ret <24 x bfloat> %result
-}
-
-define <32 x bfloat> @interleave4_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3) {
-; CHECK-LABEL: interleave4_v8bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: ldrh r7, [sp, #148]
-; CHECK-NEXT: strh r7, [r0, #62]
-; CHECK-NEXT: ldrh r1, [sp, #116]
-; CHECK-NEXT: ldrh r12, [sp, #84]
-; CHECK-NEXT: ldrh lr, [sp, #52]
-; CHECK-NEXT: ldrh r4, [sp, #144]
-; CHECK-NEXT: ldrh r9, [sp, #112]
-; CHECK-NEXT: ldrh r8, [sp, #80]
-; CHECK-NEXT: ldrh r7, [sp, #48]
-; CHECK-NEXT: strh r1, [r0, #60]
-; CHECK-NEXT: strh r12, [r0, #58]
-; CHECK-NEXT: strh lr, [r0, #56]
-; CHECK-NEXT: strh r4, [r0, #54]
-; CHECK-NEXT: strh r9, [r0, #52]
-; CHECK-NEXT: strh r8, [r0, #50]
-; CHECK-NEXT: strh r7, [r0, #48]
-; CHECK-NEXT: ldrh r1, [sp, #140]
-; CHECK-NEXT: ldrh r6, [sp, #108]
-; CHECK-NEXT: ldrh r5, [sp, #76]
-; CHECK-NEXT: ldrh r4, [sp, #44]
-; CHECK-NEXT: ldrh r12, [sp, #136]
-; CHECK-NEXT: ldrh lr, [sp, #104]
-; CHECK-NEXT: ldrh r7, [sp, #72]
-; CHECK-NEXT: strh r1, [r0, #46]
-; CHECK-NEXT: strh r6, [r0, #44]
-; CHECK-NEXT: strh r5, [r0, #42]
-; CHECK-NEXT: strh r4, [r0, #40]
-; CHECK-NEXT: strh r12, [r0, #38]
-; CHECK-NEXT: strh lr, [r0, #36]
-; CHECK-NEXT: strh r7, [r0, #34]
-; CHECK-NEXT: ldrh r1, [sp, #40]
-; CHECK-NEXT: ldrh r6, [sp, #132]
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: ldrh r4, [sp, #68]
-; CHECK-NEXT: ldrh r12, [sp, #36]
-; CHECK-NEXT: ldrh lr, [sp, #128]
-; CHECK-NEXT: ldrh r7, [sp, #96]
-; CHECK-NEXT: strh r1, [r0, #32]
-; CHECK-NEXT: strh r6, [r0, #30]
-; CHECK-NEXT: strh r5, [r0, #28]
-; CHECK-NEXT: strh r4, [r0, #26]
-; CHECK-NEXT: strh r12, [r0, #24]
-; CHECK-NEXT: strh lr, [r0, #22]
-; CHECK-NEXT: strh r7, [r0, #20]
-; CHECK-NEXT: ldrh r8, [sp, #64]
-; CHECK-NEXT: ldrh r9, [sp, #32]
-; CHECK-NEXT: ldrh r10, [sp, #124]
-; CHECK-NEXT: ldrh r4, [sp, #92]
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: ldrh r6, [sp, #120]
-; CHECK-NEXT: ldrh r7, [sp, #88]
-; CHECK-NEXT: ldrh r5, [sp, #56]
-; CHECK-NEXT: strh r8, [r0, #18]
-; CHECK-NEXT: strh r9, [r0, #16]
-; CHECK-NEXT: strh r10, [r0, #14]
-; CHECK-NEXT: strh r4, [r0, #12]
-; CHECK-NEXT: strh r1, [r0, #10]
-; CHECK-NEXT: strh r3, [r0, #8]
-; CHECK-NEXT: strh r6, [r0, #6]
-; CHECK-NEXT: strh r7, [r0, #4]
-; CHECK-NEXT: strh r5, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
- %result = call <32 x bfloat> @llvm.vector.interleave4(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3)
- ret <32 x bfloat> %result
-}
-
-
-define <48 x bfloat> @interleave6_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5) {
-; CHECK-LABEL: interleave6_v8bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r12, [sp, #212]
-; CHECK-NEXT: ldrh r1, [sp, #180]
-; CHECK-NEXT: ldrh lr, [sp, #84]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: str r1, [r0, #92]
-; CHECK-NEXT: ldrh r1, [sp, #52]
-; CHECK-NEXT: ldrh r7, [sp, #148]
-; CHECK-NEXT: ldrh r6, [sp, #116]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r9, [sp, #144]
-; CHECK-NEXT: orr r7, r6, r7, lsl #16
-; CHECK-NEXT: str r7, [r0, #88]
-; CHECK-NEXT: str r1, [r0, #84]
-; CHECK-NEXT: ldrh r1, [sp, #112]
-; CHECK-NEXT: ldrh r4, [sp, #208]
-; CHECK-NEXT: ldrh r7, [sp, #176]
-; CHECK-NEXT: orr r1, r1, r9, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #204]
-; CHECK-NEXT: orr r7, r7, r4, lsl #16
-; CHECK-NEXT: str r7, [r0, #80]
-; CHECK-NEXT: str r1, [r0, #76]
-; CHECK-NEXT: ldrh r1, [sp, #172]
-; CHECK-NEXT: ldrh r8, [sp, #80]
-; CHECK-NEXT: ldrh r7, [sp, #48]
-; CHECK-NEXT: orr r1, r1, r6, lsl #16
-; CHECK-NEXT: ldrh r4, [sp, #76]
-; CHECK-NEXT: orr r7, r7, r8, lsl #16
-; CHECK-NEXT: str r7, [r0, #72]
-; CHECK-NEXT: str r1, [r0, #68]
-; CHECK-NEXT: ldrh r1, [sp, #44]
-; CHECK-NEXT: ldrh r5, [sp, #140]
-; CHECK-NEXT: ldrh r7, [sp, #108]
-; CHECK-NEXT: orr r1, r1, r4, lsl #16
-; CHECK-NEXT: ldrh lr, [sp, #136]
-; CHECK-NEXT: orr r5, r7, r5, lsl #16
-; CHECK-NEXT: str r5, [r0, #64]
-; CHECK-NEXT: str r1, [r0, #60]
-; CHECK-NEXT: ldrh r1, [sp, #104]
-; CHECK-NEXT: ldrh r12, [sp, #200]
-; CHECK-NEXT: ldrh r5, [sp, #168]
-; CHECK-NEXT: orr r1, r1, lr, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #196]
-; CHECK-NEXT: orr r5, r5, r12, lsl #16
-; CHECK-NEXT: str r5, [r0, #56]
-; CHECK-NEXT: str r1, [r0, #52]
-; CHECK-NEXT: ldrh r1, [sp, #164]
-; CHECK-NEXT: ldrh r6, [sp, #72]
-; CHECK-NEXT: ldrh r5, [sp, #40]
-; CHECK-NEXT: orr r1, r1, r7, lsl #16
-; CHECK-NEXT: ldrh r12, [sp, #68]
-; CHECK-NEXT: orr r5, r5, r6, lsl #16
-; CHECK-NEXT: str r5, [r0, #48]
-; CHECK-NEXT: str r1, [r0, #44]
-; CHECK-NEXT: ldrh r1, [sp, #36]
-; CHECK-NEXT: ldrh r4, [sp, #132]
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: orr r1, r1, r12, lsl #16
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: orr r4, r5, r4, lsl #16
-; CHECK-NEXT: str r4, [r0, #40]
-; CHECK-NEXT: str r1, [r0, #36]
-; CHECK-NEXT: ldrh r1, [sp, #96]
-; CHECK-NEXT: ldrh lr, [sp, #192]
-; CHECK-NEXT: ldrh r4, [sp, #160]
-; CHECK-NEXT: orr r1, r1, r6, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #188]
-; CHECK-NEXT: orr r4, r4, lr, lsl #16
-; CHECK-NEXT: str r4, [r0, #32]
-; CHECK-NEXT: str r1, [r0, #28]
-; CHECK-NEXT: ldrh r1, [sp, #156]
-; CHECK-NEXT: ldrh r7, [sp, #64]
-; CHECK-NEXT: ldrh r4, [sp, #32]
-; CHECK-NEXT: orr r1, r1, r5, lsl #16
-; CHECK-NEXT: ldrh r12, [sp, #124]
-; CHECK-NEXT: orr r4, r4, r7, lsl #16
-; CHECK-NEXT: str r4, [r0, #24]
-; CHECK-NEXT: str r1, [r0, #20]
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: ldrh lr, [sp, #184]
-; CHECK-NEXT: ldrh r4, [sp, #92]
-; CHECK-NEXT: ldrh r8, [sp, #120]
-; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
-; CHECK-NEXT: ldrh r7, [sp, #152]
-; CHECK-NEXT: orr r4, r4, r12, lsl #16
-; CHECK-NEXT: ldrh r5, [sp, #56]
-; CHECK-NEXT: ldrh r6, [sp, #88]
-; CHECK-NEXT: str r4, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: orr r1, r7, lr, lsl #16
-; CHECK-NEXT: str r1, [r0, #8]
-; CHECK-NEXT: orr r1, r6, r8, lsl #16
-; CHECK-NEXT: str r1, [r0, #4]
-; CHECK-NEXT: pkhbt r1, r2, r5, lsl #16
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <48 x bfloat> @llvm.vector.interleave6(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5)
- ret <48 x bfloat> %result
-}
-
-define <64 x bfloat> @interleave8_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5, <8 x bfloat> %vec6, <8 x bfloat> %vec7) {
-; CHECK-LABEL: interleave8_v8bf16:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: add r5, sp, #256
-; CHECK-NEXT: ldrh r1, [sp, #244]
-; CHECK-NEXT: ldrh r12, [sp, #212]
-; CHECK-NEXT: ldrh r7, [r5, #20]
-; CHECK-NEXT: strh r7, [r0, #126]
-; CHECK-NEXT: strh r1, [r0, #124]
-; CHECK-NEXT: add r1, sp, #256
-; CHECK-NEXT: ldrh lr, [sp, #180]
-; CHECK-NEXT: ldrh r4, [sp, #148]
-; CHECK-NEXT: ldrh r9, [sp, #116]
-; CHECK-NEXT: ldrh r8, [sp, #84]
-; CHECK-NEXT: ldrh r7, [sp, #52]
-; CHECK-NEXT: ldrh r1, [r1, #16]
-; CHECK-NEXT: ldrh r6, [sp, #240]
-; CHECK-NEXT: strh r12, [r0, #122]
-; CHECK-NEXT: strh lr, [r0, #120]
-; CHECK-NEXT: strh r4, [r0, #118]
-; CHECK-NEXT: strh r9, [r0, #116]
-; CHECK-NEXT: strh r8, [r0, #114]
-; CHECK-NEXT: add r8, sp, #256
-; CHECK-NEXT: strh r7, [r0, #112]
-; CHECK-NEXT: strh r1, [r0, #110]
-; CHECK-NEXT: strh r6, [r0, #108]
-; CHECK-NEXT: add r6, sp, #256
-; CHECK-NEXT: ldrh r5, [sp, #208]
-; CHECK-NEXT: strh r5, [r0, #106]
-; CHECK-NEXT: ldrh r4, [sp, #176]
-; CHECK-NEXT: ldrh r12, [sp, #144]
-; CHECK-NEXT: ldrh lr, [sp, #112]
-; CHECK-NEXT: ldrh r7, [sp, #80]
-; CHECK-NEXT: ldrh r1, [sp, #48]
-; CHECK-NEXT: ldrh r6, [r6, #12]
-; CHECK-NEXT: ldrh r5, [sp, #236]
-; CHECK-NEXT: strh r4, [r0, #104]
-; CHECK-NEXT: strh r12, [r0, #102]
-; CHECK-NEXT: strh lr, [r0, #100]
-; CHECK-NEXT: strh r7, [r0, #98]
-; CHECK-NEXT: strh r1, [r0, #96]
-; CHECK-NEXT: strh r6, [r0, #94]
-; CHECK-NEXT: strh r5, [r0, #92]
-; CHECK-NEXT: add r5, sp, #256
-; CHECK-NEXT: ldrh r4, [sp, #204]
-; CHECK-NEXT: strh r4, [r0, #90]
-; CHECK-NEXT: ldrh r12, [sp, #172]
-; CHECK-NEXT: ldrh lr, [sp, #140]
-; CHECK-NEXT: ldrh r7, [sp, #108]
-; CHECK-NEXT: ldrh r1, [sp, #76]
-; CHECK-NEXT: ldrh r6, [sp, #44]
-; CHECK-NEXT: ldrh r5, [r5, #8]
-; CHECK-NEXT: ldrh r4, [sp, #232]
-; CHECK-NEXT: strh r12, [r0, #88]
-; CHECK-NEXT: strh lr, [r0, #86]
-; CHECK-NEXT: strh r7, [r0, #84]
-; CHECK-NEXT: strh r1, [r0, #82]
-; CHECK-NEXT: strh r6, [r0, #80]
-; CHECK-NEXT: strh r5, [r0, #78]
-; CHECK-NEXT: strh r4, [r0, #76]
-; CHECK-NEXT: add r4, sp, #256
-; CHECK-NEXT: ldrh r12, [sp, #200]
-; CHECK-NEXT: strh r12, [r0, #74]
-; CHECK-NEXT: ldrh lr, [sp, #168]
-; CHECK-NEXT: ldrh r7, [sp, #136]
-; CHECK-NEXT: ldrh r1, [sp, #104]
-; CHECK-NEXT: ldrh r6, [sp, #72]
-; CHECK-NEXT: ldrh r5, [sp, #40]
-; CHECK-NEXT: ldrh r4, [r4, #4]
-; CHECK-NEXT: ldrh r12, [sp, #228]
-; CHECK-NEXT: strh lr, [r0, #72]
-; CHECK-NEXT: strh r7, [r0, #70]
-; CHECK-NEXT: strh r1, [r0, #68]
-; CHECK-NEXT: strh r6, [r0, #66]
-; CHECK-NEXT: strh r5, [r0, #64]
-; CHECK-NEXT: strh r4, [r0, #62]
-; CHECK-NEXT: strh r12, [r0, #60]
-; CHECK-NEXT: ldrh lr, [sp, #196]
-; CHECK-NEXT: ldrh r7, [sp, #164]
-; CHECK-NEXT: ldrh r1, [sp, #132]
-; CHECK-NEXT: ldrh r6, [sp, #100]
-; CHECK-NEXT: ldrh r5, [sp, #68]
-; CHECK-NEXT: ldrh r4, [sp, #36]
-; CHECK-NEXT: ldrh r12, [r8]
-; CHECK-NEXT: strh lr, [r0, #58]
-; CHECK-NEXT: strh r7, [r0, #56]
-; CHECK-NEXT: strh r1, [r0, #54]
-; CHECK-NEXT: strh r6, [r0, #52]
-; CHECK-NEXT: strh r5, [r0, #50]
-; CHECK-NEXT: strh r4, [r0, #48]
-; CHECK-NEXT: strh r12, [r0, #46]
-; CHECK-NEXT: ldrh lr, [sp, #224]
-; CHECK-NEXT: ldrh r7, [sp, #192]
-; CHECK-NEXT: ldrh r1, [sp, #160]
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: ldrh r5, [sp, #96]
-; CHECK-NEXT: ldrh r4, [sp, #64]
-; CHECK-NEXT: ldrh r12, [sp, #32]
-; CHECK-NEXT: strh lr, [r0, #44]
-; CHECK-NEXT: strh r7, [r0, #42]
-; CHECK-NEXT: strh r1, [r0, #40]
-; CHECK-NEXT: strh r6, [r0, #38]
-; CHECK-NEXT: strh r5, [r0, #36]
-; CHECK-NEXT: strh r4, [r0, #34]
-; CHECK-NEXT: strh r12, [r0, #32]
-; CHECK-NEXT: ldrh lr, [sp, #252]
-; CHECK-NEXT: ldrh r7, [sp, #220]
-; CHECK-NEXT: ldrh r1, [sp, #188]
-; CHECK-NEXT: ldrh r6, [sp, #156]
-; CHECK-NEXT: ldrh r5, [sp, #124]
-; CHECK-NEXT: ldrh r4, [sp, #92]
-; CHECK-NEXT: ldrh r12, [sp, #60]
-; CHECK-NEXT: strh lr, [r0, #30]
-; CHECK-NEXT: strh r7, [r0, #28]
-; CHECK-NEXT: strh r1, [r0, #26]
-; CHECK-NEXT: strh r6, [r0, #24]
-; CHECK-NEXT: strh r5, [r0, #22]
-; CHECK-NEXT: strh r4, [r0, #20]
-; CHECK-NEXT: strh r12, [r0, #18]
-; CHECK-NEXT: strh r3, [r0, #16]
-; CHECK-NEXT: ldrh lr, [sp, #248]
-; CHECK-NEXT: ldrh r7, [sp, #216]
-; CHECK-NEXT: ldrh r1, [sp, #184]
-; CHECK-NEXT: ldrh r6, [sp, #152]
-; CHECK-NEXT: ldrh r5, [sp, #120]
-; CHECK-NEXT: ldrh r4, [sp, #88]
-; CHECK-NEXT: ldrh r3, [sp, #56]
-; CHECK-NEXT: strh lr, [r0, #14]
-; CHECK-NEXT: strh r7, [r0, #12]
-; CHECK-NEXT: strh r1, [r0, #10]
-; CHECK-NEXT: strh r6, [r0, #8]
-; CHECK-NEXT: strh r5, [r0, #6]
-; CHECK-NEXT: strh r4, [r0, #4]
-; CHECK-NEXT: strh r3, [r0, #2]
-; CHECK-NEXT: strh r2, [r0]
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
- %result = call <64 x bfloat> @llvm.vector.interleave8(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5, <8 x bfloat> %vec6, <8 x bfloat> %vec7)
- ret <64 x bfloat> %result
-}
-
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-IADISABLED: {{.*}}
-; CHECK-IAENABLED: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/ARM/vector-deinterleave.ll
similarity index 77%
rename from llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll
rename to llvm/test/CodeGen/ARM/vector-deinterleave.ll
index ee7da511d1c60..7705a9730d30b 100644
--- a/llvm/test/CodeGen/ARM/fixed-vector-deinterleave.ll
+++ b/llvm/test/CodeGen/ARM/vector-deinterleave.ll
@@ -1,15 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
-; RUN: llc -mtriple=armv8-none-none-eabi -mattr=+neon -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
+; RUN: llc -mtriple=armv8-none-none-eabihf -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
+; RUN: llc -mtriple=armv8-none-none-eabihf -mattr=+neon -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
define void @deinterleave2_v8i8(<16 x i8> %vec) {
; CHECK-LABEL: deinterleave2_v8i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vuzp.8 d17, d16
-; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: vorr d16, d0, d0
+; CHECK-NEXT: vuzp.8 d16, d1
; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: bx lr
%result = call { <8 x i8>, <8 x i8> } @llvm.vector.deinterleave2(<16 x i8> %vec)
%result0 = extractvalue { <8 x i8>, <8 x i8> } %result, 0
@@ -91,19 +90,16 @@ define void @deinterleave3_v8i8(<24 x i8> %vec) {
define void @deinterleave4_v8i8(<32 x i8> %vec) {
; CHECK-LABEL: deinterleave4_v8i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vorr d20, d18, d18
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vuzp.8 d20, d19
+; CHECK-NEXT: vorr d16, d2, d2
+; CHECK-NEXT: vorr d17, d0, d0
+; CHECK-NEXT: vuzp.8 d16, d3
+; CHECK-NEXT: vuzp.8 d17, d1
+; CHECK-NEXT: vuzp.8 d1, d3
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: vuzp.8 d17, d16
-; CHECK-NEXT: vuzp.8 d16, d19
-; CHECK-NEXT: @ fake_use: $d16
-; CHECK-NEXT: vuzp.8 d17, d20
; CHECK-NEXT: @ fake_use: $d17
-; CHECK-NEXT: @ fake_use: $d20
-; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d3 $q1
; CHECK-NEXT: bx lr
%result = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.vector.deinterleave4(<32 x i8> %vec)
%result0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 0
@@ -258,37 +254,30 @@ define void @deinterleave6_v8i8(<48 x i8> %vec) {
define void @deinterleave8_v8i8(<64 x i8> %vec) {
; CHECK-LABEL: deinterleave8_v8i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vorr d25, d16, d16
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vorr d26, d18, d18
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: vmov d23, r0, r1
-; CHECK-NEXT: vorr d24, d20, d20
-; CHECK-NEXT: vuzp.8 d25, d17
-; CHECK-NEXT: vuzp.8 d23, d22
-; CHECK-NEXT: vuzp.8 d24, d21
-; CHECK-NEXT: vuzp.8 d26, d19
-; CHECK-NEXT: vuzp.8 d25, d24
-; CHECK-NEXT: vuzp.8 d23, d26
-; CHECK-NEXT: vuzp.8 d17, d21
-; CHECK-NEXT: vuzp.8 d22, d19
-; CHECK-NEXT: vuzp.8 d23, d25
-; CHECK-NEXT: @ fake_use: $d23
-; CHECK-NEXT: vuzp.8 d19, d21
-; CHECK-NEXT: @ fake_use: $d19 $q9
-; CHECK-NEXT: vuzp.8 d22, d17
-; CHECK-NEXT: @ fake_use: $d22
-; CHECK-NEXT: vuzp.8 d26, d24
-; CHECK-NEXT: @ fake_use: $d26
-; CHECK-NEXT: @ fake_use: $d25
-; CHECK-NEXT: @ fake_use: $d17 $q8
-; CHECK-NEXT: @ fake_use: $d24
-; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: vorr d16, d6, d6
+; CHECK-NEXT: vorr d17, d4, d4
+; CHECK-NEXT: vorr d18, d2, d2
+; CHECK-NEXT: vorr d19, d0, d0
+; CHECK-NEXT: vuzp.8 d16, d7
+; CHECK-NEXT: vuzp.8 d17, d5
+; CHECK-NEXT: vuzp.8 d18, d3
+; CHECK-NEXT: vuzp.8 d19, d1
+; CHECK-NEXT: vuzp.8 d17, d16
+; CHECK-NEXT: vuzp.8 d19, d18
+; CHECK-NEXT: vuzp.8 d5, d7
+; CHECK-NEXT: vuzp.8 d1, d3
+; CHECK-NEXT: vuzp.8 d19, d17
+; CHECK-NEXT: @ fake_use: $d19
+; CHECK-NEXT: vuzp.8 d3, d7
+; CHECK-NEXT: @ fake_use: $d3 $q1
+; CHECK-NEXT: vuzp.8 d1, d5
+; CHECK-NEXT: @ fake_use: $d1 $q0
+; CHECK-NEXT: vuzp.8 d18, d16
+; CHECK-NEXT: @ fake_use: $d18
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d5 $q2
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d7 $q3
; CHECK-NEXT: bx lr
%result = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.vector.deinterleave8(<64 x i8> %vec)
%result0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %result, 0
@@ -313,11 +302,10 @@ define void @deinterleave8_v8i8(<64 x i8> %vec) {
define void @deinterleave2_v4i16(<8 x i16> %vec) {
; CHECK-LABEL: deinterleave2_v4i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vuzp.16 d17, d16
-; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: vorr d16, d0, d0
+; CHECK-NEXT: vuzp.16 d16, d1
; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: bx lr
%result = call { <4 x i16>, <4 x i16> } @llvm.vector.deinterleave2(<8 x i16> %vec)
%result0 = extractvalue { <4 x i16>, <4 x i16> } %result, 0
@@ -375,19 +363,16 @@ define void @deinterleave3_v4i16(<12 x i16> %vec) {
define void @deinterleave4_v4i16(<16 x i16> %vec) {
; CHECK-LABEL: deinterleave4_v4i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vorr d20, d18, d18
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vuzp.16 d20, d19
+; CHECK-NEXT: vorr d16, d2, d2
+; CHECK-NEXT: vorr d17, d0, d0
+; CHECK-NEXT: vuzp.16 d16, d3
+; CHECK-NEXT: vuzp.16 d17, d1
+; CHECK-NEXT: vuzp.16 d1, d3
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: vuzp.16 d17, d16
-; CHECK-NEXT: vuzp.16 d16, d19
-; CHECK-NEXT: @ fake_use: $d16
-; CHECK-NEXT: vuzp.16 d17, d20
; CHECK-NEXT: @ fake_use: $d17
-; CHECK-NEXT: @ fake_use: $d20
-; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d3 $q1
; CHECK-NEXT: bx lr
%result = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.vector.deinterleave4(<16 x i16> %vec)
%result0 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 0
@@ -494,37 +479,30 @@ define void @deinterleave6_v4i16(<24 x i16> %vec) {
define void @deinterleave8_v4i16(<32 x i16> %vec) {
; CHECK-LABEL: deinterleave8_v4i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vorr d25, d16, d16
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vorr d26, d18, d18
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: vmov d23, r0, r1
-; CHECK-NEXT: vorr d24, d20, d20
-; CHECK-NEXT: vuzp.16 d25, d17
-; CHECK-NEXT: vuzp.16 d23, d22
-; CHECK-NEXT: vuzp.16 d24, d21
-; CHECK-NEXT: vuzp.16 d26, d19
-; CHECK-NEXT: vuzp.16 d25, d24
-; CHECK-NEXT: vuzp.16 d23, d26
-; CHECK-NEXT: vuzp.16 d17, d21
-; CHECK-NEXT: vuzp.16 d22, d19
-; CHECK-NEXT: vuzp.16 d23, d25
-; CHECK-NEXT: @ fake_use: $d23
-; CHECK-NEXT: vuzp.16 d19, d21
-; CHECK-NEXT: @ fake_use: $d19 $q9
-; CHECK-NEXT: vuzp.16 d22, d17
-; CHECK-NEXT: @ fake_use: $d22
-; CHECK-NEXT: vuzp.16 d26, d24
-; CHECK-NEXT: @ fake_use: $d26
-; CHECK-NEXT: @ fake_use: $d25
-; CHECK-NEXT: @ fake_use: $d17 $q8
-; CHECK-NEXT: @ fake_use: $d24
-; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: vorr d16, d6, d6
+; CHECK-NEXT: vorr d17, d4, d4
+; CHECK-NEXT: vorr d18, d2, d2
+; CHECK-NEXT: vorr d19, d0, d0
+; CHECK-NEXT: vuzp.16 d16, d7
+; CHECK-NEXT: vuzp.16 d17, d5
+; CHECK-NEXT: vuzp.16 d18, d3
+; CHECK-NEXT: vuzp.16 d19, d1
+; CHECK-NEXT: vuzp.16 d17, d16
+; CHECK-NEXT: vuzp.16 d19, d18
+; CHECK-NEXT: vuzp.16 d5, d7
+; CHECK-NEXT: vuzp.16 d1, d3
+; CHECK-NEXT: vuzp.16 d19, d17
+; CHECK-NEXT: @ fake_use: $d19
+; CHECK-NEXT: vuzp.16 d3, d7
+; CHECK-NEXT: @ fake_use: $d3 $q1
+; CHECK-NEXT: vuzp.16 d1, d5
+; CHECK-NEXT: @ fake_use: $d1 $q0
+; CHECK-NEXT: vuzp.16 d18, d16
+; CHECK-NEXT: @ fake_use: $d18
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d5 $q2
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d7 $q3
; CHECK-NEXT: bx lr
%result = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.vector.deinterleave8(<32 x i16> %vec)
%result0 = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %result, 0
@@ -550,11 +528,10 @@ define void @deinterleave8_v4i16(<32 x i16> %vec) {
define void @deinterleave2_v2i32(<4 x i32> %vec) {
; CHECK-LABEL: deinterleave2_v2i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vtrn.32 d17, d16
-; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: vorr d16, d0, d0
+; CHECK-NEXT: vtrn.32 d16, d1
; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: bx lr
%result = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2(<4 x i32> %vec)
%result0 = extractvalue { <2 x i32>, <2 x i32> } %result, 0
@@ -597,19 +574,16 @@ define void @deinterleave3_v2i32(<6 x i32> %vec) {
define void @deinterleave4_v2i32(<8 x i32> %vec) {
; CHECK-LABEL: deinterleave4_v2i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vorr d20, d18, d18
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vtrn.32 d20, d19
+; CHECK-NEXT: vorr d16, d2, d2
+; CHECK-NEXT: vorr d17, d0, d0
+; CHECK-NEXT: vtrn.32 d16, d3
+; CHECK-NEXT: vtrn.32 d17, d1
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: vtrn.32 d17, d16
-; CHECK-NEXT: vtrn.32 d16, d19
-; CHECK-NEXT: @ fake_use: $d16
-; CHECK-NEXT: vtrn.32 d17, d20
; CHECK-NEXT: @ fake_use: $d17
-; CHECK-NEXT: @ fake_use: $d20
-; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d3 $q1
; CHECK-NEXT: bx lr
%result = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave4(<8 x i32> %vec)
%result0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 0
@@ -683,37 +657,30 @@ define void @deinterleave6_v2i32(<12 x i32> %vec) {
define void @deinterleave8_v2i32(<16 x i32> %vec) {
; CHECK-LABEL: deinterleave8_v2i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vorr d25, d16, d16
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vorr d26, d18, d18
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: vmov d23, r0, r1
-; CHECK-NEXT: vorr d24, d20, d20
-; CHECK-NEXT: vtrn.32 d25, d17
-; CHECK-NEXT: vtrn.32 d23, d22
-; CHECK-NEXT: vtrn.32 d24, d21
-; CHECK-NEXT: vtrn.32 d26, d19
-; CHECK-NEXT: vtrn.32 d25, d24
-; CHECK-NEXT: vtrn.32 d23, d26
-; CHECK-NEXT: vtrn.32 d17, d21
-; CHECK-NEXT: vtrn.32 d22, d19
-; CHECK-NEXT: vtrn.32 d23, d25
-; CHECK-NEXT: @ fake_use: $d23
-; CHECK-NEXT: vtrn.32 d19, d21
-; CHECK-NEXT: @ fake_use: $d19 $q9
-; CHECK-NEXT: vtrn.32 d22, d17
-; CHECK-NEXT: @ fake_use: $d22
-; CHECK-NEXT: vtrn.32 d26, d24
-; CHECK-NEXT: @ fake_use: $d26
-; CHECK-NEXT: @ fake_use: $d25
-; CHECK-NEXT: @ fake_use: $d17 $q8
-; CHECK-NEXT: @ fake_use: $d24
-; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: vorr d16, d6, d6
+; CHECK-NEXT: vorr d17, d4, d4
+; CHECK-NEXT: vorr d18, d2, d2
+; CHECK-NEXT: vorr d19, d0, d0
+; CHECK-NEXT: vtrn.32 d16, d7
+; CHECK-NEXT: vtrn.32 d17, d5
+; CHECK-NEXT: vtrn.32 d18, d3
+; CHECK-NEXT: vtrn.32 d19, d1
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: vtrn.32 d19, d18
+; CHECK-NEXT: vtrn.32 d5, d7
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: vtrn.32 d19, d17
+; CHECK-NEXT: @ fake_use: $d19
+; CHECK-NEXT: vtrn.32 d3, d7
+; CHECK-NEXT: @ fake_use: $d3 $q1
+; CHECK-NEXT: vtrn.32 d1, d5
+; CHECK-NEXT: @ fake_use: $d1 $q0
+; CHECK-NEXT: vtrn.32 d18, d16
+; CHECK-NEXT: @ fake_use: $d18
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d5 $q2
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d7 $q3
; CHECK-NEXT: bx lr
%result = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.vector.deinterleave8(<16 x i32> %vec)
%result0 = extractvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %result, 0
@@ -739,11 +706,10 @@ define void @deinterleave8_v2i32(<16 x i32> %vec) {
define void @deinterleave2_v2f32(<4 x float> %vec) {
; CHECK-LABEL: deinterleave2_v2f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vtrn.32 d17, d16
-; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: vorr d16, d0, d0
+; CHECK-NEXT: vtrn.32 d16, d1
; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: bx lr
%result = call { <2 x float>, <2 x float> } @llvm.vector.deinterleave2(<4 x float> %vec)
%result0 = extractvalue { <2 x float>, <2 x float> } %result, 0
@@ -758,15 +724,14 @@ define void @deinterleave3_v2f32(<6 x float> %vec) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .pad #24
; CHECK-NEXT: sub sp, sp, #24
-; CHECK-NEXT: vldr s1, [sp, #28]
-; CHECK-NEXT: vmov s3, r1
-; CHECK-NEXT: vldr s0, [sp, #24]
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmov s5, r3
+; CHECK-NEXT: @ kill: def $s5 killed $s5 killed $d2 def $d2
+; CHECK-NEXT: @ kill: def $s3 killed $s3 killed $d1 def $d1
+; CHECK-NEXT: @ kill: def $s1 killed $s1 killed $d0 def $d0
; CHECK-NEXT: mov r0, sp
-; CHECK-NEXT: vmov s4, r2
-; CHECK-NEXT: vstr d0, [sp, #16]
-; CHECK-NEXT: vstmia sp, {d1, d2}
+; CHECK-NEXT: @ kill: def $s4 killed $s4 killed $d2 def $d2
+; CHECK-NEXT: @ kill: def $s2 killed $s2 killed $d1 def $d1
+; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $d0 def $d0
+; CHECK-NEXT: vstmia sp, {d0, d1, d2}
; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r0:64]
; CHECK-NEXT: @ fake_use: $d16
; CHECK-NEXT: @ fake_use: $d17
@@ -786,19 +751,16 @@ define void @deinterleave3_v2f32(<6 x float> %vec) {
define void @deinterleave4_v2f32(<8 x float> %vec) {
; CHECK-LABEL: deinterleave4_v2f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vorr d20, d18, d18
-; CHECK-NEXT: vmov d16, r2, r3
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vtrn.32 d20, d19
+; CHECK-NEXT: vorr d16, d2, d2
+; CHECK-NEXT: vorr d17, d0, d0
+; CHECK-NEXT: vtrn.32 d16, d3
+; CHECK-NEXT: vtrn.32 d17, d1
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: @ fake_use: $d1 $q0
; CHECK-NEXT: vtrn.32 d17, d16
-; CHECK-NEXT: vtrn.32 d16, d19
-; CHECK-NEXT: @ fake_use: $d16
-; CHECK-NEXT: vtrn.32 d17, d20
; CHECK-NEXT: @ fake_use: $d17
-; CHECK-NEXT: @ fake_use: $d20
-; CHECK-NEXT: @ fake_use: $d19 $q9
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d3 $q1
; CHECK-NEXT: bx lr
%result = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.vector.deinterleave4(<8 x float> %vec)
%result0 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 0
@@ -817,39 +779,37 @@ define void @deinterleave6_v2f32(<12 x float> %vec) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .pad #48
; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: vldr s1, [sp, #76]
-; CHECK-NEXT: add r12, sp, #24
-; CHECK-NEXT: vldr s0, [sp, #72]
-; CHECK-NEXT: vldr s3, [sp, #68]
-; CHECK-NEXT: vldr s5, [sp, #60]
-; CHECK-NEXT: vldr s7, [sp, #52]
-; CHECK-NEXT: vldr s2, [sp, #64]
-; CHECK-NEXT: vldr s4, [sp, #56]
-; CHECK-NEXT: vstr d0, [sp, #40]
-; CHECK-NEXT: vmov s1, r1
-; CHECK-NEXT: vmov s0, r0
-; CHECK-NEXT: vldr s6, [sp, #48]
-; CHECK-NEXT: vstr d1, [sp, #32]
-; CHECK-NEXT: vmov s3, r3
-; CHECK-NEXT: vstr d2, [sp, #24]
-; CHECK-NEXT: vmov s2, r2
-; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r12:64]
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: @ kill: def $s11 killed $s11 killed $d5 def $d5
+; CHECK-NEXT: @ kill: def $s9 killed $s9 killed $d4 def $d4
+; CHECK-NEXT: @ kill: def $s7 killed $s7 killed $d3 def $d3
+; CHECK-NEXT: add r0, sp, #24
+; CHECK-NEXT: @ kill: def $s5 killed $s5 killed $d2 def $d2
+; CHECK-NEXT: @ kill: def $s3 killed $s3 killed $d1 def $d1
+; CHECK-NEXT: @ kill: def $s1 killed $s1 killed $d0 def $d0
+; CHECK-NEXT: @ kill: def $s10 killed $s10 killed $d5 def $d5
+; CHECK-NEXT: @ kill: def $s8 killed $s8 killed $d4 def $d4
+; CHECK-NEXT: @ kill: def $s6 killed $s6 killed $d3 def $d3
+; CHECK-NEXT: vstmia r1, {d3, d4, d5}
+; CHECK-NEXT: @ kill: def $s4 killed $s4 killed $d2 def $d2
+; CHECK-NEXT: @ kill: def $s2 killed $s2 killed $d1 def $d1
+; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $d0 def $d0
+; CHECK-NEXT: vld3.32 {d16, d17, d18}, [r0:64]
; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vorr d24, d16, d16
-; CHECK-NEXT: vstr d3, [sp, #16]
-; CHECK-NEXT: vstmia sp, {d0, d1}
+; CHECK-NEXT: vorr d26, d17, d17
+; CHECK-NEXT: vstmia sp, {d0, d1, d2}
; CHECK-NEXT: vld3.32 {d20, d21, d22}, [r0:64]
-; CHECK-NEXT: vorr d26, d21, d21
; CHECK-NEXT: vorr d25, d20, d20
-; CHECK-NEXT: vorr d20, d22, d22
-; CHECK-NEXT: vtrn.32 d26, d17
-; CHECK-NEXT: @ fake_use: $d26
+; CHECK-NEXT: vorr d27, d21, d21
+; CHECK-NEXT: vtrn.32 d22, d18
+; CHECK-NEXT: @ fake_use: $d22 $q10_q11
; CHECK-NEXT: vtrn.32 d25, d24
; CHECK-NEXT: @ fake_use: $d25
-; CHECK-NEXT: vtrn.32 d20, d18
-; CHECK-NEXT: @ fake_use: $d20
+; CHECK-NEXT: vtrn.32 d27, d26
+; CHECK-NEXT: @ fake_use: $d27
; CHECK-NEXT: @ fake_use: $d24
-; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d26
; CHECK-NEXT: @ fake_use: $d18 $q8_q9
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: bx lr
@@ -872,37 +832,30 @@ define void @deinterleave6_v2f32(<12 x float> %vec) {
define void @deinterleave8_v2f32(<16 x float> %vec) {
; CHECK-LABEL: deinterleave8_v2f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vmov d22, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vorr d25, d16, d16
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vorr d26, d18, d18
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: vmov d23, r0, r1
-; CHECK-NEXT: vorr d24, d20, d20
-; CHECK-NEXT: vtrn.32 d25, d17
-; CHECK-NEXT: vtrn.32 d23, d22
-; CHECK-NEXT: vtrn.32 d24, d21
-; CHECK-NEXT: vtrn.32 d26, d19
-; CHECK-NEXT: vtrn.32 d25, d24
-; CHECK-NEXT: vtrn.32 d23, d26
-; CHECK-NEXT: vtrn.32 d17, d21
-; CHECK-NEXT: vtrn.32 d22, d19
-; CHECK-NEXT: vtrn.32 d23, d25
-; CHECK-NEXT: @ fake_use: $d23
-; CHECK-NEXT: vtrn.32 d19, d21
-; CHECK-NEXT: @ fake_use: $d19 $q9
-; CHECK-NEXT: vtrn.32 d22, d17
-; CHECK-NEXT: @ fake_use: $d22
-; CHECK-NEXT: vtrn.32 d26, d24
-; CHECK-NEXT: @ fake_use: $d26
-; CHECK-NEXT: @ fake_use: $d25
-; CHECK-NEXT: @ fake_use: $d17 $q8
-; CHECK-NEXT: @ fake_use: $d24
-; CHECK-NEXT: @ fake_use: $d21 $q10
+; CHECK-NEXT: vorr d16, d6, d6
+; CHECK-NEXT: vorr d17, d4, d4
+; CHECK-NEXT: vorr d18, d2, d2
+; CHECK-NEXT: vorr d19, d0, d0
+; CHECK-NEXT: vtrn.32 d16, d7
+; CHECK-NEXT: vtrn.32 d17, d5
+; CHECK-NEXT: vtrn.32 d18, d3
+; CHECK-NEXT: vtrn.32 d19, d1
+; CHECK-NEXT: vtrn.32 d17, d16
+; CHECK-NEXT: vtrn.32 d19, d18
+; CHECK-NEXT: vtrn.32 d5, d7
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: vtrn.32 d19, d17
+; CHECK-NEXT: @ fake_use: $d19
+; CHECK-NEXT: vtrn.32 d3, d7
+; CHECK-NEXT: @ fake_use: $d3 $q1
+; CHECK-NEXT: vtrn.32 d1, d5
+; CHECK-NEXT: @ fake_use: $d1 $q0
+; CHECK-NEXT: vtrn.32 d18, d16
+; CHECK-NEXT: @ fake_use: $d18
+; CHECK-NEXT: @ fake_use: $d17
+; CHECK-NEXT: @ fake_use: $d5 $q2
+; CHECK-NEXT: @ fake_use: $d16
+; CHECK-NEXT: @ fake_use: $d7 $q3
; CHECK-NEXT: bx lr
%result = call { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.vector.deinterleave8(<16 x float> %vec)
%result0 = extractvalue { <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float>, <2 x float> } %result, 0
@@ -928,13 +881,9 @@ define void @deinterleave8_v2f32(<16 x float> %vec) {
define void @deinterleave2_v16i8(<32 x i8> %vec) {
; CHECK-LABEL: deinterleave2_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vmov d16, r0, r1
-; CHECK-NEXT: vuzp.8 q8, q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.8 q0, q1
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: bx lr
%result = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2(<32 x i8> %vec)
%result0 = extractvalue { <16 x i8>, <16 x i8> } %result, 0
@@ -1073,25 +1022,15 @@ define void @deinterleave3_v16i8(<48 x i8> %vec) {
define void @deinterleave4_v16i8(<64 x i8> %vec) {
; CHECK-LABEL: deinterleave4_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11, lr}
-; CHECK-NEXT: push {r11, lr}
-; CHECK-NEXT: add r12, sp, #40
-; CHECK-NEXT: vmov d21, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #24
-; CHECK-NEXT: add lr, sp, #8
-; CHECK-NEXT: vmov d20, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: vuzp.8 q10, q9
-; CHECK-NEXT: vuzp.8 q11, q8
-; CHECK-NEXT: vuzp.8 q10, q11
-; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: @ fake_use: $q11
-; CHECK-NEXT: vuzp.8 q9, q8
-; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: pop {r11, pc}
+; CHECK-NEXT: vuzp.8 q2, q3
+; CHECK-NEXT: vuzp.8 q0, q1
+; CHECK-NEXT: vuzp.8 q0, q2
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q2
+; CHECK-NEXT: vuzp.8 q1, q3
+; CHECK-NEXT: @ fake_use: $q1
+; CHECK-NEXT: @ fake_use: $q3
+; CHECK-NEXT: bx lr
%result = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.vector.deinterleave4(<64 x i8> %vec)
%result0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %result, 0
call void (...) @llvm.fake.use(<16 x i8> %result0)
@@ -1352,41 +1291,33 @@ define void @deinterleave6_v16i8(<96 x i8> %vec) {
define void @deinterleave8_v16i8(<128 x i8> %vec) {
; CHECK-LABEL: deinterleave8_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #96
-; CHECK-NEXT: vmov d31, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #80
-; CHECK-NEXT: vmov d30, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #64
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
-; CHECK-NEXT: add r12, sp, #48
-; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vuzp.8 q2, q3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r0]
+; CHECK-NEXT: vuzp.8 q0, q1
; CHECK-NEXT: vuzp.8 q9, q8
-; CHECK-NEXT: vuzp.8 q14, q10
-; CHECK-NEXT: vuzp.8 q15, q11
-; CHECK-NEXT: vuzp.8 q13, q12
-; CHECK-NEXT: vuzp.8 q14, q9
-; CHECK-NEXT: vuzp.8 q15, q13
-; CHECK-NEXT: vuzp.8 q10, q8
-; CHECK-NEXT: vuzp.8 q11, q12
-; CHECK-NEXT: vuzp.8 q15, q14
-; CHECK-NEXT: @ fake_use: $q15
-; CHECK-NEXT: @ fake_use: $q14
; CHECK-NEXT: vuzp.8 q11, q10
+; CHECK-NEXT: vuzp.8 q0, q2
+; CHECK-NEXT: vuzp.8 q11, q9
+; CHECK-NEXT: vuzp.8 q1, q3
+; CHECK-NEXT: vuzp.8 q10, q8
+; CHECK-NEXT: vuzp.8 q0, q11
+; CHECK-NEXT: @ fake_use: $q0
; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.8 q1, q10
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: vuzp.8 q13, q9
-; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: vuzp.8 q2, q9
+; CHECK-NEXT: @ fake_use: $q2
; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: vuzp.8 q12, q8
-; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: vuzp.8 q3, q8
+; CHECK-NEXT: @ fake_use: $q3
; CHECK-NEXT: @ fake_use: $q8
; CHECK-NEXT: bx lr
%result = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.vector.deinterleave8(<128 x i8> %vec)
@@ -1413,13 +1344,9 @@ define void @deinterleave8_v16i8(<128 x i8> %vec) {
define void @deinterleave2_v8i16(<16 x i16> %vec) {
; CHECK-LABEL: deinterleave2_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vmov d16, r0, r1
-; CHECK-NEXT: vuzp.16 q8, q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.16 q0, q1
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: bx lr
%result = call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2(<16 x i16> %vec)
%result0 = extractvalue { <8 x i16>, <8 x i16> } %result, 0
@@ -1510,25 +1437,15 @@ define void @deinterleave3_v8i16(<24 x i16> %vec) {
define void @deinterleave4_v8i16(<32 x i16> %vec) {
; CHECK-LABEL: deinterleave4_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11, lr}
-; CHECK-NEXT: push {r11, lr}
-; CHECK-NEXT: add r12, sp, #40
-; CHECK-NEXT: vmov d21, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #24
-; CHECK-NEXT: add lr, sp, #8
-; CHECK-NEXT: vmov d20, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: vuzp.16 q10, q9
-; CHECK-NEXT: vuzp.16 q11, q8
-; CHECK-NEXT: vuzp.16 q10, q11
-; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: @ fake_use: $q11
-; CHECK-NEXT: vuzp.16 q9, q8
-; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: pop {r11, pc}
+; CHECK-NEXT: vuzp.16 q2, q3
+; CHECK-NEXT: vuzp.16 q0, q1
+; CHECK-NEXT: vuzp.16 q0, q2
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q2
+; CHECK-NEXT: vuzp.16 q1, q3
+; CHECK-NEXT: @ fake_use: $q1
+; CHECK-NEXT: @ fake_use: $q3
+; CHECK-NEXT: bx lr
%result = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.vector.deinterleave4(<32 x i16> %vec)
%result0 = extractvalue { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %result, 0
call void (...) @llvm.fake.use(<8 x i16> %result0)
@@ -1695,41 +1612,33 @@ define void @deinterleave6_v8i16(<48 x i16> %vec) {
define void @deinterleave8_v8i16(<64 x i16> %vec) {
; CHECK-LABEL: deinterleave8_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #96
-; CHECK-NEXT: vmov d31, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #80
-; CHECK-NEXT: vmov d30, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #64
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
-; CHECK-NEXT: add r12, sp, #48
-; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vuzp.16 q2, q3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r0]
+; CHECK-NEXT: vuzp.16 q0, q1
; CHECK-NEXT: vuzp.16 q9, q8
-; CHECK-NEXT: vuzp.16 q14, q10
-; CHECK-NEXT: vuzp.16 q15, q11
-; CHECK-NEXT: vuzp.16 q13, q12
-; CHECK-NEXT: vuzp.16 q14, q9
-; CHECK-NEXT: vuzp.16 q15, q13
-; CHECK-NEXT: vuzp.16 q10, q8
-; CHECK-NEXT: vuzp.16 q11, q12
-; CHECK-NEXT: vuzp.16 q15, q14
-; CHECK-NEXT: @ fake_use: $q15
-; CHECK-NEXT: @ fake_use: $q14
; CHECK-NEXT: vuzp.16 q11, q10
+; CHECK-NEXT: vuzp.16 q0, q2
+; CHECK-NEXT: vuzp.16 q11, q9
+; CHECK-NEXT: vuzp.16 q1, q3
+; CHECK-NEXT: vuzp.16 q10, q8
+; CHECK-NEXT: vuzp.16 q0, q11
+; CHECK-NEXT: @ fake_use: $q0
; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.16 q1, q10
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: vuzp.16 q13, q9
-; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: vuzp.16 q2, q9
+; CHECK-NEXT: @ fake_use: $q2
; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: vuzp.16 q12, q8
-; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: vuzp.16 q3, q8
+; CHECK-NEXT: @ fake_use: $q3
; CHECK-NEXT: @ fake_use: $q8
; CHECK-NEXT: bx lr
%result = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.vector.deinterleave8(<64 x i16> %vec)
@@ -1756,13 +1665,9 @@ define void @deinterleave8_v8i16(<64 x i16> %vec) {
define void @deinterleave2_v4i32(<8 x i32> %vec) {
; CHECK-LABEL: deinterleave2_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vmov d16, r0, r1
-; CHECK-NEXT: vuzp.32 q8, q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.32 q0, q1
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: bx lr
%result = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2(<8 x i32> %vec)
%result0 = extractvalue { <4 x i32>, <4 x i32> } %result, 0
@@ -1829,25 +1734,15 @@ define void @deinterleave3_v4i32(<12 x i32> %vec) {
define void @deinterleave4_v4i32(<16 x i32> %vec) {
; CHECK-LABEL: deinterleave4_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11, lr}
-; CHECK-NEXT: push {r11, lr}
-; CHECK-NEXT: add r12, sp, #40
-; CHECK-NEXT: vmov d21, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #24
-; CHECK-NEXT: add lr, sp, #8
-; CHECK-NEXT: vmov d20, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: vuzp.32 q10, q9
-; CHECK-NEXT: vuzp.32 q11, q8
-; CHECK-NEXT: vuzp.32 q10, q11
-; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: @ fake_use: $q11
-; CHECK-NEXT: vuzp.32 q9, q8
-; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: pop {r11, pc}
+; CHECK-NEXT: vuzp.32 q2, q3
+; CHECK-NEXT: vuzp.32 q0, q1
+; CHECK-NEXT: vuzp.32 q0, q2
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q2
+; CHECK-NEXT: vuzp.32 q1, q3
+; CHECK-NEXT: @ fake_use: $q1
+; CHECK-NEXT: @ fake_use: $q3
+; CHECK-NEXT: bx lr
%result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave4(<16 x i32> %vec)
%result0 = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %result, 0
call void (...) @llvm.fake.use(<4 x i32> %result0)
@@ -1967,41 +1862,33 @@ define void @deinterleave6_v4i32(<24 x i32> %vec) {
define void @deinterleave8_v4i32(<32 x i32> %vec) {
; CHECK-LABEL: deinterleave8_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #96
-; CHECK-NEXT: vmov d31, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #80
-; CHECK-NEXT: vmov d30, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #64
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
-; CHECK-NEXT: add r12, sp, #48
-; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vuzp.32 q2, q3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r0]
+; CHECK-NEXT: vuzp.32 q0, q1
; CHECK-NEXT: vuzp.32 q9, q8
-; CHECK-NEXT: vuzp.32 q14, q10
-; CHECK-NEXT: vuzp.32 q15, q11
-; CHECK-NEXT: vuzp.32 q13, q12
-; CHECK-NEXT: vuzp.32 q14, q9
-; CHECK-NEXT: vuzp.32 q15, q13
-; CHECK-NEXT: vuzp.32 q10, q8
-; CHECK-NEXT: vuzp.32 q11, q12
-; CHECK-NEXT: vuzp.32 q15, q14
-; CHECK-NEXT: @ fake_use: $q15
-; CHECK-NEXT: @ fake_use: $q14
; CHECK-NEXT: vuzp.32 q11, q10
+; CHECK-NEXT: vuzp.32 q0, q2
+; CHECK-NEXT: vuzp.32 q11, q9
+; CHECK-NEXT: vuzp.32 q1, q3
+; CHECK-NEXT: vuzp.32 q10, q8
+; CHECK-NEXT: vuzp.32 q0, q11
+; CHECK-NEXT: @ fake_use: $q0
; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.32 q1, q10
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: vuzp.32 q13, q9
-; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: vuzp.32 q2, q9
+; CHECK-NEXT: @ fake_use: $q2
; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: vuzp.32 q12, q8
-; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: vuzp.32 q3, q8
+; CHECK-NEXT: @ fake_use: $q3
; CHECK-NEXT: @ fake_use: $q8
; CHECK-NEXT: bx lr
%result = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.vector.deinterleave8(<32 x i32> %vec)
@@ -2028,13 +1915,9 @@ define void @deinterleave8_v4i32(<32 x i32> %vec) {
define void @deinterleave2_v4f32(<8 x float> %vec) {
; CHECK-LABEL: deinterleave2_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov d17, r2, r3
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: vmov d16, r0, r1
-; CHECK-NEXT: vuzp.32 q8, q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: @ fake_use: $q9
+; CHECK-NEXT: vuzp.32 q0, q1
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: bx lr
%result = call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2(<8 x float> %vec)
%result0 = extractvalue { <4 x float>, <4 x float> } %result, 0
@@ -2054,22 +1937,26 @@ define void @deinterleave3_v4f32(<12 x float> %vec) {
; CHECK-NEXT: .pad #60
; CHECK-NEXT: sub sp, sp, #60
; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r12, r11, #4
-; CHECK-NEXT: vmov s7, r3
-; CHECK-NEXT: vmov s6, r2
-; CHECK-NEXT: vldmia r12, {s0, s1, s2, s3}
-; CHECK-NEXT: add r12, r11, #20
-; CHECK-NEXT: vmov s5, r1
-; CHECK-NEXT: vldmia r12, {s8, s9, s10, s11}
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vmov s4, r0
-; CHECK-NEXT: add r0, r12, #32
-; CHECK-NEXT: vst1.64 {d4, d5}, [r0:128]
-; CHECK-NEXT: mov r0, r12
-; CHECK-NEXT: vst1.64 {d2, d3}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d0, d1}, [r0]
-; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r12:64]!
-; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r12:64]
+; CHECK-NEXT: @ kill: def $s11 killed $s11 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s3 killed $s3 killed $q0 def $q0
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: @ kill: def $s10 killed $s10 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s2 killed $s2 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s7 killed $s7 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $s9 killed $s9 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s1 killed $s1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s6 killed $s6 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $s8 killed $s8 killed $q2 def $q2
+; CHECK-NEXT: vst1.64 {d4, d5}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s5 killed $s5 killed $q1 def $q1
+; CHECK-NEXT: vst1.64 {d0, d1}, [r1:128]!
+; CHECK-NEXT: @ kill: def $s4 killed $s4 killed $q1 def $q1
+; CHECK-NEXT: vst1.64 {d2, d3}, [r1]
+; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r0:64]!
+; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r0:64]
; CHECK-NEXT: @ fake_use: $q8
; CHECK-NEXT: @ fake_use: $q9
; CHECK-NEXT: @ fake_use: $q10 $q8_q9_q10_q11
@@ -2089,25 +1976,15 @@ define void @deinterleave3_v4f32(<12 x float> %vec) {
define void @deinterleave4_v4f32(<16 x float> %vec) {
; CHECK-LABEL: deinterleave4_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11, lr}
-; CHECK-NEXT: push {r11, lr}
-; CHECK-NEXT: add r12, sp, #40
-; CHECK-NEXT: vmov d21, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #24
-; CHECK-NEXT: add lr, sp, #8
-; CHECK-NEXT: vmov d20, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [lr]
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: vuzp.32 q10, q9
-; CHECK-NEXT: vuzp.32 q11, q8
-; CHECK-NEXT: vuzp.32 q10, q11
-; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: @ fake_use: $q11
-; CHECK-NEXT: vuzp.32 q9, q8
-; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: pop {r11, pc}
+; CHECK-NEXT: vuzp.32 q2, q3
+; CHECK-NEXT: vuzp.32 q0, q1
+; CHECK-NEXT: vuzp.32 q0, q2
+; CHECK-NEXT: @ fake_use: $q0
+; CHECK-NEXT: @ fake_use: $q2
+; CHECK-NEXT: vuzp.32 q1, q3
+; CHECK-NEXT: @ fake_use: $q1
+; CHECK-NEXT: @ fake_use: $q3
+; CHECK-NEXT: bx lr
%result = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave4(<16 x float> %vec)
%result0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 0
call void (...) @llvm.fake.use(<4 x float> %result0)
@@ -2123,43 +2000,54 @@ define void @deinterleave4_v4f32(<16 x float> %vec) {
define void @deinterleave6_v4f32(<24 x float> %vec) {
; CHECK-LABEL: deinterleave6_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r11, lr}
-; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
; CHECK-NEXT: .setfp r11, sp
; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: .pad #104
; CHECK-NEXT: sub sp, sp, #104
; CHECK-NEXT: bfc sp, #0, #4
-; CHECK-NEXT: add r12, r11, #40
-; CHECK-NEXT: vldmia r12, {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11}
-; CHECK-NEXT: add r12, sp, #48
-; CHECK-NEXT: add lr, r12, #32
-; CHECK-NEXT: vst1.64 {d4, d5}, [lr:128]
-; CHECK-NEXT: mov lr, r12
-; CHECK-NEXT: vmov s11, r3
-; CHECK-NEXT: vst1.64 {d0, d1}, [lr:128]!
-; CHECK-NEXT: vmov s10, r2
-; CHECK-NEXT: vmov s9, r1
-; CHECK-NEXT: vst1.64 {d2, d3}, [lr]
-; CHECK-NEXT: add lr, r11, #8
-; CHECK-NEXT: vmov s8, r0
-; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r12:64]!
-; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r12:64]
-; CHECK-NEXT: add r12, r11, #24
+; CHECK-NEXT: add r0, r11, #4
+; CHECK-NEXT: @ kill: def $s15 killed $s15 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $s11 killed $s11 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s3 killed $s3 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s7 killed $s7 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $s14 killed $s14 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $s10 killed $s10 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s2 killed $s2 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s6 killed $s6 killed $q1 def $q1
+; CHECK-NEXT: vldmia r0, {s16, s17, s18, s19, s20, s21, s22, s23}
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: add r1, r0, #32
+; CHECK-NEXT: @ kill: def $s13 killed $s13 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $s9 killed $s9 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s1 killed $s1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s5 killed $s5 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $s12 killed $s12 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $s8 killed $s8 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $s4 killed $s4 killed $q1 def $q1
+; CHECK-NEXT: vst1.64 {d10, d11}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d6, d7}, [r1:128]!
+; CHECK-NEXT: vst1.64 {d8, d9}, [r1]
+; CHECK-NEXT: vld3.32 {d16, d18, d20}, [r0:64]!
+; CHECK-NEXT: vld3.32 {d17, d19, d21}, [r0:64]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: add r1, r0, #32
; CHECK-NEXT: vorr q3, q9, q9
-; CHECK-NEXT: vldr s7, [r11, #36]
-; CHECK-NEXT: vldmia r12, {s4, s5, s6}
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: add r0, r12, #32
-; CHECK-NEXT: vldmia lr, {s0, s1, s2, s3}
-; CHECK-NEXT: vst1.64 {d2, d3}, [r0:128]
-; CHECK-NEXT: mov r0, r12
-; CHECK-NEXT: vst1.64 {d4, d5}, [r0:128]!
-; CHECK-NEXT: vst1.64 {d0, d1}, [r0]
+; CHECK-NEXT: vst1.64 {d4, d5}, [r1:128]
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: vst1.64 {d0, d1}, [r1:128]!
; CHECK-NEXT: vorr q0, q8, q8
; CHECK-NEXT: vorr q8, q10, q10
-; CHECK-NEXT: vld3.32 {d24, d26, d28}, [r12:64]!
-; CHECK-NEXT: vld3.32 {d25, d27, d29}, [r12:64]
+; CHECK-NEXT: vst1.64 {d2, d3}, [r1]
+; CHECK-NEXT: vld3.32 {d24, d26, d28}, [r0:64]!
+; CHECK-NEXT: vld3.32 {d25, d27, d29}, [r0:64]
; CHECK-NEXT: vorr q1, q12, q12
; CHECK-NEXT: vorr q2, q13, q13
; CHECK-NEXT: vorr q12, q14, q14
@@ -2172,8 +2060,11 @@ define void @deinterleave6_v4f32(<24 x float> %vec) {
; CHECK-NEXT: vuzp.32 q12, q8
; CHECK-NEXT: @ fake_use: $q12
; CHECK-NEXT: @ fake_use: $q8
-; CHECK-NEXT: mov sp, r11
-; CHECK-NEXT: pop {r11, pc}
+; CHECK-NEXT: sub sp, r11, #36
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: add sp, sp, #4
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
%result = call { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave6(<24 x float> %vec)
%result0 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } %result, 0
call void (...) @llvm.fake.use(<4 x float> %result0)
@@ -2193,41 +2084,33 @@ define void @deinterleave6_v4f32(<24 x float> %vec) {
define void @deinterleave8_v4f32(<32 x float> %vec) {
; CHECK-LABEL: deinterleave8_v4f32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: add r12, sp, #96
-; CHECK-NEXT: vmov d31, r2, r3
-; CHECK-NEXT: vld1.64 {d16, d17}, [r12]
-; CHECK-NEXT: add r12, sp, #80
-; CHECK-NEXT: vmov d30, r0, r1
-; CHECK-NEXT: vld1.64 {d18, d19}, [r12]
-; CHECK-NEXT: add r12, sp, #64
-; CHECK-NEXT: vld1.64 {d20, d21}, [r12]
-; CHECK-NEXT: mov r12, sp
-; CHECK-NEXT: vld1.64 {d22, d23}, [r12]
-; CHECK-NEXT: add r12, sp, #32
-; CHECK-NEXT: vld1.64 {d24, d25}, [r12]
-; CHECK-NEXT: add r12, sp, #16
-; CHECK-NEXT: vld1.64 {d26, d27}, [r12]
-; CHECK-NEXT: add r12, sp, #48
-; CHECK-NEXT: vld1.64 {d28, d29}, [r12]
+; CHECK-NEXT: add r0, sp, #48
+; CHECK-NEXT: vuzp.32 q2, q3
+; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vld1.64 {d20, d21}, [r0]
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r0]
+; CHECK-NEXT: vuzp.32 q0, q1
; CHECK-NEXT: vuzp.32 q9, q8
-; CHECK-NEXT: vuzp.32 q14, q10
-; CHECK-NEXT: vuzp.32 q15, q11
-; CHECK-NEXT: vuzp.32 q13, q12
-; CHECK-NEXT: vuzp.32 q14, q9
-; CHECK-NEXT: vuzp.32 q15, q13
+; CHECK-NEXT: vuzp.32 q11, q10
+; CHECK-NEXT: vuzp.32 q0, q2
+; CHECK-NEXT: vuzp.32 q11, q9
+; CHECK-NEXT: vuzp.32 q1, q3
; CHECK-NEXT: vuzp.32 q10, q8
-; CHECK-NEXT: vuzp.32 q11, q12
-; CHECK-NEXT: vuzp.32 q15, q14
-; CHECK-NEXT: @ fake_use: $q15
-; CHECK-NEXT: @ fake_use: $q14
-; CHECK-NEXT: vuzp.32 q11, q10
+; CHECK-NEXT: vuzp.32 q0, q11
+; CHECK-NEXT: @ fake_use: $q0
; CHECK-NEXT: @ fake_use: $q11
+; CHECK-NEXT: vuzp.32 q1, q10
+; CHECK-NEXT: @ fake_use: $q1
; CHECK-NEXT: @ fake_use: $q10
-; CHECK-NEXT: vuzp.32 q13, q9
-; CHECK-NEXT: @ fake_use: $q13
+; CHECK-NEXT: vuzp.32 q2, q9
+; CHECK-NEXT: @ fake_use: $q2
; CHECK-NEXT: @ fake_use: $q9
-; CHECK-NEXT: vuzp.32 q12, q8
-; CHECK-NEXT: @ fake_use: $q12
+; CHECK-NEXT: vuzp.32 q3, q8
+; CHECK-NEXT: @ fake_use: $q3
; CHECK-NEXT: @ fake_use: $q8
; CHECK-NEXT: bx lr
%result = call { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.vector.deinterleave8(<32 x float> %vec)
@@ -2256,18 +2139,22 @@ define void @deinterleave2_v4f16(<8 x half> %vec) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: ldrh r12, [sp, #24]
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh lr, [sp, #20]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r5, [sp, #16]
-; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s4
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: vmov lr, s3
; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: vmov r4, s5
; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r5, s7
+; CHECK-NEXT: @ fake_use: $r5
; CHECK-NEXT: pop {r4, r5, r11, pc}
%result = call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2(<8 x half> %vec)
%result0 = extractvalue { <4 x half>, <4 x half> } %result, 0
@@ -2280,29 +2167,33 @@ define void @deinterleave2_v4f16(<8 x half> %vec) {
define void @deinterleave3_v4f16(<12 x half> %vec) {
; CHECK-LABEL: deinterleave3_v4f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r12, [sp, #44]
+; CHECK-NEXT: .save {r4, r5, r11, lr}
+; CHECK-NEXT: push {r4, r5, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh lr, [sp, #36]
+; CHECK-NEXT: vmov r1, s3
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: vmov r12, s1
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r8, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: vmov lr, s4
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: vmov r4, s7
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: vmov r5, s10
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r1, s5
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: @ fake_use: $r8
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: vmov r3, s11
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: pop {r4, r5, r11, pc}
%result = call { <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave3(<12 x half> %vec)
%result0 = extractvalue { <4 x half>, <4 x half>, <4 x half> } %result, 0
call void (...) @llvm.fake.use(<4 x half> %result0)
@@ -2316,37 +2207,41 @@ define void @deinterleave3_v4f16(<12 x half> %vec) {
define void @deinterleave4_v4f16(<16 x half> %vec) {
; CHECK-LABEL: deinterleave4_v4f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh lr, [sp, #64]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r4, s9
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r7, s13
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: vmov r12, s1
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r8, [sp, #44]
+; CHECK-NEXT: vmov lr, s5
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: vmov r6, s2
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r7, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r5, [sp, #52]
+; CHECK-NEXT: vmov r5, s7
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r1, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #40]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: @ fake_use: $r8
-; CHECK-NEXT: @ fake_use: $r9
+; CHECK-NEXT: vmov r4, s11
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r7, s15
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave4(<16 x half> %vec)
%result0 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 0
call void (...) @llvm.fake.use(<4 x half> %result0)
@@ -2362,53 +2257,57 @@ define void @deinterleave4_v4f16(<16 x half> %vec) {
define void @deinterleave6_v4f16(<24 x half> %vec) {
; CHECK-LABEL: deinterleave6_v4f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: vmov r6, s14
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r2, s12
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: vmov r12, s7
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r2, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: ldrh r2, [sp, #28]
+; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #28]
+; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh lr, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: vmov r0, s15
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: vmov lr, s13
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: vmov r12, s4
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: vmov r4, s5
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s11
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: ldrh r1, [sp, #44]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: ldrh r3, [sp, #20]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r0, [sp, #16]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #40]
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: pop {r4, r5, r6, pc}
%result = call { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave6(<24 x half> %vec)
%result0 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 0
call void (...) @llvm.fake.use(<4 x half> %result0)
@@ -2428,69 +2327,73 @@ define void @deinterleave6_v4f16(<24 x half> %vec) {
define void @deinterleave8_v4f16(<32 x half> %vec) {
; CHECK-LABEL: deinterleave8_v4f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #108]
-; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: vmov r1, s8
+; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: vmov r3, s9
+; CHECK-NEXT: ldrh r1, [sp, #56]
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #60]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #116]
-; CHECK-NEXT: ldrh r2, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #40]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #76]
+; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #24]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #88]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #120]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: vmov r7, s11
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r2
; CHECK-NEXT: ldrh r1, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #60]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #124]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #104]
+; CHECK-NEXT: ldrh r0, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: vmov r4, s3
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r6, s13
+; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r7, [sp, #68]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh lr, [sp, #68]
+; CHECK-NEXT: ldrh r2, [sp, #44]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r8, [sp, #100]
+; CHECK-NEXT: ldrh r3, [sp, #76]
+; CHECK-NEXT: vmov r12, s2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov lr, s10
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: vmov r4, s14
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: vmov r0, s7
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r7, s15
+; CHECK-NEXT: ldrh r5, [sp, #84]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: ldrh r6, [sp, #52]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #96]
+; CHECK-NEXT: ldrh r2, [sp, #48]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #128]
-; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #80]
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.vector.deinterleave8(<32 x half> %vec)
%result0 = extractvalue { <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half>, <4 x half> } %result, 0
call void (...) @llvm.fake.use(<4 x half> %result0)
@@ -2515,37 +2418,41 @@ define void @deinterleave8_v4f16(<32 x half> %vec) {
define void @deinterleave2_v8f16(<16 x half> %vec) {
; CHECK-LABEL: deinterleave2_v8f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #56]
+; CHECK-NEXT: vmov r1, s2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r12, [sp, #40]
+; CHECK-NEXT: vmov r3, s6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r4, s12
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh lr, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r8, [sp, #52]
+; CHECK-NEXT: vmov r7, s14
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: vmov r12, s8
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: vmov lr, s10
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: vmov r6, s1
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r7, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r5, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: vmov r3, s7
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r8
-; CHECK-NEXT: @ fake_use: $r9
-; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r5, s11
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r4, s13
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r7, s15
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2(<16 x half> %vec)
%result0 = extractvalue { <8 x half>, <8 x half> } %result, 0
call void (...) @llvm.fake.use(<8 x half> %result0)
@@ -2557,53 +2464,57 @@ define void @deinterleave2_v8f16(<16 x half> %vec) {
define void @deinterleave3_v8f16(<24 x half> %vec) {
; CHECK-LABEL: deinterleave3_v8f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #68]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r3, [sp, #36]
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: ldrh r3, [sp, #24]
+; CHECK-NEXT: vmov r1, s10
+; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #72]
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: ldrh r6, [sp, #16]
+; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r3, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r7, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r12, [sp, #64]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: vmov r5, s4
+; CHECK-NEXT: ldrh r1, [sp, #28]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #88]
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: vmov lr, s15
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r6, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #96]
+; CHECK-NEXT: vmov r12, s2
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #52]
+; CHECK-NEXT: vmov r4, s11
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #44]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #20]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: pop {r4, r5, r6, pc}
%result = call { <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave3(<24 x half> %vec)
%result0 = extractvalue { <8 x half>, <8 x half>, <8 x half> } %result, 0
call void (...) @llvm.fake.use(<8 x half> %result0)
@@ -2617,69 +2528,73 @@ define void @deinterleave3_v8f16(<24 x half> %vec) {
define void @deinterleave4_v8f16(<32 x half> %vec) {
; CHECK-LABEL: deinterleave4_v8f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r4, [sp, #40]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r4, [sp, #104]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: vmov r4, s9
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #24]
-; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r5, s13
; CHECK-NEXT: ldrh r0, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #88]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #108]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r1, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #124]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: vmov r7, s2
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: vmov r6, s14
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: ldrh r0, [sp, #76]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #80]
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r4, [sp, #44]
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r2, [sp, #96]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #112]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh lr, [sp, #100]
+; CHECK-NEXT: ldrh r5, [sp, #60]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #116]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: ldrh r7, [sp, #32]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r7, [sp, #120]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: ldrh r2, [sp, #48]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r1, [sp, #128]
+; CHECK-NEXT: ldrh r3, [sp, #64]
+; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: ldrh r6, [sp, #80]
+; CHECK-NEXT: vmov lr, s5
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: vmov r1, s3
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r4, s7
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s11
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: vmov r0, s15
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r7, [sp, #84]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r2, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #36]
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave4(<32 x half> %vec)
%result0 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 0
call void (...) @llvm.fake.use(<8 x half> %result0)
@@ -2695,101 +2610,105 @@ define void @deinterleave4_v8f16(<32 x half> %vec) {
define void @deinterleave6_v8f16(<48 x half> %vec) {
; CHECK-LABEL: deinterleave6_v8f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #104]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #84]
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #108]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #180]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r4, [sp, #152]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: ldrh r0, [sp, #32]
+; CHECK-NEXT: ldrh r2, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #104]
+; CHECK-NEXT: vmov r4, s13
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #112]
-; CHECK-NEXT: ldrh r2, [sp, #136]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: ldrh r2, [sp, #128]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r1, [sp, #184]
+; CHECK-NEXT: ldrh r0, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #64]
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: ldrh r5, [sp, #56]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: ldrh r2, [sp, #36]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #128]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #156]
+; CHECK-NEXT: vmov r4, s15
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #108]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: ldrh r3, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s9
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #140]
+; CHECK-NEXT: ldrh r2, [sp, #84]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #164]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #188]
+; CHECK-NEXT: ldrh r0, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #92]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r4, [sp, #116]
+; CHECK-NEXT: vmov r6, s7
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #24]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: vmov r2, s4
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r1, [sp, #88]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: ldrh r0, [sp, #112]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r5, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r3
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r3, [sp, #24]
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: vmov r7, s1
+; CHECK-NEXT: vmov r12, s2
+; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #44]
+; CHECK-NEXT: ldrh r1, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r5
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #160]
+; CHECK-NEXT: ldrh r2, [sp, #72]
+; CHECK-NEXT: ldrh r5, [sp, #96]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #120]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r2, [sp, #144]
+; CHECK-NEXT: ldrh r3, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #144]
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r3, [sp, #168]
+; CHECK-NEXT: vmov r7, s3
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #192]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r12, [sp, #124]
+; CHECK-NEXT: vmov r6, s10
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: vmov r12, s5
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov lr, s11
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh lr, [sp, #148]
+; CHECK-NEXT: ldrh r0, [sp, #148]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #172]
+; CHECK-NEXT: ldrh r1, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r2, [sp, #100]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r5, [sp, #196]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r7, [sp, #176]
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #28]
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: ldrh r4, [sp, #52]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #68]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #100]
-; CHECK-NEXT: @ fake_use: $r0
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave6(<48 x half> %vec)
%result0 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 0
call void (...) @llvm.fake.use(<8 x half> %result0)
@@ -2809,137 +2728,137 @@ define void @deinterleave6_v8f16(<48 x half> %vec) {
define void @deinterleave8_v8f16(<64 x half> %vec) {
; CHECK-LABEL: deinterleave8_v8f16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #144]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #116]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #244]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #152]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #124]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #252]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #128]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: add r0, sp, #256
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #148]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #120]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: vmov r2, s0
+; CHECK-NEXT: ldrh r6, [sp, #184]
+; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #184]
-; CHECK-NEXT: ldrh r0, [r0]
-; CHECK-NEXT: add r4, sp, #256
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #248]
+; CHECK-NEXT: ldrh r2, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #60]
+; CHECK-NEXT: vmov r3, s8
+; CHECK-NEXT: vmov r5, s9
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #132]
-; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r1, s2
+; CHECK-NEXT: ldrh r2, [sp, #152]
+; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #156]
+; CHECK-NEXT: vmov r4, s4
+; CHECK-NEXT: ldrh r7, [sp, #24]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #156]
+; CHECK-NEXT: ldrh r3, [sp, #88]
; CHECK-NEXT: @ fake_use: $r2
; CHECK-NEXT: ldrh r2, [sp, #188]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: add r0, sp, #256
-; CHECK-NEXT: ldrh r3, [sp, #220]
-; CHECK-NEXT: ldrh r5, [r4, #12]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r5, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #96]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r3, [sp, #96]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #208]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #160]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r4, [sp, #72]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #192]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r3, [sp, #224]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [r0, #4]
+; CHECK-NEXT: ldrh r7, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r3, [sp, #28]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r6, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: ldrh r5, [sp, #192]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #32]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: ldrh r1, [sp, #160]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r2, [sp, #68]
+; CHECK-NEXT: ldrh r0, [sp, #36]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r3, [sp, #100]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [sp, #136]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r6, [sp, #176]
+; CHECK-NEXT: ldrh r6, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r4, [sp, #168]
+; CHECK-NEXT: vmov r7, s11
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #212]
+; CHECK-NEXT: ldrh r3, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r1, [sp, #68]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: add r0, sp, #256
-; CHECK-NEXT: ldrh r1, [sp, #164]
-; CHECK-NEXT: ldrh r2, [sp, #196]
+; CHECK-NEXT: ldrh r5, [sp, #100]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r3, [sp, #228]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #52]
+; CHECK-NEXT: ldrh r4, [sp, #44]
+; CHECK-NEXT: ldrh r6, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #204]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #196]
+; CHECK-NEXT: @ fake_use: $r7
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: ldrh r7, [sp, #164]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: ldrh r5, [sp, #200]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #172]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #80]
+; CHECK-NEXT: vmov r8, s3
+; CHECK-NEXT: @ fake_use: $r7
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #40]
+; CHECK-NEXT: ldrh r2, [sp, #40]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: ldrh r3, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r7, [sp, #108]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #112]
+; CHECK-NEXT: ldrh r4, [sp, #112]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #180]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #216]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #168]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r2, [sp, #200]
+; CHECK-NEXT: ldrh r1, [sp, #144]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r3, [sp, #232]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [r0, #8]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #172]
+; CHECK-NEXT: ldrh r6, [sp, #176]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #208]
+; CHECK-NEXT: vmov r12, s5
+; CHECK-NEXT: vmov lr, s13
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: vmov r8, s6
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh lr, [sp, #204]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r8, [sp, #236]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r7, [sp, #240]
+; CHECK-NEXT: vmov r2, s7
+; CHECK-NEXT: vmov r3, s15
+; CHECK-NEXT: @ fake_use: $r5
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r5, [sp, #212]
+; CHECK-NEXT: ldrh r7, [sp, #180]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r4, [sp, #148]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #108]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #140]
+; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #52]
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #84]
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r7
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
%result = call { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.vector.deinterleave8(<64 x half> %vec)
%result0 = extractvalue { <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half>, <8 x half> } %result, 0
call void (...) @llvm.fake.use(<8 x half> %result0)
@@ -2966,18 +2885,22 @@ define void @deinterleave2_v4bf16(<8 x bfloat> %vec) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r11, lr}
; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: ldrh r12, [sp, #24]
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh lr, [sp, #20]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r5, [sp, #16]
-; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s4
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: vmov lr, s3
; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: vmov r4, s5
; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r5, s7
+; CHECK-NEXT: @ fake_use: $r5
; CHECK-NEXT: pop {r4, r5, r11, pc}
%result = call { <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave2(<8 x bfloat> %vec)
%result0 = extractvalue { <4 x bfloat>, <4 x bfloat> } %result, 0
@@ -2990,29 +2913,33 @@ define void @deinterleave2_v4bf16(<8 x bfloat> %vec) {
define void @deinterleave3_v4bf16(<12 x bfloat> %vec) {
; CHECK-LABEL: deinterleave3_v4bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r12, [sp, #44]
+; CHECK-NEXT: .save {r4, r5, r11, lr}
+; CHECK-NEXT: push {r4, r5, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh lr, [sp, #36]
+; CHECK-NEXT: vmov r1, s3
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: vmov r12, s1
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r8, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: vmov lr, s4
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r7, [sp, #52]
+; CHECK-NEXT: vmov r4, s7
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: vmov r5, s10
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r1, s5
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: @ fake_use: $r8
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: vmov r3, s11
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: pop {r4, r5, r11, pc}
%result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave3(<12 x bfloat> %vec)
%result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<4 x bfloat> %result0)
@@ -3026,37 +2953,41 @@ define void @deinterleave3_v4bf16(<12 x bfloat> %vec) {
define void @deinterleave4_v4bf16(<16 x bfloat> %vec) {
; CHECK-LABEL: deinterleave4_v4bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r12, [sp, #32]
+; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh lr, [sp, #64]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r4, s9
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r7, s13
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: vmov r12, s1
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r8, [sp, #44]
+; CHECK-NEXT: vmov lr, s5
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: vmov r6, s2
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r7, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r5, [sp, #52]
+; CHECK-NEXT: vmov r5, s7
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r1, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #40]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: @ fake_use: $r8
-; CHECK-NEXT: @ fake_use: $r9
+; CHECK-NEXT: vmov r4, s11
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r7, s15
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave4(<16 x bfloat> %vec)
%result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<4 x bfloat> %result0)
@@ -3072,53 +3003,57 @@ define void @deinterleave4_v4bf16(<16 x bfloat> %vec) {
define void @deinterleave6_v4bf16(<24 x bfloat> %vec) {
; CHECK-LABEL: deinterleave6_v4bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r4, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #60]
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #88]
+; CHECK-NEXT: vmov r6, s14
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r2, s12
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: vmov r12, s7
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r2, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #80]
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: ldrh r2, [sp, #28]
+; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #28]
+; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh lr, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: vmov r0, s15
+; CHECK-NEXT: ldrh r6, [sp, #36]
+; CHECK-NEXT: vmov lr, s13
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: vmov r12, s4
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: vmov r4, s5
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s11
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: ldrh r1, [sp, #44]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: ldrh r3, [sp, #20]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: ldrh r0, [sp, #16]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #40]
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: pop {r4, r5, r6, pc}
%result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave6(<24 x bfloat> %vec)
%result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<4 x bfloat> %result0)
@@ -3138,69 +3073,73 @@ define void @deinterleave6_v4bf16(<24 x bfloat> %vec) {
define void @deinterleave8_v4bf16(<32 x bfloat> %vec) {
; CHECK-LABEL: deinterleave8_v4bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #108]
-; CHECK-NEXT: ldrh r4, [sp, #72]
+; CHECK-NEXT: vmov r1, s8
+; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: vmov r3, s9
+; CHECK-NEXT: ldrh r1, [sp, #56]
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #60]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #116]
-; CHECK-NEXT: ldrh r2, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #40]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #76]
+; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #24]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #88]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #120]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: vmov r7, s11
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r2
; CHECK-NEXT: ldrh r1, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #60]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #124]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #104]
+; CHECK-NEXT: ldrh r0, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: vmov r4, s3
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #36]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r6, s13
+; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r7, [sp, #68]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh lr, [sp, #68]
+; CHECK-NEXT: ldrh r2, [sp, #44]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r8, [sp, #100]
+; CHECK-NEXT: ldrh r3, [sp, #76]
+; CHECK-NEXT: vmov r12, s2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov lr, s10
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: vmov r4, s14
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: vmov r0, s7
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r7, s15
+; CHECK-NEXT: ldrh r5, [sp, #84]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: ldrh r6, [sp, #52]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #96]
+; CHECK-NEXT: ldrh r2, [sp, #48]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #128]
-; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r3, [sp, #80]
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.vector.deinterleave8(<32 x bfloat> %vec)
%result0 = extractvalue { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<4 x bfloat> %result0)
@@ -3225,37 +3164,41 @@ define void @deinterleave8_v4bf16(<32 x bfloat> %vec) {
define void @deinterleave2_v8bf16(<16 x bfloat> %vec) {
; CHECK-LABEL: deinterleave2_v8bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
-; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #56]
+; CHECK-NEXT: vmov r1, s2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r12, [sp, #40]
+; CHECK-NEXT: vmov r3, s6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r4, s12
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh lr, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r8, [sp, #52]
+; CHECK-NEXT: vmov r7, s14
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: vmov r12, s8
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r9, [sp, #60]
+; CHECK-NEXT: vmov lr, s10
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r6, [sp, #68]
+; CHECK-NEXT: vmov r6, s1
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r7, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r5, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: vmov r3, s7
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r8
-; CHECK-NEXT: @ fake_use: $r9
-; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: vmov r5, s11
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r4, s13
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r7, s15
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave2(<16 x bfloat> %vec)
%result0 = extractvalue { <8 x bfloat>, <8 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<8 x bfloat> %result0)
@@ -3267,53 +3210,57 @@ define void @deinterleave2_v8bf16(<16 x bfloat> %vec) {
define void @deinterleave3_v8bf16(<24 x bfloat> %vec) {
; CHECK-LABEL: deinterleave3_v8bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #68]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #24]
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r3, [sp, #36]
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #44]
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: ldrh r3, [sp, #24]
+; CHECK-NEXT: vmov r1, s10
+; CHECK-NEXT: ldrh r0, [sp, #36]
+; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r1, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #72]
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: ldrh r6, [sp, #16]
+; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r3, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r7, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r12, [sp, #64]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh lr, [sp, #76]
+; CHECK-NEXT: vmov r5, s4
+; CHECK-NEXT: ldrh r1, [sp, #28]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #88]
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: vmov lr, s15
; CHECK-NEXT: @ fake_use: $r12
-; CHECK-NEXT: ldrh r5, [sp, #100]
-; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: ldrh r6, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #96]
+; CHECK-NEXT: vmov r12, s2
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #52]
+; CHECK-NEXT: vmov r4, s11
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #44]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #20]
+; CHECK-NEXT: @ fake_use: $lr
+; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: pop {r4, r5, r6, pc}
%result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave3(<24 x bfloat> %vec)
%result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<8 x bfloat> %result0)
@@ -3327,69 +3274,73 @@ define void @deinterleave3_v8bf16(<24 x bfloat> %vec) {
define void @deinterleave4_v8bf16(<32 x bfloat> %vec) {
; CHECK-LABEL: deinterleave4_v8bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: ldrh r4, [sp, #40]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r4, [sp, #104]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: vmov r4, s9
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #24]
-; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r5, s13
; CHECK-NEXT: ldrh r0, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #88]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #108]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r1, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #124]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: vmov r7, s2
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r7, [sp, #56]
+; CHECK-NEXT: vmov r6, s14
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r6, [sp, #92]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: ldrh r0, [sp, #76]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [sp, #80]
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r4, [sp, #44]
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r2, [sp, #96]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #112]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #84]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh lr, [sp, #100]
+; CHECK-NEXT: ldrh r5, [sp, #60]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #116]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r5, [sp, #132]
+; CHECK-NEXT: ldrh r7, [sp, #32]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r7, [sp, #120]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: ldrh r2, [sp, #48]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r1, [sp, #128]
+; CHECK-NEXT: ldrh r3, [sp, #64]
+; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: ldrh r6, [sp, #80]
+; CHECK-NEXT: vmov lr, s5
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [sp, #68]
+; CHECK-NEXT: vmov r1, s3
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r4, s7
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s11
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: vmov r0, s15
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r7, [sp, #84]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r2, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #52]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #36]
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave4(<32 x bfloat> %vec)
%result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<8 x bfloat> %result0)
@@ -3405,101 +3356,105 @@ define void @deinterleave4_v8bf16(<32 x bfloat> %vec) {
define void @deinterleave6_v8bf16(<48 x bfloat> %vec) {
; CHECK-LABEL: deinterleave6_v8bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: ldrh r0, [sp, #32]
+; CHECK-NEXT: ldrh r2, [sp, #80]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: @ fake_use: $r0
; CHECK-NEXT: ldrh r0, [sp, #104]
+; CHECK-NEXT: vmov r4, s13
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #128]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #84]
-; CHECK-NEXT: ldrh r4, [sp, #56]
+; CHECK-NEXT: ldrh r0, [sp, #60]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #64]
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: ldrh r5, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: vmov r4, s15
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #108]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #136]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r5, s9
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #84]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #180]
+; CHECK-NEXT: ldrh r0, [sp, #40]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r3, [sp, #92]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r4, [sp, #152]
+; CHECK-NEXT: ldrh r4, [sp, #116]
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: @ fake_use: $r1
; CHECK-NEXT: ldrh r1, [sp, #88]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: @ fake_use: $r2
; CHECK-NEXT: ldrh r0, [sp, #112]
-; CHECK-NEXT: ldrh r2, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r5, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r3
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r1, [sp, #184]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r0, [sp, #92]
+; CHECK-NEXT: ldrh r3, [sp, #24]
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: vmov r7, s1
+; CHECK-NEXT: vmov r12, s2
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r2, [sp, #44]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #128]
+; CHECK-NEXT: ldrh r6, [sp, #132]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #156]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #116]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #140]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #164]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #188]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #36]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r0, [sp, #44]
+; CHECK-NEXT: ldrh r1, [sp, #68]
+; CHECK-NEXT: @ fake_use: $r5
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: ldrh r2, [sp, #72]
+; CHECK-NEXT: ldrh r5, [sp, #96]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r3, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #96]
+; CHECK-NEXT: ldrh r3, [sp, #120]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #132]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #160]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #120]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r2, [sp, #144]
+; CHECK-NEXT: ldrh r4, [sp, #144]
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r3, [sp, #168]
+; CHECK-NEXT: vmov r7, s3
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r0, [sp, #192]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r12, [sp, #124]
+; CHECK-NEXT: vmov r6, s10
+; CHECK-NEXT: @ fake_use: $r12
+; CHECK-NEXT: vmov r12, s5
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: vmov lr, s11
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh lr, [sp, #148]
+; CHECK-NEXT: ldrh r0, [sp, #148]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r8, [sp, #172]
+; CHECK-NEXT: ldrh r1, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r2, [sp, #100]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r5, [sp, #196]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r7, [sp, #176]
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r3, [sp, #28]
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #40]
+; CHECK-NEXT: ldrh r4, [sp, #52]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #68]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #28]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #52]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #100]
-; CHECK-NEXT: @ fake_use: $r0
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
-; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r4
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
%result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave6(<48 x bfloat> %vec)
%result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<8 x bfloat> %result0)
@@ -3519,137 +3474,137 @@ define void @deinterleave6_v8bf16(<48 x bfloat> %vec) {
define void @deinterleave8_v8bf16(<64 x bfloat> %vec) {
; CHECK-LABEL: deinterleave8_v8bf16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #144]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #116]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #244]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #152]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #124]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #252]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #128]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: add r0, sp, #256
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #148]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #120]
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: vmov r2, s0
+; CHECK-NEXT: ldrh r6, [sp, #184]
+; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #184]
-; CHECK-NEXT: ldrh r0, [r0]
-; CHECK-NEXT: add r4, sp, #256
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r1, [sp, #248]
+; CHECK-NEXT: ldrh r2, [sp, #56]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #60]
+; CHECK-NEXT: vmov r3, s8
+; CHECK-NEXT: vmov r5, s9
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r2, [sp, #60]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r0, [sp, #132]
-; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: vmov r1, s2
+; CHECK-NEXT: ldrh r2, [sp, #152]
+; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #156]
+; CHECK-NEXT: vmov r4, s4
+; CHECK-NEXT: ldrh r7, [sp, #24]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #156]
+; CHECK-NEXT: ldrh r3, [sp, #88]
; CHECK-NEXT: @ fake_use: $r2
; CHECK-NEXT: ldrh r2, [sp, #188]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: add r0, sp, #256
-; CHECK-NEXT: ldrh r3, [sp, #220]
-; CHECK-NEXT: ldrh r5, [r4, #12]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r5, [sp, #92]
+; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #80]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #32]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #64]
+; CHECK-NEXT: ldrh r1, [sp, #64]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #96]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r3, [sp, #96]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #208]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #160]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r4, [sp, #72]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #192]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r3, [sp, #224]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [r0, #4]
+; CHECK-NEXT: ldrh r7, [sp, #120]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r3, [sp, #28]
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r6, [sp, #48]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #84]
+; CHECK-NEXT: ldrh r5, [sp, #192]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: ldrh r2, [sp, #32]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: ldrh r1, [sp, #160]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r2, [sp, #68]
+; CHECK-NEXT: ldrh r0, [sp, #36]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r3, [sp, #100]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r0, [sp, #136]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r6, [sp, #176]
+; CHECK-NEXT: ldrh r6, [sp, #136]
+; CHECK-NEXT: @ fake_use: $r7
+; CHECK-NEXT: ldrh r4, [sp, #168]
+; CHECK-NEXT: vmov r7, s11
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r4, [sp, #212]
+; CHECK-NEXT: ldrh r3, [sp, #124]
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #128]
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r1, [sp, #68]
; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: add r0, sp, #256
-; CHECK-NEXT: ldrh r1, [sp, #164]
-; CHECK-NEXT: ldrh r2, [sp, #196]
+; CHECK-NEXT: ldrh r5, [sp, #100]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r3, [sp, #228]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r6, [sp, #52]
+; CHECK-NEXT: ldrh r4, [sp, #44]
+; CHECK-NEXT: ldrh r6, [sp, #140]
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: ldrh r0, [sp, #204]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: ldrh r2, [sp, #196]
+; CHECK-NEXT: @ fake_use: $r7
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: ldrh r7, [sp, #164]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: ldrh r5, [sp, #200]
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: ldrh r4, [sp, #172]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #48]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #80]
+; CHECK-NEXT: vmov r8, s3
+; CHECK-NEXT: @ fake_use: $r7
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r1, [sp, #40]
+; CHECK-NEXT: ldrh r2, [sp, #40]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r2, [sp, #72]
-; CHECK-NEXT: @ fake_use: $r6
; CHECK-NEXT: ldrh r3, [sp, #104]
+; CHECK-NEXT: @ fake_use: $r5
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r7, [sp, #108]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r7, [sp, #112]
+; CHECK-NEXT: ldrh r4, [sp, #112]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r6, [sp, #180]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r4, [sp, #216]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r1, [sp, #168]
-; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r2, [sp, #200]
+; CHECK-NEXT: ldrh r1, [sp, #144]
; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r3, [sp, #232]
-; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r0, [r0, #8]
-; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r12, [sp, #172]
+; CHECK-NEXT: ldrh r6, [sp, #176]
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #208]
+; CHECK-NEXT: vmov r12, s5
+; CHECK-NEXT: vmov lr, s13
+; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: vmov r8, s6
; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh lr, [sp, #204]
; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r8, [sp, #236]
-; CHECK-NEXT: @ fake_use: $r0
-; CHECK-NEXT: ldrh r7, [sp, #240]
+; CHECK-NEXT: vmov r2, s7
+; CHECK-NEXT: vmov r3, s15
+; CHECK-NEXT: @ fake_use: $r5
; CHECK-NEXT: @ fake_use: $r7
-; CHECK-NEXT: ldrh r6, [sp, #56]
-; CHECK-NEXT: @ fake_use: $r6
-; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r5, [sp, #212]
+; CHECK-NEXT: ldrh r7, [sp, #180]
; CHECK-NEXT: @ fake_use: $r4
-; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r4, [sp, #148]
; CHECK-NEXT: @ fake_use: $r1
-; CHECK-NEXT: ldrh r2, [sp, #76]
-; CHECK-NEXT: @ fake_use: $r2
-; CHECK-NEXT: ldrh r3, [sp, #108]
-; CHECK-NEXT: @ fake_use: $r3
-; CHECK-NEXT: ldrh r0, [sp, #140]
+; CHECK-NEXT: ldrh r1, [sp, #116]
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: ldrh r6, [sp, #52]
; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: ldrh r0, [sp, #84]
; CHECK-NEXT: @ fake_use: $r12
; CHECK-NEXT: @ fake_use: $lr
; CHECK-NEXT: @ fake_use: $r8
+; CHECK-NEXT: @ fake_use: $r2
+; CHECK-NEXT: @ fake_use: $r3
+; CHECK-NEXT: @ fake_use: $r6
+; CHECK-NEXT: @ fake_use: $r0
+; CHECK-NEXT: @ fake_use: $r1
+; CHECK-NEXT: @ fake_use: $r4
+; CHECK-NEXT: @ fake_use: $r7
; CHECK-NEXT: @ fake_use: $r5
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
%result = call { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } @llvm.vector.deinterleave8(<64 x bfloat> %vec)
%result0 = extractvalue { <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat> } %result, 0
call void (...) @llvm.fake.use(<8 x bfloat> %result0)
diff --git a/llvm/test/CodeGen/ARM/vector-interleave.ll b/llvm/test/CodeGen/ARM/vector-interleave.ll
new file mode 100644
index 0000000000000..b51faf03d57bf
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/vector-interleave.ll
@@ -0,0 +1,2352 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=armv8-none-none-eabihf -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IAENABLED
+; RUN: llc -mtriple=armv8-none-none-eabihf -mattr=+neon -lower-interleaved-accesses=false %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-IADISABLED
+
+define <16 x i8> @interleave2_v8i8(<8 x i8> %vec0, <8 x i8> %vec1) {
+; CHECK-LABEL: interleave2_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vzip.8 d0, d1
+; CHECK-NEXT: bx lr
+ %result = call <16 x i8> @llvm.vector.interleave2(<8 x i8> %vec0, <8 x i8> %vec1)
+ ret <16 x i8> %result
+}
+
+define <24 x i8> @interleave3_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2) {
+; CHECK-LABEL: interleave3_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vst3.8 {d0, d1, d2}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <24 x i8> @llvm.vector.interleave3(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2)
+ ret <24 x i8> %result
+}
+
+define <32 x i8> @interleave4_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3) {
+; CHECK-LABEL: interleave4_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vzip.8 d1, d3
+; CHECK-NEXT: vzip.8 d0, d2
+; CHECK-NEXT: vzip.8 d0, d1
+; CHECK-NEXT: vzip.8 d2, d3
+; CHECK-NEXT: bx lr
+ %result = call <32 x i8> @llvm.vector.interleave4(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3)
+ ret <32 x i8> %result
+}
+
+define <48 x i8> @interleave6_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5) {
+; CHECK-LABEL: interleave6_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vmov.f64 d18, d5
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.f64 d17, d4
+; CHECK-NEXT: vorr d16, d3, d3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vzip.8 d2, d18
+; CHECK-NEXT: vzip.8 d1, d17
+; CHECK-NEXT: vzip.8 d0, d16
+; CHECK-NEXT: vst3.8 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.8 {d0, d1, d2}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <48 x i8> @llvm.vector.interleave6(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5)
+ ret <48 x i8> %result
+}
+
+define <64 x i8> @interleave8_v8i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5, <8 x i8> %vec6, <8 x i8> %vec7) {
+; CHECK-LABEL: interleave8_v8i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d7 killed $d7 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d5 killed $d5 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d6 killed $d6 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d4 killed $d4 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vzip.8 d3, d7
+; CHECK-NEXT: vzip.8 d1, d5
+; CHECK-NEXT: vzip.8 d2, d6
+; CHECK-NEXT: vzip.8 d0, d4
+; CHECK-NEXT: vzip.8 d1, d3
+; CHECK-NEXT: vzip.8 d5, d7
+; CHECK-NEXT: vzip.8 d0, d2
+; CHECK-NEXT: vzip.8 d4, d6
+; CHECK-NEXT: vzip.8 d0, d1
+; CHECK-NEXT: vzip.8 d2, d3
+; CHECK-NEXT: vzip.8 d4, d5
+; CHECK-NEXT: vzip.8 d6, d7
+; CHECK-NEXT: bx lr
+ %result = call <64 x i8> @llvm.vector.interleave8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, <8 x i8> %vec3, <8 x i8> %vec4, <8 x i8> %vec5, <8 x i8> %vec6, <8 x i8> %vec7)
+ ret <64 x i8> %result
+}
+
+
+define <8 x i16> @interleave2_v4i16(<4 x i16> %vec0, <4 x i16> %vec1) {
+; CHECK-LABEL: interleave2_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vzip.16 d0, d1
+; CHECK-NEXT: bx lr
+ %result = call <8 x i16> @llvm.vector.interleave2(<4 x i16> %vec0, <4 x i16> %vec1)
+ ret <8 x i16> %result
+}
+
+define <12 x i16> @interleave3_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
+; CHECK-LABEL: interleave3_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vst3.16 {d0, d1, d2}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <12 x i16> @llvm.vector.interleave3(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2)
+ ret <12 x i16> %result
+}
+
+define <16 x i16> @interleave4_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3) {
+; CHECK-LABEL: interleave4_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vzip.16 d1, d3
+; CHECK-NEXT: vzip.16 d0, d2
+; CHECK-NEXT: vzip.16 d0, d1
+; CHECK-NEXT: vzip.16 d2, d3
+; CHECK-NEXT: bx lr
+ %result = call <16 x i16> @llvm.vector.interleave4(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3)
+ ret <16 x i16> %result
+}
+
+define <24 x i16> @interleave6_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5) {
+; CHECK-LABEL: interleave6_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vmov.f64 d18, d5
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.f64 d17, d4
+; CHECK-NEXT: vorr d16, d3, d3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vzip.16 d2, d18
+; CHECK-NEXT: vzip.16 d1, d17
+; CHECK-NEXT: vzip.16 d0, d16
+; CHECK-NEXT: vst3.16 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.16 {d0, d1, d2}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <24 x i16> @llvm.vector.interleave6(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5)
+ ret <24 x i16> %result
+}
+
+define <32 x i16> @interleave8_v4i16(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5, <4 x i16> %vec6, <4 x i16> %vec7) {
+; CHECK-LABEL: interleave8_v4i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d7 killed $d7 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d5 killed $d5 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d6 killed $d6 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d4 killed $d4 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vzip.16 d3, d7
+; CHECK-NEXT: vzip.16 d1, d5
+; CHECK-NEXT: vzip.16 d2, d6
+; CHECK-NEXT: vzip.16 d0, d4
+; CHECK-NEXT: vzip.16 d1, d3
+; CHECK-NEXT: vzip.16 d5, d7
+; CHECK-NEXT: vzip.16 d0, d2
+; CHECK-NEXT: vzip.16 d4, d6
+; CHECK-NEXT: vzip.16 d0, d1
+; CHECK-NEXT: vzip.16 d2, d3
+; CHECK-NEXT: vzip.16 d4, d5
+; CHECK-NEXT: vzip.16 d6, d7
+; CHECK-NEXT: bx lr
+ %result = call <32 x i16> @llvm.vector.interleave8(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2, <4 x i16> %vec3, <4 x i16> %vec4, <4 x i16> %vec5, <4 x i16> %vec6, <4 x i16> %vec7)
+ ret <32 x i16> %result
+}
+
+
+define <4 x i32> @interleave2_v2i32(<2 x i32> %vec0, <2 x i32> %vec1) {
+; CHECK-LABEL: interleave2_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vtrn.32 d0, d1
+; CHECK-NEXT: bx lr
+ %result = call <4 x i32> @llvm.vector.interleave2(<2 x i32> %vec0, <2 x i32> %vec1)
+ ret <4 x i32> %result
+}
+
+define <6 x i32> @interleave3_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) {
+; CHECK-LABEL: interleave3_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vst3.32 {d0, d1, d2}, [r1:64], r2
+; CHECK-NEXT: vldr d16, [sp]
+; CHECK-NEXT: vldr d17, [r1]
+; CHECK-NEXT: vldr d18, [sp, #16]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vstr d18, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <6 x i32> @llvm.vector.interleave3(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2)
+ ret <6 x i32> %result
+}
+
+define <8 x i32> @interleave4_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3) {
+; CHECK-LABEL: interleave4_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: vtrn.32 d0, d2
+; CHECK-NEXT: vtrn.32 d0, d1
+; CHECK-NEXT: vtrn.32 d2, d3
+; CHECK-NEXT: bx lr
+ %result = call <8 x i32> @llvm.vector.interleave4(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3)
+ ret <8 x i32> %result
+}
+
+define <12 x i32> @interleave6_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5) {
+; CHECK-LABEL: interleave6_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vmov.f64 d18, d5
+; CHECK-NEXT: add r1, sp, #24
+; CHECK-NEXT: mov r2, #8
+; CHECK-NEXT: mov r3, sp
+; CHECK-NEXT: vmov.f64 d17, d4
+; CHECK-NEXT: vorr d16, d3, d3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vtrn.32 d2, d18
+; CHECK-NEXT: vtrn.32 d1, d17
+; CHECK-NEXT: vtrn.32 d0, d16
+; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r1:64], r2
+; CHECK-NEXT: vldr d17, [sp, #24]
+; CHECK-NEXT: vldr d19, [sp, #40]
+; CHECK-NEXT: vst3.32 {d0, d1, d2}, [r3:64], r2
+; CHECK-NEXT: vldr d20, [sp]
+; CHECK-NEXT: vldr d21, [r3]
+; CHECK-NEXT: vldr d16, [sp, #16]
+; CHECK-NEXT: vldr d18, [r1]
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <12 x i32> @llvm.vector.interleave6(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5)
+ ret <12 x i32> %result
+}
+
+define <16 x i32> @interleave8_v2i32(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5, <2 x i32> %vec6, <2 x i32> %vec7) {
+; CHECK-LABEL: interleave8_v2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d7 killed $d7 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d5 killed $d5 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d6 killed $d6 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d4 killed $d4 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vtrn.32 d3, d7
+; CHECK-NEXT: vtrn.32 d1, d5
+; CHECK-NEXT: vtrn.32 d2, d6
+; CHECK-NEXT: vtrn.32 d0, d4
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: vtrn.32 d5, d7
+; CHECK-NEXT: vtrn.32 d0, d2
+; CHECK-NEXT: vtrn.32 d4, d6
+; CHECK-NEXT: vtrn.32 d0, d1
+; CHECK-NEXT: vtrn.32 d2, d3
+; CHECK-NEXT: vtrn.32 d4, d5
+; CHECK-NEXT: vtrn.32 d6, d7
+; CHECK-NEXT: bx lr
+ %result = call <16 x i32> @llvm.vector.interleave8(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2, <2 x i32> %vec3, <2 x i32> %vec4, <2 x i32> %vec5, <2 x i32> %vec6, <2 x i32> %vec7)
+ ret <16 x i32> %result
+}
+
+
+define <4 x float> @interleave2_v2f32(<2 x float> %vec0, <2 x float> %vec1) {
+; CHECK-LABEL: interleave2_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vtrn.32 d0, d1
+; CHECK-NEXT: bx lr
+ %result = call <4 x float> @llvm.vector.interleave2(<2 x float> %vec0, <2 x float> %vec1)
+ ret <4 x float> %result
+}
+
+define <6 x float> @interleave3_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2) {
+; CHECK-LABEL: interleave3_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, sp, #24
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: mov r1, #8
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vst3.32 {d0, d1, d2}, [r0:64], r1
+; CHECK-NEXT: vldr d0, [sp]
+; CHECK-NEXT: vldr d2, [sp, #16]
+; CHECK-NEXT: vldr d1, [r0]
+; CHECK-NEXT: add sp, sp, #24
+; CHECK-NEXT: bx lr
+ %result = call <6 x float> @llvm.vector.interleave3(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2)
+ ret <6 x float> %result
+}
+
+define <8 x float> @interleave4_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3) {
+; CHECK-LABEL: interleave4_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: vtrn.32 d0, d2
+; CHECK-NEXT: vtrn.32 d0, d1
+; CHECK-NEXT: vtrn.32 d2, d3
+; CHECK-NEXT: bx lr
+ %result = call <8 x float> @llvm.vector.interleave4(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3)
+ ret <8 x float> %result
+}
+
+define <12 x float> @interleave6_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5) {
+; CHECK-LABEL: interleave6_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .pad #48
+; CHECK-NEXT: sub sp, sp, #48
+; CHECK-NEXT: vmov.f64 d18, d5
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: mov r1, #8
+; CHECK-NEXT: add r2, sp, #24
+; CHECK-NEXT: vmov.f64 d17, d4
+; CHECK-NEXT: vorr d16, d3, d3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
+; CHECK-NEXT: vtrn.32 d2, d18
+; CHECK-NEXT: vtrn.32 d1, d17
+; CHECK-NEXT: vtrn.32 d0, d16
+; CHECK-NEXT: vst3.32 {d0, d1, d2}, [r0:64], r1
+; CHECK-NEXT: vldr d0, [sp]
+; CHECK-NEXT: vldr d2, [sp, #16]
+; CHECK-NEXT: vst3.32 {d16, d17, d18}, [r2:64], r1
+; CHECK-NEXT: vldr d3, [sp, #24]
+; CHECK-NEXT: vldr d5, [sp, #40]
+; CHECK-NEXT: vldr d1, [r0]
+; CHECK-NEXT: vldr d4, [r2]
+; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: bx lr
+ %result = call <12 x float> @llvm.vector.interleave6(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5)
+ ret <12 x float> %result
+}
+
+define <16 x float> @interleave8_v2f32(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5, <2 x float> %vec6, <2 x float> %vec7) {
+; CHECK-LABEL: interleave8_v2f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: @ kill: def $d7 killed $d7 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d5 killed $d5 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0
+; CHECK-NEXT: @ kill: def $d6 killed $d6 killed $q3 def $q3
+; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q1 def $q1
+; CHECK-NEXT: @ kill: def $d4 killed $d4 killed $q2 def $q2
+; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0
+; CHECK-NEXT: vtrn.32 d3, d7
+; CHECK-NEXT: vtrn.32 d1, d5
+; CHECK-NEXT: vtrn.32 d2, d6
+; CHECK-NEXT: vtrn.32 d0, d4
+; CHECK-NEXT: vtrn.32 d1, d3
+; CHECK-NEXT: vtrn.32 d5, d7
+; CHECK-NEXT: vtrn.32 d0, d2
+; CHECK-NEXT: vtrn.32 d4, d6
+; CHECK-NEXT: vtrn.32 d0, d1
+; CHECK-NEXT: vtrn.32 d2, d3
+; CHECK-NEXT: vtrn.32 d4, d5
+; CHECK-NEXT: vtrn.32 d6, d7
+; CHECK-NEXT: bx lr
+ %result = call <16 x float> @llvm.vector.interleave8(<2 x float> %vec0, <2 x float> %vec1, <2 x float> %vec2, <2 x float> %vec3, <2 x float> %vec4, <2 x float> %vec5, <2 x float> %vec6, <2 x float> %vec7)
+ ret <16 x float> %result
+}
+
+
+define <32 x i8> @interleave2_v16i8(<16 x i8> %vec0, <16 x i8> %vec1) {
+; CHECK-LABEL: interleave2_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.8 q0, q1
+; CHECK-NEXT: bx lr
+ %result = call <32 x i8> @llvm.vector.interleave2(<16 x i8> %vec0, <16 x i8> %vec1)
+ ret <32 x i8> %result
+}
+
+define <48 x i8> @interleave3_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2) {
+; CHECK-LABEL: interleave3_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vst3.8 {d0, d2, d4}, [r2:64]!
+; CHECK-NEXT: vst3.8 {d1, d3, d5}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <48 x i8> @llvm.vector.interleave3(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2)
+ ret <48 x i8> %result
+}
+
+define <64 x i8> @interleave4_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3) {
+; CHECK-LABEL: interleave4_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.8 q1, q3
+; CHECK-NEXT: vzip.8 q0, q2
+; CHECK-NEXT: vzip.8 q0, q1
+; CHECK-NEXT: vzip.8 q2, q3
+; CHECK-NEXT: bx lr
+ %result = call <64 x i8> @llvm.vector.interleave4(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3)
+ ret <64 x i8> %result
+}
+
+define <96 x i8> @interleave6_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5) {
+; CHECK-LABEL: interleave6_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: vorr q8, q3, q3
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: add r1, r11, #20
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #4
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.8 q0, q8
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.8 q2, q10
+; CHECK-NEXT: vzip.8 q1, q9
+; CHECK-NEXT: vst3.8 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.8 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vst3.8 {d0, d2, d4}, [r3:64]!
+; CHECK-NEXT: vst3.8 {d1, d3, d5}, [r3:64]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r2]!
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d24, d25}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <96 x i8> @llvm.vector.interleave6(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5)
+ ret <96 x i8> %result
+}
+
+define <128 x i8> @interleave8_v16i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5, <16 x i8> %vec6, <16 x i8> %vec7) {
+; CHECK-LABEL: interleave8_v16i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #32
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.8 q3, q8
+; CHECK-NEXT: vzip.8 q1, q9
+; CHECK-NEXT: vzip.8 q2, q10
+; CHECK-NEXT: vzip.8 q0, q11
+; CHECK-NEXT: vzip.8 q9, q8
+; CHECK-NEXT: vzip.8 q11, q10
+; CHECK-NEXT: vzip.8 q1, q3
+; CHECK-NEXT: vzip.8 q0, q2
+; CHECK-NEXT: vzip.8 q11, q9
+; CHECK-NEXT: vzip.8 q10, q8
+; CHECK-NEXT: vst1.8 {d22, d23}, [r1:128]!
+; CHECK-NEXT: vzip.8 q0, q1
+; CHECK-NEXT: vst1.8 {d18, d19}, [r1:128]!
+; CHECK-NEXT: vst1.8 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vzip.8 q2, q3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: vst1.8 {d0, d1}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d2, d3}, [r0:128]!
+; CHECK-NEXT: vst1.8 {d4, d5}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d6, d7}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <128 x i8> @llvm.vector.interleave8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4, <16 x i8> %vec5, <16 x i8> %vec6, <16 x i8> %vec7)
+ ret <128 x i8> %result
+}
+
+
+define <16 x i16> @interleave2_v8i16(<8 x i16> %vec0, <8 x i16> %vec1) {
+; CHECK-LABEL: interleave2_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.16 q0, q1
+; CHECK-NEXT: bx lr
+ %result = call <16 x i16> @llvm.vector.interleave2(<8 x i16> %vec0, <8 x i16> %vec1)
+ ret <16 x i16> %result
+}
+
+define <24 x i16> @interleave3_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2) {
+; CHECK-LABEL: interleave3_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vst3.16 {d0, d2, d4}, [r2:64]!
+; CHECK-NEXT: vst3.16 {d1, d3, d5}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <24 x i16> @llvm.vector.interleave3(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2)
+ ret <24 x i16> %result
+}
+
+define <32 x i16> @interleave4_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3) {
+; CHECK-LABEL: interleave4_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.16 q1, q3
+; CHECK-NEXT: vzip.16 q0, q2
+; CHECK-NEXT: vzip.16 q0, q1
+; CHECK-NEXT: vzip.16 q2, q3
+; CHECK-NEXT: bx lr
+ %result = call <32 x i16> @llvm.vector.interleave4(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3)
+ ret <32 x i16> %result
+}
+
+define <48 x i16> @interleave6_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5) {
+; CHECK-LABEL: interleave6_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: vorr q8, q3, q3
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: add r1, r11, #20
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #4
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.16 q0, q8
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.16 q2, q10
+; CHECK-NEXT: vzip.16 q1, q9
+; CHECK-NEXT: vst3.16 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.16 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vst3.16 {d0, d2, d4}, [r3:64]!
+; CHECK-NEXT: vst3.16 {d1, d3, d5}, [r3:64]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r2]!
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d24, d25}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <48 x i16> @llvm.vector.interleave6(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5)
+ ret <48 x i16> %result
+}
+
+define <64 x i16> @interleave8_v8i16(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5, <8 x i16> %vec6, <8 x i16> %vec7) {
+; CHECK-LABEL: interleave8_v8i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #32
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.16 q3, q8
+; CHECK-NEXT: vzip.16 q1, q9
+; CHECK-NEXT: vzip.16 q2, q10
+; CHECK-NEXT: vzip.16 q0, q11
+; CHECK-NEXT: vzip.16 q9, q8
+; CHECK-NEXT: vzip.16 q11, q10
+; CHECK-NEXT: vzip.16 q1, q3
+; CHECK-NEXT: vzip.16 q0, q2
+; CHECK-NEXT: vzip.16 q11, q9
+; CHECK-NEXT: vzip.16 q10, q8
+; CHECK-NEXT: vst1.16 {d22, d23}, [r1:128]!
+; CHECK-NEXT: vzip.16 q0, q1
+; CHECK-NEXT: vst1.16 {d18, d19}, [r1:128]!
+; CHECK-NEXT: vst1.16 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vzip.16 q2, q3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: vst1.16 {d0, d1}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d2, d3}, [r0:128]!
+; CHECK-NEXT: vst1.16 {d4, d5}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d6, d7}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <64 x i16> @llvm.vector.interleave8(<8 x i16> %vec0, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4, <8 x i16> %vec5, <8 x i16> %vec6, <8 x i16> %vec7)
+ ret <64 x i16> %result
+}
+
+define <8 x i32> @interleave2_v4i32(<4 x i32> %vec0, <4 x i32> %vec1) {
+; CHECK-LABEL: interleave2_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.32 q0, q1
+; CHECK-NEXT: bx lr
+ %result = call <8 x i32> @llvm.vector.interleave2(<4 x i32> %vec0, <4 x i32> %vec1)
+ ret <8 x i32> %result
+}
+
+define <12 x i32> @interleave3_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2) {
+; CHECK-LABEL: interleave3_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vst3.32 {d0, d2, d4}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d1, d3, d5}, [r2:64]
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <12 x i32> @llvm.vector.interleave3(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2)
+ ret <12 x i32> %result
+}
+
+define <16 x i32> @interleave4_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3) {
+; CHECK-LABEL: interleave4_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.32 q1, q3
+; CHECK-NEXT: vzip.32 q0, q2
+; CHECK-NEXT: vzip.32 q0, q1
+; CHECK-NEXT: vzip.32 q2, q3
+; CHECK-NEXT: bx lr
+ %result = call <16 x i32> @llvm.vector.interleave4(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3)
+ ret <16 x i32> %result
+}
+
+define <24 x i32> @interleave6_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5) {
+; CHECK-LABEL: interleave6_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: vorr q8, q3, q3
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: add r1, r11, #20
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #4
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.32 q0, q8
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.32 q2, q10
+; CHECK-NEXT: vzip.32 q1, q9
+; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vst3.32 {d0, d2, d4}, [r3:64]!
+; CHECK-NEXT: vst3.32 {d1, d3, d5}, [r3:64]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r2]!
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d24, d25}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <24 x i32> @llvm.vector.interleave6(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5)
+ ret <24 x i32> %result
+}
+
+define <32 x i32> @interleave8_v4i32(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7) {
+; CHECK-LABEL: interleave8_v4i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #32
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.32 q3, q8
+; CHECK-NEXT: vzip.32 q1, q9
+; CHECK-NEXT: vzip.32 q2, q10
+; CHECK-NEXT: vzip.32 q0, q11
+; CHECK-NEXT: vzip.32 q9, q8
+; CHECK-NEXT: vzip.32 q11, q10
+; CHECK-NEXT: vzip.32 q1, q3
+; CHECK-NEXT: vzip.32 q0, q2
+; CHECK-NEXT: vzip.32 q11, q9
+; CHECK-NEXT: vzip.32 q10, q8
+; CHECK-NEXT: vst1.32 {d22, d23}, [r1:128]!
+; CHECK-NEXT: vzip.32 q0, q1
+; CHECK-NEXT: vst1.32 {d18, d19}, [r1:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vzip.32 q2, q3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: vst1.32 {d0, d1}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d2, d3}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d4, d5}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d6, d7}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x i32> @llvm.vector.interleave8(<4 x i32> %vec0, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7)
+ ret <32 x i32> %result
+}
+
+
+define <8 x float> @interleave2_v4f32(<4 x float> %vec0, <4 x float> %vec1) {
+; CHECK-LABEL: interleave2_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.32 q0, q1
+; CHECK-NEXT: bx lr
+ %result = call <8 x float> @llvm.vector.interleave2(<4 x float> %vec0, <4 x float> %vec1)
+ ret <8 x float> %result
+}
+
+define <12 x float> @interleave3_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2) {
+; CHECK-LABEL: interleave3_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #60
+; CHECK-NEXT: sub sp, sp, #60
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r0, sp
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: mov r1, r0
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vst3.32 {d0, d2, d4}, [r1:64]!
+; CHECK-NEXT: vst3.32 {d1, d3, d5}, [r1:64]
+; CHECK-NEXT: vld1.64 {d0, d1}, [r0:128]!
+; CHECK-NEXT: vld1.64 {d2, d3}, [r0]!
+; CHECK-NEXT: vld1.64 {d4, d5}, [r0]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <12 x float> @llvm.vector.interleave3(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2)
+ ret <12 x float> %result
+}
+
+define <16 x float> @interleave4_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3) {
+; CHECK-LABEL: interleave4_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vzip.32 q1, q3
+; CHECK-NEXT: vzip.32 q0, q2
+; CHECK-NEXT: vzip.32 q0, q1
+; CHECK-NEXT: vzip.32 q2, q3
+; CHECK-NEXT: bx lr
+ %result = call <16 x float> @llvm.vector.interleave4(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3)
+ ret <16 x float> %result
+}
+
+define <24 x float> @interleave6_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5) {
+; CHECK-LABEL: interleave6_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11}
+; CHECK-NEXT: push {r11}
+; CHECK-NEXT: .setfp r11, sp
+; CHECK-NEXT: mov r11, sp
+; CHECK-NEXT: .pad #108
+; CHECK-NEXT: sub sp, sp, #108
+; CHECK-NEXT: bfc sp, #0, #4
+; CHECK-NEXT: vorr q8, q3, q3
+; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: add r1, r11, #20
+; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: add r1, r11, #4
+; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vzip.32 q0, q8
+; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: vzip.32 q2, q10
+; CHECK-NEXT: vzip.32 q1, q9
+; CHECK-NEXT: vst3.32 {d16, d18, d20}, [r2:64]!
+; CHECK-NEXT: vst3.32 {d17, d19, d21}, [r2:64]
+; CHECK-NEXT: mov r2, sp
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!
+; CHECK-NEXT: vst3.32 {d0, d2, d4}, [r3:64]!
+; CHECK-NEXT: vst3.32 {d1, d3, d5}, [r3:64]
+; CHECK-NEXT: vld1.64 {d18, d19}, [r2:128]!
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]!
+; CHECK-NEXT: vld1.64 {d22, d23}, [r2]!
+; CHECK-NEXT: vld1.64 {d24, d25}, [r1]
+; CHECK-NEXT: vld1.64 {d26, d27}, [r2]
+; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d22, d23}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d26, d27}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d16, d17}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d24, d25}, [r0:128]
+; CHECK-NEXT: mov sp, r11
+; CHECK-NEXT: pop {r11}
+; CHECK-NEXT: bx lr
+ %result = call <24 x float> @llvm.vector.interleave6(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5)
+ ret <24 x float> %result
+}
+
+define <32 x float> @interleave8_v4f32(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5, <4 x float> %vec6, <4 x float> %vec7) {
+; CHECK-LABEL: interleave8_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: add r1, sp, #48
+; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
+; CHECK-NEXT: add r1, sp, #16
+; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
+; CHECK-NEXT: add r1, sp, #32
+; CHECK-NEXT: vld1.64 {d20, d21}, [r1]
+; CHECK-NEXT: mov r1, sp
+; CHECK-NEXT: vld1.64 {d22, d23}, [r1]
+; CHECK-NEXT: add r1, r0, #64
+; CHECK-NEXT: vzip.32 q3, q8
+; CHECK-NEXT: vzip.32 q1, q9
+; CHECK-NEXT: vzip.32 q2, q10
+; CHECK-NEXT: vzip.32 q0, q11
+; CHECK-NEXT: vzip.32 q9, q8
+; CHECK-NEXT: vzip.32 q11, q10
+; CHECK-NEXT: vzip.32 q1, q3
+; CHECK-NEXT: vzip.32 q0, q2
+; CHECK-NEXT: vzip.32 q11, q9
+; CHECK-NEXT: vzip.32 q10, q8
+; CHECK-NEXT: vst1.32 {d22, d23}, [r1:128]!
+; CHECK-NEXT: vzip.32 q0, q1
+; CHECK-NEXT: vst1.32 {d18, d19}, [r1:128]!
+; CHECK-NEXT: vst1.32 {d20, d21}, [r1:128]!
+; CHECK-NEXT: vzip.32 q2, q3
+; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]
+; CHECK-NEXT: vst1.32 {d0, d1}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d2, d3}, [r0:128]!
+; CHECK-NEXT: vst1.32 {d4, d5}, [r0:128]!
+; CHECK-NEXT: vst1.64 {d6, d7}, [r0:128]
+; CHECK-NEXT: bx lr
+ %result = call <32 x float> @llvm.vector.interleave8(<4 x float> %vec0, <4 x float> %vec1, <4 x float> %vec2, <4 x float> %vec3, <4 x float> %vec4, <4 x float> %vec5, <4 x float> %vec6, <4 x float> %vec7)
+ ret <32 x float> %result
+}
+
+
+define <8 x half> @interleave2_v4f16(<4 x half> %vec0, <4 x half> %vec1) {
+; CHECK-LABEL: interleave2_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s8, s3
+; CHECK-NEXT: vmov.f32 s10, s2
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: vmov.f32 s1, s4
+; CHECK-NEXT: vmov.f32 s3, s5
+; CHECK-NEXT: vmov.f32 s5, s6
+; CHECK-NEXT: vmov.f32 s6, s8
+; CHECK-NEXT: vmov.f32 s4, s10
+; CHECK-NEXT: bx lr
+ %result = call <8 x half> @llvm.vector.interleave2(<4 x half> %vec0, <4 x half> %vec1)
+ ret <8 x half> %result
+}
+
+define <12 x half> @interleave3_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2) {
+; CHECK-LABEL: interleave3_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s1
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: vmov r12, s6
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: vmov lr, s9
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: pkhbt r0, r2, r0, lsl #16
+; CHECK-NEXT: vmov r2, s11
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: vmov r3, s3
+; CHECK-NEXT: vmov d16, r1, r0
+; CHECK-NEXT: pkhbt r1, r4, r12, lsl #16
+; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: vmov.u16 r4, d16[0]
+; CHECK-NEXT: pkhbt r5, r5, lr, lsl #16
+; CHECK-NEXT: vmov.u16 r7, d16[3]
+; CHECK-NEXT: vmov d17, r5, r1
+; CHECK-NEXT: vmov.u16 r12, d16[1]
+; CHECK-NEXT: vmov.u16 lr, d16[2]
+; CHECK-NEXT: vmov.u16 r5, d17[0]
+; CHECK-NEXT: pkhbt r2, r6, r2, lsl #16
+; CHECK-NEXT: pkhbt r0, r0, r3, lsl #16
+; CHECK-NEXT: vmov.u16 r3, d17[1]
+; CHECK-NEXT: vmov d16, r0, r2
+; CHECK-NEXT: vmov.u16 r0, d17[2]
+; CHECK-NEXT: vmov.u16 r2, d17[3]
+; CHECK-NEXT: vmov s0, r4
+; CHECK-NEXT: vmov.u16 r4, d16[0]
+; CHECK-NEXT: vmov s3, r7
+; CHECK-NEXT: vmov.u16 r6, d16[1]
+; CHECK-NEXT: vmov s1, r12
+; CHECK-NEXT: vmov.u16 r1, d16[2]
+; CHECK-NEXT: vmov s2, lr
+; CHECK-NEXT: vmov.u16 r7, d16[3]
+; CHECK-NEXT: vmov s4, r5
+; CHECK-NEXT: vmov s5, r3
+; CHECK-NEXT: vmov s6, r0
+; CHECK-NEXT: vmov s7, r2
+; CHECK-NEXT: vmov s8, r4
+; CHECK-NEXT: vmov s9, r6
+; CHECK-NEXT: vmov s10, r1
+; CHECK-NEXT: vmov s11, r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <12 x half> @llvm.vector.interleave3(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2)
+ ret <12 x half> %result
+}
+
+define <16 x half> @interleave4_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3) {
+; CHECK-LABEL: interleave4_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: vmov r0, s12
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: vmov r4, s15
+; CHECK-NEXT: vmov r6, s11
+; CHECK-NEXT: vmov r12, s6
+; CHECK-NEXT: vmov lr, s2
+; CHECK-NEXT: pkhbt r0, r2, r0, lsl #16
+; CHECK-NEXT: vmov r2, s10
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: vmov r3, s13
+; CHECK-NEXT: vmov d16, r1, r0
+; CHECK-NEXT: vmov r0, s9
+; CHECK-NEXT: pkhbt r6, r6, r4, lsl #16
+; CHECK-NEXT: vmov r1, s1
+; CHECK-NEXT: vmov.u16 r7, d16[1]
+; CHECK-NEXT: vmov r4, s7
+; CHECK-NEXT: pkhbt r8, r2, r5, lsl #16
+; CHECK-NEXT: vmov r2, s5
+; CHECK-NEXT: pkhbt r5, lr, r12, lsl #16
+; CHECK-NEXT: vmov d18, r5, r8
+; CHECK-NEXT: pkhbt r0, r0, r3, lsl #16
+; CHECK-NEXT: vmov r3, s3
+; CHECK-NEXT: vmov s1, r7
+; CHECK-NEXT: vmov.u16 r7, d18[1]
+; CHECK-NEXT: pkhbt r1, r1, r2, lsl #16
+; CHECK-NEXT: vmov.u16 r2, d16[0]
+; CHECK-NEXT: vmov d17, r1, r0
+; CHECK-NEXT: vmov.u16 r0, d16[2]
+; CHECK-NEXT: pkhbt r1, r3, r4, lsl #16
+; CHECK-NEXT: vmov.u16 r3, d16[3]
+; CHECK-NEXT: vmov.u16 r4, d17[0]
+; CHECK-NEXT: vmov d16, r1, r6
+; CHECK-NEXT: vmov.u16 r1, d17[1]
+; CHECK-NEXT: vmov.u16 r6, d17[2]
+; CHECK-NEXT: vmov s9, r7
+; CHECK-NEXT: vmov.u16 r5, d17[3]
+; CHECK-NEXT: vmov s0, r2
+; CHECK-NEXT: vmov.u16 r2, d18[0]
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.u16 r0, d18[2]
+; CHECK-NEXT: vmov s3, r3
+; CHECK-NEXT: vmov.u16 r3, d18[3]
+; CHECK-NEXT: vmov s4, r4
+; CHECK-NEXT: vmov.u16 r4, d16[0]
+; CHECK-NEXT: vmov s5, r1
+; CHECK-NEXT: vmov.u16 r1, d16[1]
+; CHECK-NEXT: vmov s6, r6
+; CHECK-NEXT: vmov.u16 r6, d16[2]
+; CHECK-NEXT: vmov s7, r5
+; CHECK-NEXT: vmov.u16 r5, d16[3]
+; CHECK-NEXT: vmov s8, r2
+; CHECK-NEXT: vmov s10, r0
+; CHECK-NEXT: vmov s11, r3
+; CHECK-NEXT: vmov s12, r4
+; CHECK-NEXT: vmov s13, r1
+; CHECK-NEXT: vmov s14, r6
+; CHECK-NEXT: vmov s15, r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call <16 x half> @llvm.vector.interleave4(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3)
+ ret <16 x half> %result
+}
+
+define <24 x half> @interleave6_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5) {
+; CHECK-LABEL: interleave6_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r1, s15
+; CHECK-NEXT: ldrh r3, [sp, #52]
+; CHECK-NEXT: vmov r2, s11
+; CHECK-NEXT: ldrh r4, [sp, #36]
+; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: vmov r12, s7
+; CHECK-NEXT: orr r3, r4, r3, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: str r3, [r0, #44]
+; CHECK-NEXT: vmov lr, s3
+; CHECK-NEXT: ldrh r3, [sp, #44]
+; CHECK-NEXT: orr r4, r6, r5, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #28]
+; CHECK-NEXT: vmov r7, s13
+; CHECK-NEXT: str r4, [r0, #32]
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: str r3, [r0, #20]
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: orr r4, r5, r4, lsl #16
+; CHECK-NEXT: vmov r5, s10
+; CHECK-NEXT: str r4, [r0, #8]
+; CHECK-NEXT: vmov r4, s6
+; CHECK-NEXT: pkhbt r1, r2, r1, lsl #16
+; CHECK-NEXT: vmov r2, s2
+; CHECK-NEXT: str r1, [r0, #40]
+; CHECK-NEXT: vmov r1, s9
+; CHECK-NEXT: pkhbt r6, lr, r12, lsl #16
+; CHECK-NEXT: str r6, [r0, #36]
+; CHECK-NEXT: vmov r6, s4
+; CHECK-NEXT: pkhbt r3, r5, r3, lsl #16
+; CHECK-NEXT: str r3, [r0, #28]
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: vmov r5, s12
+; CHECK-NEXT: pkhbt r2, r2, r4, lsl #16
+; CHECK-NEXT: vmov r4, s1
+; CHECK-NEXT: str r2, [r0, #24]
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: pkhbt r1, r1, r7, lsl #16
+; CHECK-NEXT: vmov r7, s0
+; CHECK-NEXT: str r1, [r0, #16]
+; CHECK-NEXT: pkhbt r1, r4, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: pkhbt r1, r2, r5, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r7, r6, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <24 x half> @llvm.vector.interleave6(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5)
+ ret <24 x half> %result
+}
+
+define <32 x half> @interleave8_v4f16(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5, <4 x half> %vec6, <4 x half> %vec7) {
+; CHECK-LABEL: interleave8_v4f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r6, s15
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: ldrh r3, [sp, #28]
+; CHECK-NEXT: strh r5, [r0, #62]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r2, [r0, #58]
+; CHECK-NEXT: strh r3, [r0, #56]
+; CHECK-NEXT: ldrh r12, [sp, #72]
+; CHECK-NEXT: ldrh lr, [sp, #56]
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: ldrh r1, [sp, #68]
+; CHECK-NEXT: ldrh r2, [sp, #52]
+; CHECK-NEXT: ldrh r3, [sp, #36]
+; CHECK-NEXT: strh r12, [r0, #46]
+; CHECK-NEXT: vmov r12, s11
+; CHECK-NEXT: strh lr, [r0, #44]
+; CHECK-NEXT: vmov lr, s9
+; CHECK-NEXT: strh r4, [r0, #42]
+; CHECK-NEXT: strh r5, [r0, #40]
+; CHECK-NEXT: strh r1, [r0, #30]
+; CHECK-NEXT: strh r2, [r0, #28]
+; CHECK-NEXT: strh r3, [r0, #26]
+; CHECK-NEXT: ldrh r3, [sp, #20]
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: ldrh r2, [sp, #16]
+; CHECK-NEXT: strh r3, [r0, #24]
+; CHECK-NEXT: vmov r3, s7
+; CHECK-NEXT: strh r4, [r0, #14]
+; CHECK-NEXT: vmov r4, s3
+; CHECK-NEXT: strh r5, [r0, #12]
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: vmov r1, s10
+; CHECK-NEXT: strh r2, [r0, #8]
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: strh r6, [r0, #54]
+; CHECK-NEXT: vmov r6, s2
+; CHECK-NEXT: strh r12, [r0, #52]
+; CHECK-NEXT: vmov r12, s13
+; CHECK-NEXT: strh r3, [r0, #50]
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: strh r4, [r0, #48]
+; CHECK-NEXT: vmov r4, s5
+; CHECK-NEXT: strh r5, [r0, #38]
+; CHECK-NEXT: vmov r5, s1
+; CHECK-NEXT: strh r1, [r0, #36]
+; CHECK-NEXT: vmov r1, s12
+; CHECK-NEXT: strh r2, [r0, #34]
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: strh r6, [r0, #32]
+; CHECK-NEXT: vmov r6, s4
+; CHECK-NEXT: strh r12, [r0, #22]
+; CHECK-NEXT: strh lr, [r0, #20]
+; CHECK-NEXT: strh r4, [r0, #18]
+; CHECK-NEXT: strh r5, [r0, #16]
+; CHECK-NEXT: strh r1, [r0, #6]
+; CHECK-NEXT: strh r2, [r0, #4]
+; CHECK-NEXT: strh r6, [r0, #2]
+; CHECK-NEXT: strh r3, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <32 x half> @llvm.vector.interleave8(<4 x half> %vec0, <4 x half> %vec1, <4 x half> %vec2, <4 x half> %vec3, <4 x half> %vec4, <4 x half> %vec5, <4 x half> %vec6, <4 x half> %vec7)
+ ret <32 x half> %result
+}
+
+
+define <16 x half> @interleave2_v8f16(<8 x half> %vec0, <8 x half> %vec1) {
+; CHECK-LABEL: interleave2_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: vmov.f32 s16, s7
+; CHECK-NEXT: vmov.f32 s18, s6
+; CHECK-NEXT: vmov.f32 s20, s5
+; CHECK-NEXT: vmov.f32 s22, s4
+; CHECK-NEXT: vmov.f32 s6, s3
+; CHECK-NEXT: vmov.f32 s4, s2
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: vmov.f32 s1, s8
+; CHECK-NEXT: vmov.f32 s3, s9
+; CHECK-NEXT: vmov.f32 s5, s10
+; CHECK-NEXT: vmov.f32 s7, s11
+; CHECK-NEXT: vmov.f32 s9, s12
+; CHECK-NEXT: vmov.f32 s11, s13
+; CHECK-NEXT: vmov.f32 s13, s14
+; CHECK-NEXT: vmov.f32 s8, s22
+; CHECK-NEXT: vmov.f32 s10, s20
+; CHECK-NEXT: vmov.f32 s12, s18
+; CHECK-NEXT: vmov.f32 s14, s16
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: bx lr
+ %result = call <16 x half> @llvm.vector.interleave2(<8 x half> %vec0, <8 x half> %vec1)
+ ret <16 x half> %result
+}
+
+define <24 x half> @interleave3_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2) {
+; CHECK-LABEL: interleave3_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r2, s13
+; CHECK-NEXT: ldrh r5, [sp, #36]
+; CHECK-NEXT: vmov r1, s15
+; CHECK-NEXT: ldrh r3, [sp, #44]
+; CHECK-NEXT: vmov r12, s9
+; CHECK-NEXT: ldrh r4, [sp, #20]
+; CHECK-NEXT: vmov lr, s11
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: pkhbt r2, r2, r5, lsl #16
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: pkhbt r1, r1, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: str r2, [r0, #32]
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: pkhbt r4, r12, r4, lsl #16
+; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: pkhbt r1, lr, r1, lsl #16
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: str r4, [r0, #8]
+; CHECK-NEXT: vmov lr, s12
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: orr r6, r4, r6, lsl #16
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: str r6, [r0, #40]
+; CHECK-NEXT: vmov r6, s3
+; CHECK-NEXT: pkhbt r2, r2, r5, lsl #16
+; CHECK-NEXT: str r2, [r0, #36]
+; CHECK-NEXT: vmov r2, s10
+; CHECK-NEXT: orr r3, r4, r3, lsl #16
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: str r3, [r0, #28]
+; CHECK-NEXT: vmov r3, s8
+; CHECK-NEXT: vmov r5, s0
+; CHECK-NEXT: pkhbt r1, r1, lr, lsl #16
+; CHECK-NEXT: str r1, [r0, #24]
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #16]
+; CHECK-NEXT: str r1, [r0, #16]
+; CHECK-NEXT: pkhbt r1, r4, r2, lsl #16
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r6, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r5, r3, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <24 x half> @llvm.vector.interleave3(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2)
+ ret <24 x half> %result
+}
+
+define <32 x half> @interleave4_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3) {
+; CHECK-LABEL: interleave4_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r6, s15
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r2, [sp, #72]
+; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: strh r5, [r0, #62]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r2, [r0, #54]
+; CHECK-NEXT: strh r3, [r0, #52]
+; CHECK-NEXT: ldrh r12, [sp, #68]
+; CHECK-NEXT: ldrh lr, [sp, #36]
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r2, [sp, #28]
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: strh r12, [r0, #46]
+; CHECK-NEXT: vmov r12, s7
+; CHECK-NEXT: strh lr, [r0, #44]
+; CHECK-NEXT: vmov lr, s3
+; CHECK-NEXT: strh r4, [r0, #38]
+; CHECK-NEXT: strh r5, [r0, #36]
+; CHECK-NEXT: strh r1, [r0, #30]
+; CHECK-NEXT: strh r2, [r0, #28]
+; CHECK-NEXT: strh r3, [r0, #22]
+; CHECK-NEXT: ldrh r3, [sp, #24]
+; CHECK-NEXT: ldrh r4, [sp, #52]
+; CHECK-NEXT: ldrh r5, [sp, #20]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: ldrh r2, [sp, #16]
+; CHECK-NEXT: strh r3, [r0, #20]
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: strh r4, [r0, #14]
+; CHECK-NEXT: vmov r4, s6
+; CHECK-NEXT: strh r5, [r0, #12]
+; CHECK-NEXT: vmov r5, s13
+; CHECK-NEXT: strh r1, [r0, #6]
+; CHECK-NEXT: vmov r1, s5
+; CHECK-NEXT: strh r2, [r0, #4]
+; CHECK-NEXT: vmov r2, s12
+; CHECK-NEXT: strh r6, [r0, #58]
+; CHECK-NEXT: vmov r6, s4
+; CHECK-NEXT: strh r12, [r0, #56]
+; CHECK-NEXT: vmov r12, s11
+; CHECK-NEXT: strh r3, [r0, #50]
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: strh r4, [r0, #48]
+; CHECK-NEXT: vmov r4, s10
+; CHECK-NEXT: strh r5, [r0, #42]
+; CHECK-NEXT: vmov r5, s2
+; CHECK-NEXT: strh r1, [r0, #40]
+; CHECK-NEXT: vmov r1, s9
+; CHECK-NEXT: strh r2, [r0, #34]
+; CHECK-NEXT: vmov r2, s1
+; CHECK-NEXT: strh r6, [r0, #32]
+; CHECK-NEXT: vmov r6, s8
+; CHECK-NEXT: strh r12, [r0, #26]
+; CHECK-NEXT: strh lr, [r0, #24]
+; CHECK-NEXT: strh r4, [r0, #18]
+; CHECK-NEXT: strh r5, [r0, #16]
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: strh r2, [r0, #8]
+; CHECK-NEXT: strh r6, [r0, #2]
+; CHECK-NEXT: strh r3, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <32 x half> @llvm.vector.interleave4(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3)
+ ret <32 x half> %result
+}
+
+define <48 x half> @interleave6_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5) {
+; CHECK-LABEL: interleave6_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: ldrh r1, [sp, #148]
+; CHECK-NEXT: ldrh r2, [sp, #116]
+; CHECK-NEXT: ldrh r5, [sp, #84]
+; CHECK-NEXT: ldrh r6, [sp, #52]
+; CHECK-NEXT: orr r1, r2, r1, lsl #16
+; CHECK-NEXT: ldrh r3, [sp, #144]
+; CHECK-NEXT: orr r2, r6, r5, lsl #16
+; CHECK-NEXT: str r1, [r0, #92]
+; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: ldrh r12, [sp, #80]
+; CHECK-NEXT: str r2, [r0, #88]
+; CHECK-NEXT: orr r1, r1, r3, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: ldrh lr, [sp, #140]
+; CHECK-NEXT: str r1, [r0, #80]
+; CHECK-NEXT: orr r2, r2, r12, lsl #16
+; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: vmov r12, s15
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: str r2, [r0, #76]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: ldrh r5, [sp, #136]
+; CHECK-NEXT: str r1, [r0, #68]
+; CHECK-NEXT: orr r2, r2, r7, lsl #16
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: str r2, [r0, #64]
+; CHECK-NEXT: orr r1, r1, r5, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: str r1, [r0, #56]
+; CHECK-NEXT: orr r2, r2, r3, lsl #16
+; CHECK-NEXT: ldrh r1, [sp, #100]
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: str r2, [r0, #52]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: orr r1, r2, r4, lsl #16
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: str r1, [r0, #40]
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: ldrh r7, [sp, #128]
+; CHECK-NEXT: vmov r4, s4
+; CHECK-NEXT: ldrh r5, [sp, #96]
+; CHECK-NEXT: ldrh r3, [sp, #64]
+; CHECK-NEXT: orr r7, r5, r7, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: str r7, [r0, #32]
+; CHECK-NEXT: ldrh r7, [sp, #124]
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #92]
+; CHECK-NEXT: str r3, [r0, #28]
+; CHECK-NEXT: ldrh r3, [sp, #60]
+; CHECK-NEXT: orr r7, r5, r7, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #28]
+; CHECK-NEXT: str r7, [r0, #20]
+; CHECK-NEXT: ldrh r7, [sp, #120]
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #88]
+; CHECK-NEXT: str r3, [r0, #16]
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: orr r7, r5, r7, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: pkhbt r6, r6, r12, lsl #16
+; CHECK-NEXT: str r7, [r0, #8]
+; CHECK-NEXT: vmov r7, s13
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: str r3, [r0, #4]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: str r6, [r0, #84]
+; CHECK-NEXT: vmov r6, s11
+; CHECK-NEXT: pkhbt r1, r1, r2, lsl #16
+; CHECK-NEXT: vmov r2, s3
+; CHECK-NEXT: str r1, [r0, #72]
+; CHECK-NEXT: vmov r1, s8
+; CHECK-NEXT: pkhbt r7, r5, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #60]
+; CHECK-NEXT: vmov r7, s10
+; CHECK-NEXT: pkhbt r3, r4, r3, lsl #16
+; CHECK-NEXT: vmov r5, s9
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: str r3, [r0, #48]
+; CHECK-NEXT: pkhbt r2, r2, r6, lsl #16
+; CHECK-NEXT: vmov r6, s0
+; CHECK-NEXT: vmov r3, s1
+; CHECK-NEXT: str r2, [r0, #36]
+; CHECK-NEXT: pkhbt r2, r4, r7, lsl #16
+; CHECK-NEXT: str r2, [r0, #24]
+; CHECK-NEXT: pkhbt r1, r6, r1, lsl #16
+; CHECK-NEXT: pkhbt r2, r3, r5, lsl #16
+; CHECK-NEXT: str r2, [r0, #12]
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <48 x half> @llvm.vector.interleave6(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5)
+ ret <48 x half> %result
+}
+
+define <64 x half> @interleave8_v8f16(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5, <8 x half> %vec6, <8 x half> %vec7) {
+; CHECK-LABEL: interleave8_v8f16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: ldrh r5, [sp, #212]
+; CHECK-NEXT: ldrh r1, [sp, #180]
+; CHECK-NEXT: strh r5, [r0, #126]
+; CHECK-NEXT: strh r1, [r0, #124]
+; CHECK-NEXT: ldrh r2, [sp, #148]
+; CHECK-NEXT: ldrh r3, [sp, #116]
+; CHECK-NEXT: ldrh r12, [sp, #84]
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: ldrh r7, [sp, #208]
+; CHECK-NEXT: ldrh r5, [sp, #176]
+; CHECK-NEXT: ldrh r1, [sp, #144]
+; CHECK-NEXT: strh r2, [r0, #122]
+; CHECK-NEXT: strh r3, [r0, #120]
+; CHECK-NEXT: strh r12, [r0, #118]
+; CHECK-NEXT: strh lr, [r0, #116]
+; CHECK-NEXT: strh r7, [r0, #110]
+; CHECK-NEXT: strh r5, [r0, #108]
+; CHECK-NEXT: strh r1, [r0, #106]
+; CHECK-NEXT: ldrh r2, [sp, #112]
+; CHECK-NEXT: ldrh r3, [sp, #80]
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: ldrh r6, [sp, #204]
+; CHECK-NEXT: ldrh r7, [sp, #172]
+; CHECK-NEXT: ldrh r5, [sp, #140]
+; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: strh r2, [r0, #104]
+; CHECK-NEXT: strh r3, [r0, #102]
+; CHECK-NEXT: strh r4, [r0, #100]
+; CHECK-NEXT: strh r6, [r0, #94]
+; CHECK-NEXT: strh r7, [r0, #92]
+; CHECK-NEXT: strh r5, [r0, #90]
+; CHECK-NEXT: strh r1, [r0, #88]
+; CHECK-NEXT: ldrh r2, [sp, #76]
+; CHECK-NEXT: ldrh r3, [sp, #44]
+; CHECK-NEXT: ldrh r4, [sp, #200]
+; CHECK-NEXT: ldrh r6, [sp, #168]
+; CHECK-NEXT: ldrh r7, [sp, #136]
+; CHECK-NEXT: ldrh r5, [sp, #104]
+; CHECK-NEXT: ldrh r1, [sp, #72]
+; CHECK-NEXT: strh r2, [r0, #86]
+; CHECK-NEXT: strh r3, [r0, #84]
+; CHECK-NEXT: strh r4, [r0, #78]
+; CHECK-NEXT: strh r6, [r0, #76]
+; CHECK-NEXT: strh r7, [r0, #74]
+; CHECK-NEXT: strh r5, [r0, #72]
+; CHECK-NEXT: strh r1, [r0, #70]
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: ldrh r3, [sp, #196]
+; CHECK-NEXT: ldrh r4, [sp, #164]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: ldrh r7, [sp, #100]
+; CHECK-NEXT: ldrh r5, [sp, #68]
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: strh r2, [r0, #68]
+; CHECK-NEXT: strh r3, [r0, #62]
+; CHECK-NEXT: strh r4, [r0, #60]
+; CHECK-NEXT: strh r6, [r0, #58]
+; CHECK-NEXT: strh r7, [r0, #56]
+; CHECK-NEXT: strh r5, [r0, #54]
+; CHECK-NEXT: strh r1, [r0, #52]
+; CHECK-NEXT: ldrh r2, [sp, #192]
+; CHECK-NEXT: ldrh r3, [sp, #160]
+; CHECK-NEXT: ldrh r4, [sp, #128]
+; CHECK-NEXT: ldrh r6, [sp, #96]
+; CHECK-NEXT: ldrh r7, [sp, #64]
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: ldrh r1, [sp, #188]
+; CHECK-NEXT: strh r2, [r0, #46]
+; CHECK-NEXT: strh r3, [r0, #44]
+; CHECK-NEXT: strh r4, [r0, #42]
+; CHECK-NEXT: strh r6, [r0, #40]
+; CHECK-NEXT: strh r7, [r0, #38]
+; CHECK-NEXT: strh r5, [r0, #36]
+; CHECK-NEXT: vmov r5, s15
+; CHECK-NEXT: strh r1, [r0, #30]
+; CHECK-NEXT: vmov r1, s7
+; CHECK-NEXT: ldrh r2, [sp, #156]
+; CHECK-NEXT: strh r2, [r0, #28]
+; CHECK-NEXT: ldrh r3, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r6, [sp, #60]
+; CHECK-NEXT: ldrh r7, [sp, #28]
+; CHECK-NEXT: ldrh r2, [sp, #184]
+; CHECK-NEXT: strh r3, [r0, #26]
+; CHECK-NEXT: strh r4, [r0, #24]
+; CHECK-NEXT: strh r6, [r0, #22]
+; CHECK-NEXT: strh r7, [r0, #20]
+; CHECK-NEXT: strh r2, [r0, #14]
+; CHECK-NEXT: ldrh r2, [sp, #152]
+; CHECK-NEXT: ldrh r3, [sp, #120]
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: ldrh r6, [sp, #56]
+; CHECK-NEXT: ldrh r7, [sp, #24]
+; CHECK-NEXT: strh r2, [r0, #12]
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: strh r3, [r0, #10]
+; CHECK-NEXT: vmov r3, s6
+; CHECK-NEXT: strh r4, [r0, #8]
+; CHECK-NEXT: vmov r4, s13
+; CHECK-NEXT: strh r6, [r0, #6]
+; CHECK-NEXT: vmov r6, s5
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: vmov r7, s12
+; CHECK-NEXT: strh r5, [r0, #114]
+; CHECK-NEXT: vmov r5, s4
+; CHECK-NEXT: strh r1, [r0, #112]
+; CHECK-NEXT: vmov r1, s11
+; CHECK-NEXT: strh r2, [r0, #98]
+; CHECK-NEXT: vmov r2, s3
+; CHECK-NEXT: strh r3, [r0, #96]
+; CHECK-NEXT: vmov r3, s10
+; CHECK-NEXT: strh r4, [r0, #82]
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: strh r6, [r0, #80]
+; CHECK-NEXT: vmov r6, s9
+; CHECK-NEXT: strh r7, [r0, #66]
+; CHECK-NEXT: vmov r7, s1
+; CHECK-NEXT: strh r5, [r0, #64]
+; CHECK-NEXT: vmov r5, s8
+; CHECK-NEXT: strh r1, [r0, #50]
+; CHECK-NEXT: vmov r1, s0
+; CHECK-NEXT: strh r2, [r0, #48]
+; CHECK-NEXT: strh r3, [r0, #34]
+; CHECK-NEXT: strh r4, [r0, #32]
+; CHECK-NEXT: strh r6, [r0, #18]
+; CHECK-NEXT: strh r7, [r0, #16]
+; CHECK-NEXT: strh r5, [r0, #2]
+; CHECK-NEXT: strh r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <64 x half> @llvm.vector.interleave8(<8 x half> %vec0, <8 x half> %vec1, <8 x half> %vec2, <8 x half> %vec3, <8 x half> %vec4, <8 x half> %vec5, <8 x half> %vec6, <8 x half> %vec7)
+ ret <64 x half> %result
+}
+
+define <8 x bfloat> @interleave2_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1) {
+; CHECK-LABEL: interleave2_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmov.f32 s8, s3
+; CHECK-NEXT: vmov.f32 s10, s2
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: vmov.f32 s1, s4
+; CHECK-NEXT: vmov.f32 s3, s5
+; CHECK-NEXT: vmov.f32 s5, s6
+; CHECK-NEXT: vmov.f32 s6, s8
+; CHECK-NEXT: vmov.f32 s4, s10
+; CHECK-NEXT: bx lr
+ %result = call <8 x bfloat> @llvm.vector.interleave2(<4 x bfloat> %vec0, <4 x bfloat> %vec1)
+ ret <8 x bfloat> %result
+}
+
+define <12 x bfloat> @interleave3_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2) {
+; CHECK-LABEL: interleave3_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r0, s1
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: vmov r12, s6
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: vmov lr, s9
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: pkhbt r0, r2, r0, lsl #16
+; CHECK-NEXT: vmov r2, s11
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: vmov r3, s3
+; CHECK-NEXT: vmov d16, r1, r0
+; CHECK-NEXT: pkhbt r1, r4, r12, lsl #16
+; CHECK-NEXT: vmov r0, s10
+; CHECK-NEXT: vmov.u16 r4, d16[0]
+; CHECK-NEXT: pkhbt r5, r5, lr, lsl #16
+; CHECK-NEXT: vmov.u16 r7, d16[3]
+; CHECK-NEXT: vmov d17, r5, r1
+; CHECK-NEXT: vmov.u16 r12, d16[1]
+; CHECK-NEXT: vmov.u16 lr, d16[2]
+; CHECK-NEXT: vmov.u16 r5, d17[0]
+; CHECK-NEXT: pkhbt r2, r6, r2, lsl #16
+; CHECK-NEXT: pkhbt r0, r0, r3, lsl #16
+; CHECK-NEXT: vmov.u16 r3, d17[1]
+; CHECK-NEXT: vmov d16, r0, r2
+; CHECK-NEXT: vmov.u16 r0, d17[2]
+; CHECK-NEXT: vmov.u16 r2, d17[3]
+; CHECK-NEXT: vmov s0, r4
+; CHECK-NEXT: vmov.u16 r4, d16[0]
+; CHECK-NEXT: vmov s3, r7
+; CHECK-NEXT: vmov.u16 r6, d16[1]
+; CHECK-NEXT: vmov s1, r12
+; CHECK-NEXT: vmov.u16 r1, d16[2]
+; CHECK-NEXT: vmov s2, lr
+; CHECK-NEXT: vmov.u16 r7, d16[3]
+; CHECK-NEXT: vmov s4, r5
+; CHECK-NEXT: vmov s5, r3
+; CHECK-NEXT: vmov s6, r0
+; CHECK-NEXT: vmov s7, r2
+; CHECK-NEXT: vmov s8, r4
+; CHECK-NEXT: vmov s9, r6
+; CHECK-NEXT: vmov s10, r1
+; CHECK-NEXT: vmov s11, r7
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <12 x bfloat> @llvm.vector.interleave3(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2)
+ ret <12 x bfloat> %result
+}
+
+define <16 x bfloat> @interleave4_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3) {
+; CHECK-LABEL: interleave4_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: vmov r0, s12
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: vmov r4, s15
+; CHECK-NEXT: vmov r6, s11
+; CHECK-NEXT: vmov r12, s6
+; CHECK-NEXT: vmov lr, s2
+; CHECK-NEXT: pkhbt r0, r2, r0, lsl #16
+; CHECK-NEXT: vmov r2, s10
+; CHECK-NEXT: pkhbt r1, r3, r1, lsl #16
+; CHECK-NEXT: vmov r3, s13
+; CHECK-NEXT: vmov d16, r1, r0
+; CHECK-NEXT: vmov r0, s9
+; CHECK-NEXT: pkhbt r6, r6, r4, lsl #16
+; CHECK-NEXT: vmov r1, s1
+; CHECK-NEXT: vmov.u16 r7, d16[1]
+; CHECK-NEXT: vmov r4, s7
+; CHECK-NEXT: pkhbt r8, r2, r5, lsl #16
+; CHECK-NEXT: vmov r2, s5
+; CHECK-NEXT: pkhbt r5, lr, r12, lsl #16
+; CHECK-NEXT: vmov d18, r5, r8
+; CHECK-NEXT: pkhbt r0, r0, r3, lsl #16
+; CHECK-NEXT: vmov r3, s3
+; CHECK-NEXT: vmov s1, r7
+; CHECK-NEXT: vmov.u16 r7, d18[1]
+; CHECK-NEXT: pkhbt r1, r1, r2, lsl #16
+; CHECK-NEXT: vmov.u16 r2, d16[0]
+; CHECK-NEXT: vmov d17, r1, r0
+; CHECK-NEXT: vmov.u16 r0, d16[2]
+; CHECK-NEXT: pkhbt r1, r3, r4, lsl #16
+; CHECK-NEXT: vmov.u16 r3, d16[3]
+; CHECK-NEXT: vmov.u16 r4, d17[0]
+; CHECK-NEXT: vmov d16, r1, r6
+; CHECK-NEXT: vmov.u16 r1, d17[1]
+; CHECK-NEXT: vmov.u16 r6, d17[2]
+; CHECK-NEXT: vmov s9, r7
+; CHECK-NEXT: vmov.u16 r5, d17[3]
+; CHECK-NEXT: vmov s0, r2
+; CHECK-NEXT: vmov.u16 r2, d18[0]
+; CHECK-NEXT: vmov s2, r0
+; CHECK-NEXT: vmov.u16 r0, d18[2]
+; CHECK-NEXT: vmov s3, r3
+; CHECK-NEXT: vmov.u16 r3, d18[3]
+; CHECK-NEXT: vmov s4, r4
+; CHECK-NEXT: vmov.u16 r4, d16[0]
+; CHECK-NEXT: vmov s5, r1
+; CHECK-NEXT: vmov.u16 r1, d16[1]
+; CHECK-NEXT: vmov s6, r6
+; CHECK-NEXT: vmov.u16 r6, d16[2]
+; CHECK-NEXT: vmov s7, r5
+; CHECK-NEXT: vmov.u16 r5, d16[3]
+; CHECK-NEXT: vmov s8, r2
+; CHECK-NEXT: vmov s10, r0
+; CHECK-NEXT: vmov s11, r3
+; CHECK-NEXT: vmov s12, r4
+; CHECK-NEXT: vmov s13, r1
+; CHECK-NEXT: vmov s14, r6
+; CHECK-NEXT: vmov s15, r5
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+ %result = call <16 x bfloat> @llvm.vector.interleave4(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3)
+ ret <16 x bfloat> %result
+}
+
+define <24 x bfloat> @interleave6_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5) {
+; CHECK-LABEL: interleave6_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: vmov r1, s15
+; CHECK-NEXT: ldrh r3, [sp, #52]
+; CHECK-NEXT: vmov r2, s11
+; CHECK-NEXT: ldrh r4, [sp, #36]
+; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: vmov r12, s7
+; CHECK-NEXT: orr r3, r4, r3, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #32]
+; CHECK-NEXT: str r3, [r0, #44]
+; CHECK-NEXT: vmov lr, s3
+; CHECK-NEXT: ldrh r3, [sp, #44]
+; CHECK-NEXT: orr r4, r6, r5, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #28]
+; CHECK-NEXT: vmov r7, s13
+; CHECK-NEXT: str r4, [r0, #32]
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: str r3, [r0, #20]
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: orr r4, r5, r4, lsl #16
+; CHECK-NEXT: vmov r5, s10
+; CHECK-NEXT: str r4, [r0, #8]
+; CHECK-NEXT: vmov r4, s6
+; CHECK-NEXT: pkhbt r1, r2, r1, lsl #16
+; CHECK-NEXT: vmov r2, s2
+; CHECK-NEXT: str r1, [r0, #40]
+; CHECK-NEXT: vmov r1, s9
+; CHECK-NEXT: pkhbt r6, lr, r12, lsl #16
+; CHECK-NEXT: str r6, [r0, #36]
+; CHECK-NEXT: vmov r6, s4
+; CHECK-NEXT: pkhbt r3, r5, r3, lsl #16
+; CHECK-NEXT: str r3, [r0, #28]
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: vmov r5, s12
+; CHECK-NEXT: pkhbt r2, r2, r4, lsl #16
+; CHECK-NEXT: vmov r4, s1
+; CHECK-NEXT: str r2, [r0, #24]
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: pkhbt r1, r1, r7, lsl #16
+; CHECK-NEXT: vmov r7, s0
+; CHECK-NEXT: str r1, [r0, #16]
+; CHECK-NEXT: pkhbt r1, r4, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: pkhbt r1, r2, r5, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r7, r6, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <24 x bfloat> @llvm.vector.interleave6(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5)
+ ret <24 x bfloat> %result
+}
+
+define <32 x bfloat> @interleave8_v4bf16(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5, <4 x bfloat> %vec6, <4 x bfloat> %vec7) {
+; CHECK-LABEL: interleave8_v4bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r6, s15
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: ldrh r3, [sp, #28]
+; CHECK-NEXT: strh r5, [r0, #62]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r2, [r0, #58]
+; CHECK-NEXT: strh r3, [r0, #56]
+; CHECK-NEXT: ldrh r12, [sp, #72]
+; CHECK-NEXT: ldrh lr, [sp, #56]
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: ldrh r1, [sp, #68]
+; CHECK-NEXT: ldrh r2, [sp, #52]
+; CHECK-NEXT: ldrh r3, [sp, #36]
+; CHECK-NEXT: strh r12, [r0, #46]
+; CHECK-NEXT: vmov r12, s11
+; CHECK-NEXT: strh lr, [r0, #44]
+; CHECK-NEXT: vmov lr, s9
+; CHECK-NEXT: strh r4, [r0, #42]
+; CHECK-NEXT: strh r5, [r0, #40]
+; CHECK-NEXT: strh r1, [r0, #30]
+; CHECK-NEXT: strh r2, [r0, #28]
+; CHECK-NEXT: strh r3, [r0, #26]
+; CHECK-NEXT: ldrh r3, [sp, #20]
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r5, [sp, #48]
+; CHECK-NEXT: ldrh r1, [sp, #32]
+; CHECK-NEXT: ldrh r2, [sp, #16]
+; CHECK-NEXT: strh r3, [r0, #24]
+; CHECK-NEXT: vmov r3, s7
+; CHECK-NEXT: strh r4, [r0, #14]
+; CHECK-NEXT: vmov r4, s3
+; CHECK-NEXT: strh r5, [r0, #12]
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: vmov r1, s10
+; CHECK-NEXT: strh r2, [r0, #8]
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: strh r6, [r0, #54]
+; CHECK-NEXT: vmov r6, s2
+; CHECK-NEXT: strh r12, [r0, #52]
+; CHECK-NEXT: vmov r12, s13
+; CHECK-NEXT: strh r3, [r0, #50]
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: strh r4, [r0, #48]
+; CHECK-NEXT: vmov r4, s5
+; CHECK-NEXT: strh r5, [r0, #38]
+; CHECK-NEXT: vmov r5, s1
+; CHECK-NEXT: strh r1, [r0, #36]
+; CHECK-NEXT: vmov r1, s12
+; CHECK-NEXT: strh r2, [r0, #34]
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: strh r6, [r0, #32]
+; CHECK-NEXT: vmov r6, s4
+; CHECK-NEXT: strh r12, [r0, #22]
+; CHECK-NEXT: strh lr, [r0, #20]
+; CHECK-NEXT: strh r4, [r0, #18]
+; CHECK-NEXT: strh r5, [r0, #16]
+; CHECK-NEXT: strh r1, [r0, #6]
+; CHECK-NEXT: strh r2, [r0, #4]
+; CHECK-NEXT: strh r6, [r0, #2]
+; CHECK-NEXT: strh r3, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <32 x bfloat> @llvm.vector.interleave8(<4 x bfloat> %vec0, <4 x bfloat> %vec1, <4 x bfloat> %vec2, <4 x bfloat> %vec3, <4 x bfloat> %vec4, <4 x bfloat> %vec5, <4 x bfloat> %vec6, <4 x bfloat> %vec7)
+ ret <32 x bfloat> %result
+}
+
+define <16 x bfloat> @interleave2_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1) {
+; CHECK-LABEL: interleave2_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: vmov.f32 s16, s7
+; CHECK-NEXT: vmov.f32 s18, s6
+; CHECK-NEXT: vmov.f32 s20, s5
+; CHECK-NEXT: vmov.f32 s22, s4
+; CHECK-NEXT: vmov.f32 s6, s3
+; CHECK-NEXT: vmov.f32 s4, s2
+; CHECK-NEXT: vmov.f32 s2, s1
+; CHECK-NEXT: vmov.f32 s1, s8
+; CHECK-NEXT: vmov.f32 s3, s9
+; CHECK-NEXT: vmov.f32 s5, s10
+; CHECK-NEXT: vmov.f32 s7, s11
+; CHECK-NEXT: vmov.f32 s9, s12
+; CHECK-NEXT: vmov.f32 s11, s13
+; CHECK-NEXT: vmov.f32 s13, s14
+; CHECK-NEXT: vmov.f32 s8, s22
+; CHECK-NEXT: vmov.f32 s10, s20
+; CHECK-NEXT: vmov.f32 s12, s18
+; CHECK-NEXT: vmov.f32 s14, s16
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: bx lr
+ %result = call <16 x bfloat> @llvm.vector.interleave2(<8 x bfloat> %vec0, <8 x bfloat> %vec1)
+ ret <16 x bfloat> %result
+}
+
+define <24 x bfloat> @interleave3_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2) {
+; CHECK-LABEL: interleave3_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r2, s13
+; CHECK-NEXT: ldrh r5, [sp, #36]
+; CHECK-NEXT: vmov r1, s15
+; CHECK-NEXT: ldrh r3, [sp, #44]
+; CHECK-NEXT: vmov r12, s9
+; CHECK-NEXT: ldrh r4, [sp, #20]
+; CHECK-NEXT: vmov lr, s11
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: pkhbt r2, r2, r5, lsl #16
+; CHECK-NEXT: vmov r5, s14
+; CHECK-NEXT: pkhbt r1, r1, r3, lsl #16
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: str r2, [r0, #32]
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: vmov r3, s5
+; CHECK-NEXT: ldrh r1, [sp, #28]
+; CHECK-NEXT: pkhbt r4, r12, r4, lsl #16
+; CHECK-NEXT: vmov r12, s1
+; CHECK-NEXT: pkhbt r1, lr, r1, lsl #16
+; CHECK-NEXT: str r1, [r0, #20]
+; CHECK-NEXT: str r4, [r0, #8]
+; CHECK-NEXT: vmov lr, s12
+; CHECK-NEXT: ldrh r4, [sp, #40]
+; CHECK-NEXT: vmov r1, s4
+; CHECK-NEXT: orr r6, r4, r6, lsl #16
+; CHECK-NEXT: ldrh r4, [sp, #32]
+; CHECK-NEXT: str r6, [r0, #40]
+; CHECK-NEXT: vmov r6, s3
+; CHECK-NEXT: pkhbt r2, r2, r5, lsl #16
+; CHECK-NEXT: str r2, [r0, #36]
+; CHECK-NEXT: vmov r2, s10
+; CHECK-NEXT: orr r3, r4, r3, lsl #16
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: str r3, [r0, #28]
+; CHECK-NEXT: vmov r3, s8
+; CHECK-NEXT: vmov r5, s0
+; CHECK-NEXT: pkhbt r1, r1, lr, lsl #16
+; CHECK-NEXT: str r1, [r0, #24]
+; CHECK-NEXT: ldrh r1, [sp, #24]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r6, [sp, #16]
+; CHECK-NEXT: str r1, [r0, #16]
+; CHECK-NEXT: pkhbt r1, r4, r2, lsl #16
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: orr r1, r6, r12, lsl #16
+; CHECK-NEXT: str r1, [r0, #4]
+; CHECK-NEXT: pkhbt r1, r5, r3, lsl #16
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <24 x bfloat> @llvm.vector.interleave3(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2)
+ ret <24 x bfloat> %result
+}
+
+define <32 x bfloat> @interleave4_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3) {
+; CHECK-LABEL: interleave4_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: vmov r6, s15
+; CHECK-NEXT: ldrh r5, [sp, #76]
+; CHECK-NEXT: ldrh r1, [sp, #44]
+; CHECK-NEXT: ldrh r2, [sp, #72]
+; CHECK-NEXT: ldrh r3, [sp, #40]
+; CHECK-NEXT: strh r5, [r0, #62]
+; CHECK-NEXT: strh r1, [r0, #60]
+; CHECK-NEXT: strh r2, [r0, #54]
+; CHECK-NEXT: strh r3, [r0, #52]
+; CHECK-NEXT: ldrh r12, [sp, #68]
+; CHECK-NEXT: ldrh lr, [sp, #36]
+; CHECK-NEXT: ldrh r4, [sp, #64]
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: ldrh r1, [sp, #60]
+; CHECK-NEXT: ldrh r2, [sp, #28]
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: strh r12, [r0, #46]
+; CHECK-NEXT: vmov r12, s7
+; CHECK-NEXT: strh lr, [r0, #44]
+; CHECK-NEXT: vmov lr, s3
+; CHECK-NEXT: strh r4, [r0, #38]
+; CHECK-NEXT: strh r5, [r0, #36]
+; CHECK-NEXT: strh r1, [r0, #30]
+; CHECK-NEXT: strh r2, [r0, #28]
+; CHECK-NEXT: strh r3, [r0, #22]
+; CHECK-NEXT: ldrh r3, [sp, #24]
+; CHECK-NEXT: ldrh r4, [sp, #52]
+; CHECK-NEXT: ldrh r5, [sp, #20]
+; CHECK-NEXT: ldrh r1, [sp, #48]
+; CHECK-NEXT: ldrh r2, [sp, #16]
+; CHECK-NEXT: strh r3, [r0, #20]
+; CHECK-NEXT: vmov r3, s14
+; CHECK-NEXT: strh r4, [r0, #14]
+; CHECK-NEXT: vmov r4, s6
+; CHECK-NEXT: strh r5, [r0, #12]
+; CHECK-NEXT: vmov r5, s13
+; CHECK-NEXT: strh r1, [r0, #6]
+; CHECK-NEXT: vmov r1, s5
+; CHECK-NEXT: strh r2, [r0, #4]
+; CHECK-NEXT: vmov r2, s12
+; CHECK-NEXT: strh r6, [r0, #58]
+; CHECK-NEXT: vmov r6, s4
+; CHECK-NEXT: strh r12, [r0, #56]
+; CHECK-NEXT: vmov r12, s11
+; CHECK-NEXT: strh r3, [r0, #50]
+; CHECK-NEXT: vmov r3, s0
+; CHECK-NEXT: strh r4, [r0, #48]
+; CHECK-NEXT: vmov r4, s10
+; CHECK-NEXT: strh r5, [r0, #42]
+; CHECK-NEXT: vmov r5, s2
+; CHECK-NEXT: strh r1, [r0, #40]
+; CHECK-NEXT: vmov r1, s9
+; CHECK-NEXT: strh r2, [r0, #34]
+; CHECK-NEXT: vmov r2, s1
+; CHECK-NEXT: strh r6, [r0, #32]
+; CHECK-NEXT: vmov r6, s8
+; CHECK-NEXT: strh r12, [r0, #26]
+; CHECK-NEXT: strh lr, [r0, #24]
+; CHECK-NEXT: strh r4, [r0, #18]
+; CHECK-NEXT: strh r5, [r0, #16]
+; CHECK-NEXT: strh r1, [r0, #10]
+; CHECK-NEXT: strh r2, [r0, #8]
+; CHECK-NEXT: strh r6, [r0, #2]
+; CHECK-NEXT: strh r3, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, pc}
+ %result = call <32 x bfloat> @llvm.vector.interleave4(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3)
+ ret <32 x bfloat> %result
+}
+
+
+define <48 x bfloat> @interleave6_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5) {
+; CHECK-LABEL: interleave6_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: ldrh r1, [sp, #148]
+; CHECK-NEXT: ldrh r2, [sp, #116]
+; CHECK-NEXT: ldrh r5, [sp, #84]
+; CHECK-NEXT: ldrh r6, [sp, #52]
+; CHECK-NEXT: orr r1, r2, r1, lsl #16
+; CHECK-NEXT: ldrh r3, [sp, #144]
+; CHECK-NEXT: orr r2, r6, r5, lsl #16
+; CHECK-NEXT: str r1, [r0, #92]
+; CHECK-NEXT: ldrh r1, [sp, #112]
+; CHECK-NEXT: ldrh r12, [sp, #80]
+; CHECK-NEXT: str r2, [r0, #88]
+; CHECK-NEXT: orr r1, r1, r3, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #48]
+; CHECK-NEXT: ldrh lr, [sp, #140]
+; CHECK-NEXT: str r1, [r0, #80]
+; CHECK-NEXT: orr r2, r2, r12, lsl #16
+; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: vmov r12, s15
+; CHECK-NEXT: ldrh r7, [sp, #76]
+; CHECK-NEXT: str r2, [r0, #76]
+; CHECK-NEXT: orr r1, r1, lr, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #44]
+; CHECK-NEXT: ldrh r5, [sp, #136]
+; CHECK-NEXT: str r1, [r0, #68]
+; CHECK-NEXT: orr r2, r2, r7, lsl #16
+; CHECK-NEXT: ldrh r1, [sp, #104]
+; CHECK-NEXT: ldrh r3, [sp, #72]
+; CHECK-NEXT: str r2, [r0, #64]
+; CHECK-NEXT: orr r1, r1, r5, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: str r1, [r0, #56]
+; CHECK-NEXT: orr r2, r2, r3, lsl #16
+; CHECK-NEXT: ldrh r1, [sp, #100]
+; CHECK-NEXT: ldrh r4, [sp, #68]
+; CHECK-NEXT: str r2, [r0, #52]
+; CHECK-NEXT: orr r1, r1, r6, lsl #16
+; CHECK-NEXT: ldrh r2, [sp, #36]
+; CHECK-NEXT: vmov r6, s7
+; CHECK-NEXT: str r1, [r0, #44]
+; CHECK-NEXT: orr r1, r2, r4, lsl #16
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: str r1, [r0, #40]
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: ldrh r7, [sp, #128]
+; CHECK-NEXT: vmov r4, s4
+; CHECK-NEXT: ldrh r5, [sp, #96]
+; CHECK-NEXT: ldrh r3, [sp, #64]
+; CHECK-NEXT: orr r7, r5, r7, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: str r7, [r0, #32]
+; CHECK-NEXT: ldrh r7, [sp, #124]
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #92]
+; CHECK-NEXT: str r3, [r0, #28]
+; CHECK-NEXT: ldrh r3, [sp, #60]
+; CHECK-NEXT: orr r7, r5, r7, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #28]
+; CHECK-NEXT: str r7, [r0, #20]
+; CHECK-NEXT: ldrh r7, [sp, #120]
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #88]
+; CHECK-NEXT: str r3, [r0, #16]
+; CHECK-NEXT: ldrh r3, [sp, #56]
+; CHECK-NEXT: orr r7, r5, r7, lsl #16
+; CHECK-NEXT: ldrh r5, [sp, #24]
+; CHECK-NEXT: pkhbt r6, r6, r12, lsl #16
+; CHECK-NEXT: str r7, [r0, #8]
+; CHECK-NEXT: vmov r7, s13
+; CHECK-NEXT: orr r3, r5, r3, lsl #16
+; CHECK-NEXT: vmov r5, s5
+; CHECK-NEXT: str r3, [r0, #4]
+; CHECK-NEXT: vmov r3, s12
+; CHECK-NEXT: str r6, [r0, #84]
+; CHECK-NEXT: vmov r6, s11
+; CHECK-NEXT: pkhbt r1, r1, r2, lsl #16
+; CHECK-NEXT: vmov r2, s3
+; CHECK-NEXT: str r1, [r0, #72]
+; CHECK-NEXT: vmov r1, s8
+; CHECK-NEXT: pkhbt r7, r5, r7, lsl #16
+; CHECK-NEXT: str r7, [r0, #60]
+; CHECK-NEXT: vmov r7, s10
+; CHECK-NEXT: pkhbt r3, r4, r3, lsl #16
+; CHECK-NEXT: vmov r5, s9
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: str r3, [r0, #48]
+; CHECK-NEXT: pkhbt r2, r2, r6, lsl #16
+; CHECK-NEXT: vmov r6, s0
+; CHECK-NEXT: vmov r3, s1
+; CHECK-NEXT: str r2, [r0, #36]
+; CHECK-NEXT: pkhbt r2, r4, r7, lsl #16
+; CHECK-NEXT: str r2, [r0, #24]
+; CHECK-NEXT: pkhbt r1, r6, r1, lsl #16
+; CHECK-NEXT: pkhbt r2, r3, r5, lsl #16
+; CHECK-NEXT: str r2, [r0, #12]
+; CHECK-NEXT: str r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <48 x bfloat> @llvm.vector.interleave6(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5)
+ ret <48 x bfloat> %result
+}
+
+define <64 x bfloat> @interleave8_v8bf16(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5, <8 x bfloat> %vec6, <8 x bfloat> %vec7) {
+; CHECK-LABEL: interleave8_v8bf16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: ldrh r5, [sp, #212]
+; CHECK-NEXT: ldrh r1, [sp, #180]
+; CHECK-NEXT: strh r5, [r0, #126]
+; CHECK-NEXT: strh r1, [r0, #124]
+; CHECK-NEXT: ldrh r2, [sp, #148]
+; CHECK-NEXT: ldrh r3, [sp, #116]
+; CHECK-NEXT: ldrh r12, [sp, #84]
+; CHECK-NEXT: ldrh lr, [sp, #52]
+; CHECK-NEXT: ldrh r7, [sp, #208]
+; CHECK-NEXT: ldrh r5, [sp, #176]
+; CHECK-NEXT: ldrh r1, [sp, #144]
+; CHECK-NEXT: strh r2, [r0, #122]
+; CHECK-NEXT: strh r3, [r0, #120]
+; CHECK-NEXT: strh r12, [r0, #118]
+; CHECK-NEXT: strh lr, [r0, #116]
+; CHECK-NEXT: strh r7, [r0, #110]
+; CHECK-NEXT: strh r5, [r0, #108]
+; CHECK-NEXT: strh r1, [r0, #106]
+; CHECK-NEXT: ldrh r2, [sp, #112]
+; CHECK-NEXT: ldrh r3, [sp, #80]
+; CHECK-NEXT: ldrh r4, [sp, #48]
+; CHECK-NEXT: ldrh r6, [sp, #204]
+; CHECK-NEXT: ldrh r7, [sp, #172]
+; CHECK-NEXT: ldrh r5, [sp, #140]
+; CHECK-NEXT: ldrh r1, [sp, #108]
+; CHECK-NEXT: strh r2, [r0, #104]
+; CHECK-NEXT: strh r3, [r0, #102]
+; CHECK-NEXT: strh r4, [r0, #100]
+; CHECK-NEXT: strh r6, [r0, #94]
+; CHECK-NEXT: strh r7, [r0, #92]
+; CHECK-NEXT: strh r5, [r0, #90]
+; CHECK-NEXT: strh r1, [r0, #88]
+; CHECK-NEXT: ldrh r2, [sp, #76]
+; CHECK-NEXT: ldrh r3, [sp, #44]
+; CHECK-NEXT: ldrh r4, [sp, #200]
+; CHECK-NEXT: ldrh r6, [sp, #168]
+; CHECK-NEXT: ldrh r7, [sp, #136]
+; CHECK-NEXT: ldrh r5, [sp, #104]
+; CHECK-NEXT: ldrh r1, [sp, #72]
+; CHECK-NEXT: strh r2, [r0, #86]
+; CHECK-NEXT: strh r3, [r0, #84]
+; CHECK-NEXT: strh r4, [r0, #78]
+; CHECK-NEXT: strh r6, [r0, #76]
+; CHECK-NEXT: strh r7, [r0, #74]
+; CHECK-NEXT: strh r5, [r0, #72]
+; CHECK-NEXT: strh r1, [r0, #70]
+; CHECK-NEXT: ldrh r2, [sp, #40]
+; CHECK-NEXT: ldrh r3, [sp, #196]
+; CHECK-NEXT: ldrh r4, [sp, #164]
+; CHECK-NEXT: ldrh r6, [sp, #132]
+; CHECK-NEXT: ldrh r7, [sp, #100]
+; CHECK-NEXT: ldrh r5, [sp, #68]
+; CHECK-NEXT: ldrh r1, [sp, #36]
+; CHECK-NEXT: strh r2, [r0, #68]
+; CHECK-NEXT: strh r3, [r0, #62]
+; CHECK-NEXT: strh r4, [r0, #60]
+; CHECK-NEXT: strh r6, [r0, #58]
+; CHECK-NEXT: strh r7, [r0, #56]
+; CHECK-NEXT: strh r5, [r0, #54]
+; CHECK-NEXT: strh r1, [r0, #52]
+; CHECK-NEXT: ldrh r2, [sp, #192]
+; CHECK-NEXT: ldrh r3, [sp, #160]
+; CHECK-NEXT: ldrh r4, [sp, #128]
+; CHECK-NEXT: ldrh r6, [sp, #96]
+; CHECK-NEXT: ldrh r7, [sp, #64]
+; CHECK-NEXT: ldrh r5, [sp, #32]
+; CHECK-NEXT: ldrh r1, [sp, #188]
+; CHECK-NEXT: strh r2, [r0, #46]
+; CHECK-NEXT: strh r3, [r0, #44]
+; CHECK-NEXT: strh r4, [r0, #42]
+; CHECK-NEXT: strh r6, [r0, #40]
+; CHECK-NEXT: strh r7, [r0, #38]
+; CHECK-NEXT: strh r5, [r0, #36]
+; CHECK-NEXT: vmov r5, s15
+; CHECK-NEXT: strh r1, [r0, #30]
+; CHECK-NEXT: vmov r1, s7
+; CHECK-NEXT: ldrh r2, [sp, #156]
+; CHECK-NEXT: strh r2, [r0, #28]
+; CHECK-NEXT: ldrh r3, [sp, #124]
+; CHECK-NEXT: ldrh r4, [sp, #92]
+; CHECK-NEXT: ldrh r6, [sp, #60]
+; CHECK-NEXT: ldrh r7, [sp, #28]
+; CHECK-NEXT: ldrh r2, [sp, #184]
+; CHECK-NEXT: strh r3, [r0, #26]
+; CHECK-NEXT: strh r4, [r0, #24]
+; CHECK-NEXT: strh r6, [r0, #22]
+; CHECK-NEXT: strh r7, [r0, #20]
+; CHECK-NEXT: strh r2, [r0, #14]
+; CHECK-NEXT: ldrh r2, [sp, #152]
+; CHECK-NEXT: ldrh r3, [sp, #120]
+; CHECK-NEXT: ldrh r4, [sp, #88]
+; CHECK-NEXT: ldrh r6, [sp, #56]
+; CHECK-NEXT: ldrh r7, [sp, #24]
+; CHECK-NEXT: strh r2, [r0, #12]
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: strh r3, [r0, #10]
+; CHECK-NEXT: vmov r3, s6
+; CHECK-NEXT: strh r4, [r0, #8]
+; CHECK-NEXT: vmov r4, s13
+; CHECK-NEXT: strh r6, [r0, #6]
+; CHECK-NEXT: vmov r6, s5
+; CHECK-NEXT: strh r7, [r0, #4]
+; CHECK-NEXT: vmov r7, s12
+; CHECK-NEXT: strh r5, [r0, #114]
+; CHECK-NEXT: vmov r5, s4
+; CHECK-NEXT: strh r1, [r0, #112]
+; CHECK-NEXT: vmov r1, s11
+; CHECK-NEXT: strh r2, [r0, #98]
+; CHECK-NEXT: vmov r2, s3
+; CHECK-NEXT: strh r3, [r0, #96]
+; CHECK-NEXT: vmov r3, s10
+; CHECK-NEXT: strh r4, [r0, #82]
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: strh r6, [r0, #80]
+; CHECK-NEXT: vmov r6, s9
+; CHECK-NEXT: strh r7, [r0, #66]
+; CHECK-NEXT: vmov r7, s1
+; CHECK-NEXT: strh r5, [r0, #64]
+; CHECK-NEXT: vmov r5, s8
+; CHECK-NEXT: strh r1, [r0, #50]
+; CHECK-NEXT: vmov r1, s0
+; CHECK-NEXT: strh r2, [r0, #48]
+; CHECK-NEXT: strh r3, [r0, #34]
+; CHECK-NEXT: strh r4, [r0, #32]
+; CHECK-NEXT: strh r6, [r0, #18]
+; CHECK-NEXT: strh r7, [r0, #16]
+; CHECK-NEXT: strh r5, [r0, #2]
+; CHECK-NEXT: strh r1, [r0]
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
+ %result = call <64 x bfloat> @llvm.vector.interleave8(<8 x bfloat> %vec0, <8 x bfloat> %vec1, <8 x bfloat> %vec2, <8 x bfloat> %vec3, <8 x bfloat> %vec4, <8 x bfloat> %vec5, <8 x bfloat> %vec6, <8 x bfloat> %vec7)
+ ret <64 x bfloat> %result
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-IADISABLED: {{.*}}
+; CHECK-IAENABLED: {{.*}}
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