[llvm] [AArch64] Fix register offset ld/st predicate (PR #225645)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 05:46:20 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Tomer Shafir (tomershafir)
<details>
<summary>Changes</summary>
The previous extension check was wrong - `CheckMemExtLSL` would always return false because it used stale memory extend type checker: `getMemExtendType`, passing a sign bit that is shifted and masked unsoundly. This patch accurately returns true for:
- W sized offset, which requires an extension by the ISA
- Shifted X sized offset
Note that UXTX and SXTX are effectively a no-op in this case so we effectively reject those.
I plan to remove stale `CheckMemExtLSL` and siblings in a followup.
---
Patch is 162.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225645.diff
5 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64SchedPredicates.td (+43-38)
- (modified) llvm/test/tools/llvm-mca/AArch64/Apple/Cyclone-register-offset.s (+630-15)
- (modified) llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s (+61-61)
- (added) llvm/test/tools/llvm-mca/AArch64/Apple/M1-register-offset.s (+644)
- (modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s (+5-5)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index cbaaafccd164d..b2fc95a64846b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -197,38 +197,41 @@ def IsStoreASIMDPostOp : CheckOpcode<[ST1Onev8b_POST, ST1Onev4h_POST, ST1One
def IsLoadStoreASIMDPostOp : CheckOpcode<!listconcat(IsLoadASIMDPostOp.ValidOpcodes,
IsStoreASIMDPostOp.ValidOpcodes)>;
-// Identify whether an instruction is a load
-// using the register offset addressing mode.
-def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX,
- LDRBBroW, LDRBBroX,
- LDRSBWroW, LDRSBWroX, LDRSBXroW, LDRSBXroX,
- LDRHHroW, LDRHHroX,
- LDRSHWroW, LDRSHWroX, LDRSHXroW, LDRSHXroX,
- LDRWroW, LDRWroX,
- LDRSWroW, LDRSWroX,
- LDRXroW, LDRXroX,
- LDRBroW, LDRBroX,
- LDRHroW, LDRHroX,
- LDRSroW, LDRSroX,
- LDRDroW, LDRDroX,
- LDRQroW, LDRQroX]>;
-
-// Identify whether an instruction is a store
-// using the register offset addressing mode.
-def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX,
- STRHHroW, STRHHroX,
- STRWroW, STRWroX,
- STRXroW, STRXroX,
- STRBroW, STRBroX,
- STRHroW, STRHroX,
- STRSroW, STRSroX,
- STRDroW, STRDroX,
- STRQroW, STRQroX]>;
-
-// Identify whether an instruction is a load or
-// store using the register offset addressing mode.
-def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetOp.ValidOpcodes,
- IsStoreRegOffsetOp.ValidOpcodes)>;
+// Identify whether an instruction is a load using the register offset
+// addressing mode.
+
+def IsLoadRegOffsetWOp : CheckOpcode<[PRFMroW,
+ LDRBBroW, LDRSBWroW, LDRSBXroW,
+ LDRHHroW, LDRSHWroW, LDRSHXroW,
+ LDRWroW, LDRSWroW, LDRXroW,
+ LDRBroW, LDRHroW, LDRSroW,
+ LDRDroW, LDRQroW]>;
+def IsLoadRegOffsetXOp : CheckOpcode<[PRFMroX,
+ LDRBBroX, LDRSBWroX, LDRSBXroX,
+ LDRHHroX, LDRSHWroX, LDRSHXroX,
+ LDRWroX, LDRSWroX, LDRXroX,
+ LDRBroX, LDRHroX, LDRSroX,
+ LDRDroX, LDRQroX]>;
+def IsLoadRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetWOp.ValidOpcodes,
+ IsLoadRegOffsetXOp.ValidOpcodes)>;
+
+def IsStoreRegOffsetWOp : CheckOpcode<[STRBBroW, STRHHroW,
+ STRWroW, STRXroW,
+ STRBroW, STRHroW, STRSroW,
+ STRDroW, STRQroW]>;
+def IsStoreRegOffsetXOp : CheckOpcode<[STRBBroX, STRHHroX,
+ STRWroX, STRXroX,
+ STRBroX, STRHroX, STRSroX,
+ STRDroX, STRQroX]>;
+def IsStoreRegOffsetOp : CheckOpcode<!listconcat(IsStoreRegOffsetWOp.ValidOpcodes,
+ IsStoreRegOffsetXOp.ValidOpcodes)>;
+
+def IsLoadStoreRegOffsetWOp : CheckOpcode<!listconcat(IsLoadRegOffsetWOp.ValidOpcodes,
+ IsStoreRegOffsetWOp.ValidOpcodes)>;
+def IsLoadStoreRegOffsetXOp : CheckOpcode<!listconcat(IsLoadRegOffsetXOp.ValidOpcodes,
+ IsStoreRegOffsetXOp.ValidOpcodes)>;
+def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadStoreRegOffsetWOp.ValidOpcodes,
+ IsLoadStoreRegOffsetXOp.ValidOpcodes)>;
// Target predicates.
@@ -258,15 +261,17 @@ def RegShiftedFn : TIIPredicate<"hasShiftedReg",
MCReturnStatement<FalsePred>>>;
def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
-// Identify a load or store using the register offset addressing mode
-// with an extended or scaled register.
+// Identify a load or store using the register offset addressing mode where the
+// index requires extension or scaling. The W forms always extend Wm to 64 bits;
+// the X forms use uxtx/sxtx, which are no-ops, so only the scaling bit matters.
def ScaledIdxFn : TIIPredicate<"isScaledAddr",
MCOpcodeSwitchStatement<
[MCOpcodeSwitchCase<
- IsLoadStoreRegOffsetOp.ValidOpcodes,
- MCReturnStatement<
- CheckAny<[CheckNot<CheckMemExtLSL>,
- CheckMemScaled]>>>],
+ IsLoadStoreRegOffsetWOp.ValidOpcodes,
+ MCReturnStatement<TruePred>>,
+ MCOpcodeSwitchCase<
+ IsLoadStoreRegOffsetXOp.ValidOpcodes,
+ MCReturnStatement<CheckMemScaled>>],
MCReturnStatement<FalsePred>>>;
def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/Cyclone-register-offset.s b/llvm/test/tools/llvm-mca/AArch64/Apple/Cyclone-register-offset.s
index 37ad0b2bba135..c8064ecf22f0a 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Apple/Cyclone-register-offset.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Apple/Cyclone-register-offset.s
@@ -1,19 +1,221 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -march=aarch64 -mcpu=cyclone -resource-pressure=false < %s | FileCheck %s
+# RUN: llvm-mca -march=aarch64 -mcpu=cyclone -instruction-tables < %s | FileCheck %s
- ldr x7, [x1, #8]
- ldr x6, [x1, x2]
- ldr x4, [x1, x2, sxtx]
+ prfm pldl1keep, [x1, x2]
+ prfm pldl1keep, [x1, x2, lsl #3]
+ prfm pldl1keep, [x1, x2, sxtx]
+ prfm pldl1keep, [x1, x2, sxtx #3]
+ prfm pldl1keep, [x1, w2, uxtw]
+ prfm pldl1keep, [x1, w2, uxtw #3]
+ prfm pldl1keep, [x1, w2, sxtw]
+ prfm pldl1keep, [x1, w2, sxtw #3]
-# CHECK: Iterations: 100
-# CHECK-NEXT: Instructions: 300
-# CHECK-NEXT: Total Cycles: 157
-# CHECK-NEXT: Total uOps: 500
+ ldrb w0, [x1, x2]
+ ldrb w0, [x1, x2, lsl #0]
+ ldrb w0, [x1, x2, sxtx]
+ ldrb w0, [x1, x2, sxtx #0]
+ ldrb w0, [x1, w2, uxtw]
+ ldrb w0, [x1, w2, uxtw #0]
+ ldrb w0, [x1, w2, sxtw]
+ ldrb w0, [x1, w2, sxtw #0]
-# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 3.18
-# CHECK-NEXT: IPC: 1.91
-# CHECK-NEXT: Block RThroughput: 1.5
+ ldrsb w0, [x1, x2]
+ ldrsb w0, [x1, x2, lsl #0]
+ ldrsb w0, [x1, x2, sxtx]
+ ldrsb w0, [x1, x2, sxtx #0]
+ ldrsb w0, [x1, w2, uxtw]
+ ldrsb w0, [x1, w2, uxtw #0]
+ ldrsb w0, [x1, w2, sxtw]
+ ldrsb w0, [x1, w2, sxtw #0]
+
+ ldrsb x0, [x1, x2]
+ ldrsb x0, [x1, x2, lsl #0]
+ ldrsb x0, [x1, x2, sxtx]
+ ldrsb x0, [x1, x2, sxtx #0]
+ ldrsb x0, [x1, w2, uxtw]
+ ldrsb x0, [x1, w2, uxtw #0]
+ ldrsb x0, [x1, w2, sxtw]
+ ldrsb x0, [x1, w2, sxtw #0]
+
+ ldrh w0, [x1, x2]
+ ldrh w0, [x1, x2, lsl #1]
+ ldrh w0, [x1, x2, sxtx]
+ ldrh w0, [x1, x2, sxtx #1]
+ ldrh w0, [x1, w2, uxtw]
+ ldrh w0, [x1, w2, uxtw #1]
+ ldrh w0, [x1, w2, sxtw]
+ ldrh w0, [x1, w2, sxtw #1]
+
+ ldrsh w0, [x1, x2]
+ ldrsh w0, [x1, x2, lsl #1]
+ ldrsh w0, [x1, x2, sxtx]
+ ldrsh w0, [x1, x2, sxtx #1]
+ ldrsh w0, [x1, w2, uxtw]
+ ldrsh w0, [x1, w2, uxtw #1]
+ ldrsh w0, [x1, w2, sxtw]
+ ldrsh w0, [x1, w2, sxtw #1]
+
+ ldrsh x0, [x1, x2]
+ ldrsh x0, [x1, x2, lsl #1]
+ ldrsh x0, [x1, x2, sxtx]
+ ldrsh x0, [x1, x2, sxtx #1]
+ ldrsh x0, [x1, w2, uxtw]
+ ldrsh x0, [x1, w2, uxtw #1]
+ ldrsh x0, [x1, w2, sxtw]
+ ldrsh x0, [x1, w2, sxtw #1]
+
+ ldr w0, [x1, x2]
+ ldr w0, [x1, x2, lsl #2]
+ ldr w0, [x1, x2, sxtx]
+ ldr w0, [x1, x2, sxtx #2]
+ ldr w0, [x1, w2, uxtw]
+ ldr w0, [x1, w2, uxtw #2]
+ ldr w0, [x1, w2, sxtw]
+ ldr w0, [x1, w2, sxtw #2]
+
+ ldrsw x0, [x1, x2]
+ ldrsw x0, [x1, x2, lsl #2]
+ ldrsw x0, [x1, x2, sxtx]
+ ldrsw x0, [x1, x2, sxtx #2]
+ ldrsw x0, [x1, w2, uxtw]
+ ldrsw x0, [x1, w2, uxtw #2]
+ ldrsw x0, [x1, w2, sxtw]
+ ldrsw x0, [x1, w2, sxtw #2]
+
+ ldr x0, [x1, x2]
+ ldr x0, [x1, x2, lsl #3]
+ ldr x0, [x1, x2, sxtx]
+ ldr x0, [x1, x2, sxtx #3]
+ ldr x0, [x1, w2, uxtw]
+ ldr x0, [x1, w2, uxtw #3]
+ ldr x0, [x1, w2, sxtw]
+ ldr x0, [x1, w2, sxtw #3]
+
+ ldr b0, [x1, x2]
+ ldr b0, [x1, x2, lsl #0]
+ ldr b0, [x1, x2, sxtx]
+ ldr b0, [x1, x2, sxtx #0]
+ ldr b0, [x1, w2, uxtw]
+ ldr b0, [x1, w2, uxtw #0]
+ ldr b0, [x1, w2, sxtw]
+ ldr b0, [x1, w2, sxtw #0]
+
+ ldr h0, [x1, x2]
+ ldr h0, [x1, x2, lsl #1]
+ ldr h0, [x1, x2, sxtx]
+ ldr h0, [x1, x2, sxtx #1]
+ ldr h0, [x1, w2, uxtw]
+ ldr h0, [x1, w2, uxtw #1]
+ ldr h0, [x1, w2, sxtw]
+ ldr h0, [x1, w2, sxtw #1]
+
+ ldr s0, [x1, x2]
+ ldr s0, [x1, x2, lsl #2]
+ ldr s0, [x1, x2, sxtx]
+ ldr s0, [x1, x2, sxtx #2]
+ ldr s0, [x1, w2, uxtw]
+ ldr s0, [x1, w2, uxtw #2]
+ ldr s0, [x1, w2, sxtw]
+ ldr s0, [x1, w2, sxtw #2]
+
+ ldr d0, [x1, x2]
+ ldr d0, [x1, x2, lsl #3]
+ ldr d0, [x1, x2, sxtx]
+ ldr d0, [x1, x2, sxtx #3]
+ ldr d0, [x1, w2, uxtw]
+ ldr d0, [x1, w2, uxtw #3]
+ ldr d0, [x1, w2, sxtw]
+ ldr d0, [x1, w2, sxtw #3]
+
+ ldr q0, [x1, x2]
+ ldr q0, [x1, x2, lsl #4]
+ ldr q0, [x1, x2, sxtx]
+ ldr q0, [x1, x2, sxtx #4]
+ ldr q0, [x1, w2, uxtw]
+ ldr q0, [x1, w2, uxtw #4]
+ ldr q0, [x1, w2, sxtw]
+ ldr q0, [x1, w2, sxtw #4]
+
+ strb w0, [x1, x2]
+ strb w0, [x1, x2, lsl #0]
+ strb w0, [x1, x2, sxtx]
+ strb w0, [x1, x2, sxtx #0]
+ strb w0, [x1, w2, uxtw]
+ strb w0, [x1, w2, uxtw #0]
+ strb w0, [x1, w2, sxtw]
+ strb w0, [x1, w2, sxtw #0]
+
+ strh w0, [x1, x2]
+ strh w0, [x1, x2, lsl #1]
+ strh w0, [x1, x2, sxtx]
+ strh w0, [x1, x2, sxtx #1]
+ strh w0, [x1, w2, uxtw]
+ strh w0, [x1, w2, uxtw #1]
+ strh w0, [x1, w2, sxtw]
+ strh w0, [x1, w2, sxtw #1]
+
+ str w0, [x1, x2]
+ str w0, [x1, x2, lsl #2]
+ str w0, [x1, x2, sxtx]
+ str w0, [x1, x2, sxtx #2]
+ str w0, [x1, w2, uxtw]
+ str w0, [x1, w2, uxtw #2]
+ str w0, [x1, w2, sxtw]
+ str w0, [x1, w2, sxtw #2]
+
+ str x0, [x1, x2]
+ str x0, [x1, x2, lsl #3]
+ str x0, [x1, x2, sxtx]
+ str x0, [x1, x2, sxtx #3]
+ str x0, [x1, w2, uxtw]
+ str x0, [x1, w2, uxtw #3]
+ str x0, [x1, w2, sxtw]
+ str x0, [x1, w2, sxtw #3]
+
+ str b0, [x1, x2]
+ str b0, [x1, x2, lsl #0]
+ str b0, [x1, x2, sxtx]
+ str b0, [x1, x2, sxtx #0]
+ str b0, [x1, w2, uxtw]
+ str b0, [x1, w2, uxtw #0]
+ str b0, [x1, w2, sxtw]
+ str b0, [x1, w2, sxtw #0]
+
+ str h0, [x1, x2]
+ str h0, [x1, x2, lsl #1]
+ str h0, [x1, x2, sxtx]
+ str h0, [x1, x2, sxtx #1]
+ str h0, [x1, w2, uxtw]
+ str h0, [x1, w2, uxtw #1]
+ str h0, [x1, w2, sxtw]
+ str h0, [x1, w2, sxtw #1]
+
+ str s0, [x1, x2]
+ str s0, [x1, x2, lsl #2]
+ str s0, [x1, x2, sxtx]
+ str s0, [x1, x2, sxtx #2]
+ str s0, [x1, w2, uxtw]
+ str s0, [x1, w2, uxtw #2]
+ str s0, [x1, w2, sxtw]
+ str s0, [x1, w2, sxtw #2]
+
+ str d0, [x1, x2]
+ str d0, [x1, x2, lsl #3]
+ str d0, [x1, x2, sxtx]
+ str d0, [x1, x2, sxtx #3]
+ str d0, [x1, w2, uxtw]
+ str d0, [x1, w2, uxtw #3]
+ str d0, [x1, w2, sxtw]
+ str d0, [x1, w2, sxtw #3]
+
+ str q0, [x1, x2]
+ str q0, [x1, x2, lsl #4]
+ str q0, [x1, x2, sxtx]
+ str q0, [x1, x2, sxtx #4]
+ str q0, [x1, w2, uxtw]
+ str q0, [x1, w2, uxtw #4]
+ str q0, [x1, w2, sxtw]
+ str q0, [x1, w2, sxtw #4]
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -24,6 +226,419 @@
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 4 0.50 * ldr x7, [x1, #8]
-# CHECK-NEXT: 2 5 0.50 * ldr x6, [x1, x2]
-# CHECK-NEXT: 2 5 0.50 * ldr x4, [x1, x2, sxtx]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, x2]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, x2, lsl #3]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, x2, sxtx]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, x2, sxtx #3]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, w2, uxtw]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, w2, uxtw #3]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, w2, sxtw]
+# CHECK-NEXT: 1 4 0.50 U prfm pldl1keep, [x1, w2, sxtw #3]
+# CHECK-NEXT: 1 4 0.50 * ldrb w0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrb w0, [x1, x2, lsl #0]
+# CHECK-NEXT: 1 4 0.50 * ldrb w0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrb w0, [x1, x2, sxtx #0]
+# CHECK-NEXT: 2 5 0.50 * ldrb w0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrb w0, [x1, w2, uxtw #0]
+# CHECK-NEXT: 2 5 0.50 * ldrb w0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrb w0, [x1, w2, sxtw #0]
+# CHECK-NEXT: 1 4 0.50 * ldrsb w0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrsb w0, [x1, x2, lsl #0]
+# CHECK-NEXT: 1 4 0.50 * ldrsb w0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrsb w0, [x1, x2, sxtx #0]
+# CHECK-NEXT: 2 5 0.50 * ldrsb w0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsb w0, [x1, w2, uxtw #0]
+# CHECK-NEXT: 2 5 0.50 * ldrsb w0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsb w0, [x1, w2, sxtw #0]
+# CHECK-NEXT: 1 4 0.50 * ldrsb x0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrsb x0, [x1, x2, lsl #0]
+# CHECK-NEXT: 1 4 0.50 * ldrsb x0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrsb x0, [x1, x2, sxtx #0]
+# CHECK-NEXT: 2 5 0.50 * ldrsb x0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsb x0, [x1, w2, uxtw #0]
+# CHECK-NEXT: 2 5 0.50 * ldrsb x0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsb x0, [x1, w2, sxtw #0]
+# CHECK-NEXT: 1 4 0.50 * ldrh w0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrh w0, [x1, x2, lsl #1]
+# CHECK-NEXT: 1 4 0.50 * ldrh w0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrh w0, [x1, x2, sxtx #1]
+# CHECK-NEXT: 2 5 0.50 * ldrh w0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrh w0, [x1, w2, uxtw #1]
+# CHECK-NEXT: 2 5 0.50 * ldrh w0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrh w0, [x1, w2, sxtw #1]
+# CHECK-NEXT: 1 4 0.50 * ldrsh w0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrsh w0, [x1, x2, lsl #1]
+# CHECK-NEXT: 1 4 0.50 * ldrsh w0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrsh w0, [x1, x2, sxtx #1]
+# CHECK-NEXT: 2 5 0.50 * ldrsh w0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsh w0, [x1, w2, uxtw #1]
+# CHECK-NEXT: 2 5 0.50 * ldrsh w0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsh w0, [x1, w2, sxtw #1]
+# CHECK-NEXT: 1 4 0.50 * ldrsh x0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrsh x0, [x1, x2, lsl #1]
+# CHECK-NEXT: 1 4 0.50 * ldrsh x0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrsh x0, [x1, x2, sxtx #1]
+# CHECK-NEXT: 2 5 0.50 * ldrsh x0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsh x0, [x1, w2, uxtw #1]
+# CHECK-NEXT: 2 5 0.50 * ldrsh x0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsh x0, [x1, w2, sxtw #1]
+# CHECK-NEXT: 1 4 0.50 * ldr w0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldr w0, [x1, x2, lsl #2]
+# CHECK-NEXT: 1 4 0.50 * ldr w0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldr w0, [x1, x2, sxtx #2]
+# CHECK-NEXT: 2 5 0.50 * ldr w0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldr w0, [x1, w2, uxtw #2]
+# CHECK-NEXT: 2 5 0.50 * ldr w0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldr w0, [x1, w2, sxtw #2]
+# CHECK-NEXT: 1 4 0.50 * ldrsw x0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldrsw x0, [x1, x2, lsl #2]
+# CHECK-NEXT: 1 4 0.50 * ldrsw x0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldrsw x0, [x1, x2, sxtx #2]
+# CHECK-NEXT: 2 5 0.50 * ldrsw x0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsw x0, [x1, w2, uxtw #2]
+# CHECK-NEXT: 2 5 0.50 * ldrsw x0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldrsw x0, [x1, w2, sxtw #2]
+# CHECK-NEXT: 1 4 0.50 * ldr x0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldr x0, [x1, x2, lsl #3]
+# CHECK-NEXT: 1 4 0.50 * ldr x0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldr x0, [x1, x2, sxtx #3]
+# CHECK-NEXT: 2 5 0.50 * ldr x0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldr x0, [x1, w2, uxtw #3]
+# CHECK-NEXT: 2 5 0.50 * ldr x0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldr x0, [x1, w2, sxtw #3]
+# CHECK-NEXT: 1 4 0.50 * ldr b0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldr b0, [x1, x2, lsl #0]
+# CHECK-NEXT: 1 4 0.50 * ldr b0, [x1, x2, sxtx]
+# CHECK-NEXT: 2 5 0.50 * ldr b0, [x1, x2, sxtx #0]
+# CHECK-NEXT: 2 5 0.50 * ldr b0, [x1, w2, uxtw]
+# CHECK-NEXT: 2 5 0.50 * ldr b0, [x1, w2, uxtw #0]
+# CHECK-NEXT: 2 5 0.50 * ldr b0, [x1, w2, sxtw]
+# CHECK-NEXT: 2 5 0.50 * ldr b0, [x1, w2, sxtw #0]
+# CHECK-NEXT: 1 4 0.50 * ldr h0, [x1, x2]
+# CHECK-NEXT: 2 5 0.50 * ldr h0, [x1, ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225645
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