[llvm] [AArch64] Add sext(shl x, imm)/sext(sra x, imm) selection patterns (PR #226065)

[Hari Limaye via llvm-commits]

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@@ -339,3 +339,143 @@ define i64 @sign_extend_inreg_isdef32(i64) {
   %6 = zext i32 %5 to i64
   ret i64 %6
 }
+
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hazzlim wrote:

When adding new tests like this, it's often nice to separate the PR into an initial commit which adds the tests (with the baseline CHECK lines), and then a second commit which adds the compiler changes and updates the tests, so we can see the change in the code generation easily

https://github.com/llvm/llvm-project/pull/226065