[llvm] [AMDGPU] Mark CDBG branches as having side effects (PR #226123)

[Alexander Hück via llvm-commits]

https://github.com/ahueck created https://github.com/llvm/llvm-project/pull/226123

The change marks all four CDBG branch variants as having unmodeled side effects, consistent with reading externally controlled debug state.

>From 1811c83ee4b865eb80c64c401800102f507a3414 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alexander=20H=C3=BCck?= <alexander.huck at amd.com>
Date: Thu, 24 Sep 2026 07:06:29 -0400
Subject: [PATCH] [AMDGPU] Mark CDBG branches as having side effects

---
 llvm/lib/Target/AMDGPU/SOPInstructions.td     |  2 ++
 .../Target/AMDGPU/AMDGPUUnitTests.cpp         | 29 +++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index bdcef208f52e9..b336af3bcd01f 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1623,6 +1623,7 @@ defm S_CBRANCH_EXECNZ : SOPP_With_Relaxation <
 >;
 } // End Uses = [EXEC]
 
+let hasSideEffects = 1 in {
 defm S_CBRANCH_CDBGSYS : SOPP_With_Relaxation <
   "s_cbranch_cdbgsys" , (ins SOPPBrTarget:$simm16),
   "$simm16"
@@ -1642,6 +1643,7 @@ defm S_CBRANCH_CDBGUSER : SOPP_With_Relaxation <
   "s_cbranch_cdbguser" , (ins SOPPBrTarget:$simm16),
   "$simm16"
 >;
+} // End hasSideEffects = 1
 
 } // End isBranch = 1
 } // End isTerminator = 1
diff --git a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
index 51fda88e66eca..b2c7d4f229770 100644
--- a/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
+++ b/llvm/unittests/Target/AMDGPU/AMDGPUUnitTests.cpp
@@ -10,6 +10,7 @@
 #include "AMDGPUGenSubtargetInfo.inc"
 #include "AMDGPUTargetMachine.h"
 #include "GCNSubtarget.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/TargetParser/AMDGPUTargetParser.h"
@@ -375,3 +376,31 @@ TEST_F(AMDGPUTestBase, TestGetNamedOperandIdx) {
     }
   }
 }
+
+TEST_F(AMDGPUTestBase, TestBranchUnmodeledSideEffects) {
+  auto TM = createAMDGPUTargetMachine(Triple("amdgpu9.00-amd-"), "", "");
+  ASSERT_TRUE(TM);
+  const MCInstrInfo *MCII = TM->getMCInstrInfo();
+  ASSERT_NE(MCII, nullptr);
+
+  const struct {
+    unsigned Opcode;
+    bool HasSideEffects;
+  } Cases[] = {
+      {AMDGPU::S_CBRANCH_CDBGSYS, true},
+      {AMDGPU::S_CBRANCH_CDBGUSER, true},
+      {AMDGPU::S_CBRANCH_CDBGSYS_OR_USER, true},
+      {AMDGPU::S_CBRANCH_CDBGSYS_AND_USER, true},
+      {AMDGPU::S_CBRANCH_CDBGSYS_pad_s_nop, true},
+      {AMDGPU::S_CBRANCH_CDBGUSER_pad_s_nop, true},
+      {AMDGPU::S_CBRANCH_CDBGSYS_OR_USER_pad_s_nop, true},
+      {AMDGPU::S_CBRANCH_CDBGSYS_AND_USER_pad_s_nop, true},
+      {AMDGPU::S_CBRANCH_SCC0, false},
+      {AMDGPU::S_CBRANCH_SCC0_pad_s_nop, false},
+  };
+
+  for (const auto &Case : Cases)
+    EXPECT_EQ(Case.HasSideEffects,
+              MCII->get(Case.Opcode).hasUnmodeledSideEffects())
+        << MCII->getName(Case.Opcode);
+}