[llvm] [X86] Prepare bdver fp<->int tests for TuningPrefer128Bit (PR #226121)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 04:18:40 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/226121
Ensure the check prefixes can handle bdver targets independently, I've also reordered some of the tests so we can cleanly order the eventual AVX128/AVX256/AVX512 checks
Help reduce the diff for #225838
>From ed677658e3d4f42b21fbdc48d10d987ee1af3943 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Thu, 24 Sep 2026 12:17:50 +0100
Subject: [PATCH] [X86] Prepare bdver fp<->int tests for TuningPrefer128Bit
Ensure the check prefixes can handle bdver targets independently, I've also reordered some of the tests so we can cleanly order the eventual AVX128/AVX256/AVX512 checks
Help reduce the diff for #225838
---
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 46 ++++++++-------
.../Transforms/SLPVectorizer/X86/fptosi.ll | 46 ++++++++-------
.../Transforms/SLPVectorizer/X86/fptoui.ll | 44 +++++++-------
.../SLPVectorizer/X86/sitofp-inseltpoison.ll | 56 +++++++++---------
.../Transforms/SLPVectorizer/X86/sitofp.ll | 56 +++++++++---------
.../Transforms/SLPVectorizer/X86/uitofp.ll | 59 ++++++++-----------
6 files changed, 152 insertions(+), 155 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index 673114cc0321de..7c049376ca2745 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -78,12 +78,6 @@ define void @fptosi_8f64_8i64() #0 {
; AVX256NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @fptosi_8f64_8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i64>
-; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @fptosi_8f64_8i64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i64>
@@ -92,6 +86,12 @@ define void @fptosi_8f64_8i64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i64>
; AVX256DQ-NEXT: store <4 x i64> [[TMP4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f64_8i64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i64>
+; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -290,12 +290,6 @@ define void @fptosi_8f32_8i64() #0 {
; AVX256NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @fptosi_8f32_8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i64>
-; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @fptosi_8f32_8i64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i64>
@@ -304,6 +298,12 @@ define void @fptosi_8f32_8i64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i64>
; AVX256DQ-NEXT: store <4 x i64> [[TMP4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f32_8i64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i64>
+; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -488,3 +488,5 @@ define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3)
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index 159f3106235544..a44801cfc6a8e2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -78,12 +78,6 @@ define void @fptosi_8f64_8i64() #0 {
; AVX256NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @fptosi_8f64_8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i64>
-; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @fptosi_8f64_8i64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i64>
@@ -92,6 +86,12 @@ define void @fptosi_8f64_8i64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i64>
; AVX256DQ-NEXT: store <4 x i64> [[TMP4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f64_8i64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i64>
+; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -290,12 +290,6 @@ define void @fptosi_8f32_8i64() #0 {
; AVX256NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @fptosi_8f32_8i64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i64>
-; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @fptosi_8f32_8i64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i64>
@@ -304,6 +298,12 @@ define void @fptosi_8f32_8i64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i64>
; AVX256DQ-NEXT: store <4 x i64> [[TMP4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f32_8i64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i64>
+; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -488,3 +488,5 @@ define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3)
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
index ae0905db4cfbe7..b6cd8a9c360e2b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512F
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512F
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512F
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -78,12 +78,6 @@ define void @fptoui_8f64_8i64() #0 {
; AVX256NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512F-LABEL: @fptoui_8f64_8i64(
-; AVX512F-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX512F-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i64>
-; AVX512F-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
-; AVX512F-NEXT: ret void
-;
; AVX256DQ-LABEL: @fptoui_8f64_8i64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
; AVX256DQ-NEXT: [[TMP2:%.*]] = fptoui <4 x double> [[TMP1]] to <4 x i64>
@@ -92,6 +86,12 @@ define void @fptoui_8f64_8i64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = fptoui <4 x double> [[TMP3]] to <4 x i64>
; AVX256DQ-NEXT: store <4 x i64> [[TMP4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptoui_8f64_8i64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i64>
+; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -290,12 +290,6 @@ define void @fptoui_8f32_8i64() #0 {
; AVX256NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512F-LABEL: @fptoui_8f32_8i64(
-; AVX512F-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX512F-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i64>
-; AVX512F-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
-; AVX512F-NEXT: ret void
-;
; AVX256DQ-LABEL: @fptoui_8f32_8i64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
; AVX256DQ-NEXT: [[TMP2:%.*]] = fptoui <4 x float> [[TMP1]] to <4 x i64>
@@ -304,6 +298,12 @@ define void @fptoui_8f32_8i64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = fptoui <4 x float> [[TMP3]] to <4 x i64>
; AVX256DQ-NEXT: store <4 x i64> [[TMP4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptoui_8f32_8i64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i64>
+; AVX512-NEXT: store <8 x i64> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -444,3 +444,5 @@ define void @fptoui_8f32_8i8() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index 0866e56cf46b29..f20e90cc69a93d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -43,17 +43,17 @@ define void @sitofp_2i64_2f64() #0 {
; AVX256NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_2i64_2f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
-; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_2i64_2f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
; AVX256DQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_2i64_2f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -95,17 +95,17 @@ define void @sitofp_4i64_4f64() #0 {
; AVX256NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_4i64_4f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
-; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_4i64_4f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i64_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -177,12 +177,6 @@ define void @sitofp_8i64_8f64() #0 {
; AVX256NODQ-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_8i64_8f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x double>
-; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_8i64_8f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
@@ -191,6 +185,12 @@ define void @sitofp_8i64_8f64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x double>
; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i64_8f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x double>
+; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -557,17 +557,17 @@ define void @sitofp_2i64_2f32() #0 {
; AVX256NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_2i64_2f32(
-; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x float>
-; AVX512-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_2i64_2f32(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x float>
; AVX256DQ-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_2i64_2f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x float>
+; AVX512-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
index 316dfd0a76ff9f..194dfd4c115417 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -43,17 +43,17 @@ define void @sitofp_2i64_2f64() #0 {
; AVX256NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_2i64_2f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
-; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_2i64_2f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
; AVX256DQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_2i64_2f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -95,17 +95,17 @@ define void @sitofp_4i64_4f64() #0 {
; AVX256NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_4i64_4f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
-; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_4i64_4f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i64_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -177,12 +177,6 @@ define void @sitofp_8i64_8f64() #0 {
; AVX256NODQ-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_8i64_8f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x double>
-; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_8i64_8f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
@@ -191,6 +185,12 @@ define void @sitofp_8i64_8f64() #0 {
; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x double>
; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i64_8f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x double>
+; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -557,17 +557,17 @@ define void @sitofp_2i64_2f32() #0 {
; AVX256NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; AVX256NODQ-NEXT: ret void
;
-; AVX512-LABEL: @sitofp_2i64_2f32(
-; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x float>
-; AVX512-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @sitofp_2i64_2f32(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x float>
; AVX256DQ-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_2i64_2f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x float>
+; AVX512-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
index c978095422b5d4..9b4123c0218d8d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX2
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -151,17 +151,17 @@ define void @uitofp_2i32_2f64() #0 {
; AVX2-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; AVX2-NEXT: ret void
;
-; AVX512-LABEL: @uitofp_2i32_2f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
-; AVX512-NEXT: [[TMP2:%.*]] = uitofp <2 x i32> [[TMP1]] to <2 x double>
-; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX512-NEXT: ret void
-;
; AVX256DQ-LABEL: @uitofp_2i32_2f64(
; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
; AVX256DQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i32> [[TMP1]] to <2 x double>
; AVX256DQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @uitofp_2i32_2f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = uitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
@@ -485,35 +485,26 @@ define void @uitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
-; AVX1-LABEL: @uitofp_2i64_2f32(
-; AVX1-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX1-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX1-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
-; AVX1-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
-; AVX1-NEXT: store float [[CVT0]], ptr @dst32, align 64
-; AVX1-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
-; AVX1-NEXT: ret void
+; AVX256NODQ-LABEL: @uitofp_2i64_2f32(
+; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
+; AVX256NODQ-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
+; AVX256NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX256NODQ-NEXT: ret void
;
-; AVX2-LABEL: @uitofp_2i64_2f32(
-; AVX2-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX2-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX2-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
-; AVX2-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
-; AVX2-NEXT: store float [[CVT0]], ptr @dst32, align 64
-; AVX2-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
-; AVX2-NEXT: ret void
+; AVX256DQ-LABEL: @uitofp_2i64_2f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x float>
+; AVX256DQ-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @uitofp_2i64_2f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
; AVX512-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x float>
; AVX512-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
; AVX512-NEXT: ret void
-;
-; AVX256DQ-LABEL: @uitofp_2i64_2f32(
-; AVX256DQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX256DQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x float>
-; AVX256DQ-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256DQ-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
More information about the llvm-commits
mailing list