[llvm] [LLVM][CodeGen] Enable the AArch64PTrueCoalescing pass. (PR #225830)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 04:14:00 PDT 2026
https://github.com/paulwalker-arm updated https://github.com/llvm/llvm-project/pull/225830
>From fa9af67265711fc16899ddf76076bf88f76b9cf5 Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Wed, 23 Sep 2026 15:35:07 +0000
Subject: [PATCH] [LLVM][CodeGen] Enable the AArch64PTrueCoalescing pass.
---
.../Target/AArch64/AArch64PTrueCoalescing.cpp | 2 +-
.../insert-subvector-res-legalization.ll | 4 -
.../CodeGen/AArch64/llvm-ir-to-intrinsic.ll | 12 +-
.../CodeGen/AArch64/masked-srem-scalable.ll | 3 +-
.../CodeGen/AArch64/masked-urem-scalable.ll | 3 +-
.../test/CodeGen/AArch64/sve-bf16-combines.ll | 4 -
.../CodeGen/AArch64/sve-bf16-int-converts.ll | 13 +-
llvm/test/CodeGen/AArch64/sve-bitcast.ll | 370 ++++++------------
llvm/test/CodeGen/AArch64/sve-fpext-load.ll | 1 -
.../sve-ld1-addressing-mode-reg-imm.ll | 108 ++---
.../AArch64/sve-load-store-legalisation.ll | 164 ++++----
llvm/test/CodeGen/AArch64/sve-lsrchain.ll | 39 +-
.../AArch64/sve-partial-reduce-dot-product.ll | 6 -
.../AArch64/sve-partial-reduce-wide-add.ll | 1 -
.../CodeGen/AArch64/sve-pred-selectop2.ll | 80 ++--
.../AArch64/sve-shift-trunc-combine.ll | 15 +-
.../sve-st1-addressing-mode-reg-imm.ll | 88 ++---
.../AArch64/vec-combine-compare-to-bitmask.ll | 3 +-
.../AArch64/vector-absolute-difference.ll | 6 -
.../AArch64/vscale-fixups.ll | 5 +-
20 files changed, 339 insertions(+), 588 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp b/llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
index 0bab8e42555790..61b19624d2493e 100644
--- a/llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
@@ -38,7 +38,7 @@ using namespace llvm;
#define DEBUG_TYPE "aarch64-ptrue-coalesce"
static cl::opt<bool> EnablePTrueCoalescing(
- "aarch64-enable-ptrue-coalescing", cl::init(false), cl::Hidden,
+ "aarch64-enable-ptrue-coalescing", cl::init(true), cl::Hidden,
cl::desc("Enable coalescing of compatible AArch64 SVE PTRUE instructions"));
namespace {
diff --git a/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll b/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
index d0026db0176e11..7ea57fc1eebcc7 100644
--- a/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
+++ b/llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
@@ -10,7 +10,6 @@ define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(ptr %a, ptr %
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1]
; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
@@ -26,7 +25,6 @@ define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(ptr %a, pt
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1]
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
@@ -42,7 +40,6 @@ define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(ptr %a, ptr
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1]
; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
@@ -58,7 +55,6 @@ define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(ptr %a,
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1]
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
diff --git a/llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll b/llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
index 6b4ebbe2be5ae7..1b23deb21b833d 100644
--- a/llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
+++ b/llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
@@ -112,7 +112,7 @@ define <vscale x 16 x i8> @srem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
; CHECK: // %bb.0:
; CHECK-NEXT: sunpkhi z2.h, z1.b
; CHECK-NEXT: sunpkhi z3.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: sunpkhi z4.s, z2.h
; CHECK-NEXT: sunpkhi z5.s, z3.h
; CHECK-NEXT: sunpklo z2.s, z2.h
@@ -128,7 +128,6 @@ define <vscale x 16 x i8> @srem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s
; CHECK-NEXT: uzp1 z2.h, z2.h, z4.h
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s
-; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: uzp1 z3.h, z3.h, z6.h
; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b
; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b
@@ -142,12 +141,11 @@ define <vscale x 8 x i16> @srem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b
; CHECK: // %bb.0:
; CHECK-NEXT: sunpkhi z2.s, z1.h
; CHECK-NEXT: sunpkhi z3.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sunpklo z4.s, z0.h
; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: sunpklo z3.s, z1.h
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
; CHECK-NEXT: ret
@@ -291,7 +289,7 @@ define <vscale x 16 x i8> @urem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z2.h, z1.b
; CHECK-NEXT: uunpkhi z3.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: uunpkhi z4.s, z2.h
; CHECK-NEXT: uunpkhi z5.s, z3.h
; CHECK-NEXT: uunpklo z2.s, z2.h
@@ -307,7 +305,6 @@ define <vscale x 16 x i8> @urem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s
; CHECK-NEXT: uzp1 z2.h, z2.h, z4.h
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s
-; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: uzp1 z3.h, z3.h, z6.h
; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b
; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b
@@ -321,12 +318,11 @@ define <vscale x 8 x i16> @urem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b
; CHECK: // %bb.0:
; CHECK-NEXT: uunpkhi z2.s, z1.h
; CHECK-NEXT: uunpkhi z3.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uunpklo z4.s, z0.h
; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: uunpklo z3.s, z1.h
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/masked-srem-scalable.ll b/llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
index aebe7a7bf3b201..a4658a5358b97e 100644
--- a/llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
@@ -58,12 +58,11 @@ define <vscale x 8 x i16> @srem_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16
; CHECK-NEXT: sunpklo z4.s, z0.h
; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
; CHECK-NEXT: sunpkhi z2.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sunpkhi z3.s, z1.h
; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: sunpklo z3.s, z1.h
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/masked-urem-scalable.ll b/llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
index af6b372ce7eb7d..e733addb29b669 100644
--- a/llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
+++ b/llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
@@ -58,12 +58,11 @@ define <vscale x 8 x i16> @urem_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16
; CHECK-NEXT: uunpklo z4.s, z0.h
; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
; CHECK-NEXT: uunpkhi z2.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uunpkhi z3.s, z1.h
; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: uunpklo z3.s, z1.h
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
-; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll b/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
index f1c08eaab6a7a5..8a48fa41b8d40e 100644
--- a/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
+++ b/llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
@@ -155,7 +155,6 @@ define <vscale x 8 x bfloat> @fmls_nxv8bf16(<vscale x 8 x bfloat> %acc, <vscale
; BF16_NONSTREAMING-NEXT: uunpkhi z5.s, z2.h
; BF16_NONSTREAMING-NEXT: uunpklo z2.s, z2.h
; BF16_NONSTREAMING-NEXT: fneg z1.h, p0/m, z1.h
-; BF16_NONSTREAMING-NEXT: ptrue p0.s
; BF16_NONSTREAMING-NEXT: zip2 z6.h, z3.h, z0.h
; BF16_NONSTREAMING-NEXT: zip1 z0.h, z3.h, z0.h
; BF16_NONSTREAMING-NEXT: uunpkhi z4.s, z1.h
@@ -186,7 +185,6 @@ define <vscale x 8 x bfloat> @fmls_nxv8bf16(<vscale x 8 x bfloat> %acc, <vscale
; BF16_STREAMING-NEXT: uunpkhi z5.s, z2.h
; BF16_STREAMING-NEXT: uunpklo z2.s, z2.h
; BF16_STREAMING-NEXT: fneg z1.h, p0/m, z1.h
-; BF16_STREAMING-NEXT: ptrue p0.s
; BF16_STREAMING-NEXT: zip2 z6.h, z3.h, z0.h
; BF16_STREAMING-NEXT: zip1 z0.h, z3.h, z0.h
; BF16_STREAMING-NEXT: uunpkhi z4.s, z1.h
@@ -435,7 +433,6 @@ define <vscale x 8 x bfloat> @fmls_sel_nxv8bf16(<vscale x 8 x i1> %pred, <vscale
; BF16_NONSTREAMING-NEXT: uunpkhi z5.s, z2.h
; BF16_NONSTREAMING-NEXT: uunpklo z2.s, z2.h
; BF16_NONSTREAMING-NEXT: fneg z1.h, p1/m, z1.h
-; BF16_NONSTREAMING-NEXT: ptrue p1.s
; BF16_NONSTREAMING-NEXT: zip2 z6.h, z3.h, z0.h
; BF16_NONSTREAMING-NEXT: zip1 z3.h, z3.h, z0.h
; BF16_NONSTREAMING-NEXT: uunpkhi z4.s, z1.h
@@ -465,7 +462,6 @@ define <vscale x 8 x bfloat> @fmls_sel_nxv8bf16(<vscale x 8 x i1> %pred, <vscale
; BF16_STREAMING-NEXT: uunpkhi z5.s, z2.h
; BF16_STREAMING-NEXT: uunpklo z2.s, z2.h
; BF16_STREAMING-NEXT: fneg z1.h, p1/m, z1.h
-; BF16_STREAMING-NEXT: ptrue p1.s
; BF16_STREAMING-NEXT: zip2 z6.h, z3.h, z0.h
; BF16_STREAMING-NEXT: zip1 z3.h, z3.h, z0.h
; BF16_STREAMING-NEXT: uunpkhi z4.s, z1.h
diff --git a/llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll b/llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
index 0d4be4a2fcfd5f..cb19d8de0befef 100644
--- a/llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
+++ b/llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
@@ -126,12 +126,11 @@ define <vscale x 8 x i1> @fptosi_nxv8bf16_to_nxv8i1(<vscale x 8 x bfloat> %a) {
; SVE-LABEL: fptosi_nxv8bf16_to_nxv8i1:
; SVE: // %bb.0:
; SVE-NEXT: movi v1.2d, #0000000000000000
-; SVE-NEXT: ptrue p0.s
+; SVE-NEXT: ptrue p0.h
; SVE-NEXT: zip2 z2.h, z1.h, z0.h
; SVE-NEXT: zip1 z0.h, z1.h, z0.h
; SVE-NEXT: fcvtzs z2.s, p0/m, z2.s
; SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; SVE-NEXT: ptrue p0.h
; SVE-NEXT: uzp1 z0.h, z0.h, z2.h
; SVE-NEXT: cmpne p0.h, p0/z, z0.h, #0
; SVE-NEXT: ret
@@ -139,12 +138,11 @@ define <vscale x 8 x i1> @fptosi_nxv8bf16_to_nxv8i1(<vscale x 8 x bfloat> %a) {
; STREAMING-SVE-LABEL: fptosi_nxv8bf16_to_nxv8i1:
; STREAMING-SVE: // %bb.0:
; STREAMING-SVE-NEXT: mov z1.h, #0 // =0x0
-; STREAMING-SVE-NEXT: ptrue p0.s
+; STREAMING-SVE-NEXT: ptrue p0.h
; STREAMING-SVE-NEXT: zip2 z2.h, z1.h, z0.h
; STREAMING-SVE-NEXT: zip1 z0.h, z1.h, z0.h
; STREAMING-SVE-NEXT: fcvtzs z2.s, p0/m, z2.s
; STREAMING-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; STREAMING-SVE-NEXT: ptrue p0.h
; STREAMING-SVE-NEXT: uzp1 z0.h, z0.h, z2.h
; STREAMING-SVE-NEXT: cmpne p0.h, p0/z, z0.h, #0
; STREAMING-SVE-NEXT: ret
@@ -380,12 +378,11 @@ define <vscale x 8 x i1> @fptoui_nxv8bf16_to_nxv8i1(<vscale x 8 x bfloat> %a) {
; SVE-LABEL: fptoui_nxv8bf16_to_nxv8i1:
; SVE: // %bb.0:
; SVE-NEXT: movi v1.2d, #0000000000000000
-; SVE-NEXT: ptrue p0.s
+; SVE-NEXT: ptrue p0.h
; SVE-NEXT: zip2 z2.h, z1.h, z0.h
; SVE-NEXT: zip1 z0.h, z1.h, z0.h
; SVE-NEXT: fcvtzs z2.s, p0/m, z2.s
; SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; SVE-NEXT: ptrue p0.h
; SVE-NEXT: uzp1 z0.h, z0.h, z2.h
; SVE-NEXT: cmpne p0.h, p0/z, z0.h, #0
; SVE-NEXT: ret
@@ -393,12 +390,11 @@ define <vscale x 8 x i1> @fptoui_nxv8bf16_to_nxv8i1(<vscale x 8 x bfloat> %a) {
; STREAMING-SVE-LABEL: fptoui_nxv8bf16_to_nxv8i1:
; STREAMING-SVE: // %bb.0:
; STREAMING-SVE-NEXT: mov z1.h, #0 // =0x0
-; STREAMING-SVE-NEXT: ptrue p0.s
+; STREAMING-SVE-NEXT: ptrue p0.h
; STREAMING-SVE-NEXT: zip2 z2.h, z1.h, z0.h
; STREAMING-SVE-NEXT: zip1 z0.h, z1.h, z0.h
; STREAMING-SVE-NEXT: fcvtzs z2.s, p0/m, z2.s
; STREAMING-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
-; STREAMING-SVE-NEXT: ptrue p0.h
; STREAMING-SVE-NEXT: uzp1 z0.h, z0.h, z2.h
; STREAMING-SVE-NEXT: cmpne p0.h, p0/z, z0.h, #0
; STREAMING-SVE-NEXT: ret
@@ -659,7 +655,6 @@ define <vscale x 8 x bfloat> @sitofp_nxv8i8_to_nxv8bf16(<vscale x 8 x i8> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sxtb z0.h, p0/m, z0.h
-; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: sunpkhi z1.s, z0.h
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: scvtf z1.s, p0/m, z1.s
diff --git a/llvm/test/CodeGen/AArch64/sve-bitcast.ll b/llvm/test/CodeGen/AArch64/sve-bitcast.ll
index be80af89f270c8..d6516a3928db66 100644
--- a/llvm/test/CodeGen/AArch64/sve-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/sve-bitcast.ll
@@ -129,9 +129,8 @@ define <vscale x 8 x i16> @bitcast_nxv4i32_to_nxv8i16(<vscale x 4 x i32> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv4i32_to_nxv8i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i32> %v to <vscale x 8 x i16>
@@ -145,9 +144,8 @@ define <vscale x 8 x i16> @bitcast_nxv2i64_to_nxv8i16(<vscale x 2 x i64> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv2i64_to_nxv8i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i64> %v to <vscale x 8 x i16>
@@ -173,9 +171,8 @@ define <vscale x 8 x i16> @bitcast_nxv4f32_to_nxv8i16(<vscale x 4 x float> %v) #
;
; CHECK_BE-LABEL: bitcast_nxv4f32_to_nxv8i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x float> %v to <vscale x 8 x i16>
@@ -189,9 +186,8 @@ define <vscale x 8 x i16> @bitcast_nxv2f64_to_nxv8i16(<vscale x 2 x double> %v)
;
; CHECK_BE-LABEL: bitcast_nxv2f64_to_nxv8i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x double> %v to <vscale x 8 x i16>
@@ -237,7 +233,6 @@ define <vscale x 4 x i32> @bitcast_nxv8i16_to_nxv4i32(<vscale x 8 x i16> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x i16> %v to <vscale x 4 x i32>
@@ -251,9 +246,8 @@ define <vscale x 4 x i32> @bitcast_nxv2i64_to_nxv4i32(<vscale x 2 x i64> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv2i64_to_nxv4i32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i64> %v to <vscale x 4 x i32>
@@ -269,7 +263,6 @@ define <vscale x 4 x i32> @bitcast_nxv8f16_to_nxv4i32(<vscale x 8 x half> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x half> %v to <vscale x 4 x i32>
@@ -295,9 +288,8 @@ define <vscale x 4 x i32> @bitcast_nxv2f64_to_nxv4i32(<vscale x 2 x double> %v)
;
; CHECK_BE-LABEL: bitcast_nxv2f64_to_nxv4i32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x double> %v to <vscale x 4 x i32>
@@ -313,7 +305,6 @@ define <vscale x 4 x i32> @bitcast_nxv8bf16_to_nxv4i32(<vscale x 8 x bfloat> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 4 x i32>
@@ -347,7 +338,6 @@ define <vscale x 2 x i64> @bitcast_nxv8i16_to_nxv2i64(<vscale x 8 x i16> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x i16> %v to <vscale x 2 x i64>
@@ -363,7 +353,6 @@ define <vscale x 2 x i64> @bitcast_nxv4i32_to_nxv2i64(<vscale x 4 x i32> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i32> %v to <vscale x 2 x i64>
@@ -379,7 +368,6 @@ define <vscale x 2 x i64> @bitcast_nxv8f16_to_nxv2i64(<vscale x 8 x half> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x half> %v to <vscale x 2 x i64>
@@ -395,7 +383,6 @@ define <vscale x 2 x i64> @bitcast_nxv4f32_to_nxv2i64(<vscale x 4 x float> %v) #
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x float> %v to <vscale x 2 x i64>
@@ -423,7 +410,6 @@ define <vscale x 2 x i64> @bitcast_nxv8bf16_to_nxv2i64(<vscale x 8 x bfloat> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 2 x i64>
@@ -467,9 +453,8 @@ define <vscale x 8 x half> @bitcast_nxv4i32_to_nxv8f16(<vscale x 4 x i32> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv4i32_to_nxv8f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i32> %v to <vscale x 8 x half>
@@ -483,9 +468,8 @@ define <vscale x 8 x half> @bitcast_nxv2i64_to_nxv8f16(<vscale x 2 x i64> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv2i64_to_nxv8f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i64> %v to <vscale x 8 x half>
@@ -499,9 +483,8 @@ define <vscale x 8 x half> @bitcast_nxv4f32_to_nxv8f16(<vscale x 4 x float> %v)
;
; CHECK_BE-LABEL: bitcast_nxv4f32_to_nxv8f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x float> %v to <vscale x 8 x half>
@@ -515,9 +498,8 @@ define <vscale x 8 x half> @bitcast_nxv2f64_to_nxv8f16(<vscale x 2 x double> %v)
;
; CHECK_BE-LABEL: bitcast_nxv2f64_to_nxv8f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x double> %v to <vscale x 8 x half>
@@ -563,7 +545,6 @@ define <vscale x 4 x float> @bitcast_nxv8i16_to_nxv4f32(<vscale x 8 x i16> %v) #
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x i16> %v to <vscale x 4 x float>
@@ -589,9 +570,8 @@ define <vscale x 4 x float> @bitcast_nxv2i64_to_nxv4f32(<vscale x 2 x i64> %v) #
;
; CHECK_BE-LABEL: bitcast_nxv2i64_to_nxv4f32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i64> %v to <vscale x 4 x float>
@@ -607,7 +587,6 @@ define <vscale x 4 x float> @bitcast_nxv8f16_to_nxv4f32(<vscale x 8 x half> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x half> %v to <vscale x 4 x float>
@@ -621,9 +600,8 @@ define <vscale x 4 x float> @bitcast_nxv2f64_to_nxv4f32(<vscale x 2 x double> %v
;
; CHECK_BE-LABEL: bitcast_nxv2f64_to_nxv4f32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x double> %v to <vscale x 4 x float>
@@ -639,7 +617,6 @@ define <vscale x 4 x float> @bitcast_nxv8bf16_to_nxv4f32(<vscale x 8 x bfloat> %
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 4 x float>
@@ -673,7 +650,6 @@ define <vscale x 2 x double> @bitcast_nxv8i16_to_nxv2f64(<vscale x 8 x i16> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x i16> %v to <vscale x 2 x double>
@@ -689,7 +665,6 @@ define <vscale x 2 x double> @bitcast_nxv4i32_to_nxv2f64(<vscale x 4 x i32> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i32> %v to <vscale x 2 x double>
@@ -717,7 +692,6 @@ define <vscale x 2 x double> @bitcast_nxv8f16_to_nxv2f64(<vscale x 8 x half> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x half> %v to <vscale x 2 x double>
@@ -733,7 +707,6 @@ define <vscale x 2 x double> @bitcast_nxv4f32_to_nxv2f64(<vscale x 4 x float> %v
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x float> %v to <vscale x 2 x double>
@@ -749,7 +722,6 @@ define <vscale x 2 x double> @bitcast_nxv8bf16_to_nxv2f64(<vscale x 8 x bfloat>
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 8 x bfloat> %v to <vscale x 2 x double>
@@ -793,9 +765,8 @@ define <vscale x 8 x bfloat> @bitcast_nxv4i32_to_nxv8bf16(<vscale x 4 x i32> %v)
;
; CHECK_BE-LABEL: bitcast_nxv4i32_to_nxv8bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i32> %v to <vscale x 8 x bfloat>
@@ -809,9 +780,8 @@ define <vscale x 8 x bfloat> @bitcast_nxv2i64_to_nxv8bf16(<vscale x 2 x i64> %v)
;
; CHECK_BE-LABEL: bitcast_nxv2i64_to_nxv8bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i64> %v to <vscale x 8 x bfloat>
@@ -837,9 +807,8 @@ define <vscale x 8 x bfloat> @bitcast_nxv4f32_to_nxv8bf16(<vscale x 4 x float> %
;
; CHECK_BE-LABEL: bitcast_nxv4f32_to_nxv8bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x float> %v to <vscale x 8 x bfloat>
@@ -853,9 +822,8 @@ define <vscale x 8 x bfloat> @bitcast_nxv2f64_to_nxv8bf16(<vscale x 2 x double>
;
; CHECK_BE-LABEL: bitcast_nxv2f64_to_nxv8bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x double> %v to <vscale x 8 x bfloat>
@@ -871,10 +839,9 @@ define <vscale x 8 x i8> @bitcast_nxv4i16_to_nxv8i8(<vscale x 4 x i16> %v) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -883,10 +850,9 @@ define <vscale x 8 x i8> @bitcast_nxv4i16_to_nxv8i8(<vscale x 4 x i16> %v) #0 {
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.h
+; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -899,10 +865,9 @@ define <vscale x 8 x i8> @bitcast_nxv2i32_to_nxv8i8(<vscale x 2 x i32> %v) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -911,10 +876,9 @@ define <vscale x 8 x i8> @bitcast_nxv2i32_to_nxv8i8(<vscale x 2 x i32> %v) #0 {
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.h
+; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -943,10 +907,9 @@ define <vscale x 8 x i8> @bitcast_nxv4f16_to_nxv8i8(<vscale x 4 x half> %v) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -955,10 +918,9 @@ define <vscale x 8 x i8> @bitcast_nxv4f16_to_nxv8i8(<vscale x 4 x half> %v) #0 {
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.h
+; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -971,10 +933,9 @@ define <vscale x 8 x i8> @bitcast_nxv2f32_to_nxv8i8(<vscale x 2 x float> %v) #0
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -983,10 +944,9 @@ define <vscale x 8 x i8> @bitcast_nxv2f32_to_nxv8i8(<vscale x 2 x float> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.h
+; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1015,10 +975,9 @@ define <vscale x 8 x i8> @bitcast_nxv4bf16_to_nxv8i8(<vscale x 4 x bfloat> %v) #
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1027,10 +986,9 @@ define <vscale x 8 x i8> @bitcast_nxv4bf16_to_nxv8i8(<vscale x 4 x bfloat> %v) #
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.h
+; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.h }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.h }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1048,9 +1006,8 @@ define <vscale x 4 x i16> @bitcast_nxv8i8_to_nxv4i16(<vscale x 8 x i8> %v) #0 {
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1060,9 +1017,8 @@ define <vscale x 4 x i16> @bitcast_nxv8i8_to_nxv4i16(<vscale x 8 x i8> %v) #0 {
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.h
-; CHECK_BE-NEXT: ptrue p1.s
; CHECK_BE-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1075,10 +1031,9 @@ define <vscale x 4 x i16> @bitcast_nxv2i32_to_nxv4i16(<vscale x 2 x i32> %v) #0
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1087,10 +1042,9 @@ define <vscale x 4 x i16> @bitcast_nxv2i32_to_nxv4i16(<vscale x 2 x i32> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1106,9 +1060,8 @@ define <vscale x 4 x i16> @bitcast_nxv1i64_to_nxv4i16(<vscale x 1 x i64> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv1i64_to_nxv4i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: ret
@@ -1125,7 +1078,6 @@ define <vscale x 4 x i16> @bitcast_nxv4f16_to_nxv4i16(<vscale x 4 x half> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x half> %v to <vscale x 4 x i16>
@@ -1137,10 +1089,9 @@ define <vscale x 4 x i16> @bitcast_nxv2f32_to_nxv4i16(<vscale x 2 x float> %v) #
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1149,10 +1100,9 @@ define <vscale x 4 x i16> @bitcast_nxv2f32_to_nxv4i16(<vscale x 2 x float> %v) #
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1168,9 +1118,8 @@ define <vscale x 4 x i16> @bitcast_nxv1f64_to_nxv4i16(<vscale x 1 x double> %v)
;
; CHECK_BE-LABEL: bitcast_nxv1f64_to_nxv4i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: ret
@@ -1187,7 +1136,6 @@ define <vscale x 4 x i16> @bitcast_nxv4bf16_to_nxv4i16(<vscale x 4 x bfloat> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x bfloat> %v to <vscale x 4 x i16>
@@ -1204,9 +1152,8 @@ define <vscale x 2 x i32> @bitcast_nxv8i8_to_nxv2i32(<vscale x 8 x i8> %v) #0 {
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1216,9 +1163,8 @@ define <vscale x 2 x i32> @bitcast_nxv8i8_to_nxv2i32(<vscale x 8 x i8> %v) #0 {
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.h
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1232,9 +1178,8 @@ define <vscale x 2 x i32> @bitcast_nxv4i16_to_nxv2i32(<vscale x 4 x i16> %v) #0
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1244,9 +1189,8 @@ define <vscale x 2 x i32> @bitcast_nxv4i16_to_nxv2i32(<vscale x 4 x i16> %v) #0
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1262,9 +1206,8 @@ define <vscale x 2 x i32> @bitcast_nxv1i64_to_nxv2i32(<vscale x 1 x i64> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv1i64_to_nxv2i32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: uunpklo z0.d, z0.s
; CHECK_BE-NEXT: ret
@@ -1278,9 +1221,8 @@ define <vscale x 2 x i32> @bitcast_nxv4f16_to_nxv2i32(<vscale x 4 x half> %v) #0
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1290,9 +1232,8 @@ define <vscale x 2 x i32> @bitcast_nxv4f16_to_nxv2i32(<vscale x 4 x half> %v) #0
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1309,7 +1250,6 @@ define <vscale x 2 x i32> @bitcast_nxv2f32_to_nxv2i32(<vscale x 2 x float> %v) #
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x float> %v to <vscale x 2 x i32>
@@ -1324,9 +1264,8 @@ define <vscale x 2 x i32> @bitcast_nxv1f64_to_nxv2i32(<vscale x 1 x double> %v)
;
; CHECK_BE-LABEL: bitcast_nxv1f64_to_nxv2i32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: uunpklo z0.d, z0.s
; CHECK_BE-NEXT: ret
@@ -1340,9 +1279,8 @@ define <vscale x 2 x i32> @bitcast_nxv4bf16_to_nxv2i32(<vscale x 4 x bfloat> %v)
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1352,9 +1290,8 @@ define <vscale x 2 x i32> @bitcast_nxv4bf16_to_nxv2i32(<vscale x 4 x bfloat> %v)
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1393,7 +1330,6 @@ define <vscale x 1 x i64> @bitcast_nxv4i16_to_nxv1i64(<vscale x 4 x i16> %v) #0
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i16> %v to <vscale x 1 x i64>
@@ -1411,7 +1347,6 @@ define <vscale x 1 x i64> @bitcast_nxv2i32_to_nxv1i64(<vscale x 2 x i32> %v) #0
; CHECK_BE-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i32> %v to <vscale x 1 x i64>
@@ -1429,7 +1364,6 @@ define <vscale x 1 x i64> @bitcast_nxv4f16_to_nxv1i64(<vscale x 4 x half> %v) #0
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x half> %v to <vscale x 1 x i64>
@@ -1447,7 +1381,6 @@ define <vscale x 1 x i64> @bitcast_nxv2f32_to_nxv1i64(<vscale x 2 x float> %v) #
; CHECK_BE-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x float> %v to <vscale x 1 x i64>
@@ -1477,7 +1410,6 @@ define <vscale x 1 x i64> @bitcast_nxv4bf16_to_nxv1i64(<vscale x 4 x bfloat> %v)
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x bfloat> %v to <vscale x 1 x i64>
@@ -1494,9 +1426,8 @@ define <vscale x 4 x half> @bitcast_nxv8i8_to_nxv4f16(<vscale x 8 x i8> %v) #0 {
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1506,9 +1437,8 @@ define <vscale x 4 x half> @bitcast_nxv8i8_to_nxv4f16(<vscale x 8 x i8> %v) #0 {
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.h
-; CHECK_BE-NEXT: ptrue p1.s
; CHECK_BE-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1523,9 +1453,8 @@ define <vscale x 4 x half> @bitcast_nxv4i16_to_nxv4f16(<vscale x 4 x i16> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv4i16_to_nxv4f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i16> %v to <vscale x 4 x half>
@@ -1537,10 +1466,9 @@ define <vscale x 4 x half> @bitcast_nxv2i32_to_nxv4f16(<vscale x 2 x i32> %v) #0
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1549,10 +1477,9 @@ define <vscale x 4 x half> @bitcast_nxv2i32_to_nxv4f16(<vscale x 2 x i32> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1568,9 +1495,8 @@ define <vscale x 4 x half> @bitcast_nxv1i64_to_nxv4f16(<vscale x 1 x i64> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv1i64_to_nxv4f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: ret
@@ -1583,10 +1509,9 @@ define <vscale x 4 x half> @bitcast_nxv2f32_to_nxv4f16(<vscale x 2 x float> %v)
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1595,10 +1520,9 @@ define <vscale x 4 x half> @bitcast_nxv2f32_to_nxv4f16(<vscale x 2 x float> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1614,9 +1538,8 @@ define <vscale x 4 x half> @bitcast_nxv1f64_to_nxv4f16(<vscale x 1 x double> %v)
;
; CHECK_BE-LABEL: bitcast_nxv1f64_to_nxv4f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: ret
@@ -1646,9 +1569,8 @@ define <vscale x 2 x float> @bitcast_nxv8i8_to_nxv2f32(<vscale x 8 x i8> %v) #0
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1658,9 +1580,8 @@ define <vscale x 2 x float> @bitcast_nxv8i8_to_nxv2f32(<vscale x 8 x i8> %v) #0
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.h
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1674,9 +1595,8 @@ define <vscale x 2 x float> @bitcast_nxv4i16_to_nxv2f32(<vscale x 4 x i16> %v) #
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1686,9 +1606,8 @@ define <vscale x 2 x float> @bitcast_nxv4i16_to_nxv2f32(<vscale x 4 x i16> %v) #
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1703,9 +1622,8 @@ define <vscale x 2 x float> @bitcast_nxv2i32_to_nxv2f32(<vscale x 2 x i32> %v) #
;
; CHECK_BE-LABEL: bitcast_nxv2i32_to_nxv2f32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i32> %v to <vscale x 2 x float>
@@ -1720,9 +1638,8 @@ define <vscale x 2 x float> @bitcast_nxv1i64_to_nxv2f32(<vscale x 1 x i64> %v) #
;
; CHECK_BE-LABEL: bitcast_nxv1i64_to_nxv2f32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: uunpklo z0.d, z0.s
; CHECK_BE-NEXT: ret
@@ -1736,9 +1653,8 @@ define <vscale x 2 x float> @bitcast_nxv4f16_to_nxv2f32(<vscale x 4 x half> %v)
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1748,9 +1664,8 @@ define <vscale x 2 x float> @bitcast_nxv4f16_to_nxv2f32(<vscale x 4 x half> %v)
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1766,9 +1681,8 @@ define <vscale x 2 x float> @bitcast_nxv1f64_to_nxv2f32(<vscale x 1 x double> %v
;
; CHECK_BE-LABEL: bitcast_nxv1f64_to_nxv2f32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.s
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: uunpklo z0.d, z0.s
; CHECK_BE-NEXT: ret
@@ -1782,9 +1696,8 @@ define <vscale x 2 x float> @bitcast_nxv4bf16_to_nxv2f32(<vscale x 4 x bfloat> %
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1794,9 +1707,8 @@ define <vscale x 2 x float> @bitcast_nxv4bf16_to_nxv2f32(<vscale x 4 x bfloat> %
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1835,7 +1747,6 @@ define <vscale x 1 x double> @bitcast_nxv4i16_to_nxv1f64(<vscale x 4 x i16> %v)
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i16> %v to <vscale x 1 x double>
@@ -1853,7 +1764,6 @@ define <vscale x 1 x double> @bitcast_nxv2i32_to_nxv1f64(<vscale x 2 x i32> %v)
; CHECK_BE-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i32> %v to <vscale x 1 x double>
@@ -1883,7 +1793,6 @@ define <vscale x 1 x double> @bitcast_nxv4f16_to_nxv1f64(<vscale x 4 x half> %v)
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x half> %v to <vscale x 1 x double>
@@ -1901,7 +1810,6 @@ define <vscale x 1 x double> @bitcast_nxv2f32_to_nxv1f64(<vscale x 2 x float> %v
; CHECK_BE-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x float> %v to <vscale x 1 x double>
@@ -1919,7 +1827,6 @@ define <vscale x 1 x double> @bitcast_nxv4bf16_to_nxv1f64(<vscale x 4 x bfloat>
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x bfloat> %v to <vscale x 1 x double>
@@ -1936,9 +1843,8 @@ define <vscale x 4 x bfloat> @bitcast_nxv8i8_to_nxv4bf16(<vscale x 8 x i8> %v) #
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1948,9 +1854,8 @@ define <vscale x 4 x bfloat> @bitcast_nxv8i8_to_nxv4bf16(<vscale x 8 x i8> %v) #
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.h
-; CHECK_BE-NEXT: ptrue p1.s
; CHECK_BE-NEXT: st1b { z0.h }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -1965,9 +1870,8 @@ define <vscale x 4 x bfloat> @bitcast_nxv4i16_to_nxv4bf16(<vscale x 4 x i16> %v)
;
; CHECK_BE-LABEL: bitcast_nxv4i16_to_nxv4bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 4 x i16> %v to <vscale x 4 x bfloat>
@@ -1979,10 +1883,9 @@ define <vscale x 4 x bfloat> @bitcast_nxv2i32_to_nxv4bf16(<vscale x 2 x i32> %v)
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -1991,10 +1894,9 @@ define <vscale x 4 x bfloat> @bitcast_nxv2i32_to_nxv4bf16(<vscale x 2 x i32> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2010,9 +1912,8 @@ define <vscale x 4 x bfloat> @bitcast_nxv1i64_to_nxv4bf16(<vscale x 1 x i64> %v)
;
; CHECK_BE-LABEL: bitcast_nxv1i64_to_nxv4bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: ret
@@ -2037,10 +1938,9 @@ define <vscale x 4 x bfloat> @bitcast_nxv2f32_to_nxv4bf16(<vscale x 2 x float> %
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2049,10 +1949,9 @@ define <vscale x 4 x bfloat> @bitcast_nxv2f32_to_nxv4bf16(<vscale x 2 x float> %
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1w { z0.d }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.s }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.s }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2068,9 +1967,8 @@ define <vscale x 4 x bfloat> @bitcast_nxv1f64_to_nxv4bf16(<vscale x 1 x double>
;
; CHECK_BE-LABEL: bitcast_nxv1f64_to_nxv4bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: ret
@@ -2087,10 +1985,9 @@ define <vscale x 4 x i8> @bitcast_nxv2i16_to_nxv4i8(<vscale x 2 x i16> %v) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ld1b { z0.s }, p1/z, [sp, #3, mul vl]
+; CHECK-NEXT: ld1b { z0.s }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2099,10 +1996,9 @@ define <vscale x 4 x i8> @bitcast_nxv2i16_to_nxv4i8(<vscale x 2 x i16> %v) #0 {
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.s }, p1/z, [sp, #3, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.s }, p0/z, [sp, #3, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2133,10 +2029,9 @@ define <vscale x 4 x i8> @bitcast_nxv2f16_to_nxv4i8(<vscale x 2 x half> %v) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ld1b { z0.s }, p1/z, [sp, #3, mul vl]
+; CHECK-NEXT: ld1b { z0.s }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2145,10 +2040,9 @@ define <vscale x 4 x i8> @bitcast_nxv2f16_to_nxv4i8(<vscale x 2 x half> %v) #0 {
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.s }, p1/z, [sp, #3, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.s }, p0/z, [sp, #3, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2163,10 +2057,9 @@ define <vscale x 4 x i8> @bitcast_nxv2bf16_to_nxv4i8(<vscale x 2 x bfloat> %v) #
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ld1b { z0.s }, p1/z, [sp, #3, mul vl]
+; CHECK-NEXT: ld1b { z0.s }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2175,10 +2068,9 @@ define <vscale x 4 x i8> @bitcast_nxv2bf16_to_nxv4i8(<vscale x 2 x bfloat> %v) #
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: st1h { z0.d }, p0, [sp, #3, mul vl]
-; CHECK_BE-NEXT: ld1b { z0.s }, p1/z, [sp, #3, mul vl]
+; CHECK_BE-NEXT: ld1b { z0.s }, p0/z, [sp, #3, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2196,9 +2088,8 @@ define <vscale x 2 x i16> @bitcast_nxv4i8_to_nxv2i16(<vscale x 4 x i8> %v) #0 {
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1b { z0.s }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ld1h { z0.d }, p1/z, [sp, #3, mul vl]
+; CHECK-NEXT: ld1h { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2208,9 +2099,8 @@ define <vscale x 2 x i16> @bitcast_nxv4i8_to_nxv2i16(<vscale x 4 x i8> %v) #0 {
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1b { z0.s }, p0, [sp, #3, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.d }, p1/z, [sp, #3, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2227,9 +2117,8 @@ define <vscale x 2 x i16> @bitcast_nxv1i32_to_nxv2i16(<vscale x 1 x i32> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv1i32_to_nxv2i16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: uunpklo z0.s, z0.h
; CHECK_BE-NEXT: uunpklo z0.d, z0.s
@@ -2247,7 +2136,6 @@ define <vscale x 2 x i16> @bitcast_nxv2f16_to_nxv2i16(<vscale x 2 x half> %v) #0
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x half> %v to <vscale x 2 x i16>
@@ -2265,7 +2153,6 @@ define <vscale x 2 x i16> @bitcast_nxv2bf16_to_nxv2i16(<vscale x 2 x bfloat> %v)
; CHECK_BE: // %bb.0:
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.d
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x bfloat> %v to <vscale x 2 x i16>
@@ -2307,7 +2194,6 @@ define <vscale x 1 x i32> @bitcast_nxv2i16_to_nxv1i32(<vscale x 2 x i16> %v) #0
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i16> %v to <vscale x 1 x i32>
@@ -2327,7 +2213,6 @@ define <vscale x 1 x i32> @bitcast_nxv2f16_to_nxv1i32(<vscale x 2 x half> %v) #0
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x half> %v to <vscale x 1 x i32>
@@ -2349,7 +2234,6 @@ define <vscale x 1 x i32> @bitcast_nxv2bf16_to_nxv1i32(<vscale x 2 x bfloat> %v)
; CHECK_BE-NEXT: ptrue p0.h
; CHECK_BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
-; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x bfloat> %v to <vscale x 1 x i32>
@@ -2366,9 +2250,8 @@ define <vscale x 2 x half> @bitcast_nxv4i8_to_nxv2f16(<vscale x 4 x i8> %v) #0 {
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1b { z0.s }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ld1h { z0.d }, p1/z, [sp, #3, mul vl]
+; CHECK-NEXT: ld1h { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2378,9 +2261,8 @@ define <vscale x 2 x half> @bitcast_nxv4i8_to_nxv2f16(<vscale x 4 x i8> %v) #0 {
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1b { z0.s }, p0, [sp, #3, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.d }, p1/z, [sp, #3, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2395,9 +2277,8 @@ define <vscale x 2 x half> @bitcast_nxv2i16_to_nxv2f16(<vscale x 2 x i16> %v) #0
;
; CHECK_BE-LABEL: bitcast_nxv2i16_to_nxv2f16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i16> %v to <vscale x 2 x half>
@@ -2439,9 +2320,8 @@ define <vscale x 2 x bfloat> @bitcast_nxv4i8_to_nxv2bf16(<vscale x 4 x i8> %v) #
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: st1b { z0.s }, p0, [sp, #3, mul vl]
-; CHECK-NEXT: ld1h { z0.d }, p1/z, [sp, #3, mul vl]
+; CHECK-NEXT: ld1h { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2451,9 +2331,8 @@ define <vscale x 2 x bfloat> @bitcast_nxv4i8_to_nxv2bf16(<vscale x 4 x i8> %v) #
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: st1b { z0.s }, p0, [sp, #3, mul vl]
-; CHECK_BE-NEXT: ld1h { z0.d }, p1/z, [sp, #3, mul vl]
+; CHECK_BE-NEXT: ld1h { z0.d }, p0/z, [sp, #3, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
@@ -2468,9 +2347,8 @@ define <vscale x 2 x bfloat> @bitcast_nxv2i16_to_nxv2bf16(<vscale x 2 x i16> %v)
;
; CHECK_BE-LABEL: bitcast_nxv2i16_to_nxv2bf16:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ptrue p0.h
+; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK_BE-NEXT: ret
%bc = bitcast <vscale x 2 x i16> %v to <vscale x 2 x bfloat>
@@ -2576,10 +2454,9 @@ define <vscale x 2 x i32> @bitcast_short_float_to_i32(<vscale x 2 x double> %v)
;
; CHECK_BE-LABEL: bitcast_short_float_to_i32:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: fcvt z0.s, p0/m, z0.d
-; CHECK_BE-NEXT: revb z0.s, p1/m, z0.s
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
; CHECK_BE-NEXT: ret
%trunc = fptrunc <vscale x 2 x double> %v to <vscale x 2 x float>
@@ -2596,10 +2473,9 @@ define <vscale x 2 x double> @bitcast_short_i32_to_float(<vscale x 2 x i64> %v)
;
; CHECK_BE-LABEL: bitcast_short_i32_to_float:
; CHECK_BE: // %bb.0:
-; CHECK_BE-NEXT: ptrue p0.d
-; CHECK_BE-NEXT: ptrue p1.s
+; CHECK_BE-NEXT: ptrue p0.s
; CHECK_BE-NEXT: revb z0.d, p0/m, z0.d
-; CHECK_BE-NEXT: revb z0.s, p1/m, z0.s
+; CHECK_BE-NEXT: revb z0.s, p0/m, z0.s
; CHECK_BE-NEXT: fcvt z0.d, p0/m, z0.s
; CHECK_BE-NEXT: ret
%trunc = trunc <vscale x 2 x i64> %v to <vscale x 2 x i32>
@@ -2614,10 +2490,9 @@ define <vscale x 2 x float> @bitcast_short_half_to_float(<vscale x 4 x half> %v)
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-1
; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z0.h
; CHECK-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
@@ -2627,10 +2502,9 @@ define <vscale x 2 x float> @bitcast_short_half_to_float(<vscale x 4 x half> %v)
; CHECK_BE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK_BE-NEXT: addvl sp, sp, #-1
; CHECK_BE-NEXT: ptrue p0.s
-; CHECK_BE-NEXT: ptrue p1.d
; CHECK_BE-NEXT: fadd z0.h, p0/m, z0.h, z0.h
; CHECK_BE-NEXT: st1h { z0.s }, p0, [sp, #1, mul vl]
-; CHECK_BE-NEXT: ld1w { z0.d }, p1/z, [sp, #1, mul vl]
+; CHECK_BE-NEXT: ld1w { z0.d }, p0/z, [sp, #1, mul vl]
; CHECK_BE-NEXT: addvl sp, sp, #1
; CHECK_BE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK_BE-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sve-fpext-load.ll b/llvm/test/CodeGen/AArch64/sve-fpext-load.ll
index 9812c3775d4160..39973201d64fbb 100644
--- a/llvm/test/CodeGen/AArch64/sve-fpext-load.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fpext-load.ll
@@ -20,7 +20,6 @@ define <vscale x 4 x double> @ext4_f16_f64(ptr %ptr, i64 %index) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z2.d, z0.s
; CHECK-NEXT: movprfx z0, z1
diff --git a/llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll b/llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
index 3e2aed22764c52..e9a238cd43f377 100644
--- a/llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+disable-unpredicated-ld-st-lower < %s | FileCheck --check-prefixes=COMMON-NO-UPLS-LOWER,NO-UPLS-LOWER %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=a64fx < %s | FileCheck --check-prefixes=COMMON-NO-UPLS-LOWER,A64FX %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+disable-unpredicated-ld-st-lower < %s | FileCheck --check-prefix=COMMON-NO-UPLS-LOWER %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=a64fx < %s | FileCheck --check-prefix=COMMON-NO-UPLS-LOWER %s
; LD1B
@@ -13,8 +13,8 @@ define <vscale x 16 x i8> @ld1b_lower_bound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1b_lower_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, #-8, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, #-8, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 -8
%load = load <vscale x 16 x i8>, ptr %base
@@ -29,8 +29,8 @@ define <vscale x 16 x i8> @ld1b_inbound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1b_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, #2, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 2
%load = load <vscale x 16 x i8>, ptr %base
@@ -45,8 +45,8 @@ define <vscale x 16 x i8> @ld1b_upper_bound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1b_upper_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, #7, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, #7, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 7
%load = load <vscale x 16 x i8>, ptr %base
@@ -61,9 +61,9 @@ define <vscale x 16 x i8> @ld1b_out_of_upper_bound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1b_out_of_upper_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #8
-; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #8
+; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 8
%load = load <vscale x 16 x i8>, ptr %base
@@ -78,9 +78,9 @@ define <vscale x 16 x i8> @ld1b_out_of_lower_bound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1b_out_of_lower_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #-9
-; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #-9
+; COMMON-NO-UPLS-LOWER-NEXT: ld1b { z0.b }, p0/z, [x0, x8]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 -9
%load = load <vscale x 16 x i8>, ptr %base
@@ -97,8 +97,8 @@ define <vscale x 8 x i16> @ld1h_inbound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1h_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.h
-; COMMON-NO-UPLS-LOWER-NEXT: ld1h { z0.h }, p0/z, [x0, #-2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.h
+; COMMON-NO-UPLS-LOWER-NEXT: ld1h { z0.h }, p0/z, [x0, #-2, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, ptr %a, i64 -2
%load = load <vscale x 8 x i16>, ptr %base
@@ -115,8 +115,8 @@ define <vscale x 4 x i32> @ld1s_inbound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1s_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
-; COMMON-NO-UPLS-LOWER-NEXT: ld1w { z0.s }, p0/z, [x0, #4, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
+; COMMON-NO-UPLS-LOWER-NEXT: ld1w { z0.s }, p0/z, [x0, #4, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, ptr %a, i64 4
%load = load <vscale x 4 x i32>, ptr %base
@@ -133,8 +133,8 @@ define <vscale x 2 x i64> @ld1d_inbound(ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: ld1d_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.d
-; COMMON-NO-UPLS-LOWER-NEXT: ld1d { z0.d }, p0/z, [x0, #6, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.d
+; COMMON-NO-UPLS-LOWER-NEXT: ld1d { z0.d }, p0/z, [x0, #6, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, ptr %a, i64 6
%load = load <vscale x 2 x i64>, ptr %base
@@ -144,27 +144,17 @@ define <vscale x 2 x i64> @ld1d_inbound(ptr %a) {
define void @load_nxv6f16(ptr %a) {
; CHECK-LABEL: load_nxv6f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ld1h { z0.s }, p1/z, [x0]
+; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ret
;
-; NO-UPLS-LOWER-LABEL: load_nxv6f16:
-; NO-UPLS-LOWER: // %bb.0:
-; NO-UPLS-LOWER-NEXT: ptrue p0.d
-; NO-UPLS-LOWER-NEXT: ptrue p1.s
-; NO-UPLS-LOWER-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
-; NO-UPLS-LOWER-NEXT: ld1h { z0.s }, p1/z, [x0]
-; NO-UPLS-LOWER-NEXT: ret
-;
-; A64FX-LABEL: load_nxv6f16:
-; A64FX: // %bb.0:
-; A64FX-NEXT: ptrue p0.d
-; A64FX-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
-; A64FX-NEXT: ptrue p0.s
-; A64FX-NEXT: ld1h { z0.s }, p0/z, [x0]
-; A64FX-NEXT: ret
+; COMMON-NO-UPLS-LOWER-LABEL: load_nxv6f16:
+; COMMON-NO-UPLS-LOWER: // %bb.0:
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
+; COMMON-NO-UPLS-LOWER-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ld1h { z0.s }, p0/z, [x0]
+; COMMON-NO-UPLS-LOWER-NEXT: ret
%val = load volatile <vscale x 6 x half>, ptr %a
ret void
}
@@ -177,21 +167,12 @@ define void @load_nxv6f32(ptr %a) {
; CHECK-NEXT: ldr z0, [x0]
; CHECK-NEXT: ret
;
-; NO-UPLS-LOWER-LABEL: load_nxv6f32:
-; NO-UPLS-LOWER: // %bb.0:
-; NO-UPLS-LOWER-NEXT: ptrue p0.d
-; NO-UPLS-LOWER-NEXT: ptrue p1.s
-; NO-UPLS-LOWER-NEXT: ld1w { z0.d }, p0/z, [x0, #2, mul vl]
-; NO-UPLS-LOWER-NEXT: ld1w { z0.s }, p1/z, [x0]
-; NO-UPLS-LOWER-NEXT: ret
-;
-; A64FX-LABEL: load_nxv6f32:
-; A64FX: // %bb.0:
-; A64FX-NEXT: ptrue p0.d
-; A64FX-NEXT: ld1w { z0.d }, p0/z, [x0, #2, mul vl]
-; A64FX-NEXT: ptrue p0.s
-; A64FX-NEXT: ld1w { z0.s }, p0/z, [x0]
-; A64FX-NEXT: ret
+; COMMON-NO-UPLS-LOWER-LABEL: load_nxv6f32:
+; COMMON-NO-UPLS-LOWER: // %bb.0:
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
+; COMMON-NO-UPLS-LOWER-NEXT: ld1w { z0.d }, p0/z, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ld1w { z0.s }, p0/z, [x0]
+; COMMON-NO-UPLS-LOWER-NEXT: ret
%val = load volatile <vscale x 6 x float>, ptr %a
ret void
}
@@ -204,21 +185,12 @@ define void @load_nxv12f16(ptr %a) {
; CHECK-NEXT: ldr z0, [x0]
; CHECK-NEXT: ret
;
-; NO-UPLS-LOWER-LABEL: load_nxv12f16:
-; NO-UPLS-LOWER: // %bb.0:
-; NO-UPLS-LOWER-NEXT: ptrue p0.s
-; NO-UPLS-LOWER-NEXT: ptrue p1.h
-; NO-UPLS-LOWER-NEXT: ld1h { z0.s }, p0/z, [x0, #2, mul vl]
-; NO-UPLS-LOWER-NEXT: ld1h { z0.h }, p1/z, [x0]
-; NO-UPLS-LOWER-NEXT: ret
-;
-; A64FX-LABEL: load_nxv12f16:
-; A64FX: // %bb.0:
-; A64FX-NEXT: ptrue p0.s
-; A64FX-NEXT: ld1h { z0.s }, p0/z, [x0, #2, mul vl]
-; A64FX-NEXT: ptrue p0.h
-; A64FX-NEXT: ld1h { z0.h }, p0/z, [x0]
-; A64FX-NEXT: ret
+; COMMON-NO-UPLS-LOWER-LABEL: load_nxv12f16:
+; COMMON-NO-UPLS-LOWER: // %bb.0:
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.h
+; COMMON-NO-UPLS-LOWER-NEXT: ld1h { z0.s }, p0/z, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ld1h { z0.h }, p0/z, [x0]
+; COMMON-NO-UPLS-LOWER-NEXT: ret
%val = load volatile <vscale x 12 x half>, ptr %a
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll b/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
index 4f9dc9beb9e084..c39567b1898059 100644
--- a/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
+++ b/llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
@@ -76,12 +76,11 @@ define void @sve_load_store_nxv5i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv6i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv6i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ld1b { z1.s }, p1/z, [x0]
+; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
-; CHECK-NEXT: st1b { z1.s }, p1, [x1]
+; CHECK-NEXT: st1b { z1.s }, p0, [x1]
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uunpklo z0.d, z0.s
@@ -139,17 +138,16 @@ define void @sve_load_store_nxv9i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv10i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv10i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #4, mul vl]
-; CHECK-NEXT: ld1b { z1.h }, p1/z, [x0]
+; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z1.b, z0.b
; CHECK-NEXT: uunpkhi z1.h, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: st1b { z0.h }, p1, [x1]
+; CHECK-NEXT: st1b { z0.h }, p0, [x1]
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: st1b { z1.d }, p0, [x1, #4, mul vl]
; CHECK-NEXT: ret
@@ -177,16 +175,15 @@ define void @sve_load_store_nxv11i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv12i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv12i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ptrue p1.h
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ld1b { z1.h }, p1/z, [x0]
+; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z1.b, z0.b
; CHECK-NEXT: uunpkhi z1.h, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: st1b { z0.h }, p1, [x1]
+; CHECK-NEXT: st1b { z0.h }, p0, [x1]
; CHECK-NEXT: st1b { z1.s }, p0, [x1, #2, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 12 x i8>, ptr %a
@@ -213,22 +210,20 @@ define void @sve_load_store_nxv13i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv14i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv14i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: ptrue p2.h
-; CHECK-NEXT: ld1b { z1.s }, p1/z, [x0, #2, mul vl]
+; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
-; CHECK-NEXT: ld1b { z1.h }, p2/z, [x0]
+; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]
; CHECK-NEXT: uzp1 z0.b, z1.b, z0.b
; CHECK-NEXT: uunpkhi z1.h, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpkhi z2.s, z1.h
; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: st1b { z0.h }, p2, [x1]
+; CHECK-NEXT: st1b { z0.h }, p0, [x1]
; CHECK-NEXT: uunpklo z2.d, z2.s
-; CHECK-NEXT: st1b { z1.s }, p1, [x1, #2, mul vl]
+; CHECK-NEXT: st1b { z1.s }, p0, [x1, #2, mul vl]
; CHECK-NEXT: st1b { z2.d }, p0, [x1, #6, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 14 x i8>, ptr %a
@@ -365,9 +360,8 @@ define void @sve_load_store_nxv22i8(ptr %a, ptr %b) {
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: cntw x8, all, mul #5
; CHECK-NEXT: ldr z2, [x0]
-; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #4, mul vl]
-; CHECK-NEXT: ld1b { z1.d }, p1/z, [x0, x8]
+; CHECK-NEXT: ld1b { z1.d }, p0/z, [x0, x8]
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
@@ -379,7 +373,7 @@ define void @sve_load_store_nxv22i8(ptr %a, ptr %b) {
; CHECK-NEXT: uunpkhi z1.s, z0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: st1b { z1.d }, p1, [x1, x8]
+; CHECK-NEXT: st1b { z1.d }, p0, [x1, x8]
; CHECK-NEXT: st1b { z0.s }, p0, [x1, #4, mul vl]
; CHECK-NEXT: str z2, [x1]
; CHECK-NEXT: ret
@@ -445,12 +439,11 @@ define void @sve_load_store_nxv25i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv26i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv26i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: cnth x8, all, mul #3
; CHECK-NEXT: ldr z2, [x0]
-; CHECK-NEXT: ptrue p1.h
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, x8]
-; CHECK-NEXT: ld1b { z1.h }, p1/z, [x0, #2, mul vl]
+; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z1.b, z0.b
@@ -459,7 +452,7 @@ define void @sve_load_store_nxv26i8(ptr %a, ptr %b) {
; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: st1b { z1.d }, p0, [x1, x8]
-; CHECK-NEXT: st1b { z0.h }, p1, [x1, #2, mul vl]
+; CHECK-NEXT: st1b { z0.h }, p0, [x1, #2, mul vl]
; CHECK-NEXT: str z2, [x1]
; CHECK-NEXT: ret
%c = load <vscale x 26 x i8>, ptr %a
@@ -489,19 +482,18 @@ define void @sve_load_store_nxv27i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv28i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv28i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: ldr z2, [x0]
-; CHECK-NEXT: ptrue p1.h
-; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: ld1b { z1.h }, p1/z, [x0, #2, mul vl]
-; CHECK-NEXT: str z2, [x1]
-; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
-; CHECK-NEXT: uzp1 z0.b, z1.b, z0.b
-; CHECK-NEXT: uunpkhi z1.h, z0.b
-; CHECK-NEXT: uunpklo z0.h, z0.b
-; CHECK-NEXT: uunpklo z1.s, z1.h
-; CHECK-NEXT: st1b { z0.h }, p1, [x1, #2, mul vl]
-; CHECK-NEXT: st1b { z1.s }, p0, [x1, #6, mul vl]
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT: ld1b { z2.h }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: uzp1 z1.h, z1.h, z0.h
+; CHECK-NEXT: uzp1 z1.b, z2.b, z1.b
+; CHECK-NEXT: uunpkhi z2.h, z1.b
+; CHECK-NEXT: uunpklo z1.h, z1.b
+; CHECK-NEXT: uunpklo z2.s, z2.h
+; CHECK-NEXT: st1b { z1.h }, p0, [x1, #2, mul vl]
+; CHECK-NEXT: st1b { z2.s }, p0, [x1, #6, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 28 x i8>, ptr %a
store <vscale x 28 x i8> %c, ptr %b
@@ -530,14 +522,12 @@ define void @sve_load_store_nxv29i8(ptr %a, ptr %b) {
define void @sve_load_store_nxv30i8(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv30i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: cntw x8, all, mul #7
; CHECK-NEXT: ldr z3, [x0]
-; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0, x8]
-; CHECK-NEXT: ptrue p2.h
-; CHECK-NEXT: ld1b { z1.s }, p1/z, [x0, #6, mul vl]
-; CHECK-NEXT: ld1b { z2.h }, p2/z, [x0, #2, mul vl]
+; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT: ld1b { z2.h }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: uzp1 z0.b, z2.b, z0.b
@@ -547,8 +537,8 @@ define void @sve_load_store_nxv30i8(ptr %a, ptr %b) {
; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: st1b { z2.d }, p0, [x1, x8]
-; CHECK-NEXT: st1b { z0.h }, p2, [x1, #2, mul vl]
-; CHECK-NEXT: st1b { z1.s }, p1, [x1, #6, mul vl]
+; CHECK-NEXT: st1b { z0.h }, p0, [x1, #2, mul vl]
+; CHECK-NEXT: st1b { z1.s }, p0, [x1, #6, mul vl]
; CHECK-NEXT: str z3, [x1]
; CHECK-NEXT: ret
%c = load <vscale x 30 x i8>, ptr %a
@@ -661,16 +651,15 @@ define void @sve_load_store_nxv5i16(ptr %a, ptr %b) {
define void @sve_load_store_nxv6i16(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv6i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ld1h { z1.s }, p1/z, [x0]
+; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: uunpkhi z1.s, z0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: st1h { z0.s }, p1, [x1]
+; CHECK-NEXT: st1h { z0.s }, p0, [x1]
; CHECK-NEXT: st1h { z1.d }, p0, [x1, #2, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 6 x i16>, ptr %a
@@ -802,19 +791,18 @@ define void @sve_load_store_nxv13i16(ptr %a, ptr %b) {
define void @sve_load_store_nxv14i16(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv14i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z2, [x0]
-; CHECK-NEXT: ptrue p1.s
-; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: ld1h { z1.s }, p1/z, [x0, #2, mul vl]
-; CHECK-NEXT: str z2, [x1]
-; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
-; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
-; CHECK-NEXT: uunpkhi z1.s, z0.h
-; CHECK-NEXT: uunpklo z0.s, z0.h
-; CHECK-NEXT: uunpklo z1.d, z1.s
-; CHECK-NEXT: st1h { z0.s }, p1, [x1, #2, mul vl]
-; CHECK-NEXT: st1h { z1.d }, p0, [x1, #6, mul vl]
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT: ld1h { z2.s }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: uzp1 z1.s, z1.s, z0.s
+; CHECK-NEXT: uzp1 z1.h, z2.h, z1.h
+; CHECK-NEXT: uunpkhi z2.s, z1.h
+; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: uunpklo z2.d, z2.s
+; CHECK-NEXT: st1h { z1.s }, p0, [x1, #2, mul vl]
+; CHECK-NEXT: st1h { z2.d }, p0, [x1, #6, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 14 x i16>, ptr %a
store <vscale x 14 x i16> %c, ptr %b
@@ -1107,12 +1095,11 @@ define void @sve_load_store_nxv5f16(ptr %a, ptr %b) {
define void @sve_load_store_nxv6f16(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv6f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ld1h { z1.s }, p1/z, [x0]
+; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
; CHECK-NEXT: st1h { z0.d }, p0, [x1, #2, mul vl]
-; CHECK-NEXT: st1h { z1.s }, p1, [x1]
+; CHECK-NEXT: st1h { z1.s }, p0, [x1]
; CHECK-NEXT: ret
%c = load <vscale x 6 x half>, ptr %a
store <vscale x 6 x half> %c, ptr %b
@@ -1237,14 +1224,13 @@ define void @sve_load_store_nxv13f16(ptr %a, ptr %b) {
define void @sve_load_store_nxv14f16(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv14f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z2, [x0]
-; CHECK-NEXT: ptrue p1.s
-; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: ld1h { z1.s }, p1/z, [x0, #2, mul vl]
-; CHECK-NEXT: str z2, [x1]
-; CHECK-NEXT: st1h { z0.d }, p0, [x1, #6, mul vl]
-; CHECK-NEXT: st1h { z1.s }, p1, [x1, #2, mul vl]
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT: ld1h { z2.s }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: st1h { z1.d }, p0, [x1, #6, mul vl]
+; CHECK-NEXT: st1h { z2.s }, p0, [x1, #2, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 14 x half>, ptr %a
store <vscale x 14 x half> %c, ptr %b
@@ -1535,12 +1521,11 @@ define void @sve_load_store_nxv5bf16(ptr %a, ptr %b) {
define void @sve_load_store_nxv6bf16(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv6bf16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ptrue p1.s
+; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
-; CHECK-NEXT: ld1h { z1.s }, p1/z, [x0]
+; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
; CHECK-NEXT: st1h { z0.d }, p0, [x1, #2, mul vl]
-; CHECK-NEXT: st1h { z1.s }, p1, [x1]
+; CHECK-NEXT: st1h { z1.s }, p0, [x1]
; CHECK-NEXT: ret
%c = load <vscale x 6 x bfloat>, ptr %a
store <vscale x 6 x bfloat> %c, ptr %b
@@ -1665,14 +1650,13 @@ define void @sve_load_store_nxv13bf16(ptr %a, ptr %b) {
define void @sve_load_store_nxv14bf16(ptr %a, ptr %b) {
; CHECK-LABEL: sve_load_store_nxv14bf16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: ldr z2, [x0]
-; CHECK-NEXT: ptrue p1.s
-; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #6, mul vl]
-; CHECK-NEXT: ld1h { z1.s }, p1/z, [x0, #2, mul vl]
-; CHECK-NEXT: str z2, [x1]
-; CHECK-NEXT: st1h { z0.d }, p0, [x1, #6, mul vl]
-; CHECK-NEXT: st1h { z1.s }, p1, [x1, #2, mul vl]
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, #6, mul vl]
+; CHECK-NEXT: ld1h { z2.s }, p0/z, [x0, #2, mul vl]
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: st1h { z1.d }, p0, [x1, #6, mul vl]
+; CHECK-NEXT: st1h { z2.s }, p0, [x1, #2, mul vl]
; CHECK-NEXT: ret
%c = load <vscale x 14 x bfloat>, ptr %a
store <vscale x 14 x bfloat> %c, ptr %b
@@ -1968,14 +1952,13 @@ define <vscale x 14 x i16> @sve_sextload_nxv14i8(ptr %a, ptr %b) {
; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: whilelo p0.h, xzr, x8
; CHECK-NEXT: ld1sb { z2.h }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpkhi z1.s, z0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: str z2, [sp]
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: st1h { z0.s }, p1, [sp, #2, mul vl]
; CHECK-NEXT: ldr z0, [sp]
-; CHECK-NEXT: st1h { z1.d }, p0, [sp, #6, mul vl]
+; CHECK-NEXT: st1h { z1.d }, p1, [sp, #6, mul vl]
; CHECK-NEXT: ldr z1, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
@@ -2490,14 +2473,13 @@ define <vscale x 14 x i16> @sve_zextload_nxv14i8(ptr %a, ptr %b) {
; CHECK-NEXT: ld1sb { z0.h }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: whilelo p0.h, xzr, x8
; CHECK-NEXT: ld1sb { z2.h }, p0/z, [x0]
-; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpkhi z1.s, z0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: str z2, [sp]
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: st1h { z0.s }, p1, [sp, #2, mul vl]
; CHECK-NEXT: ldr z0, [sp]
-; CHECK-NEXT: st1h { z1.d }, p0, [sp, #6, mul vl]
+; CHECK-NEXT: st1h { z1.d }, p1, [sp, #6, mul vl]
; CHECK-NEXT: ldr z1, [sp, #1, mul vl]
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/sve-lsrchain.ll b/llvm/test/CodeGen/AArch64/sve-lsrchain.ll
index 17fd2d99603eb0..38be159d57d609 100644
--- a/llvm/test/CodeGen/AArch64/sve-lsrchain.ll
+++ b/llvm/test/CodeGen/AArch64/sve-lsrchain.ll
@@ -12,10 +12,9 @@ define void @test(ptr nocapture noundef readonly %kernel, i32 noundef %kw, float
; CHECK-NEXT: ands x11, x8, x9
; CHECK-NEXT: b.eq .LBB0_6
; CHECK-NEXT: // %bb.2: // %for.body.us.preheader
-; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: add x11, x2, x11, lsl #1
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: mov w8, wzr
-; CHECK-NEXT: ptrue p1.h
; CHECK-NEXT: mov x9, xzr
; CHECK-NEXT: mov w10, wzr
; CHECK-NEXT: mov x12, #4 // =0x4
@@ -47,43 +46,43 @@ define void @test(ptr nocapture noundef readonly %kernel, i32 noundef %kw, float
; CHECK-NEXT: add x18, x16, x14
; CHECK-NEXT: add x3, x17, #8
; CHECK-NEXT: add x4, x17, #16
-; CHECK-NEXT: fmad z4.h, p1/m, z0.h, z5.h
+; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
; CHECK-NEXT: ld1b { z5.b }, p0/z, [x16, x15]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z1.h
-; CHECK-NEXT: ld1h { z5.h }, p1/z, [x17, x12, lsl #1]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z2.h
-; CHECK-NEXT: ld1h { z5.h }, p1/z, [x17, x13, lsl #1]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z3.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
+; CHECK-NEXT: ld1h { z5.h }, p0/z, [x17, x12, lsl #1]
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
+; CHECK-NEXT: ld1h { z5.h }, p0/z, [x17, x13, lsl #1]
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
; CHECK-NEXT: ldr z5, [x16, #1, mul vl]
; CHECK-NEXT: str z4, [x16]
; CHECK-NEXT: ldr z4, [x18, #1, mul vl]
-; CHECK-NEXT: fmad z4.h, p1/m, z0.h, z5.h
+; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
; CHECK-NEXT: ldr z5, [x17, #1, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z1.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
; CHECK-NEXT: ldr z5, [x3, #1, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z2.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
; CHECK-NEXT: ldr z5, [x4, #1, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z3.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
; CHECK-NEXT: ldr z5, [x16, #2, mul vl]
; CHECK-NEXT: str z4, [x16, #1, mul vl]
; CHECK-NEXT: ldr z4, [x18, #2, mul vl]
-; CHECK-NEXT: fmad z4.h, p1/m, z0.h, z5.h
+; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
; CHECK-NEXT: ldr z5, [x17, #2, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z1.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
; CHECK-NEXT: ldr z5, [x3, #2, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z2.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
; CHECK-NEXT: ldr z5, [x4, #2, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z3.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
; CHECK-NEXT: ldr z5, [x16, #3, mul vl]
; CHECK-NEXT: str z4, [x16, #2, mul vl]
; CHECK-NEXT: ldr z4, [x18, #3, mul vl]
-; CHECK-NEXT: fmad z4.h, p1/m, z0.h, z5.h
+; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
; CHECK-NEXT: ldr z5, [x17, #3, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z1.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
; CHECK-NEXT: ldr z5, [x3, #3, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z2.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
; CHECK-NEXT: ldr z5, [x4, #3, mul vl]
-; CHECK-NEXT: fmla z4.h, p1/m, z5.h, z3.h
+; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
; CHECK-NEXT: str z4, [x16, #3, mul vl]
; CHECK-NEXT: incb x16, all, mul #4
; CHECK-NEXT: cmp x16, x11
diff --git a/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll b/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
index db6ead120c7de2..b03efa349583ad 100644
--- a/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
+++ b/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
@@ -816,7 +816,6 @@ define <vscale x 2 x i64> @sdot_different_types(<vscale x 2 x i64> %acc, <vscale
; CHECK-SVE2-NEXT: sunpklo z3.s, z1.h
; CHECK-SVE2-NEXT: sunpkhi z1.s, z1.h
; CHECK-SVE2-NEXT: sxtb z2.h, p0/m, z2.h
-; CHECK-SVE2-NEXT: ptrue p0.d
; CHECK-SVE2-NEXT: sunpklo z5.d, z3.s
; CHECK-SVE2-NEXT: sunpkhi z3.d, z3.s
; CHECK-SVE2-NEXT: sunpklo z4.s, z2.h
@@ -839,7 +838,6 @@ define <vscale x 2 x i64> @sdot_different_types(<vscale x 2 x i64> %acc, <vscale
; CHECK-SVE2-I8MM-NEXT: sunpklo z3.s, z1.h
; CHECK-SVE2-I8MM-NEXT: sunpkhi z1.s, z1.h
; CHECK-SVE2-I8MM-NEXT: sxtb z2.h, p0/m, z2.h
-; CHECK-SVE2-I8MM-NEXT: ptrue p0.d
; CHECK-SVE2-I8MM-NEXT: sunpklo z5.d, z3.s
; CHECK-SVE2-I8MM-NEXT: sunpkhi z3.d, z3.s
; CHECK-SVE2-I8MM-NEXT: sunpklo z4.s, z2.h
@@ -862,7 +860,6 @@ define <vscale x 2 x i64> @sdot_different_types(<vscale x 2 x i64> %acc, <vscale
; CHECK-SME-NEXT: sunpklo z3.s, z1.h
; CHECK-SME-NEXT: sunpkhi z1.s, z1.h
; CHECK-SME-NEXT: sxtb z2.h, p0/m, z2.h
-; CHECK-SME-NEXT: ptrue p0.d
; CHECK-SME-NEXT: sunpklo z5.d, z3.s
; CHECK-SME-NEXT: sunpkhi z3.d, z3.s
; CHECK-SME-NEXT: sunpklo z4.s, z2.h
@@ -893,7 +890,6 @@ define <vscale x 2 x i64> @usdot_different_types(<vscale x 2 x i64> %acc, <vscal
; CHECK-SVE2-NEXT: uunpklo z3.s, z1.h
; CHECK-SVE2-NEXT: uunpkhi z1.s, z1.h
; CHECK-SVE2-NEXT: sxtb z2.h, p0/m, z2.h
-; CHECK-SVE2-NEXT: ptrue p0.d
; CHECK-SVE2-NEXT: uunpklo z5.d, z3.s
; CHECK-SVE2-NEXT: uunpkhi z3.d, z3.s
; CHECK-SVE2-NEXT: sunpklo z4.s, z2.h
@@ -916,7 +912,6 @@ define <vscale x 2 x i64> @usdot_different_types(<vscale x 2 x i64> %acc, <vscal
; CHECK-SVE2-I8MM-NEXT: uunpklo z3.s, z1.h
; CHECK-SVE2-I8MM-NEXT: uunpkhi z1.s, z1.h
; CHECK-SVE2-I8MM-NEXT: sxtb z2.h, p0/m, z2.h
-; CHECK-SVE2-I8MM-NEXT: ptrue p0.d
; CHECK-SVE2-I8MM-NEXT: uunpklo z5.d, z3.s
; CHECK-SVE2-I8MM-NEXT: uunpkhi z3.d, z3.s
; CHECK-SVE2-I8MM-NEXT: sunpklo z4.s, z2.h
@@ -939,7 +934,6 @@ define <vscale x 2 x i64> @usdot_different_types(<vscale x 2 x i64> %acc, <vscal
; CHECK-SME-NEXT: uunpklo z3.s, z1.h
; CHECK-SME-NEXT: uunpkhi z1.s, z1.h
; CHECK-SME-NEXT: sxtb z2.h, p0/m, z2.h
-; CHECK-SME-NEXT: ptrue p0.d
; CHECK-SME-NEXT: uunpklo z5.d, z3.s
; CHECK-SME-NEXT: uunpkhi z3.d, z3.s
; CHECK-SME-NEXT: sunpklo z4.s, z2.h
diff --git a/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll b/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
index d9a602022256de..f65ed71c403533 100644
--- a/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
+++ b/llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
@@ -172,7 +172,6 @@ define <vscale x 2 x i32> @signed_wide_add_nxv4i16(<vscale x 2 x i32> %acc, <vsc
; CHECK-SVE2: // %bb.0: // %entry
; CHECK-SVE2-NEXT: ptrue p0.s
; CHECK-SVE2-NEXT: sxth z1.s, p0/m, z1.s
-; CHECK-SVE2-NEXT: ptrue p0.d
; CHECK-SVE2-NEXT: sadalp z0.d, p0/m, z1.s
; CHECK-SVE2-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll b/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
index 51a106e011d8b5..b195f8826e51e9 100644
--- a/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
+++ b/llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
@@ -204,13 +204,12 @@ define <vscale x 8 x i16> @sdiv_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.s, z1.h
; CHECK-NEXT: sunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sunpklo z1.s, z1.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: sunpklo z4.s, z0.h
; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z4.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z1.h, z1.h, z3.h
; CHECK-NEXT: mov z0.h, p1/m, z1.h
; CHECK-NEXT: ret
@@ -226,8 +225,9 @@ define <vscale x 16 x i8> @sdiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.h, z1.b
; CHECK-NEXT: sunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: sunpklo z1.h, z1.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: sunpkhi z5.s, z3.h
; CHECK-NEXT: sunpkhi z6.s, z4.h
; CHECK-NEXT: sunpklo z3.s, z3.h
@@ -242,8 +242,6 @@ define <vscale x 16 x i8> @sdiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z4.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z1.h, z1.h, z6.h
; CHECK-NEXT: uzp1 z1.b, z1.b, z3.b
; CHECK-NEXT: mov z0.b, p1/m, z1.b
@@ -290,13 +288,12 @@ define <vscale x 8 x i16> @udiv_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.s, z1.h
; CHECK-NEXT: uunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uunpklo z1.s, z1.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: uunpklo z4.s, z0.h
; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z4.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z1.h, z1.h, z3.h
; CHECK-NEXT: mov z0.h, p1/m, z1.h
; CHECK-NEXT: ret
@@ -312,8 +309,9 @@ define <vscale x 16 x i8> @udiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.h, z1.b
; CHECK-NEXT: uunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: uunpklo z1.h, z1.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uunpkhi z5.s, z3.h
; CHECK-NEXT: uunpkhi z6.s, z4.h
; CHECK-NEXT: uunpklo z3.s, z3.h
@@ -328,8 +326,6 @@ define <vscale x 16 x i8> @udiv_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z4.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z1.h, z1.h, z6.h
; CHECK-NEXT: uzp1 z1.b, z1.b, z3.b
; CHECK-NEXT: mov z0.b, p1/m, z1.b
@@ -378,13 +374,12 @@ define <vscale x 8 x i16> @srem_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.s, z1.h
; CHECK-NEXT: sunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sunpklo z5.s, z0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: sunpklo z4.s, z1.h
; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h
; CHECK-NEXT: mls z0.h, p1/m, z2.h, z1.h
; CHECK-NEXT: ret
@@ -400,7 +395,8 @@ define <vscale x 16 x i8> @srem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.h, z1.b
; CHECK-NEXT: sunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: sunpkhi z5.s, z3.h
; CHECK-NEXT: sunpkhi z6.s, z4.h
; CHECK-NEXT: sunpklo z3.s, z3.h
@@ -416,8 +412,6 @@ define <vscale x 16 x i8> @srem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z24.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z6.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b
; CHECK-NEXT: mls z0.b, p1/m, z2.b, z1.b
@@ -466,13 +460,12 @@ define <vscale x 8 x i16> @urem_nxv8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.s, z1.h
; CHECK-NEXT: uunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uunpklo z5.s, z0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: uunpklo z4.s, z1.h
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h
; CHECK-NEXT: mls z0.h, p1/m, z2.h, z1.h
; CHECK-NEXT: ret
@@ -488,7 +481,8 @@ define <vscale x 16 x i8> @urem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.h, z1.b
; CHECK-NEXT: uunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uunpkhi z5.s, z3.h
; CHECK-NEXT: uunpkhi z6.s, z4.h
; CHECK-NEXT: uunpklo z3.s, z3.h
@@ -504,8 +498,6 @@ define <vscale x 16 x i8> @urem_nxv16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z24.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z6.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b
; CHECK-NEXT: mls z0.b, p1/m, z2.b, z1.b
@@ -1653,13 +1645,12 @@ define <vscale x 8 x i16> @sdiv_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.s, z1.h
; CHECK-NEXT: sunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sunpklo z0.s, z0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: sunpklo z4.s, z1.h
; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z4.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
; CHECK-NEXT: ret
@@ -1675,8 +1666,9 @@ define <vscale x 16 x i8> @sdiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.h, z1.b
; CHECK-NEXT: sunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: sunpklo z0.h, z0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: sunpkhi z5.s, z3.h
; CHECK-NEXT: sunpkhi z6.s, z4.h
; CHECK-NEXT: sunpklo z3.s, z3.h
@@ -1691,8 +1683,6 @@ define <vscale x 16 x i8> @sdiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z4.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z0.h, z0.h, z6.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z3.b
; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
@@ -1739,13 +1729,12 @@ define <vscale x 8 x i16> @udiv_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.s, z1.h
; CHECK-NEXT: uunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: uunpklo z4.s, z1.h
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z4.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
; CHECK-NEXT: ret
@@ -1761,8 +1750,9 @@ define <vscale x 16 x i8> @udiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.h, z1.b
; CHECK-NEXT: uunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: uunpklo z0.h, z0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uunpkhi z5.s, z3.h
; CHECK-NEXT: uunpkhi z6.s, z4.h
; CHECK-NEXT: uunpklo z3.s, z3.h
@@ -1777,8 +1767,6 @@ define <vscale x 16 x i8> @udiv_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z4.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z0.h, z0.h, z6.h
; CHECK-NEXT: uzp1 z0.b, z0.b, z3.b
; CHECK-NEXT: sel z0.b, p1, z0.b, z1.b
@@ -1829,13 +1817,12 @@ define <vscale x 8 x i16> @srem_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.s, z1.h
; CHECK-NEXT: sunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: sunpklo z5.s, z0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: sunpklo z4.s, z1.h
; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h
; CHECK-NEXT: msb z1.h, p1/m, z2.h, z0.h
; CHECK-NEXT: mov z0.d, z1.d
@@ -1852,7 +1839,8 @@ define <vscale x 16 x i8> @srem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sunpkhi z3.h, z1.b
; CHECK-NEXT: sunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: sunpkhi z5.s, z3.h
; CHECK-NEXT: sunpkhi z6.s, z4.h
; CHECK-NEXT: sunpklo z3.s, z3.h
@@ -1868,8 +1856,6 @@ define <vscale x 16 x i8> @srem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z24.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z6.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b
; CHECK-NEXT: msb z1.b, p1/m, z2.b, z0.b
@@ -1921,13 +1907,12 @@ define <vscale x 8 x i16> @urem_nxv8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.s, z1.h
; CHECK-NEXT: uunpkhi z4.s, z0.h
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: uunpklo z5.s, z0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
; CHECK-NEXT: uunpklo z4.s, z1.h
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: cmpgt p1.h, p0/z, z2.h, #0
; CHECK-NEXT: uzp1 z2.h, z4.h, z3.h
; CHECK-NEXT: msb z1.h, p1/m, z2.h, z0.h
; CHECK-NEXT: mov z0.d, z1.d
@@ -1944,7 +1929,8 @@ define <vscale x 16 x i8> @urem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: uunpkhi z3.h, z1.b
; CHECK-NEXT: uunpkhi z4.h, z0.b
-; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uunpkhi z5.s, z3.h
; CHECK-NEXT: uunpkhi z6.s, z4.h
; CHECK-NEXT: uunpklo z3.s, z3.h
@@ -1960,8 +1946,6 @@ define <vscale x 16 x i8> @urem_nxv16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x
; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z24.s
; CHECK-NEXT: uzp1 z3.h, z3.h, z5.h
; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z6.s
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: cmpgt p1.b, p0/z, z2.b, #0
; CHECK-NEXT: uzp1 z4.h, z4.h, z7.h
; CHECK-NEXT: uzp1 z2.b, z4.b, z3.b
; CHECK-NEXT: msb z1.b, p1/m, z2.b, z0.b
diff --git a/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll b/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
index 28e3840fbc96ce..aebaadbac87511 100644
--- a/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
@@ -17,10 +17,9 @@ define void @lshr_trunc_i16_load_scalable(ptr %src, ptr %dst) #0 {
;
; BE-LABEL: lshr_trunc_i16_load_scalable:
; BE: // %bb.0:
-; BE-NEXT: ptrue p0.h
+; BE-NEXT: ptrue p0.b
; BE-NEXT: ld1h { z0.h }, p0/z, [x0, #1, mul vl]
; BE-NEXT: ld1h { z1.h }, p0/z, [x0]
-; BE-NEXT: ptrue p0.b
; BE-NEXT: uzp2 z0.b, z1.b, z0.b
; BE-NEXT: st1b { z0.b }, p0, [x1]
; BE-NEXT: ret
@@ -65,10 +64,9 @@ define void @ashr_trunc_i16_load(ptr %src, ptr %dst)#0 {
;
; BE-LABEL: ashr_trunc_i16_load:
; BE: // %bb.0:
-; BE-NEXT: ptrue p0.h
+; BE-NEXT: ptrue p0.b
; BE-NEXT: ld1h { z0.h }, p0/z, [x0, #1, mul vl]
; BE-NEXT: ld1h { z1.h }, p0/z, [x0]
-; BE-NEXT: ptrue p0.b
; BE-NEXT: uzp2 z0.b, z1.b, z0.b
; BE-NEXT: st1b { z0.b }, p0, [x1]
; BE-NEXT: ret
@@ -90,10 +88,9 @@ define void @lshr_trunc_i32_load(ptr %src, ptr %dst) #0 {
;
; BE-LABEL: lshr_trunc_i32_load:
; BE: // %bb.0:
-; BE-NEXT: ptrue p0.s
+; BE-NEXT: ptrue p0.h
; BE-NEXT: ld1w { z0.s }, p0/z, [x0, #1, mul vl]
; BE-NEXT: ld1w { z1.s }, p0/z, [x0]
-; BE-NEXT: ptrue p0.h
; BE-NEXT: uzp2 z0.h, z1.h, z0.h
; BE-NEXT: st1h { z0.h }, p0, [x1]
; BE-NEXT: ret
@@ -115,10 +112,9 @@ define void @lshr_trunc_i64_load(ptr %src, ptr %dst) #0 {
;
; BE-LABEL: lshr_trunc_i64_load:
; BE: // %bb.0:
-; BE-NEXT: ptrue p0.d
+; BE-NEXT: ptrue p0.s
; BE-NEXT: ld1d { z0.d }, p0/z, [x0, #1, mul vl]
; BE-NEXT: ld1d { z1.d }, p0/z, [x0]
-; BE-NEXT: ptrue p0.s
; BE-NEXT: uzp2 z0.s, z1.s, z0.s
; BE-NEXT: st1w { z0.s }, p0, [x1]
; BE-NEXT: ret
@@ -143,10 +139,9 @@ define void @lshr_trunc_wrong_amount(ptr %src, ptr %dst) #0 {
;
; BE-LABEL: lshr_trunc_wrong_amount:
; BE: // %bb.0:
-; BE-NEXT: ptrue p0.h
+; BE-NEXT: ptrue p0.b
; BE-NEXT: ld1h { z0.h }, p0/z, [x0]
; BE-NEXT: ld1h { z1.h }, p0/z, [x0, #1, mul vl]
-; BE-NEXT: ptrue p0.b
; BE-NEXT: lsr z1.h, z1.h, #7
; BE-NEXT: lsr z0.h, z0.h, #7
; BE-NEXT: uzp1 z0.b, z0.b, z1.b
diff --git a/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll b/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
index 35f39ce5069bdc..e223fede2a271f 100644
--- a/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+disable-unpredicated-ld-st-lower < %s | FileCheck --check-prefixes=COMMON-NO-UPLS-LOWER,NO-UPLS-LOWER %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=a64fx < %s | FileCheck --check-prefixes=COMMON-NO-UPLS-LOWER,A64FX %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+disable-unpredicated-ld-st-lower < %s | FileCheck --check-prefix=COMMON-NO-UPLS-LOWER %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=a64fx < %s | FileCheck --check-prefix=COMMON-NO-UPLS-LOWER %s
; ST1B
@@ -13,8 +13,8 @@ define void @st1b_lower_bound(<vscale x 16 x i8> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1b_lower_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, #-8, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, #-8, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 -8
store <vscale x 16 x i8> %data, ptr %base
@@ -29,8 +29,8 @@ define void @st1b_inbound(<vscale x 16 x i8> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1b_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, #1, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, #1, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 1
store <vscale x 16 x i8> %data, ptr %base
@@ -45,8 +45,8 @@ define void @st1b_upper_bound(<vscale x 16 x i8> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1b_upper_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, #7, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, #7, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 7
store <vscale x 16 x i8> %data, ptr %base
@@ -61,9 +61,9 @@ define void @st1b_out_of_upper_bound(<vscale x 16 x i8> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1b_out_of_upper_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #8
-; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, x8]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #8
+; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, x8]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 8
store <vscale x 16 x i8> %data, ptr %base
@@ -78,9 +78,9 @@ define void @st1b_out_of_lower_bound(<vscale x 16 x i8> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1b_out_of_lower_bound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
-; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #-9
-; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, x8]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.b
+; COMMON-NO-UPLS-LOWER-NEXT: rdvl x8, #-9
+; COMMON-NO-UPLS-LOWER-NEXT: st1b { z0.b }, p0, [x0, x8]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, ptr %a, i64 -9
store <vscale x 16 x i8> %data, ptr %base
@@ -97,8 +97,8 @@ define void @st1h_inbound(<vscale x 8 x i16> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1h_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.h
-; COMMON-NO-UPLS-LOWER-NEXT: st1h { z0.h }, p0, [x0, #-6, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.h
+; COMMON-NO-UPLS-LOWER-NEXT: st1h { z0.h }, p0, [x0, #-6, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, ptr %a, i64 -6
store <vscale x 8 x i16> %data, ptr %base
@@ -115,8 +115,8 @@ define void @st1w_inbound(<vscale x 4 x i32> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1w_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
-; COMMON-NO-UPLS-LOWER-NEXT: st1w { z0.s }, p0, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
+; COMMON-NO-UPLS-LOWER-NEXT: st1w { z0.s }, p0, [x0, #2, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, ptr %a, i64 2
store <vscale x 4 x i32> %data, ptr %base
@@ -133,8 +133,8 @@ define void @st1d_inbound(<vscale x 2 x i64> %data, ptr %a) {
;
; COMMON-NO-UPLS-LOWER-LABEL: st1d_inbound:
; COMMON-NO-UPLS-LOWER: // %bb.0:
-; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.d
-; COMMON-NO-UPLS-LOWER-NEXT: st1d { z0.d }, p0, [x0, #5, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.d
+; COMMON-NO-UPLS-LOWER-NEXT: st1d { z0.d }, p0, [x0, #5, mul vl]
; COMMON-NO-UPLS-LOWER-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, ptr %a, i64 5
store <vscale x 2 x i64> %data, ptr %base
@@ -191,23 +191,13 @@ define void @store_nxv6f32(ptr %out) {
; CHECK-NEXT: str z0, [x0]
; CHECK-NEXT: ret
;
-; NO-UPLS-LOWER-LABEL: store_nxv6f32:
-; NO-UPLS-LOWER: // %bb.0:
-; NO-UPLS-LOWER-NEXT: fmov z0.s, #1.00000000
-; NO-UPLS-LOWER-NEXT: ptrue p0.d
-; NO-UPLS-LOWER-NEXT: ptrue p1.s
-; NO-UPLS-LOWER-NEXT: st1w { z0.d }, p0, [x0, #2, mul vl]
-; NO-UPLS-LOWER-NEXT: st1w { z0.s }, p1, [x0]
-; NO-UPLS-LOWER-NEXT: ret
-;
-; A64FX-LABEL: store_nxv6f32:
-; A64FX: // %bb.0:
-; A64FX-NEXT: fmov z0.s, #1.00000000
-; A64FX-NEXT: ptrue p0.d
-; A64FX-NEXT: st1w { z0.d }, p0, [x0, #2, mul vl]
-; A64FX-NEXT: ptrue p0.s
-; A64FX-NEXT: st1w { z0.s }, p0, [x0]
-; A64FX-NEXT: ret
+; COMMON-NO-UPLS-LOWER-LABEL: store_nxv6f32:
+; COMMON-NO-UPLS-LOWER: // %bb.0:
+; COMMON-NO-UPLS-LOWER-NEXT: fmov z0.s, #1.00000000
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.s
+; COMMON-NO-UPLS-LOWER-NEXT: st1w { z0.d }, p0, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: st1w { z0.s }, p0, [x0]
+; COMMON-NO-UPLS-LOWER-NEXT: ret
store <vscale x 6 x float> splat(float 1.0), ptr %out
ret void
}
@@ -221,23 +211,13 @@ define void @store_nxv12f16(ptr %out) {
; CHECK-NEXT: str z0, [x0]
; CHECK-NEXT: ret
;
-; NO-UPLS-LOWER-LABEL: store_nxv12f16:
-; NO-UPLS-LOWER: // %bb.0:
-; NO-UPLS-LOWER-NEXT: fmov z0.h, #1.00000000
-; NO-UPLS-LOWER-NEXT: ptrue p0.s
-; NO-UPLS-LOWER-NEXT: ptrue p1.h
-; NO-UPLS-LOWER-NEXT: st1h { z0.s }, p0, [x0, #2, mul vl]
-; NO-UPLS-LOWER-NEXT: st1h { z0.h }, p1, [x0]
-; NO-UPLS-LOWER-NEXT: ret
-;
-; A64FX-LABEL: store_nxv12f16:
-; A64FX: // %bb.0:
-; A64FX-NEXT: fmov z0.h, #1.00000000
-; A64FX-NEXT: ptrue p0.s
-; A64FX-NEXT: st1h { z0.s }, p0, [x0, #2, mul vl]
-; A64FX-NEXT: ptrue p0.h
-; A64FX-NEXT: st1h { z0.h }, p0, [x0]
-; A64FX-NEXT: ret
+; COMMON-NO-UPLS-LOWER-LABEL: store_nxv12f16:
+; COMMON-NO-UPLS-LOWER: // %bb.0:
+; COMMON-NO-UPLS-LOWER-NEXT: fmov z0.h, #1.00000000
+; COMMON-NO-UPLS-LOWER-NEXT: ptrue p0.h
+; COMMON-NO-UPLS-LOWER-NEXT: st1h { z0.s }, p0, [x0, #2, mul vl]
+; COMMON-NO-UPLS-LOWER-NEXT: st1h { z0.h }, p0, [x0]
+; COMMON-NO-UPLS-LOWER-NEXT: ret
store <vscale x 12 x half> splat(half 1.0), ptr %out
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
index be6905d06097ea..f3e5605a752b61 100644
--- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
@@ -2264,12 +2264,11 @@ define i8 @bitmask_v8i32_sve(<8 x i32> %v) vscale_range(2,2) "target-features"="
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: splice z0.s, p0, z0.s, z1.s
-; CHECK-BE-NEXT: ptrue p0.s
+; CHECK-BE-NEXT: ptrue p0.h
; CHECK-BE-NEXT: ld1 { v1.8h }, [x8]
; CHECK-BE-NEXT: cmpne p1.s, p0/z, z0.s, #0
; CHECK-BE-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
; CHECK-BE-NEXT: revb z0.s, p0/m, z0.s
-; CHECK-BE-NEXT: ptrue p0.h
; CHECK-BE-NEXT: revb z0.h, p0/m, z0.h
; CHECK-BE-NEXT: uzp1 z0.h, z0.h, z0.h
; CHECK-BE-NEXT: and v0.16b, v0.16b, v1.16b
diff --git a/llvm/test/CodeGen/AArch64/vector-absolute-difference.ll b/llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
index da32588cea1a0f..4fc4e73a71fd02 100644
--- a/llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
+++ b/llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
@@ -33,7 +33,6 @@ define <vscale x 8 x i16> @sabs_nxv16i8_wide_add(<vscale x 8 x i16> %acc, <vscal
; SVE2: // %bb.0:
; SVE2-NEXT: ptrue p0.b
; SVE2-NEXT: sabd z1.b, p0/m, z1.b, z2.b
-; SVE2-NEXT: ptrue p0.h
; SVE2-NEXT: uadalp z0.h, p0/m, z1.b
; SVE2-NEXT: ret
;
@@ -54,7 +53,6 @@ define <vscale x 4 x i32> @sabs_nxv8i16_wide_add(<vscale x 4 x i32> %acc, <vscal
; SVE2: // %bb.0:
; SVE2-NEXT: ptrue p0.h
; SVE2-NEXT: sabd z1.h, p0/m, z1.h, z2.h
-; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: uadalp z0.s, p0/m, z1.h
; SVE2-NEXT: ret
;
@@ -75,7 +73,6 @@ define <vscale x 2 x i64> @sabs_nxv4i32_wide_add(<vscale x 2 x i64> %acc, <vscal
; SVE2: // %bb.0:
; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: sabd z1.s, p0/m, z1.s, z2.s
-; SVE2-NEXT: ptrue p0.d
; SVE2-NEXT: uadalp z0.d, p0/m, z1.s
; SVE2-NEXT: ret
;
@@ -134,7 +131,6 @@ define <vscale x 8 x i16> @uabs_nxv16i8_wide_add(<vscale x 8 x i16> %acc, <vscal
; SVE2: // %bb.0:
; SVE2-NEXT: ptrue p0.b
; SVE2-NEXT: uabd z1.b, p0/m, z1.b, z2.b
-; SVE2-NEXT: ptrue p0.h
; SVE2-NEXT: uadalp z0.h, p0/m, z1.b
; SVE2-NEXT: ret
;
@@ -155,7 +151,6 @@ define <vscale x 4 x i32> @uabs_nxv8i16_wide_add(<vscale x 4 x i32> %acc, <vscal
; SVE2: // %bb.0:
; SVE2-NEXT: ptrue p0.h
; SVE2-NEXT: uabd z1.h, p0/m, z1.h, z2.h
-; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: uadalp z0.s, p0/m, z1.h
; SVE2-NEXT: ret
;
@@ -176,7 +171,6 @@ define <vscale x 2 x i64> @uabs_nxv4i32_wide_add(<vscale x 2 x i64> %acc, <vscal
; SVE2: // %bb.0:
; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: uabd z1.s, p0/m, z1.s, z2.s
-; SVE2-NEXT: ptrue p0.d
; SVE2-NEXT: uadalp z0.d, p0/m, z1.s
; SVE2-NEXT: ret
;
diff --git a/llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
index 9f54e725043864..ef4e392e24f8ec 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
@@ -201,17 +201,16 @@ for.exit:
define void @mixed_offsets_fixed_then_scalable(ptr %src, ptr %dst, i64 %count) #0 {
; COMMON-LABEL: mixed_offsets_fixed_then_scalable:
; COMMON: // %bb.0: // %entry
-; COMMON-NEXT: ptrue p0.s
; COMMON-NEXT: rdvl x8, #4
+; COMMON-NEXT: ptrue p0.b
; COMMON-NEXT: mov x9, #8 // =0x8
-; COMMON-NEXT: ptrue p1.b
; COMMON-NEXT: orr x8, x8, #0x20
; COMMON-NEXT: .LBB4_1: // %for.body
; COMMON-NEXT: // =>This Inner Loop Header: Depth=1
; COMMON-NEXT: ldr z0, [x0]
; COMMON-NEXT: ld1w { z1.s }, p0/z, [x0, x9, lsl #2]
; COMMON-NEXT: decw x2
-; COMMON-NEXT: ld1b { z2.b }, p1/z, [x0, x8]
+; COMMON-NEXT: ld1b { z2.b }, p0/z, [x0, x8]
; COMMON-NEXT: incb x0
; COMMON-NEXT: add z0.s, z0.s, z1.s
; COMMON-NEXT: add z0.s, z0.s, z2.s
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