[llvm] 453900c - [X86] Prepare bdver tests for TuningPrefer128Bit (#226103)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 03:48:30 PDT 2026
Author: Simon Pilgrim
Date: 2026-09-24T10:48:21Z
New Revision: 453900c197e9bccfd9b9426338c22173d3021410
URL: https://github.com/llvm/llvm-project/commit/453900c197e9bccfd9b9426338c22173d3021410
DIFF: https://github.com/llvm/llvm-project/commit/453900c197e9bccfd9b9426338c22173d3021410.diff
LOG: [X86] Prepare bdver tests for TuningPrefer128Bit (#226103)
Ensure the check prefixes correctly handle XOP targets independently,
I've also reordered some of the tests so we can cleanly order the
eventual AVX128/AVX256/AVX512 checks
Help reduce the diff for #225838
Added:
Modified:
llvm/test/CodeGen/X86/memset.ll
llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
llvm/test/Transforms/SLPVectorizer/X86/fma.ll
llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/memset.ll b/llvm/test/CodeGen/X86/memset.ll
index 910c73a5097e9..f0715151c51e2 100644
--- a/llvm/test/CodeGen/X86/memset.ll
+++ b/llvm/test/CodeGen/X86/memset.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=XMM
-; RUN: llc < %s -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
+; RUN: llc < %s -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=AVX,AVX1
+; RUN: llc < %s -mcpu=haswell -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefixes=AVX,AVX2
%struct.x = type { i16, i16 }
@@ -23,29 +24,41 @@ define void @t() nounwind {
; X86-NEXT: addl $44, %esp
; X86-NEXT: retl
;
-; XMM-LABEL: t:
-; XMM: ## %bb.0: ## %entry
-; XMM-NEXT: subl $60, %esp
-; XMM-NEXT: xorps %xmm0, %xmm0
-; XMM-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; XMM-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; XMM-NEXT: leal {{[0-9]+}}(%esp), %eax
-; XMM-NEXT: movl %eax, (%esp)
-; XMM-NEXT: calll _foo
-; XMM-NEXT: addl $60, %esp
-; XMM-NEXT: retl
+; SSE-LABEL: t:
+; SSE: ## %bb.0: ## %entry
+; SSE-NEXT: subl $60, %esp
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
+; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
+; SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: movl %eax, (%esp)
+; SSE-NEXT: calll _foo
+; SSE-NEXT: addl $60, %esp
+; SSE-NEXT: retl
;
-; YMM-LABEL: t:
-; YMM: ## %bb.0: ## %entry
-; YMM-NEXT: subl $60, %esp
-; YMM-NEXT: leal {{[0-9]+}}(%esp), %eax
-; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; YMM-NEXT: vmovups %ymm0, {{[0-9]+}}(%esp)
-; YMM-NEXT: movl %eax, (%esp)
-; YMM-NEXT: vzeroupper
-; YMM-NEXT: calll _foo
-; YMM-NEXT: addl $60, %esp
-; YMM-NEXT: retl
+; AVX1-LABEL: t:
+; AVX1: ## %bb.0: ## %entry
+; AVX1-NEXT: subl $60, %esp
+; AVX1-NEXT: leal {{[0-9]+}}(%esp), %eax
+; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vmovups %ymm0, {{[0-9]+}}(%esp)
+; AVX1-NEXT: movl %eax, (%esp)
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: calll _foo
+; AVX1-NEXT: addl $60, %esp
+; AVX1-NEXT: retl
+;
+; AVX2-LABEL: t:
+; AVX2: ## %bb.0: ## %entry
+; AVX2-NEXT: subl $60, %esp
+; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX2-NEXT: vmovups %ymm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: leal {{[0-9]+}}(%esp), %eax
+; AVX2-NEXT: movl %eax, (%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll _foo
+; AVX2-NEXT: addl $60, %esp
+; AVX2-NEXT: retl
entry:
%up_mvd = alloca [8 x %struct.x] ; <ptr> [#uses=2]
%up_mvd116 = getelementptr [8 x %struct.x], ptr %up_mvd, i32 0, i32 0 ; <ptr> [#uses=1]
@@ -72,23 +85,23 @@ define void @PR15348(ptr %a) {
; X86-NEXT: movl $0, (%eax)
; X86-NEXT: retl
;
-; XMM-LABEL: PR15348:
-; XMM: ## %bb.0:
-; XMM-NEXT: movl {{[0-9]+}}(%esp), %eax
-; XMM-NEXT: movb $0, 16(%eax)
-; XMM-NEXT: movl $0, 12(%eax)
-; XMM-NEXT: movl $0, 8(%eax)
-; XMM-NEXT: movl $0, 4(%eax)
-; XMM-NEXT: movl $0, (%eax)
-; XMM-NEXT: retl
+; SSE-LABEL: PR15348:
+; SSE: ## %bb.0:
+; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT: movb $0, 16(%eax)
+; SSE-NEXT: movl $0, 12(%eax)
+; SSE-NEXT: movl $0, 8(%eax)
+; SSE-NEXT: movl $0, 4(%eax)
+; SSE-NEXT: movl $0, (%eax)
+; SSE-NEXT: retl
;
-; YMM-LABEL: PR15348:
-; YMM: ## %bb.0:
-; YMM-NEXT: movl {{[0-9]+}}(%esp), %eax
-; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; YMM-NEXT: vmovups %xmm0, (%eax)
-; YMM-NEXT: movb $0, 16(%eax)
-; YMM-NEXT: retl
+; AVX-LABEL: PR15348:
+; AVX: ## %bb.0:
+; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vmovups %xmm0, (%eax)
+; AVX-NEXT: movb $0, 16(%eax)
+; AVX-NEXT: retl
call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 17, i1 false)
ret void
}
@@ -110,30 +123,40 @@ define void @PR83077(ptr %a) {
; X86-NEXT: popl %edi
; X86-NEXT: retl
;
-; XMM-LABEL: PR83077:
-; XMM: ## %bb.0:
-; XMM-NEXT: pushl %edi
-; XMM-NEXT: .cfi_def_cfa_offset 8
-; XMM-NEXT: .cfi_offset %edi, -8
-; XMM-NEXT: movl {{[0-9]+}}(%esp), %edx
-; XMM-NEXT: movl $-1, %eax
-; XMM-NEXT: movl $22, %ecx
-; XMM-NEXT: movl %edx, %edi
-; XMM-NEXT: rep;stosl %eax, %es:(%edi)
-; XMM-NEXT: movw $-1, 88(%edx)
-; XMM-NEXT: popl %edi
-; XMM-NEXT: retl
+; SSE-LABEL: PR83077:
+; SSE: ## %bb.0:
+; SSE-NEXT: pushl %edi
+; SSE-NEXT: .cfi_def_cfa_offset 8
+; SSE-NEXT: .cfi_offset %edi, -8
+; SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
+; SSE-NEXT: movl $-1, %eax
+; SSE-NEXT: movl $22, %ecx
+; SSE-NEXT: movl %edx, %edi
+; SSE-NEXT: rep;stosl %eax, %es:(%edi)
+; SSE-NEXT: movw $-1, 88(%edx)
+; SSE-NEXT: popl %edi
+; SSE-NEXT: retl
+;
+; AVX1-LABEL: PR83077:
+; AVX1: ## %bb.0:
+; AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
+; AVX1-NEXT: vmovups %ymm0, 58(%eax)
+; AVX1-NEXT: vmovups %ymm0, 32(%eax)
+; AVX1-NEXT: vmovups %ymm0, (%eax)
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retl
;
-; YMM-LABEL: PR83077:
-; YMM: ## %bb.0:
-; YMM-NEXT: movl {{[0-9]+}}(%esp), %eax
-; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; YMM-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
-; YMM-NEXT: vmovups %ymm0, 58(%eax)
-; YMM-NEXT: vmovups %ymm0, 32(%eax)
-; YMM-NEXT: vmovups %ymm0, (%eax)
-; YMM-NEXT: vzeroupper
-; YMM-NEXT: retl
+; AVX2-LABEL: PR83077:
+; AVX2: ## %bb.0:
+; AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0
+; AVX2-NEXT: vmovdqu %ymm0, 58(%eax)
+; AVX2-NEXT: vmovdqu %ymm0, 32(%eax)
+; AVX2-NEXT: vmovdqu %ymm0, (%eax)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retl
call void @llvm.memset.p0.i32(ptr noundef nonnull align 4 dereferenceable(90) %a, i8 -1, i32 90, i1 false)
ret void
}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
index 9c7c1e353352b..daee52035f5a4 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
@@ -1,6 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -S %s | FileCheck %s --check-prefix=CHECK
-; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
+; RUN: opt -mcpu=sandybridge -passes=loop-vectorize -S %s | FileCheck %s --check-prefixes=CHECK,AVX1
+; RUN: opt -mcpu=haswell -passes=loop-vectorize -S %s | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -S %s | FileCheck %s --check-prefixes=CHECK,XOP
+; RUN: opt -mcpu=sandybridge -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefixes=CHECK-COST
+; RUN: opt -mcpu=haswell -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefixes=CHECK-COST
+; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefixes=CHECK-COST
; REQUIRES: asserts
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -135,103 +139,269 @@ while.end:
; CHECK-COST-LABEL: fshl
define void @fshl(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocapture noalias %pDst, i32 %blockSize) #0 {
-; CHECK-LABEL: @fshl(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
-; CHECK: iter.check:
-; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
-; CHECK: vector.main.loop.iter.check:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 128
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
-; CHECK: vector.ph:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 127
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
-; CHECK-NEXT: [[DOTCAST8:%.*]] = trunc i64 [[N_VEC]] to i32
-; CHECK-NEXT: [[IND_END9:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST8]]
-; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[N_VEC]]
-; CHECK-NEXT: [[IND_END14:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[N_VEC]]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <32 x i8> poison, i8 [[OFFSET:%.*]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <32 x i8> [[BROADCAST_SPLATINSERT]], <32 x i8> poison, <32 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX]]
-; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 32
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 64
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 96
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[NEXT_GEP]], align 2
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <32 x i8>, ptr [[TMP1]], align 2
-; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <32 x i8>, ptr [[TMP2]], align 2
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <32 x i8>, ptr [[TMP3]], align 2
-; CHECK-NEXT: [[TMP4:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD]], <32 x i8> [[WIDE_LOAD]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP5:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD3]], <32 x i8> [[WIDE_LOAD3]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP6:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD4]], <32 x i8> [[WIDE_LOAD4]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP7:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD5]], <32 x i8> [[WIDE_LOAD5]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 32
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 64
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 96
-; CHECK-NEXT: store <32 x i8> [[TMP4]], ptr [[NEXT_GEP2]], align 2
-; CHECK-NEXT: store <32 x i8> [[TMP5]], ptr [[TMP8]], align 2
-; CHECK-NEXT: store <32 x i8> [[TMP6]], ptr [[TMP9]], align 2
-; CHECK-NEXT: store <32 x i8> [[TMP7]], ptr [[TMP10]], align 2
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 128
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
-; CHECK: middle.block:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
-; CHECK: vec.epilog.iter.check:
-; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF7:![0-9]+]]
-; CHECK: vec.epilog.ph:
-; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[N_MOD_VF6:%.*]] = and i64 [[TMP0]], 7
-; CHECK-NEXT: [[N_VEC7:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF6]]
-; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC7]] to i32
-; CHECK-NEXT: [[IND_END:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST]]
-; CHECK-NEXT: [[IND_END10:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC7]]
-; CHECK-NEXT: [[IND_END13:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC7]]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT20:%.*]] = insertelement <8 x i8> poison, i8 [[OFFSET]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT21:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT20]], <8 x i8> poison, <8 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
-; CHECK: vec.epilog.vector.body:
-; CHECK-NEXT: [[INDEX16:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT22:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
-; CHECK-NEXT: [[NEXT_GEP17:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX16]]
-; CHECK-NEXT: [[NEXT_GEP18:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX16]]
-; CHECK-NEXT: [[WIDE_LOAD19:%.*]] = load <8 x i8>, ptr [[NEXT_GEP17]], align 2
-; CHECK-NEXT: [[TMP12:%.*]] = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> [[WIDE_LOAD19]], <8 x i8> [[WIDE_LOAD19]], <8 x i8> [[BROADCAST_SPLAT21]])
-; CHECK-NEXT: store <8 x i8> [[TMP12]], ptr [[NEXT_GEP18]], align 2
-; CHECK-NEXT: [[INDEX_NEXT22]] = add nuw i64 [[INDEX16]], 8
-; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT22]], [[N_VEC7]]
-; CHECK-NEXT: br i1 [[TMP13]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
-; CHECK: vec.epilog.middle.block:
-; CHECK-NEXT: [[CMP_N15:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC7]]
-; CHECK-NEXT: br i1 [[CMP_N15]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
-; CHECK: vec.epilog.scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END9]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL12:%.*]] = phi ptr [ [[IND_END10]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END11]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL15:%.*]] = phi ptr [ [[IND_END13]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END14]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
-; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
-; CHECK: while.body:
-; CHECK-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ]
-; CHECK-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL12]], [[VEC_EPILOG_SCALAR_PH]] ]
-; CHECK-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL15]], [[VEC_EPILOG_SCALAR_PH]] ]
-; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[PSRC_ADDR_08]], i32 1
-; CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr [[PSRC_ADDR_08]], align 2
-; CHECK-NEXT: [[TMP15:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[TMP14]], i8 [[TMP14]], i8 [[OFFSET]])
-; CHECK-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i8, ptr [[PDST_ADDR_07]], i32 1
-; CHECK-NEXT: store i8 [[TMP15]], ptr [[PDST_ADDR_07]], align 2
-; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
-; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
-; CHECK: while.end.loopexit:
-; CHECK-NEXT: br label [[WHILE_END]]
-; CHECK: while.end:
-; CHECK-NEXT: ret void
+; AVX1-LABEL: @fshl(
+; AVX1-NEXT: entry:
+; AVX1-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; AVX1-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
+; AVX1: iter.check:
+; AVX1-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
+; AVX1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; AVX1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
+; AVX1: vector.main.loop.iter.check:
+; AVX1-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 16
+; AVX1-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
+; AVX1: vector.ph:
+; AVX1-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 15
+; AVX1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; AVX1-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
+; AVX1-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
+; AVX1-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[N_VEC]]
+; AVX1-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[N_VEC]]
+; AVX1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[OFFSET:%.*]], i64 0
+; AVX1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
+; AVX1-NEXT: br label [[VECTOR_BODY:%.*]]
+; AVX1: vector.body:
+; AVX1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX1-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX]]
+; AVX1-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX]]
+; AVX1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[NEXT_GEP]], align 2
+; AVX1-NEXT: [[TMP6:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD]], <16 x i8> [[WIDE_LOAD]], <16 x i8> [[BROADCAST_SPLAT]])
+; AVX1-NEXT: store <16 x i8> [[TMP6]], ptr [[NEXT_GEP2]], align 2
+; AVX1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; AVX1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX1-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; AVX1: middle.block:
+; AVX1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; AVX1-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
+; AVX1: vec.epilog.iter.check:
+; AVX1-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; AVX1-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF7:![0-9]+]]
+; AVX1: vec.epilog.ph:
+; AVX1-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; AVX1-NEXT: [[TMP8:%.*]] = and i64 [[TMP0]], 7
+; AVX1-NEXT: [[N_VEC5:%.*]] = sub i64 [[TMP0]], [[TMP8]]
+; AVX1-NEXT: [[TMP9:%.*]] = trunc i64 [[N_VEC5]] to i32
+; AVX1-NEXT: [[TMP10:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP9]]
+; AVX1-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC5]]
+; AVX1-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC5]]
+; AVX1-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <8 x i8> poison, i8 [[OFFSET]], i64 0
+; AVX1-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT6]], <8 x i8> poison, <8 x i32> zeroinitializer
+; AVX1-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
+; AVX1: vec.epilog.vector.body:
+; AVX1-NEXT: [[INDEX8:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT12:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
+; AVX1-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX8]]
+; AVX1-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX8]]
+; AVX1-NEXT: [[WIDE_LOAD11:%.*]] = load <8 x i8>, ptr [[NEXT_GEP9]], align 2
+; AVX1-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> [[WIDE_LOAD11]], <8 x i8> [[WIDE_LOAD11]], <8 x i8> [[BROADCAST_SPLAT7]])
+; AVX1-NEXT: store <8 x i8> [[TMP13]], ptr [[NEXT_GEP10]], align 2
+; AVX1-NEXT: [[INDEX_NEXT12]] = add nuw i64 [[INDEX8]], 8
+; AVX1-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT12]], [[N_VEC5]]
+; AVX1-NEXT: br i1 [[TMP14]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; AVX1: vec.epilog.middle.block:
+; AVX1-NEXT: [[CMP_N13:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC5]]
+; AVX1-NEXT: br i1 [[CMP_N13]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
+; AVX1: vec.epilog.scalar.ph:
+; AVX1-NEXT: [[BC_RESUME_VAL14:%.*]] = phi i32 [ [[TMP10]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
+; AVX1-NEXT: [[BC_RESUME_VAL15:%.*]] = phi ptr [ [[TMP11]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP4]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
+; AVX1-NEXT: [[BC_RESUME_VAL16:%.*]] = phi ptr [ [[TMP12]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP5]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
+; AVX1-NEXT: br label [[WHILE_BODY:%.*]]
+; AVX1: while.body:
+; AVX1-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL14]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX1-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL15]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX1-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL16]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX1-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[PSRC_ADDR_08]], i32 1
+; AVX1-NEXT: [[TMP15:%.*]] = load i8, ptr [[PSRC_ADDR_08]], align 2
+; AVX1-NEXT: [[TMP16:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[TMP15]], i8 [[TMP15]], i8 [[OFFSET]])
+; AVX1-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i8, ptr [[PDST_ADDR_07]], i32 1
+; AVX1-NEXT: store i8 [[TMP16]], ptr [[PDST_ADDR_07]], align 2
+; AVX1-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
+; AVX1-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
+; AVX1-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; AVX1: while.end.loopexit:
+; AVX1-NEXT: br label [[WHILE_END]]
+; AVX1: while.end:
+; AVX1-NEXT: ret void
+;
+; AVX2-LABEL: @fshl(
+; AVX2-NEXT: entry:
+; AVX2-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; AVX2-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
+; AVX2: iter.check:
+; AVX2-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
+; AVX2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
+; AVX2: vector.main.loop.iter.check:
+; AVX2-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 32
+; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
+; AVX2: vector.ph:
+; AVX2-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 31
+; AVX2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; AVX2-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
+; AVX2-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
+; AVX2-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[N_VEC]]
+; AVX2-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[N_VEC]]
+; AVX2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <32 x i8> poison, i8 [[OFFSET:%.*]], i64 0
+; AVX2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <32 x i8> [[BROADCAST_SPLATINSERT]], <32 x i8> poison, <32 x i32> zeroinitializer
+; AVX2-NEXT: br label [[VECTOR_BODY:%.*]]
+; AVX2: vector.body:
+; AVX2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX2-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX]]
+; AVX2-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX]]
+; AVX2-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[NEXT_GEP]], align 2
+; AVX2-NEXT: [[TMP6:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD]], <32 x i8> [[WIDE_LOAD]], <32 x i8> [[BROADCAST_SPLAT]])
+; AVX2-NEXT: store <32 x i8> [[TMP6]], ptr [[NEXT_GEP2]], align 2
+; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
+; AVX2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX2-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; AVX2: middle.block:
+; AVX2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; AVX2-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
+; AVX2: vec.epilog.iter.check:
+; AVX2-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; AVX2-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF7:![0-9]+]]
+; AVX2: vec.epilog.ph:
+; AVX2-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; AVX2-NEXT: [[TMP8:%.*]] = and i64 [[TMP0]], 7
+; AVX2-NEXT: [[N_VEC5:%.*]] = sub i64 [[TMP0]], [[TMP8]]
+; AVX2-NEXT: [[TMP9:%.*]] = trunc i64 [[N_VEC5]] to i32
+; AVX2-NEXT: [[TMP10:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP9]]
+; AVX2-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC5]]
+; AVX2-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC5]]
+; AVX2-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <8 x i8> poison, i8 [[OFFSET]], i64 0
+; AVX2-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT6]], <8 x i8> poison, <8 x i32> zeroinitializer
+; AVX2-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
+; AVX2: vec.epilog.vector.body:
+; AVX2-NEXT: [[INDEX8:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT12:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
+; AVX2-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX8]]
+; AVX2-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX8]]
+; AVX2-NEXT: [[WIDE_LOAD11:%.*]] = load <8 x i8>, ptr [[NEXT_GEP9]], align 2
+; AVX2-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> [[WIDE_LOAD11]], <8 x i8> [[WIDE_LOAD11]], <8 x i8> [[BROADCAST_SPLAT7]])
+; AVX2-NEXT: store <8 x i8> [[TMP13]], ptr [[NEXT_GEP10]], align 2
+; AVX2-NEXT: [[INDEX_NEXT12]] = add nuw i64 [[INDEX8]], 8
+; AVX2-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT12]], [[N_VEC5]]
+; AVX2-NEXT: br i1 [[TMP14]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; AVX2: vec.epilog.middle.block:
+; AVX2-NEXT: [[CMP_N13:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC5]]
+; AVX2-NEXT: br i1 [[CMP_N13]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
+; AVX2: vec.epilog.scalar.ph:
+; AVX2-NEXT: [[BC_RESUME_VAL14:%.*]] = phi i32 [ [[TMP10]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
+; AVX2-NEXT: [[BC_RESUME_VAL15:%.*]] = phi ptr [ [[TMP11]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP4]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
+; AVX2-NEXT: [[BC_RESUME_VAL16:%.*]] = phi ptr [ [[TMP12]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP5]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
+; AVX2-NEXT: br label [[WHILE_BODY:%.*]]
+; AVX2: while.body:
+; AVX2-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL14]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX2-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL15]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX2-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL16]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX2-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[PSRC_ADDR_08]], i32 1
+; AVX2-NEXT: [[TMP15:%.*]] = load i8, ptr [[PSRC_ADDR_08]], align 2
+; AVX2-NEXT: [[TMP16:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[TMP15]], i8 [[TMP15]], i8 [[OFFSET]])
+; AVX2-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i8, ptr [[PDST_ADDR_07]], i32 1
+; AVX2-NEXT: store i8 [[TMP16]], ptr [[PDST_ADDR_07]], align 2
+; AVX2-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
+; AVX2-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
+; AVX2-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; AVX2: while.end.loopexit:
+; AVX2-NEXT: br label [[WHILE_END]]
+; AVX2: while.end:
+; AVX2-NEXT: ret void
+;
+; XOP-LABEL: @fshl(
+; XOP-NEXT: entry:
+; XOP-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; XOP-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
+; XOP: iter.check:
+; XOP-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
+; XOP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; XOP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
+; XOP: vector.main.loop.iter.check:
+; XOP-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 128
+; XOP-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
+; XOP: vector.ph:
+; XOP-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 127
+; XOP-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; XOP-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
+; XOP-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
+; XOP-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[N_VEC]]
+; XOP-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[N_VEC]]
+; XOP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <32 x i8> poison, i8 [[OFFSET:%.*]], i64 0
+; XOP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <32 x i8> [[BROADCAST_SPLATINSERT]], <32 x i8> poison, <32 x i32> zeroinitializer
+; XOP-NEXT: br label [[VECTOR_BODY:%.*]]
+; XOP: vector.body:
+; XOP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; XOP-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX]]
+; XOP-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX]]
+; XOP-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 32
+; XOP-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 64
+; XOP-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 96
+; XOP-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[NEXT_GEP]], align 2
+; XOP-NEXT: [[WIDE_LOAD3:%.*]] = load <32 x i8>, ptr [[TMP6]], align 2
+; XOP-NEXT: [[WIDE_LOAD4:%.*]] = load <32 x i8>, ptr [[TMP7]], align 2
+; XOP-NEXT: [[WIDE_LOAD5:%.*]] = load <32 x i8>, ptr [[TMP8]], align 2
+; XOP-NEXT: [[TMP9:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD]], <32 x i8> [[WIDE_LOAD]], <32 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP10:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD3]], <32 x i8> [[WIDE_LOAD3]], <32 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP11:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD4]], <32 x i8> [[WIDE_LOAD4]], <32 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP12:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD5]], <32 x i8> [[WIDE_LOAD5]], <32 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 32
+; XOP-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 64
+; XOP-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 96
+; XOP-NEXT: store <32 x i8> [[TMP9]], ptr [[NEXT_GEP2]], align 2
+; XOP-NEXT: store <32 x i8> [[TMP10]], ptr [[TMP13]], align 2
+; XOP-NEXT: store <32 x i8> [[TMP11]], ptr [[TMP14]], align 2
+; XOP-NEXT: store <32 x i8> [[TMP12]], ptr [[TMP15]], align 2
+; XOP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 128
+; XOP-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; XOP-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; XOP: middle.block:
+; XOP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; XOP-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
+; XOP: vec.epilog.iter.check:
+; XOP-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; XOP-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF7:![0-9]+]]
+; XOP: vec.epilog.ph:
+; XOP-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; XOP-NEXT: [[TMP17:%.*]] = and i64 [[TMP0]], 7
+; XOP-NEXT: [[N_VEC8:%.*]] = sub i64 [[TMP0]], [[TMP17]]
+; XOP-NEXT: [[TMP18:%.*]] = trunc i64 [[N_VEC8]] to i32
+; XOP-NEXT: [[TMP19:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP18]]
+; XOP-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC8]]
+; XOP-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC8]]
+; XOP-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <8 x i8> poison, i8 [[OFFSET]], i64 0
+; XOP-NEXT: [[BROADCAST_SPLAT10:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT9]], <8 x i8> poison, <8 x i32> zeroinitializer
+; XOP-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
+; XOP: vec.epilog.vector.body:
+; XOP-NEXT: [[INDEX11:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
+; XOP-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX11]]
+; XOP-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX11]]
+; XOP-NEXT: [[WIDE_LOAD14:%.*]] = load <8 x i8>, ptr [[NEXT_GEP12]], align 2
+; XOP-NEXT: [[TMP22:%.*]] = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> [[WIDE_LOAD14]], <8 x i8> [[WIDE_LOAD14]], <8 x i8> [[BROADCAST_SPLAT10]])
+; XOP-NEXT: store <8 x i8> [[TMP22]], ptr [[NEXT_GEP13]], align 2
+; XOP-NEXT: [[INDEX_NEXT15]] = add nuw i64 [[INDEX11]], 8
+; XOP-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT15]], [[N_VEC8]]
+; XOP-NEXT: br i1 [[TMP23]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; XOP: vec.epilog.middle.block:
+; XOP-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC8]]
+; XOP-NEXT: br i1 [[CMP_N16]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
+; XOP: vec.epilog.scalar.ph:
+; XOP-NEXT: [[BC_RESUME_VAL17:%.*]] = phi i32 [ [[TMP19]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
+; XOP-NEXT: [[BC_RESUME_VAL18:%.*]] = phi ptr [ [[TMP20]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP4]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
+; XOP-NEXT: [[BC_RESUME_VAL19:%.*]] = phi ptr [ [[TMP21]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP5]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
+; XOP-NEXT: br label [[WHILE_BODY:%.*]]
+; XOP: while.body:
+; XOP-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL17]], [[VEC_EPILOG_SCALAR_PH]] ]
+; XOP-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL18]], [[VEC_EPILOG_SCALAR_PH]] ]
+; XOP-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL19]], [[VEC_EPILOG_SCALAR_PH]] ]
+; XOP-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[PSRC_ADDR_08]], i32 1
+; XOP-NEXT: [[TMP24:%.*]] = load i8, ptr [[PSRC_ADDR_08]], align 2
+; XOP-NEXT: [[TMP25:%.*]] = tail call i8 @llvm.fshl.i8(i8 [[TMP24]], i8 [[TMP24]], i8 [[OFFSET]])
+; XOP-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i8, ptr [[PDST_ADDR_07]], i32 1
+; XOP-NEXT: store i8 [[TMP25]], ptr [[PDST_ADDR_07]], align 2
+; XOP-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
+; XOP-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
+; XOP-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; XOP: while.end.loopexit:
+; XOP-NEXT: br label [[WHILE_END]]
+; XOP: while.end:
+; XOP-NEXT: ret void
;
entry:
%cmp.not6 = icmp eq i32 %blockSize, 0
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
index 4fbc7f01735d0..5f83d5e172c6e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
index ee370e537983e..fda4998772c83 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index e1ad4acf0f25d..bec493efe4774 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA512
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
index f134086a293e4..fc2ac392b17b5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,COREI7
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -103,46 +103,6 @@ define void @fmaxnum_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
-; COREI7-LABEL: @fmaxnum_8f64(
-; COREI7-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; COREI7-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; COREI7-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; COREI7-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; COREI7-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; COREI7-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; COREI7-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; COREI7-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; COREI7-NEXT: ret void
-;
-; BDVER1-LABEL: @fmaxnum_8f64(
-; BDVER1-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; BDVER1-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; BDVER1-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; BDVER1-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; BDVER1-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; BDVER1-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; BDVER1-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; BDVER1-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; BDVER1-NEXT: ret void
-;
-; AVX2-LABEL: @fmaxnum_8f64(
-; AVX2-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; AVX2-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; AVX2-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX2-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; AVX2-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; AVX2-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; AVX2-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; AVX2-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; AVX2-NEXT: ret void
-;
-; AVX512-LABEL: @fmaxnum_8f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
-; AVX512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
-; AVX512-NEXT: [[TMP3:%.*]] = call <8 x double> @llvm.maxnum.v8f64(<8 x double> [[TMP1]], <8 x double> [[TMP2]])
-; AVX512-NEXT: store <8 x double> [[TMP3]], ptr @dst64, align 4
-; AVX512-NEXT: ret void
-;
; AVX256-LABEL: @fmaxnum_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
@@ -153,6 +113,13 @@ define void @fmaxnum_8f64() #0 {
; AVX256-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
; AVX256-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fmaxnum_8f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <8 x double> @llvm.maxnum.v8f64(<8 x double> [[TMP1]], <8 x double> [[TMP2]])
+; AVX512-NEXT: store <8 x double> [[TMP3]], ptr @dst64, align 4
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 4
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 4
@@ -290,46 +257,6 @@ define void @fmaxnum_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
-; COREI7-LABEL: @fmaxnum_16f32(
-; COREI7-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; COREI7-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; COREI7-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; COREI7-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; COREI7-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; COREI7-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; COREI7-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; COREI7-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; COREI7-NEXT: ret void
-;
-; BDVER1-LABEL: @fmaxnum_16f32(
-; BDVER1-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; BDVER1-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; BDVER1-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; BDVER1-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; BDVER1-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; BDVER1-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; BDVER1-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; BDVER1-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; BDVER1-NEXT: ret void
-;
-; AVX2-LABEL: @fmaxnum_16f32(
-; AVX2-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX2-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX2-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX2-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX2-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; AVX2-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; AVX2-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; AVX2-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; AVX2-NEXT: ret void
-;
-; AVX512-LABEL: @fmaxnum_16f32(
-; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
-; AVX512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
-; AVX512-NEXT: [[TMP3:%.*]] = call <16 x float> @llvm.maxnum.v16f32(<16 x float> [[TMP1]], <16 x float> [[TMP2]])
-; AVX512-NEXT: store <16 x float> [[TMP3]], ptr @dst32, align 4
-; AVX512-NEXT: ret void
-;
; AVX256-LABEL: @fmaxnum_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -340,6 +267,13 @@ define void @fmaxnum_16f32() #0 {
; AVX256-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
; AVX256-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fmaxnum_16f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <16 x float> @llvm.maxnum.v16f32(<16 x float> [[TMP1]], <16 x float> [[TMP2]])
+; AVX512-NEXT: store <16 x float> [[TMP3]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
index f890ca169f59c..d49c6bd5d6312 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,COREI7
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -103,46 +103,6 @@ define void @fminnum_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
-; COREI7-LABEL: @fminnum_8f64(
-; COREI7-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; COREI7-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; COREI7-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; COREI7-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; COREI7-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; COREI7-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; COREI7-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; COREI7-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; COREI7-NEXT: ret void
-;
-; BDVER1-LABEL: @fminnum_8f64(
-; BDVER1-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; BDVER1-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; BDVER1-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; BDVER1-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; BDVER1-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; BDVER1-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; BDVER1-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; BDVER1-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; BDVER1-NEXT: ret void
-;
-; AVX2-LABEL: @fminnum_8f64(
-; AVX2-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; AVX2-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; AVX2-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX2-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; AVX2-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; AVX2-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; AVX2-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; AVX2-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; AVX2-NEXT: ret void
-;
-; AVX512-LABEL: @fminnum_8f64(
-; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
-; AVX512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
-; AVX512-NEXT: [[TMP3:%.*]] = call <8 x double> @llvm.minnum.v8f64(<8 x double> [[TMP1]], <8 x double> [[TMP2]])
-; AVX512-NEXT: store <8 x double> [[TMP3]], ptr @dst64, align 4
-; AVX512-NEXT: ret void
-;
; AVX256-LABEL: @fminnum_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
@@ -153,6 +113,13 @@ define void @fminnum_8f64() #0 {
; AVX256-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
; AVX256-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fminnum_8f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <8 x double> @llvm.minnum.v8f64(<8 x double> [[TMP1]], <8 x double> [[TMP2]])
+; AVX512-NEXT: store <8 x double> [[TMP3]], ptr @dst64, align 4
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 4
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 4
@@ -290,46 +257,6 @@ define void @fminnum_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
-; COREI7-LABEL: @fminnum_16f32(
-; COREI7-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; COREI7-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; COREI7-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; COREI7-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; COREI7-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; COREI7-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; COREI7-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; COREI7-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; COREI7-NEXT: ret void
-;
-; BDVER1-LABEL: @fminnum_16f32(
-; BDVER1-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; BDVER1-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; BDVER1-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; BDVER1-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; BDVER1-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; BDVER1-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; BDVER1-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; BDVER1-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; BDVER1-NEXT: ret void
-;
-; AVX2-LABEL: @fminnum_16f32(
-; AVX2-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX2-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX2-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX2-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX2-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; AVX2-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; AVX2-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; AVX2-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; AVX2-NEXT: ret void
-;
-; AVX512-LABEL: @fminnum_16f32(
-; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
-; AVX512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
-; AVX512-NEXT: [[TMP3:%.*]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[TMP1]], <16 x float> [[TMP2]])
-; AVX512-NEXT: store <16 x float> [[TMP3]], ptr @dst32, align 4
-; AVX512-NEXT: ret void
-;
; AVX256-LABEL: @fminnum_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -340,6 +267,13 @@ define void @fminnum_16f32() #0 {
; AVX256-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
; AVX256-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fminnum_16f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <16 x float> @llvm.minnum.v16f32(<16 x float> [[TMP1]], <16 x float> [[TMP2]])
+; AVX512-NEXT: store <16 x float> [[TMP3]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
index 49a83f3e6f02b..5c1d6f59e0d49 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
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