[llvm] M68k: Use data register classes for the 16->32 extending move pseudos (PR #226099)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-m68k

Author: Matt Arsenault (arsenm)

<details>
<summary>Changes</summary>

MOVSXd32d16 and MOVZXd32d16 declared both operands with the XR32/XR16
classes, which include the address registers. The post-RA expansion of
these pseudos emits AND32di, MOV16dd and EXT32, all of which require a
data register, so allocating an address register produces invalid code:

  $a6 = AND32di $a6(tied-def 0), 65535, implicit-def $ccr

Every pattern selecting these pseudos already restricts the source to
MxDRD16, so constrain the pseudos to the data register classes.

This fixes machine verifier errors in the touched test.

Co-Authored-By: Claude Opus 5 <noreply@<!-- -->anthropic.com>

---
Full diff: https://github.com/llvm/llvm-project/pull/226099.diff


2 Files Affected:

- (modified) llvm/lib/Target/M68k/M68kInstrData.td (+1-1) 
- (modified) llvm/test/CodeGen/M68k/register-spills.ll (+86-61) 


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</details>


https://github.com/llvm/llvm-project/pull/226099