[llvm] [AArch64] Materialize a common offset for paired load/store optimization (PR #222697)
Andrew Savonichev via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 03:01:15 PDT 2026
https://github.com/asavonic updated https://github.com/llvm/llvm-project/pull/222697
>From 9dafbf7f7521ad999eac612de3c5c44395a4251e Mon Sep 17 00:00:00 2001
From: Andrew Savonichev <andrew.savonichev at gmail.com>
Date: Mon, 7 Sep 2026 22:30:51 +0900
Subject: [PATCH 1/2] Pre-commit tests
---
.../CodeGen/AArch64/large-stack-memset.ll | 136 +
.../test/CodeGen/AArch64/large-stack-spill.ll | 3641 +++++++++++++++++
.../AArch64/ldst-opt-reduce-offset.mir | 509 +++
3 files changed, 4286 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/large-stack-memset.ll
create mode 100644 llvm/test/CodeGen/AArch64/large-stack-spill.ll
create mode 100644 llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir
diff --git a/llvm/test/CodeGen/AArch64/large-stack-memset.ll b/llvm/test/CodeGen/AArch64/large-stack-memset.ll
new file mode 100644
index 0000000000000..8572f4e3b827e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/large-stack-memset.ll
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; Test that inlined memset of a stack alloca is optimized to STP
+; instructions. Attribute noimplicitfloat (clang's
+; -mno-implicit-float) is here to prevent the compiler from using 128
+; bit STP, which have a greater range for the offset.
+;
+; Two tests here differ in the order of allocas, which directly
+; corresponds to the order of stack objects:
+;
+; - test1 has a smaller alloca %i before larger alloca %j.
+; - test2 has %j before %i.
+;
+; In test1, SP-relative offset to %i is greater than the maximum
+; allowed STP offset (7-bit signed, -64 <= offset <= 63).
+; In test2, %i is closer to SP, so it gets optimized naturally.
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "aarch64-unknown-unknown"
+
+define void @test1() #1 {
+; CHECK-LABEL: test1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: sub sp, sp, #768
+; CHECK-NEXT: .cfi_def_cfa_offset 784
+; CHECK-NEXT: mov x0, sp
+; CHECK-NEXT: mov w1, wzr
+; CHECK-NEXT: mov w2, #512 // =0x200
+; CHECK-NEXT: str xzr, [sp, #760]
+; CHECK-NEXT: str xzr, [sp, #752]
+; CHECK-NEXT: str xzr, [sp, #744]
+; CHECK-NEXT: str xzr, [sp, #736]
+; CHECK-NEXT: str xzr, [sp, #728]
+; CHECK-NEXT: str xzr, [sp, #720]
+; CHECK-NEXT: str xzr, [sp, #712]
+; CHECK-NEXT: str xzr, [sp, #704]
+; CHECK-NEXT: str xzr, [sp, #696]
+; CHECK-NEXT: str xzr, [sp, #688]
+; CHECK-NEXT: str xzr, [sp, #680]
+; CHECK-NEXT: str xzr, [sp, #672]
+; CHECK-NEXT: str xzr, [sp, #664]
+; CHECK-NEXT: str xzr, [sp, #656]
+; CHECK-NEXT: str xzr, [sp, #648]
+; CHECK-NEXT: str xzr, [sp, #640]
+; CHECK-NEXT: str xzr, [sp, #632]
+; CHECK-NEXT: str xzr, [sp, #624]
+; CHECK-NEXT: str xzr, [sp, #616]
+; CHECK-NEXT: str xzr, [sp, #608]
+; CHECK-NEXT: str xzr, [sp, #600]
+; CHECK-NEXT: str xzr, [sp, #592]
+; CHECK-NEXT: str xzr, [sp, #584]
+; CHECK-NEXT: str xzr, [sp, #576]
+; CHECK-NEXT: str xzr, [sp, #568]
+; CHECK-NEXT: str xzr, [sp, #560]
+; CHECK-NEXT: str xzr, [sp, #552]
+; CHECK-NEXT: str xzr, [sp, #544]
+; CHECK-NEXT: str xzr, [sp, #536]
+; CHECK-NEXT: str xzr, [sp, #528]
+; CHECK-NEXT: str xzr, [sp, #520]
+; CHECK-NEXT: str xzr, [sp, #512]
+; CHECK-NEXT: bl memset
+; CHECK-NEXT: add x0, sp, #512
+; CHECK-NEXT: mov x1, sp
+; CHECK-NEXT: bl use
+; CHECK-NEXT: add sp, sp, #768
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: .cfi_restore w30
+; CHECK-NEXT: .cfi_restore w29
+; CHECK-NEXT: ret
+entry:
+ %i = alloca [64 x i32], align 4
+ %j = alloca [64 x ptr], align 8
+ call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(256) %i, i8 0, i64 256, i1 false)
+ call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(512) %j, i8 0, i64 512, i1 false)
+ call void @use(ptr noundef nonnull %i, ptr noundef nonnull %j)
+ ret void
+}
+
+define void @test2() #1 {
+; CHECK-LABEL: test2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -8
+; CHECK-NEXT: .cfi_offset w29, -16
+; CHECK-NEXT: sub sp, sp, #768
+; CHECK-NEXT: .cfi_def_cfa_offset 784
+; CHECK-NEXT: add x0, sp, #256
+; CHECK-NEXT: mov w1, wzr
+; CHECK-NEXT: mov w2, #512 // =0x200
+; CHECK-NEXT: stp xzr, xzr, [sp, #240]
+; CHECK-NEXT: stp xzr, xzr, [sp, #224]
+; CHECK-NEXT: stp xzr, xzr, [sp, #208]
+; CHECK-NEXT: stp xzr, xzr, [sp, #192]
+; CHECK-NEXT: stp xzr, xzr, [sp, #176]
+; CHECK-NEXT: stp xzr, xzr, [sp, #160]
+; CHECK-NEXT: stp xzr, xzr, [sp, #144]
+; CHECK-NEXT: stp xzr, xzr, [sp, #128]
+; CHECK-NEXT: stp xzr, xzr, [sp, #112]
+; CHECK-NEXT: stp xzr, xzr, [sp, #96]
+; CHECK-NEXT: stp xzr, xzr, [sp, #80]
+; CHECK-NEXT: stp xzr, xzr, [sp, #64]
+; CHECK-NEXT: stp xzr, xzr, [sp, #48]
+; CHECK-NEXT: stp xzr, xzr, [sp, #32]
+; CHECK-NEXT: stp xzr, xzr, [sp, #16]
+; CHECK-NEXT: stp xzr, xzr, [sp]
+; CHECK-NEXT: bl memset
+; CHECK-NEXT: mov x0, sp
+; CHECK-NEXT: add x1, sp, #256
+; CHECK-NEXT: bl use
+; CHECK-NEXT: add sp, sp, #768
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: .cfi_restore w30
+; CHECK-NEXT: .cfi_restore w29
+; CHECK-NEXT: ret
+entry:
+ %j = alloca [64 x ptr], align 8
+ %i = alloca [64 x i32], align 4
+ call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(256) %i, i8 0, i64 256, i1 false)
+ call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(512) %j, i8 0, i64 512, i1 false)
+ call void @use(ptr noundef nonnull %i, ptr noundef nonnull %j)
+ ret void
+}
+
+declare void @use(ptr noundef nonnull align 1 dereferenceable(1), ptr noundef, ptr noundef)
+
+attributes #1 = { mustprogress noimplicitfloat nounwind uwtable }
diff --git a/llvm/test/CodeGen/AArch64/large-stack-spill.ll b/llvm/test/CodeGen/AArch64/large-stack-spill.ll
new file mode 100644
index 0000000000000..c4d195cbe703d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/large-stack-spill.ll
@@ -0,0 +1,3641 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -O3 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; Snippet from LLVM test-suite
+; MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow.c
+;
+; The compiler should use paired stores for spills in the loop.
+
+source_filename = "MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow.c"
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "aarch64-unknown-linux-gnu"
+
+ at DEPTH = dso_local global i32 3, align 4
+ at off = dso_local local_unnamed_addr global i32 0, align 4
+ at C4VERT = dso_local local_unnamed_addr global i64 0, align 8
+ at C3VERT = dso_local local_unnamed_addr global i64 0, align 8
+ at C2VERT = dso_local local_unnamed_addr global i64 0, align 8
+ at C4HORIZ = dso_local local_unnamed_addr global i64 0, align 8
+ at C3HORIZ = dso_local local_unnamed_addr global i64 0, align 8
+ at C2HORIZ = dso_local local_unnamed_addr global i64 0, align 8
+ at C4UP_R = dso_local local_unnamed_addr global i64 0, align 8
+ at C3UP_R = dso_local local_unnamed_addr global i64 0, align 8
+ at C2UP_R = dso_local local_unnamed_addr global i64 0, align 8
+ at C4UP_L = dso_local local_unnamed_addr global i64 0, align 8
+ at C3UP_L = dso_local local_unnamed_addr global i64 0, align 8
+ at C2UP_L = dso_local local_unnamed_addr global i64 0, align 8
+
+define dso_local i32 @value(i64 noundef %b1, i64 noundef %b2) {
+; CHECK-LABEL: value:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: stp x29, x30, [sp, #-96]! // 16-byte Folded Spill
+; CHECK-NEXT: stp x28, x27, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill
+; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill
+; CHECK-NEXT: sub sp, sp, #1824
+; CHECK-NEXT: .cfi_def_cfa_offset 1920
+; CHECK-NEXT: .cfi_offset w19, -8
+; CHECK-NEXT: .cfi_offset w20, -16
+; CHECK-NEXT: .cfi_offset w21, -24
+; CHECK-NEXT: .cfi_offset w22, -32
+; CHECK-NEXT: .cfi_offset w23, -40
+; CHECK-NEXT: .cfi_offset w24, -48
+; CHECK-NEXT: .cfi_offset w25, -56
+; CHECK-NEXT: .cfi_offset w26, -64
+; CHECK-NEXT: .cfi_offset w27, -72
+; CHECK-NEXT: .cfi_offset w28, -80
+; CHECK-NEXT: .cfi_offset w30, -88
+; CHECK-NEXT: .cfi_offset w29, -96
+; CHECK-NEXT: adrp x10, .L_MergedGlobals
+; CHECK-NEXT: add x10, x10, :lo12:.L_MergedGlobals
+; CHECK-NEXT: str x0, [sp, #1808] // 8-byte Spill
+; CHECK-NEXT: ldp x3, x4, [x10, #88]
+; CHECK-NEXT: str x1, [sp, #1816] // 8-byte Spill
+; CHECK-NEXT: ldp x9, x13, [x10, #8]
+; CHECK-NEXT: fmov s1, #10.00000000
+; CHECK-NEXT: ldp x0, x16, [x10, #24]
+; CHECK-NEXT: fmov s2, #-1.00000000
+; CHECK-NEXT: lsl x11, x4, #12
+; CHECK-NEXT: ldp x14, x15, [x10, #56]
+; CHECK-NEXT: str x9, [sp, #1536] // 8-byte Spill
+; CHECK-NEXT: ldr s0, [x10]
+; CHECK-NEXT: fmov s3, #20.00000000
+; CHECK-NEXT: str x11, [sp, #1712] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x4, #15
+; CHECK-NEXT: fmov s4, #5.00000000
+; CHECK-NEXT: ldp x1, x2, [x10, #40]
+; CHECK-NEXT: scvtf s0, s0
+; CHECK-NEXT: str x11, [sp, #1704] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #1
+; CHECK-NEXT: mov w8, wzr
+; CHECK-NEXT: ldp x10, x5, [x10, #72]
+; CHECK-NEXT: str x16, [sp, #1776] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1696] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #2
+; CHECK-NEXT: fdiv s0, s0, s1
+; CHECK-NEXT: fmov s1, #1.00000000
+; CHECK-NEXT: str x14, [sp, #1792] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1688] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #3
+; CHECK-NEXT: str x10, [sp, #1720] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1680] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #4
+; CHECK-NEXT: str x5, [sp, #1728] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1672] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #5
+; CHECK-NEXT: str x13, [sp, #1800] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1664] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #6
+; CHECK-NEXT: str x1, [sp, #1760] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1656] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #7
+; CHECK-NEXT: str x15, [sp, #1784] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1648] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #8
+; CHECK-NEXT: str x3, [sp, #1744] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1640] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #9
+; CHECK-NEXT: str x0, [sp, #1768] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1632] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #10
+; CHECK-NEXT: str x2, [sp, #1752] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1624] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #11
+; CHECK-NEXT: str x4, [sp, #1736] // 8-byte Spill
+; CHECK-NEXT: str x11, [sp, #1616] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #12
+; CHECK-NEXT: str x11, [sp, #1608] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #13
+; CHECK-NEXT: str x11, [sp, #1600] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #14
+; CHECK-NEXT: str x11, [sp, #1592] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #15
+; CHECK-NEXT: str x11, [sp, #1584] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #16
+; CHECK-NEXT: str x11, [sp, #1576] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #17
+; CHECK-NEXT: str x11, [sp, #1568] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #18
+; CHECK-NEXT: ldr x12, [sp, #1568] // 8-byte Reload
+; CHECK-NEXT: str x11, [sp, #1560] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x9, #19
+; CHECK-NEXT: lsl x9, x9, #20
+; CHECK-NEXT: ldr x17, [sp, #1560] // 8-byte Reload
+; CHECK-NEXT: str x9, [sp, #1544] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #1
+; CHECK-NEXT: str x11, [sp, #1552] // 8-byte Spill
+; CHECK-NEXT: lsl x11, x0, #12
+; CHECK-NEXT: str x9, [sp, #1528] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #2
+; CHECK-NEXT: ldr x18, [sp, #1552] // 8-byte Reload
+; CHECK-NEXT: str x9, [sp, #1520] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #3
+; CHECK-NEXT: str x9, [sp, #1512] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #6
+; CHECK-NEXT: str x9, [sp, #1504] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #7
+; CHECK-NEXT: str x9, [sp, #1496] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #8
+; CHECK-NEXT: str x9, [sp, #1488] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #9
+; CHECK-NEXT: str x9, [sp, #1480] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #12
+; CHECK-NEXT: str x9, [sp, #1472] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #13
+; CHECK-NEXT: str x9, [sp, #1464] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #14
+; CHECK-NEXT: str x9, [sp, #1456] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #15
+; CHECK-NEXT: str x9, [sp, #1448] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #18
+; CHECK-NEXT: str x9, [sp, #1440] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #19
+; CHECK-NEXT: str x9, [sp, #1432] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #20
+; CHECK-NEXT: str x9, [sp, #1424] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #21
+; CHECK-NEXT: str x9, [sp, #1416] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #24
+; CHECK-NEXT: str x9, [sp, #1408] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #25
+; CHECK-NEXT: str x9, [sp, #1400] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #26
+; CHECK-NEXT: str x9, [sp, #1392] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #27
+; CHECK-NEXT: str x9, [sp, #1384] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #30
+; CHECK-NEXT: str x9, [sp, #1376] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #31
+; CHECK-NEXT: str x9, [sp, #1368] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #32
+; CHECK-NEXT: str x9, [sp, #1360] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x16, #33
+; CHECK-NEXT: str x9, [sp, #1352] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #1
+; CHECK-NEXT: str x9, [sp, #1344] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #2
+; CHECK-NEXT: str x9, [sp, #1336] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #3
+; CHECK-NEXT: str x9, [sp, #1328] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #6
+; CHECK-NEXT: str x9, [sp, #1320] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #7
+; CHECK-NEXT: str x9, [sp, #1312] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #8
+; CHECK-NEXT: str x9, [sp, #1304] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #9
+; CHECK-NEXT: str x9, [sp, #1296] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #12
+; CHECK-NEXT: str x9, [sp, #1288] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #13
+; CHECK-NEXT: str x9, [sp, #1280] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #14
+; CHECK-NEXT: str x9, [sp, #1272] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x14, #15
+; CHECK-NEXT: str x9, [sp, #1264] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #1
+; CHECK-NEXT: str x9, [sp, #1256] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #2
+; CHECK-NEXT: str x9, [sp, #1248] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #3
+; CHECK-NEXT: str x9, [sp, #1240] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #6
+; CHECK-NEXT: str x9, [sp, #1232] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #7
+; CHECK-NEXT: str x9, [sp, #1224] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #8
+; CHECK-NEXT: str x9, [sp, #1216] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #9
+; CHECK-NEXT: str x9, [sp, #1208] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #12
+; CHECK-NEXT: str x9, [sp, #1200] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #13
+; CHECK-NEXT: str x9, [sp, #1192] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #14
+; CHECK-NEXT: str x9, [sp, #1184] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x5, #15
+; CHECK-NEXT: str x9, [sp, #1176] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #1
+; CHECK-NEXT: str x9, [sp, #1168] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #2
+; CHECK-NEXT: str x9, [sp, #1160] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #3
+; CHECK-NEXT: str x9, [sp, #1152] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #4
+; CHECK-NEXT: str x9, [sp, #1144] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #5
+; CHECK-NEXT: str x9, [sp, #1136] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #6
+; CHECK-NEXT: str x9, [sp, #1128] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #7
+; CHECK-NEXT: str x9, [sp, #1120] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #8
+; CHECK-NEXT: str x9, [sp, #1112] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #9
+; CHECK-NEXT: str x9, [sp, #1104] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #10
+; CHECK-NEXT: str x9, [sp, #1096] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #11
+; CHECK-NEXT: str x9, [sp, #1088] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #12
+; CHECK-NEXT: str x9, [sp, #1080] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #13
+; CHECK-NEXT: str x9, [sp, #1072] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #14
+; CHECK-NEXT: str x9, [sp, #1064] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #15
+; CHECK-NEXT: str x9, [sp, #1056] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #16
+; CHECK-NEXT: str x9, [sp, #1048] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #17
+; CHECK-NEXT: str x9, [sp, #1040] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #18
+; CHECK-NEXT: str x9, [sp, #1032] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #19
+; CHECK-NEXT: str x9, [sp, #1024] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x13, #20
+; CHECK-NEXT: str x9, [sp, #1016] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #1
+; CHECK-NEXT: str x9, [sp, #1008] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #2
+; CHECK-NEXT: str x9, [sp, #1000] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #3
+; CHECK-NEXT: str x9, [sp, #992] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #4
+; CHECK-NEXT: str x9, [sp, #984] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #6
+; CHECK-NEXT: str x9, [sp, #976] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #7
+; CHECK-NEXT: str x9, [sp, #968] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #8
+; CHECK-NEXT: str x9, [sp, #960] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #9
+; CHECK-NEXT: str x9, [sp, #952] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #10
+; CHECK-NEXT: str x9, [sp, #944] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #12
+; CHECK-NEXT: str x9, [sp, #936] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #13
+; CHECK-NEXT: str x9, [sp, #928] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #14
+; CHECK-NEXT: str x9, [sp, #920] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #15
+; CHECK-NEXT: str x9, [sp, #912] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #16
+; CHECK-NEXT: str x9, [sp, #904] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #18
+; CHECK-NEXT: str x9, [sp, #896] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #19
+; CHECK-NEXT: str x9, [sp, #888] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #20
+; CHECK-NEXT: str x9, [sp, #880] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #21
+; CHECK-NEXT: str x9, [sp, #872] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #22
+; CHECK-NEXT: str x9, [sp, #864] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #24
+; CHECK-NEXT: str x9, [sp, #856] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #25
+; CHECK-NEXT: str x9, [sp, #848] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #26
+; CHECK-NEXT: str x9, [sp, #840] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #27
+; CHECK-NEXT: str x9, [sp, #832] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #28
+; CHECK-NEXT: str x9, [sp, #824] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #30
+; CHECK-NEXT: str x9, [sp, #816] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #31
+; CHECK-NEXT: str x9, [sp, #808] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #32
+; CHECK-NEXT: str x9, [sp, #800] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #33
+; CHECK-NEXT: str x9, [sp, #792] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x1, #34
+; CHECK-NEXT: str x9, [sp, #784] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #1
+; CHECK-NEXT: str x9, [sp, #776] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #2
+; CHECK-NEXT: str x9, [sp, #768] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #3
+; CHECK-NEXT: str x9, [sp, #760] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #6
+; CHECK-NEXT: str x9, [sp, #752] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #7
+; CHECK-NEXT: str x9, [sp, #744] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #8
+; CHECK-NEXT: str x9, [sp, #736] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #9
+; CHECK-NEXT: str x9, [sp, #728] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #12
+; CHECK-NEXT: str x9, [sp, #720] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #13
+; CHECK-NEXT: str x9, [sp, #712] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #14
+; CHECK-NEXT: str x9, [sp, #704] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x15, #15
+; CHECK-NEXT: str x9, [sp, #696] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #1
+; CHECK-NEXT: str x9, [sp, #688] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #2
+; CHECK-NEXT: str x9, [sp, #680] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #3
+; CHECK-NEXT: str x9, [sp, #672] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #6
+; CHECK-NEXT: str x9, [sp, #664] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #7
+; CHECK-NEXT: str x9, [sp, #656] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #8
+; CHECK-NEXT: str x9, [sp, #648] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #9
+; CHECK-NEXT: str x9, [sp, #640] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #12
+; CHECK-NEXT: str x9, [sp, #632] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #13
+; CHECK-NEXT: str x9, [sp, #624] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #14
+; CHECK-NEXT: str x9, [sp, #616] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x3, #15
+; CHECK-NEXT: str x9, [sp, #608] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #1
+; CHECK-NEXT: str x9, [sp, #600] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #2
+; CHECK-NEXT: str x9, [sp, #592] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #3
+; CHECK-NEXT: str x9, [sp, #584] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #4
+; CHECK-NEXT: str x9, [sp, #576] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #5
+; CHECK-NEXT: str x9, [sp, #568] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #6
+; CHECK-NEXT: str x9, [sp, #560] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #7
+; CHECK-NEXT: str x9, [sp, #552] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #8
+; CHECK-NEXT: str x9, [sp, #544] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #9
+; CHECK-NEXT: str x9, [sp, #536] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #10
+; CHECK-NEXT: str x9, [sp, #528] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #11
+; CHECK-NEXT: str x9, [sp, #520] // 8-byte Spill
+; CHECK-NEXT: lsl x9, x0, #13
+; CHECK-NEXT: stp x9, x11, [sp, #504] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x0, #14
+; CHECK-NEXT: lsl x9, x0, #15
+; CHECK-NEXT: stp x9, x11, [sp, #488] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x0, #16
+; CHECK-NEXT: lsl x9, x0, #17
+; CHECK-NEXT: stp x9, x11, [sp, #472] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x0, #18
+; CHECK-NEXT: lsl x9, x0, #19
+; CHECK-NEXT: stp x9, x11, [sp, #456] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x0, #20
+; CHECK-NEXT: lsl x9, x2, #1
+; CHECK-NEXT: stp x9, x11, [sp, #440] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #2
+; CHECK-NEXT: lsl x9, x2, #3
+; CHECK-NEXT: stp x9, x11, [sp, #424] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #4
+; CHECK-NEXT: lsl x9, x2, #5
+; CHECK-NEXT: stp x9, x11, [sp, #408] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #6
+; CHECK-NEXT: lsl x9, x2, #7
+; CHECK-NEXT: stp x9, x11, [sp, #392] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #8
+; CHECK-NEXT: lsl x9, x2, #9
+; CHECK-NEXT: stp x9, x11, [sp, #376] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #10
+; CHECK-NEXT: lsl x9, x2, #11
+; CHECK-NEXT: stp x9, x11, [sp, #360] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #12
+; CHECK-NEXT: lsl x9, x2, #13
+; CHECK-NEXT: stp x9, x11, [sp, #344] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #14
+; CHECK-NEXT: lsl x9, x2, #15
+; CHECK-NEXT: stp x9, x11, [sp, #328] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #16
+; CHECK-NEXT: lsl x9, x2, #17
+; CHECK-NEXT: stp x9, x11, [sp, #312] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #18
+; CHECK-NEXT: lsl x9, x2, #19
+; CHECK-NEXT: stp x9, x11, [sp, #296] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #20
+; CHECK-NEXT: lsl x9, x2, #21
+; CHECK-NEXT: stp x9, x11, [sp, #280] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #22
+; CHECK-NEXT: lsl x9, x2, #23
+; CHECK-NEXT: stp x9, x11, [sp, #264] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #24
+; CHECK-NEXT: lsl x9, x2, #25
+; CHECK-NEXT: stp x9, x11, [sp, #248] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #26
+; CHECK-NEXT: lsl x9, x2, #27
+; CHECK-NEXT: stp x9, x11, [sp, #232] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #28
+; CHECK-NEXT: lsl x9, x2, #29
+; CHECK-NEXT: stp x9, x11, [sp, #216] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #30
+; CHECK-NEXT: lsl x9, x2, #31
+; CHECK-NEXT: stp x9, x11, [sp, #200] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #32
+; CHECK-NEXT: lsl x9, x2, #33
+; CHECK-NEXT: stp x9, x11, [sp, #184] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x2, #34
+; CHECK-NEXT: lsl x9, x2, #35
+; CHECK-NEXT: stp x9, x11, [sp, #168] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x10, #1
+; CHECK-NEXT: lsl x9, x10, #2
+; CHECK-NEXT: stp x9, x11, [sp, #152] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x10, #3
+; CHECK-NEXT: lsl x9, x10, #6
+; CHECK-NEXT: stp x9, x11, [sp, #136] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x10, #7
+; CHECK-NEXT: lsl x9, x10, #8
+; CHECK-NEXT: stp x9, x11, [sp, #120] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x10, #9
+; CHECK-NEXT: lsl x9, x10, #12
+; CHECK-NEXT: stp x9, x11, [sp, #104] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x10, #13
+; CHECK-NEXT: lsl x9, x10, #14
+; CHECK-NEXT: stp x9, x11, [sp, #88] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x11, x10, #15
+; CHECK-NEXT: lsl x9, x4, #1
+; CHECK-NEXT: lsl x10, x4, #2
+; CHECK-NEXT: stp x9, x11, [sp, #72] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x9, x4, #3
+; CHECK-NEXT: stp x9, x10, [sp, #56] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x10, x4, #6
+; CHECK-NEXT: lsl x9, x4, #7
+; CHECK-NEXT: stp x9, x10, [sp, #40] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x10, x4, #8
+; CHECK-NEXT: lsl x9, x4, #9
+; CHECK-NEXT: stp x9, x10, [sp, #24] // 16-byte Folded Spill
+; CHECK-NEXT: lsl x10, x4, #13
+; CHECK-NEXT: lsl x9, x4, #14
+; CHECK-NEXT: stp x9, x10, [sp, #8] // 16-byte Folded Spill
+; CHECK-NEXT: mov w10, #1148846080 // =0x447a0000
+; CHECK-NEXT: fmov s5, w10
+; CHECK-NEXT: mov w10, #1 // =0x1
+; CHECK-NEXT: .LBB0_1: // %for.body
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ands w2, w10, #0x1
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldr x10, [sp, #1816] // 8-byte Reload
+; CHECK-NEXT: fcsel s6, s2, s1, ne
+; CHECK-NEXT: ldr x14, [sp, #1808] // 8-byte Reload
+; CHECK-NEXT: ldr x0, [sp, #1536] // 8-byte Reload
+; CHECK-NEXT: ldr x16, [sp, #1696] // 8-byte Reload
+; CHECK-NEXT: ldr x4, [sp, #1688] // 8-byte Reload
+; CHECK-NEXT: ldr x5, [sp, #1680] // 8-byte Reload
+; CHECK-NEXT: csel x3, x14, x10, ne
+; CHECK-NEXT: csel x10, x10, x14, ne
+; CHECK-NEXT: ldr x19, [sp, #1672] // 8-byte Reload
+; CHECK-NEXT: fadd s6, s0, s6
+; CHECK-NEXT: bics xzr, x0, x3
+; CHECK-NEXT: ldr x20, [sp, #1664] // 8-byte Reload
+; CHECK-NEXT: ldr x21, [sp, #1656] // 8-byte Reload
+; CHECK-NEXT: ldr x22, [sp, #1648] // 8-byte Reload
+; CHECK-NEXT: ldr x23, [sp, #1640] // 8-byte Reload
+; CHECK-NEXT: ldr x24, [sp, #1632] // 8-byte Reload
+; CHECK-NEXT: ldr x25, [sp, #1624] // 8-byte Reload
+; CHECK-NEXT: ldr x26, [sp, #1616] // 8-byte Reload
+; CHECK-NEXT: ldr x27, [sp, #1608] // 8-byte Reload
+; CHECK-NEXT: ldr x28, [sp, #1600] // 8-byte Reload
+; CHECK-NEXT: ldr x29, [sp, #1592] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: ldr x30, [sp, #1584] // 8-byte Reload
+; CHECK-NEXT: ldr x11, [sp, #1576] // 8-byte Reload
+; CHECK-NEXT: ldr x9, [sp, #1544] // 8-byte Reload
+; CHECK-NEXT: ldr x14, [sp, #1776] // 8-byte Reload
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x16, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x4, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x5, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x19, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x20, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x21, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x22, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x23, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x24, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x25, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x26, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x27, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x28, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x29, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x30, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x12, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x17, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x18, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1528] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1520] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1512] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1504] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1496] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1488] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1480] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1472] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1464] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1456] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1448] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1440] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1432] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1424] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1416] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1408] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1400] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1392] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1384] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1376] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1368] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1360] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1352] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1792] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1344] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1336] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1328] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1320] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1312] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1304] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1296] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1288] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1280] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1272] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1264] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1728] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1256] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1248] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1240] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1232] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1224] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1216] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1208] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1200] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1192] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1184] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: ldr x14, [sp, #1176] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: bics xzr, x14, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s5, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w13, w13, w8, eq
+; CHECK-NEXT: ldr x8, [sp, #1800] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w13
+; CHECK-NEXT: bic x15, x8, x3
+; CHECK-NEXT: and x8, x0, x10
+; CHECK-NEXT: orr x15, x15, x8
+; CHECK-NEXT: cmp x15, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w14, s7
+; CHECK-NEXT: csel w13, w14, w13, eq
+; CHECK-NEXT: ldr x14, [sp, #1168] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w13
+; CHECK-NEXT: bic x0, x14, x3
+; CHECK-NEXT: and x14, x16, x10
+; CHECK-NEXT: ldr x16, [sp, #1144] // 8-byte Reload
+; CHECK-NEXT: orr x0, x0, x14
+; CHECK-NEXT: cmp x0, #0
+; CHECK-NEXT: bic x7, x16, x3
+; CHECK-NEXT: ldr x16, [sp, #1136] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w15, s7
+; CHECK-NEXT: csel w15, w15, w13, eq
+; CHECK-NEXT: ldr x13, [sp, #1160] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w15
+; CHECK-NEXT: bic x1, x13, x3
+; CHECK-NEXT: and x13, x4, x10
+; CHECK-NEXT: orr x1, x1, x13
+; CHECK-NEXT: cmp x1, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w0, s7
+; CHECK-NEXT: csel w0, w0, w15, eq
+; CHECK-NEXT: ldr x15, [sp, #1152] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w0
+; CHECK-NEXT: bic x6, x15, x3
+; CHECK-NEXT: and x15, x5, x10
+; CHECK-NEXT: orr x6, x6, x15
+; CHECK-NEXT: cmp x6, #0
+; CHECK-NEXT: and x6, x19, x10
+; CHECK-NEXT: bic x19, x16, x3
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: orr x7, x7, x6
+; CHECK-NEXT: ldr x16, [sp, #1128] // 8-byte Reload
+; CHECK-NEXT: fcvtzs w1, s7
+; CHECK-NEXT: csel w0, w1, w0, eq
+; CHECK-NEXT: cmp x7, #0
+; CHECK-NEXT: scvtf s7, w0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w1, s7
+; CHECK-NEXT: csel w0, w1, w0, eq
+; CHECK-NEXT: and x1, x20, x10
+; CHECK-NEXT: bic x20, x16, x3
+; CHECK-NEXT: scvtf s7, w0
+; CHECK-NEXT: orr x19, x19, x1
+; CHECK-NEXT: ldr x16, [sp, #1120] // 8-byte Reload
+; CHECK-NEXT: cmp x19, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w7, s7
+; CHECK-NEXT: csel w7, w7, w0, eq
+; CHECK-NEXT: and x0, x21, x10
+; CHECK-NEXT: bic x21, x16, x3
+; CHECK-NEXT: scvtf s7, w7
+; CHECK-NEXT: orr x20, x20, x0
+; CHECK-NEXT: ldr x16, [sp, #1112] // 8-byte Reload
+; CHECK-NEXT: cmp x20, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w19, s7
+; CHECK-NEXT: csel w19, w19, w7, eq
+; CHECK-NEXT: and x7, x22, x10
+; CHECK-NEXT: bic x22, x16, x3
+; CHECK-NEXT: scvtf s7, w19
+; CHECK-NEXT: orr x21, x21, x7
+; CHECK-NEXT: ldr x16, [sp, #1104] // 8-byte Reload
+; CHECK-NEXT: cmp x21, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w20, s7
+; CHECK-NEXT: csel w20, w20, w19, eq
+; CHECK-NEXT: and x19, x23, x10
+; CHECK-NEXT: bic x23, x16, x3
+; CHECK-NEXT: scvtf s7, w20
+; CHECK-NEXT: orr x22, x22, x19
+; CHECK-NEXT: ldr x16, [sp, #1096] // 8-byte Reload
+; CHECK-NEXT: cmp x22, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w21, s7
+; CHECK-NEXT: csel w21, w21, w20, eq
+; CHECK-NEXT: and x20, x24, x10
+; CHECK-NEXT: bic x24, x16, x3
+; CHECK-NEXT: scvtf s7, w21
+; CHECK-NEXT: orr x23, x23, x20
+; CHECK-NEXT: ldr x16, [sp, #1088] // 8-byte Reload
+; CHECK-NEXT: cmp x23, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w22, s7
+; CHECK-NEXT: csel w22, w22, w21, eq
+; CHECK-NEXT: and x21, x25, x10
+; CHECK-NEXT: bic x25, x16, x3
+; CHECK-NEXT: scvtf s7, w22
+; CHECK-NEXT: orr x24, x24, x21
+; CHECK-NEXT: ldr x16, [sp, #1080] // 8-byte Reload
+; CHECK-NEXT: cmp x24, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w23, s7
+; CHECK-NEXT: csel w23, w23, w22, eq
+; CHECK-NEXT: and x22, x26, x10
+; CHECK-NEXT: bic x26, x16, x3
+; CHECK-NEXT: scvtf s7, w23
+; CHECK-NEXT: orr x25, x25, x22
+; CHECK-NEXT: ldr x16, [sp, #1072] // 8-byte Reload
+; CHECK-NEXT: cmp x25, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w24, s7
+; CHECK-NEXT: csel w24, w24, w23, eq
+; CHECK-NEXT: and x23, x27, x10
+; CHECK-NEXT: bic x27, x16, x3
+; CHECK-NEXT: scvtf s7, w24
+; CHECK-NEXT: orr x26, x26, x23
+; CHECK-NEXT: ldr x16, [sp, #1064] // 8-byte Reload
+; CHECK-NEXT: cmp x26, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w25, s7
+; CHECK-NEXT: csel w25, w25, w24, eq
+; CHECK-NEXT: and x24, x28, x10
+; CHECK-NEXT: bic x28, x16, x3
+; CHECK-NEXT: scvtf s7, w25
+; CHECK-NEXT: orr x27, x27, x24
+; CHECK-NEXT: ldr x16, [sp, #1056] // 8-byte Reload
+; CHECK-NEXT: cmp x27, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w26, s7
+; CHECK-NEXT: csel w26, w26, w25, eq
+; CHECK-NEXT: and x25, x29, x10
+; CHECK-NEXT: bic x29, x16, x3
+; CHECK-NEXT: scvtf s7, w26
+; CHECK-NEXT: orr x28, x28, x25
+; CHECK-NEXT: ldr x16, [sp, #1048] // 8-byte Reload
+; CHECK-NEXT: cmp x28, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w27, s7
+; CHECK-NEXT: csel w27, w27, w26, eq
+; CHECK-NEXT: and x26, x30, x10
+; CHECK-NEXT: bic x30, x16, x3
+; CHECK-NEXT: scvtf s7, w27
+; CHECK-NEXT: orr x29, x29, x26
+; CHECK-NEXT: cmp x29, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w28, s7
+; CHECK-NEXT: csel w28, w28, w27, eq
+; CHECK-NEXT: and x27, x11, x10
+; CHECK-NEXT: ldr x11, [sp, #1040] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w28
+; CHECK-NEXT: orr x30, x30, x27
+; CHECK-NEXT: cmp x30, #0
+; CHECK-NEXT: bic x16, x11, x3
+; CHECK-NEXT: ldr x11, [sp, #1032] // 8-byte Reload
+; CHECK-NEXT: bic x4, x11, x3
+; CHECK-NEXT: ldr x11, [sp, #1024] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: bic x5, x11, x3
+; CHECK-NEXT: ldr x11, [sp, #1016] // 8-byte Reload
+; CHECK-NEXT: fcvtzs w29, s7
+; CHECK-NEXT: csel w29, w29, w28, eq
+; CHECK-NEXT: and x28, x12, x10
+; CHECK-NEXT: scvtf s7, w29
+; CHECK-NEXT: orr x16, x16, x28
+; CHECK-NEXT: cmp x16, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w30, s7
+; CHECK-NEXT: csel w16, w30, w29, eq
+; CHECK-NEXT: and x29, x17, x10
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: orr x4, x4, x29
+; CHECK-NEXT: cmp x4, #0
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w30, s7
+; CHECK-NEXT: csel w16, w30, w16, eq
+; CHECK-NEXT: and x30, x18, x10
+; CHECK-NEXT: and x10, x9, x10
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: orr x5, x5, x30
+; CHECK-NEXT: ldr x9, [sp, #1008] // 8-byte Reload
+; CHECK-NEXT: cmp x5, #0
+; CHECK-NEXT: bic x5, x11, x3
+; CHECK-NEXT: orr x5, x5, x10
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: cmp x5, #0
+; CHECK-NEXT: ldr x5, [sp, #1760] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x5, x3
+; CHECK-NEXT: ldr x5, [sp, #1784] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #1000] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #992] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #984] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #976] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #968] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #960] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #952] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #944] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #936] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #928] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #920] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #912] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #904] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #896] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #888] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #880] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #872] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #864] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #856] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #848] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #840] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #832] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #824] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #816] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #808] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #800] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #792] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #784] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #776] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x5, x3
+; CHECK-NEXT: ldr x5, [sp, #1744] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #768] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #760] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #752] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #744] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #736] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #728] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #720] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #712] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #704] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #696] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #688] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x5, x3
+; CHECK-NEXT: ldr x5, [sp, #1768] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: bic x5, x5, x3
+; CHECK-NEXT: orr x8, x5, x8
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #680] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #672] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #664] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #656] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #648] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #640] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #632] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #624] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #616] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #608] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #600] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s3, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w16, w4, w16, eq
+; CHECK-NEXT: cmp x8, #0
+; CHECK-NEXT: scvtf s7, w16
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w4, s7
+; CHECK-NEXT: csel w8, w4, w16, eq
+; CHECK-NEXT: bic x4, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #592] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x4, x14
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w16, s7
+; CHECK-NEXT: csel w8, w16, w8, eq
+; CHECK-NEXT: bic x16, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #584] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x13, x16, x13
+; CHECK-NEXT: cmp x13, #0
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w14, s7
+; CHECK-NEXT: csel w8, w14, w8, eq
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #576] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x15
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: ldr x9, [sp, #568] // 8-byte Reload
+; CHECK-NEXT: orr x14, x14, x6
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x1
+; CHECK-NEXT: ldr x9, [sp, #560] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x0
+; CHECK-NEXT: ldr x9, [sp, #552] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x7
+; CHECK-NEXT: ldr x9, [sp, #544] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x19
+; CHECK-NEXT: ldr x9, [sp, #536] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x20
+; CHECK-NEXT: ldr x9, [sp, #528] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x21
+; CHECK-NEXT: ldr x9, [sp, #520] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x22
+; CHECK-NEXT: ldp x9, x11, [sp, #504] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x23
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x24
+; CHECK-NEXT: ldp x9, x11, [sp, #488] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x25
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x26
+; CHECK-NEXT: ldp x9, x11, [sp, #472] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x27
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x28
+; CHECK-NEXT: ldp x9, x11, [sp, #456] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x29
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x14, x14, x30
+; CHECK-NEXT: ldp x9, x11, [sp, #440] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x14, #0
+; CHECK-NEXT: bic x14, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: orr x10, x14, x10
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: cmp x10, #0
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w13, s7
+; CHECK-NEXT: csel w8, w13, w8, eq
+; CHECK-NEXT: ldr x13, [sp, #1752] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: bics xzr, x13, x3
+; CHECK-NEXT: ldr x13, [sp, #1720] // 8-byte Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #424] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #408] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #392] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #376] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #360] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #344] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #328] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #312] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #296] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #280] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #264] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #248] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #232] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #216] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #200] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #184] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #168] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #152] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x13, x3
+; CHECK-NEXT: ldr x13, [sp, #1736] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #136] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #120] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #104] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #88] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #72] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x13, x3
+; CHECK-NEXT: ldr x13, [sp, #1712] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #56] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #40] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #24] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: ldp x9, x11, [sp, #8] // 16-byte Folded Reload
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x13, x3
+; CHECK-NEXT: ldr x13, [sp, #1704] // 8-byte Reload
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x11, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x9, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s7, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s7
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: bics xzr, x13, x3
+; CHECK-NEXT: scvtf s7, w8
+; CHECK-NEXT: fmadd s6, s6, s4, s7
+; CHECK-NEXT: fcvtzs w10, s6
+; CHECK-NEXT: csel w8, w10, w8, eq
+; CHECK-NEXT: mov w10, wzr
+; CHECK-NEXT: cbnz w2, .LBB0_1
+; CHECK-NEXT: // %bb.2: // %for.end334
+; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: add sp, sp, #1824
+; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x28, x27, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x30, [sp], #96 // 16-byte Folded Reload
+; CHECK-NEXT: ret
+entry:
+ %0 = load i64, ptr @C4VERT, align 8
+ %1 = load i64, ptr @C4HORIZ, align 8
+ %2 = load i64, ptr @C4UP_R, align 8
+ %3 = load i64, ptr @C4UP_L, align 8
+ %4 = load i64, ptr @C3VERT, align 8
+ %5 = load i64, ptr @C3HORIZ, align 8
+ %6 = load i64, ptr @C3UP_R, align 8
+ %7 = load i64, ptr @C3UP_L, align 8
+ %8 = load i64, ptr @C2VERT, align 8
+ %9 = load i64, ptr @C2HORIZ, align 8
+ %10 = load i64, ptr @C2UP_R, align 8
+ %11 = load i64, ptr @C2UP_L, align 8
+ %12 = load i32, ptr @off, align 4
+ %conv2 = sitofp i32 %12 to float
+ %div3 = fdiv float %conv2, 1.000000e+01
+ %shl313.2679 = shl i64 %11, 12
+ %shl313.3.2 = shl i64 %11, 15
+ %shl.1 = shl i64 %0, 1
+ %shl.2 = shl i64 %0, 2
+ %shl.3 = shl i64 %0, 3
+ %shl.4 = shl i64 %0, 4
+ %shl.5 = shl i64 %0, 5
+ %shl.6 = shl i64 %0, 6
+ %shl.7 = shl i64 %0, 7
+ %shl.8 = shl i64 %0, 8
+ %shl.9 = shl i64 %0, 9
+ %shl.10 = shl i64 %0, 10
+ %shl.11 = shl i64 %0, 11
+ %shl.12 = shl i64 %0, 12
+ %shl.13 = shl i64 %0, 13
+ %shl.14 = shl i64 %0, 14
+ %shl.15 = shl i64 %0, 15
+ %shl.16 = shl i64 %0, 16
+ %shl.17 = shl i64 %0, 17
+ %shl.18 = shl i64 %0, 18
+ %shl.19 = shl i64 %0, 19
+ %shl.20 = shl i64 %0, 20
+ %shl27.1 = shl i64 %1, 1
+ %shl27.2 = shl i64 %1, 2
+ %shl27.3 = shl i64 %1, 3
+ %shl27.1507 = shl i64 %1, 6
+ %shl27.1.1 = shl i64 %1, 7
+ %shl27.2.1 = shl i64 %1, 8
+ %shl27.3.1 = shl i64 %1, 9
+ %shl27.2513 = shl i64 %1, 12
+ %shl27.1.2 = shl i64 %1, 13
+ %shl27.2.2 = shl i64 %1, 14
+ %shl27.3.2 = shl i64 %1, 15
+ %shl27.3519 = shl i64 %1, 18
+ %shl27.1.3 = shl i64 %1, 19
+ %shl27.2.3 = shl i64 %1, 20
+ %shl27.3.3 = shl i64 %1, 21
+ %shl27.4 = shl i64 %1, 24
+ %shl27.1.4 = shl i64 %1, 25
+ %shl27.2.4 = shl i64 %1, 26
+ %shl27.3.4 = shl i64 %1, 27
+ %shl27.5 = shl i64 %1, 30
+ %shl27.1.5 = shl i64 %1, 31
+ %shl27.2.5 = shl i64 %1, 32
+ %shl27.3.5 = shl i64 %1, 33
+ %shl57.1 = shl i64 %2, 1
+ %shl57.2 = shl i64 %2, 2
+ %shl57.3 = shl i64 %2, 3
+ %shl57.1529 = shl i64 %2, 6
+ %shl57.1.1 = shl i64 %2, 7
+ %shl57.2.1 = shl i64 %2, 8
+ %shl57.3.1 = shl i64 %2, 9
+ %shl57.2535 = shl i64 %2, 12
+ %shl57.1.2 = shl i64 %2, 13
+ %shl57.2.2 = shl i64 %2, 14
+ %shl57.3.2 = shl i64 %2, 15
+ %shl87.1 = shl i64 %3, 1
+ %shl87.2 = shl i64 %3, 2
+ %shl87.3 = shl i64 %3, 3
+ %shl87.1545 = shl i64 %3, 6
+ %shl87.1.1 = shl i64 %3, 7
+ %shl87.2.1 = shl i64 %3, 8
+ %shl87.3.1 = shl i64 %3, 9
+ %shl87.2551 = shl i64 %3, 12
+ %shl87.1.2 = shl i64 %3, 13
+ %shl87.2.2 = shl i64 %3, 14
+ %shl87.3.2 = shl i64 %3, 15
+ %shl111.1 = shl i64 %4, 1
+ %shl111.2 = shl i64 %4, 2
+ %shl111.3 = shl i64 %4, 3
+ %shl111.4 = shl i64 %4, 4
+ %shl111.5 = shl i64 %4, 5
+ %shl111.6 = shl i64 %4, 6
+ %shl111.7 = shl i64 %4, 7
+ %shl111.8 = shl i64 %4, 8
+ %shl111.9 = shl i64 %4, 9
+ %shl111.10 = shl i64 %4, 10
+ %shl111.11 = shl i64 %4, 11
+ %shl111.12 = shl i64 %4, 12
+ %shl111.13 = shl i64 %4, 13
+ %shl111.14 = shl i64 %4, 14
+ %shl111.15 = shl i64 %4, 15
+ %shl111.16 = shl i64 %4, 16
+ %shl111.17 = shl i64 %4, 17
+ %shl111.18 = shl i64 %4, 18
+ %shl111.19 = shl i64 %4, 19
+ %shl111.20 = shl i64 %4, 20
+ %shl139.1 = shl i64 %5, 1
+ %shl139.2 = shl i64 %5, 2
+ %shl139.3 = shl i64 %5, 3
+ %shl139.4 = shl i64 %5, 4
+ %shl139.1562 = shl i64 %5, 6
+ %shl139.1.1 = shl i64 %5, 7
+ %shl139.2.1 = shl i64 %5, 8
+ %shl139.3.1 = shl i64 %5, 9
+ %shl139.4.1 = shl i64 %5, 10
+ %shl139.2568 = shl i64 %5, 12
+ %shl139.1.2 = shl i64 %5, 13
+ %shl139.2.2 = shl i64 %5, 14
+ %shl139.3.2 = shl i64 %5, 15
+ %shl139.4.2 = shl i64 %5, 16
+ %shl139.3574 = shl i64 %5, 18
+ %shl139.1.3 = shl i64 %5, 19
+ %shl139.2.3 = shl i64 %5, 20
+ %shl139.3.3 = shl i64 %5, 21
+ %shl139.4.3 = shl i64 %5, 22
+ %shl139.4580 = shl i64 %5, 24
+ %shl139.1.4 = shl i64 %5, 25
+ %shl139.2.4 = shl i64 %5, 26
+ %shl139.3.4 = shl i64 %5, 27
+ %shl139.4.4 = shl i64 %5, 28
+ %shl139.5 = shl i64 %5, 30
+ %shl139.1.5 = shl i64 %5, 31
+ %shl139.2.5 = shl i64 %5, 32
+ %shl139.3.5 = shl i64 %5, 33
+ %shl139.4.5 = shl i64 %5, 34
+ %shl169.1 = shl i64 %6, 1
+ %shl169.2 = shl i64 %6, 2
+ %shl169.3 = shl i64 %6, 3
+ %shl169.1590 = shl i64 %6, 6
+ %shl169.1.1 = shl i64 %6, 7
+ %shl169.2.1 = shl i64 %6, 8
+ %shl169.3.1 = shl i64 %6, 9
+ %shl169.2596 = shl i64 %6, 12
+ %shl169.1.2 = shl i64 %6, 13
+ %shl169.2.2 = shl i64 %6, 14
+ %shl169.3.2 = shl i64 %6, 15
+ %shl199.1 = shl i64 %7, 1
+ %shl199.2 = shl i64 %7, 2
+ %shl199.3 = shl i64 %7, 3
+ %shl199.1606 = shl i64 %7, 6
+ %shl199.1.1 = shl i64 %7, 7
+ %shl199.2.1 = shl i64 %7, 8
+ %shl199.3.1 = shl i64 %7, 9
+ %shl199.2612 = shl i64 %7, 12
+ %shl199.1.2 = shl i64 %7, 13
+ %shl199.2.2 = shl i64 %7, 14
+ %shl199.3.2 = shl i64 %7, 15
+ %shl223.1 = shl i64 %8, 1
+ %shl223.2 = shl i64 %8, 2
+ %shl223.3 = shl i64 %8, 3
+ %shl223.4 = shl i64 %8, 4
+ %shl223.5 = shl i64 %8, 5
+ %shl223.6 = shl i64 %8, 6
+ %shl223.7 = shl i64 %8, 7
+ %shl223.8 = shl i64 %8, 8
+ %shl223.9 = shl i64 %8, 9
+ %shl223.10 = shl i64 %8, 10
+ %shl223.11 = shl i64 %8, 11
+ %shl223.12 = shl i64 %8, 12
+ %shl223.13 = shl i64 %8, 13
+ %shl223.14 = shl i64 %8, 14
+ %shl223.15 = shl i64 %8, 15
+ %shl223.16 = shl i64 %8, 16
+ %shl223.17 = shl i64 %8, 17
+ %shl223.18 = shl i64 %8, 18
+ %shl223.19 = shl i64 %8, 19
+ %shl223.20 = shl i64 %8, 20
+ %shl253.1 = shl i64 %9, 1
+ %shl253.2 = shl i64 %9, 2
+ %shl253.3 = shl i64 %9, 3
+ %shl253.4 = shl i64 %9, 4
+ %shl253.5 = shl i64 %9, 5
+ %shl253.1623 = shl i64 %9, 6
+ %shl253.1.1 = shl i64 %9, 7
+ %shl253.2.1 = shl i64 %9, 8
+ %shl253.3.1 = shl i64 %9, 9
+ %shl253.4.1 = shl i64 %9, 10
+ %shl253.5.1 = shl i64 %9, 11
+ %shl253.2629 = shl i64 %9, 12
+ %shl253.1.2 = shl i64 %9, 13
+ %shl253.2.2 = shl i64 %9, 14
+ %shl253.3.2 = shl i64 %9, 15
+ %shl253.4.2 = shl i64 %9, 16
+ %shl253.5.2 = shl i64 %9, 17
+ %shl253.3635 = shl i64 %9, 18
+ %shl253.1.3 = shl i64 %9, 19
+ %shl253.2.3 = shl i64 %9, 20
+ %shl253.3.3 = shl i64 %9, 21
+ %shl253.4.3 = shl i64 %9, 22
+ %shl253.5.3 = shl i64 %9, 23
+ %shl253.4641 = shl i64 %9, 24
+ %shl253.1.4 = shl i64 %9, 25
+ %shl253.2.4 = shl i64 %9, 26
+ %shl253.3.4 = shl i64 %9, 27
+ %shl253.4.4 = shl i64 %9, 28
+ %shl253.5.4 = shl i64 %9, 29
+ %shl253.5647 = shl i64 %9, 30
+ %shl253.1.5 = shl i64 %9, 31
+ %shl253.2.5 = shl i64 %9, 32
+ %shl253.3.5 = shl i64 %9, 33
+ %shl253.4.5 = shl i64 %9, 34
+ %shl253.5.5 = shl i64 %9, 35
+ %shl283.1 = shl i64 %10, 1
+ %shl283.2 = shl i64 %10, 2
+ %shl283.3 = shl i64 %10, 3
+ %shl283.1657 = shl i64 %10, 6
+ %shl283.1.1 = shl i64 %10, 7
+ %shl283.2.1 = shl i64 %10, 8
+ %shl283.3.1 = shl i64 %10, 9
+ %shl283.2663 = shl i64 %10, 12
+ %shl283.1.2 = shl i64 %10, 13
+ %shl283.2.2 = shl i64 %10, 14
+ %shl283.3.2 = shl i64 %10, 15
+ %shl313.1 = shl i64 %11, 1
+ %shl313.2 = shl i64 %11, 2
+ %shl313.3 = shl i64 %11, 3
+ %shl313.1673 = shl i64 %11, 6
+ %shl313.1.1 = shl i64 %11, 7
+ %shl313.2.1 = shl i64 %11, 8
+ %shl313.3.1 = shl i64 %11, 9
+ %shl313.1.2 = shl i64 %11, 13
+ %shl313.2.2 = shl i64 %11, 14
+ br label %for.body
+
+for.body: ; preds = %entry, %for.body
+ %value.0501 = phi i32 [ 0, %entry ], [ %value.33.3.2, %for.body ]
+ %cmp1 = phi i1 [ true, %entry ], [ false, %for.body ]
+ %b1.b2 = select i1 %cmp1, i64 %b1, i64 %b2
+ %add.add4.v = select i1 %cmp1, float -1.000000e+00, float 1.000000e+00
+ %add.add4 = fadd float %div3, %add.add4.v
+ %and = and i64 %0, %b1.b2
+ %cmp11 = icmp eq i64 %and, %0
+ %conv14 = sitofp i32 %value.0501 to float
+ %13 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14)
+ %conv15 = fptosi float %13 to i32
+ %value.2 = select i1 %cmp11, i32 %conv15, i32 %value.0501
+ %and.1 = and i64 %shl.1, %b1.b2
+ %cmp11.1 = icmp eq i64 %and.1, %shl.1
+ %conv14.1 = sitofp i32 %value.2 to float
+ %14 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.1)
+ %conv15.1 = fptosi float %14 to i32
+ %value.2.1 = select i1 %cmp11.1, i32 %conv15.1, i32 %value.2
+ %and.2 = and i64 %shl.2, %b1.b2
+ %cmp11.2 = icmp eq i64 %and.2, %shl.2
+ %conv14.2 = sitofp i32 %value.2.1 to float
+ %15 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.2)
+ %conv15.2 = fptosi float %15 to i32
+ %value.2.2 = select i1 %cmp11.2, i32 %conv15.2, i32 %value.2.1
+ %and.3 = and i64 %shl.3, %b1.b2
+ %cmp11.3 = icmp eq i64 %and.3, %shl.3
+ %conv14.3 = sitofp i32 %value.2.2 to float
+ %16 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.3)
+ %conv15.3 = fptosi float %16 to i32
+ %value.2.3 = select i1 %cmp11.3, i32 %conv15.3, i32 %value.2.2
+ %and.4 = and i64 %shl.4, %b1.b2
+ %cmp11.4 = icmp eq i64 %and.4, %shl.4
+ %conv14.4 = sitofp i32 %value.2.3 to float
+ %17 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.4)
+ %conv15.4 = fptosi float %17 to i32
+ %value.2.4 = select i1 %cmp11.4, i32 %conv15.4, i32 %value.2.3
+ %and.5 = and i64 %shl.5, %b1.b2
+ %cmp11.5 = icmp eq i64 %and.5, %shl.5
+ %conv14.5 = sitofp i32 %value.2.4 to float
+ %18 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.5)
+ %conv15.5 = fptosi float %18 to i32
+ %value.2.5 = select i1 %cmp11.5, i32 %conv15.5, i32 %value.2.4
+ %and.6 = and i64 %shl.6, %b1.b2
+ %cmp11.6 = icmp eq i64 %and.6, %shl.6
+ %conv14.6 = sitofp i32 %value.2.5 to float
+ %19 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.6)
+ %conv15.6 = fptosi float %19 to i32
+ %value.2.6 = select i1 %cmp11.6, i32 %conv15.6, i32 %value.2.5
+ %and.7 = and i64 %shl.7, %b1.b2
+ %cmp11.7 = icmp eq i64 %and.7, %shl.7
+ %conv14.7 = sitofp i32 %value.2.6 to float
+ %20 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.7)
+ %conv15.7 = fptosi float %20 to i32
+ %value.2.7 = select i1 %cmp11.7, i32 %conv15.7, i32 %value.2.6
+ %and.8 = and i64 %shl.8, %b1.b2
+ %cmp11.8 = icmp eq i64 %and.8, %shl.8
+ %conv14.8 = sitofp i32 %value.2.7 to float
+ %21 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.8)
+ %conv15.8 = fptosi float %21 to i32
+ %value.2.8 = select i1 %cmp11.8, i32 %conv15.8, i32 %value.2.7
+ %and.9 = and i64 %shl.9, %b1.b2
+ %cmp11.9 = icmp eq i64 %and.9, %shl.9
+ %conv14.9 = sitofp i32 %value.2.8 to float
+ %22 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.9)
+ %conv15.9 = fptosi float %22 to i32
+ %value.2.9 = select i1 %cmp11.9, i32 %conv15.9, i32 %value.2.8
+ %and.10 = and i64 %shl.10, %b1.b2
+ %cmp11.10 = icmp eq i64 %and.10, %shl.10
+ %conv14.10 = sitofp i32 %value.2.9 to float
+ %23 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.10)
+ %conv15.10 = fptosi float %23 to i32
+ %value.2.10 = select i1 %cmp11.10, i32 %conv15.10, i32 %value.2.9
+ %and.11 = and i64 %shl.11, %b1.b2
+ %cmp11.11 = icmp eq i64 %and.11, %shl.11
+ %conv14.11 = sitofp i32 %value.2.10 to float
+ %24 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.11)
+ %conv15.11 = fptosi float %24 to i32
+ %value.2.11 = select i1 %cmp11.11, i32 %conv15.11, i32 %value.2.10
+ %and.12 = and i64 %shl.12, %b1.b2
+ %cmp11.12 = icmp eq i64 %and.12, %shl.12
+ %conv14.12 = sitofp i32 %value.2.11 to float
+ %25 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.12)
+ %conv15.12 = fptosi float %25 to i32
+ %value.2.12 = select i1 %cmp11.12, i32 %conv15.12, i32 %value.2.11
+ %and.13 = and i64 %shl.13, %b1.b2
+ %cmp11.13 = icmp eq i64 %and.13, %shl.13
+ %conv14.13 = sitofp i32 %value.2.12 to float
+ %26 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.13)
+ %conv15.13 = fptosi float %26 to i32
+ %value.2.13 = select i1 %cmp11.13, i32 %conv15.13, i32 %value.2.12
+ %and.14 = and i64 %shl.14, %b1.b2
+ %cmp11.14 = icmp eq i64 %and.14, %shl.14
+ %conv14.14 = sitofp i32 %value.2.13 to float
+ %27 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.14)
+ %conv15.14 = fptosi float %27 to i32
+ %value.2.14 = select i1 %cmp11.14, i32 %conv15.14, i32 %value.2.13
+ %and.15 = and i64 %shl.15, %b1.b2
+ %cmp11.15 = icmp eq i64 %and.15, %shl.15
+ %conv14.15 = sitofp i32 %value.2.14 to float
+ %28 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.15)
+ %conv15.15 = fptosi float %28 to i32
+ %value.2.15 = select i1 %cmp11.15, i32 %conv15.15, i32 %value.2.14
+ %and.16 = and i64 %shl.16, %b1.b2
+ %cmp11.16 = icmp eq i64 %and.16, %shl.16
+ %conv14.16 = sitofp i32 %value.2.15 to float
+ %29 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.16)
+ %conv15.16 = fptosi float %29 to i32
+ %value.2.16 = select i1 %cmp11.16, i32 %conv15.16, i32 %value.2.15
+ %and.17 = and i64 %shl.17, %b1.b2
+ %cmp11.17 = icmp eq i64 %and.17, %shl.17
+ %conv14.17 = sitofp i32 %value.2.16 to float
+ %30 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.17)
+ %conv15.17 = fptosi float %30 to i32
+ %value.2.17 = select i1 %cmp11.17, i32 %conv15.17, i32 %value.2.16
+ %and.18 = and i64 %shl.18, %b1.b2
+ %cmp11.18 = icmp eq i64 %and.18, %shl.18
+ %conv14.18 = sitofp i32 %value.2.17 to float
+ %31 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.18)
+ %conv15.18 = fptosi float %31 to i32
+ %value.2.18 = select i1 %cmp11.18, i32 %conv15.18, i32 %value.2.17
+ %and.19 = and i64 %shl.19, %b1.b2
+ %cmp11.19 = icmp eq i64 %and.19, %shl.19
+ %conv14.19 = sitofp i32 %value.2.18 to float
+ %32 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.19)
+ %conv15.19 = fptosi float %32 to i32
+ %value.2.19 = select i1 %cmp11.19, i32 %conv15.19, i32 %value.2.18
+ %and.20 = and i64 %shl.20, %b1.b2
+ %cmp11.20 = icmp eq i64 %and.20, %shl.20
+ %conv14.20 = sitofp i32 %value.2.19 to float
+ %33 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv14.20)
+ %conv15.20 = fptosi float %33 to i32
+ %value.2.20 = select i1 %cmp11.20, i32 %conv15.20, i32 %value.2.19
+ %and28 = and i64 %1, %b1.b2
+ %cmp33 = icmp eq i64 %and28, %1
+ %conv37 = sitofp i32 %value.2.20 to float
+ %34 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37)
+ %conv38 = fptosi float %34 to i32
+ %value.5 = select i1 %cmp33, i32 %conv38, i32 %value.2.20
+ %and28.1 = and i64 %shl27.1, %b1.b2
+ %cmp33.1 = icmp eq i64 %and28.1, %shl27.1
+ %conv37.1 = sitofp i32 %value.5 to float
+ %35 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1)
+ %conv38.1 = fptosi float %35 to i32
+ %value.5.1 = select i1 %cmp33.1, i32 %conv38.1, i32 %value.5
+ %and28.2 = and i64 %shl27.2, %b1.b2
+ %cmp33.2 = icmp eq i64 %and28.2, %shl27.2
+ %conv37.2 = sitofp i32 %value.5.1 to float
+ %36 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2)
+ %conv38.2 = fptosi float %36 to i32
+ %value.5.2 = select i1 %cmp33.2, i32 %conv38.2, i32 %value.5.1
+ %and28.3 = and i64 %shl27.3, %b1.b2
+ %cmp33.3 = icmp eq i64 %and28.3, %shl27.3
+ %conv37.3 = sitofp i32 %value.5.2 to float
+ %37 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3)
+ %conv38.3 = fptosi float %37 to i32
+ %value.5.3 = select i1 %cmp33.3, i32 %conv38.3, i32 %value.5.2
+ %and28.1508 = and i64 %shl27.1507, %b1.b2
+ %cmp33.1509 = icmp eq i64 %and28.1508, %shl27.1507
+ %conv37.1510 = sitofp i32 %value.5.3 to float
+ %38 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1510)
+ %conv38.1511 = fptosi float %38 to i32
+ %value.5.1512 = select i1 %cmp33.1509, i32 %conv38.1511, i32 %value.5.3
+ %and28.1.1 = and i64 %shl27.1.1, %b1.b2
+ %cmp33.1.1 = icmp eq i64 %and28.1.1, %shl27.1.1
+ %conv37.1.1 = sitofp i32 %value.5.1512 to float
+ %39 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1.1)
+ %conv38.1.1 = fptosi float %39 to i32
+ %value.5.1.1 = select i1 %cmp33.1.1, i32 %conv38.1.1, i32 %value.5.1512
+ %and28.2.1 = and i64 %shl27.2.1, %b1.b2
+ %cmp33.2.1 = icmp eq i64 %and28.2.1, %shl27.2.1
+ %conv37.2.1 = sitofp i32 %value.5.1.1 to float
+ %40 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2.1)
+ %conv38.2.1 = fptosi float %40 to i32
+ %value.5.2.1 = select i1 %cmp33.2.1, i32 %conv38.2.1, i32 %value.5.1.1
+ %and28.3.1 = and i64 %shl27.3.1, %b1.b2
+ %cmp33.3.1 = icmp eq i64 %and28.3.1, %shl27.3.1
+ %conv37.3.1 = sitofp i32 %value.5.2.1 to float
+ %41 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3.1)
+ %conv38.3.1 = fptosi float %41 to i32
+ %value.5.3.1 = select i1 %cmp33.3.1, i32 %conv38.3.1, i32 %value.5.2.1
+ %and28.2514 = and i64 %shl27.2513, %b1.b2
+ %cmp33.2515 = icmp eq i64 %and28.2514, %shl27.2513
+ %conv37.2516 = sitofp i32 %value.5.3.1 to float
+ %42 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2516)
+ %conv38.2517 = fptosi float %42 to i32
+ %value.5.2518 = select i1 %cmp33.2515, i32 %conv38.2517, i32 %value.5.3.1
+ %and28.1.2 = and i64 %shl27.1.2, %b1.b2
+ %cmp33.1.2 = icmp eq i64 %and28.1.2, %shl27.1.2
+ %conv37.1.2 = sitofp i32 %value.5.2518 to float
+ %43 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1.2)
+ %conv38.1.2 = fptosi float %43 to i32
+ %value.5.1.2 = select i1 %cmp33.1.2, i32 %conv38.1.2, i32 %value.5.2518
+ %and28.2.2 = and i64 %shl27.2.2, %b1.b2
+ %cmp33.2.2 = icmp eq i64 %and28.2.2, %shl27.2.2
+ %conv37.2.2 = sitofp i32 %value.5.1.2 to float
+ %44 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2.2)
+ %conv38.2.2 = fptosi float %44 to i32
+ %value.5.2.2 = select i1 %cmp33.2.2, i32 %conv38.2.2, i32 %value.5.1.2
+ %and28.3.2 = and i64 %shl27.3.2, %b1.b2
+ %cmp33.3.2 = icmp eq i64 %and28.3.2, %shl27.3.2
+ %conv37.3.2 = sitofp i32 %value.5.2.2 to float
+ %45 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3.2)
+ %conv38.3.2 = fptosi float %45 to i32
+ %value.5.3.2 = select i1 %cmp33.3.2, i32 %conv38.3.2, i32 %value.5.2.2
+ %and28.3520 = and i64 %shl27.3519, %b1.b2
+ %cmp33.3521 = icmp eq i64 %and28.3520, %shl27.3519
+ %conv37.3522 = sitofp i32 %value.5.3.2 to float
+ %46 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3522)
+ %conv38.3523 = fptosi float %46 to i32
+ %value.5.3524 = select i1 %cmp33.3521, i32 %conv38.3523, i32 %value.5.3.2
+ %and28.1.3 = and i64 %shl27.1.3, %b1.b2
+ %cmp33.1.3 = icmp eq i64 %and28.1.3, %shl27.1.3
+ %conv37.1.3 = sitofp i32 %value.5.3524 to float
+ %47 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1.3)
+ %conv38.1.3 = fptosi float %47 to i32
+ %value.5.1.3 = select i1 %cmp33.1.3, i32 %conv38.1.3, i32 %value.5.3524
+ %and28.2.3 = and i64 %shl27.2.3, %b1.b2
+ %cmp33.2.3 = icmp eq i64 %and28.2.3, %shl27.2.3
+ %conv37.2.3 = sitofp i32 %value.5.1.3 to float
+ %48 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2.3)
+ %conv38.2.3 = fptosi float %48 to i32
+ %value.5.2.3 = select i1 %cmp33.2.3, i32 %conv38.2.3, i32 %value.5.1.3
+ %and28.3.3 = and i64 %shl27.3.3, %b1.b2
+ %cmp33.3.3 = icmp eq i64 %and28.3.3, %shl27.3.3
+ %conv37.3.3 = sitofp i32 %value.5.2.3 to float
+ %49 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3.3)
+ %conv38.3.3 = fptosi float %49 to i32
+ %value.5.3.3 = select i1 %cmp33.3.3, i32 %conv38.3.3, i32 %value.5.2.3
+ %and28.4 = and i64 %shl27.4, %b1.b2
+ %cmp33.4 = icmp eq i64 %and28.4, %shl27.4
+ %conv37.4 = sitofp i32 %value.5.3.3 to float
+ %50 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.4)
+ %conv38.4 = fptosi float %50 to i32
+ %value.5.4 = select i1 %cmp33.4, i32 %conv38.4, i32 %value.5.3.3
+ %and28.1.4 = and i64 %shl27.1.4, %b1.b2
+ %cmp33.1.4 = icmp eq i64 %and28.1.4, %shl27.1.4
+ %conv37.1.4 = sitofp i32 %value.5.4 to float
+ %51 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1.4)
+ %conv38.1.4 = fptosi float %51 to i32
+ %value.5.1.4 = select i1 %cmp33.1.4, i32 %conv38.1.4, i32 %value.5.4
+ %and28.2.4 = and i64 %shl27.2.4, %b1.b2
+ %cmp33.2.4 = icmp eq i64 %and28.2.4, %shl27.2.4
+ %conv37.2.4 = sitofp i32 %value.5.1.4 to float
+ %52 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2.4)
+ %conv38.2.4 = fptosi float %52 to i32
+ %value.5.2.4 = select i1 %cmp33.2.4, i32 %conv38.2.4, i32 %value.5.1.4
+ %and28.3.4 = and i64 %shl27.3.4, %b1.b2
+ %cmp33.3.4 = icmp eq i64 %and28.3.4, %shl27.3.4
+ %conv37.3.4 = sitofp i32 %value.5.2.4 to float
+ %53 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3.4)
+ %conv38.3.4 = fptosi float %53 to i32
+ %value.5.3.4 = select i1 %cmp33.3.4, i32 %conv38.3.4, i32 %value.5.2.4
+ %and28.5 = and i64 %shl27.5, %b1.b2
+ %cmp33.5 = icmp eq i64 %and28.5, %shl27.5
+ %conv37.5 = sitofp i32 %value.5.3.4 to float
+ %54 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.5)
+ %conv38.5 = fptosi float %54 to i32
+ %value.5.5 = select i1 %cmp33.5, i32 %conv38.5, i32 %value.5.3.4
+ %and28.1.5 = and i64 %shl27.1.5, %b1.b2
+ %cmp33.1.5 = icmp eq i64 %and28.1.5, %shl27.1.5
+ %conv37.1.5 = sitofp i32 %value.5.5 to float
+ %55 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.1.5)
+ %conv38.1.5 = fptosi float %55 to i32
+ %value.5.1.5 = select i1 %cmp33.1.5, i32 %conv38.1.5, i32 %value.5.5
+ %and28.2.5 = and i64 %shl27.2.5, %b1.b2
+ %cmp33.2.5 = icmp eq i64 %and28.2.5, %shl27.2.5
+ %conv37.2.5 = sitofp i32 %value.5.1.5 to float
+ %56 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.2.5)
+ %conv38.2.5 = fptosi float %56 to i32
+ %value.5.2.5 = select i1 %cmp33.2.5, i32 %conv38.2.5, i32 %value.5.1.5
+ %and28.3.5 = and i64 %shl27.3.5, %b1.b2
+ %cmp33.3.5 = icmp eq i64 %and28.3.5, %shl27.3.5
+ %conv37.3.5 = sitofp i32 %value.5.2.5 to float
+ %57 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv37.3.5)
+ %conv38.3.5 = fptosi float %57 to i32
+ %value.5.3.5 = select i1 %cmp33.3.5, i32 %conv38.3.5, i32 %value.5.2.5
+ %and58 = and i64 %2, %b1.b2
+ %cmp63 = icmp eq i64 %and58, %2
+ %conv67 = sitofp i32 %value.5.3.5 to float
+ %58 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67)
+ %conv68 = fptosi float %58 to i32
+ %value.8 = select i1 %cmp63, i32 %conv68, i32 %value.5.3.5
+ %and58.1 = and i64 %shl57.1, %b1.b2
+ %cmp63.1 = icmp eq i64 %and58.1, %shl57.1
+ %conv67.1 = sitofp i32 %value.8 to float
+ %59 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.1)
+ %conv68.1 = fptosi float %59 to i32
+ %value.8.1 = select i1 %cmp63.1, i32 %conv68.1, i32 %value.8
+ %and58.2 = and i64 %shl57.2, %b1.b2
+ %cmp63.2 = icmp eq i64 %and58.2, %shl57.2
+ %conv67.2 = sitofp i32 %value.8.1 to float
+ %60 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.2)
+ %conv68.2 = fptosi float %60 to i32
+ %value.8.2 = select i1 %cmp63.2, i32 %conv68.2, i32 %value.8.1
+ %and58.3 = and i64 %shl57.3, %b1.b2
+ %cmp63.3 = icmp eq i64 %and58.3, %shl57.3
+ %conv67.3 = sitofp i32 %value.8.2 to float
+ %61 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.3)
+ %conv68.3 = fptosi float %61 to i32
+ %value.8.3 = select i1 %cmp63.3, i32 %conv68.3, i32 %value.8.2
+ %and58.1530 = and i64 %shl57.1529, %b1.b2
+ %cmp63.1531 = icmp eq i64 %and58.1530, %shl57.1529
+ %conv67.1532 = sitofp i32 %value.8.3 to float
+ %62 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.1532)
+ %conv68.1533 = fptosi float %62 to i32
+ %value.8.1534 = select i1 %cmp63.1531, i32 %conv68.1533, i32 %value.8.3
+ %and58.1.1 = and i64 %shl57.1.1, %b1.b2
+ %cmp63.1.1 = icmp eq i64 %and58.1.1, %shl57.1.1
+ %conv67.1.1 = sitofp i32 %value.8.1534 to float
+ %63 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.1.1)
+ %conv68.1.1 = fptosi float %63 to i32
+ %value.8.1.1 = select i1 %cmp63.1.1, i32 %conv68.1.1, i32 %value.8.1534
+ %and58.2.1 = and i64 %shl57.2.1, %b1.b2
+ %cmp63.2.1 = icmp eq i64 %and58.2.1, %shl57.2.1
+ %conv67.2.1 = sitofp i32 %value.8.1.1 to float
+ %64 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.2.1)
+ %conv68.2.1 = fptosi float %64 to i32
+ %value.8.2.1 = select i1 %cmp63.2.1, i32 %conv68.2.1, i32 %value.8.1.1
+ %and58.3.1 = and i64 %shl57.3.1, %b1.b2
+ %cmp63.3.1 = icmp eq i64 %and58.3.1, %shl57.3.1
+ %conv67.3.1 = sitofp i32 %value.8.2.1 to float
+ %65 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.3.1)
+ %conv68.3.1 = fptosi float %65 to i32
+ %value.8.3.1 = select i1 %cmp63.3.1, i32 %conv68.3.1, i32 %value.8.2.1
+ %and58.2536 = and i64 %shl57.2535, %b1.b2
+ %cmp63.2537 = icmp eq i64 %and58.2536, %shl57.2535
+ %conv67.2538 = sitofp i32 %value.8.3.1 to float
+ %66 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.2538)
+ %conv68.2539 = fptosi float %66 to i32
+ %value.8.2540 = select i1 %cmp63.2537, i32 %conv68.2539, i32 %value.8.3.1
+ %and58.1.2 = and i64 %shl57.1.2, %b1.b2
+ %cmp63.1.2 = icmp eq i64 %and58.1.2, %shl57.1.2
+ %conv67.1.2 = sitofp i32 %value.8.2540 to float
+ %67 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.1.2)
+ %conv68.1.2 = fptosi float %67 to i32
+ %value.8.1.2 = select i1 %cmp63.1.2, i32 %conv68.1.2, i32 %value.8.2540
+ %and58.2.2 = and i64 %shl57.2.2, %b1.b2
+ %cmp63.2.2 = icmp eq i64 %and58.2.2, %shl57.2.2
+ %conv67.2.2 = sitofp i32 %value.8.1.2 to float
+ %68 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.2.2)
+ %conv68.2.2 = fptosi float %68 to i32
+ %value.8.2.2 = select i1 %cmp63.2.2, i32 %conv68.2.2, i32 %value.8.1.2
+ %and58.3.2 = and i64 %shl57.3.2, %b1.b2
+ %cmp63.3.2 = icmp eq i64 %and58.3.2, %shl57.3.2
+ %conv67.3.2 = sitofp i32 %value.8.2.2 to float
+ %69 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv67.3.2)
+ %conv68.3.2 = fptosi float %69 to i32
+ %value.8.3.2 = select i1 %cmp63.3.2, i32 %conv68.3.2, i32 %value.8.2.2
+ %and88 = and i64 %3, %b1.b2
+ %cmp93 = icmp eq i64 %and88, %3
+ %conv97 = sitofp i32 %value.8.3.2 to float
+ %70 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97)
+ %conv98 = fptosi float %70 to i32
+ %value.11 = select i1 %cmp93, i32 %conv98, i32 %value.8.3.2
+ %and88.1 = and i64 %shl87.1, %b1.b2
+ %cmp93.1 = icmp eq i64 %and88.1, %shl87.1
+ %conv97.1 = sitofp i32 %value.11 to float
+ %71 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.1)
+ %conv98.1 = fptosi float %71 to i32
+ %value.11.1 = select i1 %cmp93.1, i32 %conv98.1, i32 %value.11
+ %and88.2 = and i64 %shl87.2, %b1.b2
+ %cmp93.2 = icmp eq i64 %and88.2, %shl87.2
+ %conv97.2 = sitofp i32 %value.11.1 to float
+ %72 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.2)
+ %conv98.2 = fptosi float %72 to i32
+ %value.11.2 = select i1 %cmp93.2, i32 %conv98.2, i32 %value.11.1
+ %and88.3 = and i64 %shl87.3, %b1.b2
+ %cmp93.3 = icmp eq i64 %and88.3, %shl87.3
+ %conv97.3 = sitofp i32 %value.11.2 to float
+ %73 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.3)
+ %conv98.3 = fptosi float %73 to i32
+ %value.11.3 = select i1 %cmp93.3, i32 %conv98.3, i32 %value.11.2
+ %and88.1546 = and i64 %shl87.1545, %b1.b2
+ %cmp93.1547 = icmp eq i64 %and88.1546, %shl87.1545
+ %conv97.1548 = sitofp i32 %value.11.3 to float
+ %74 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.1548)
+ %conv98.1549 = fptosi float %74 to i32
+ %value.11.1550 = select i1 %cmp93.1547, i32 %conv98.1549, i32 %value.11.3
+ %and88.1.1 = and i64 %shl87.1.1, %b1.b2
+ %cmp93.1.1 = icmp eq i64 %and88.1.1, %shl87.1.1
+ %conv97.1.1 = sitofp i32 %value.11.1550 to float
+ %75 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.1.1)
+ %conv98.1.1 = fptosi float %75 to i32
+ %value.11.1.1 = select i1 %cmp93.1.1, i32 %conv98.1.1, i32 %value.11.1550
+ %and88.2.1 = and i64 %shl87.2.1, %b1.b2
+ %cmp93.2.1 = icmp eq i64 %and88.2.1, %shl87.2.1
+ %conv97.2.1 = sitofp i32 %value.11.1.1 to float
+ %76 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.2.1)
+ %conv98.2.1 = fptosi float %76 to i32
+ %value.11.2.1 = select i1 %cmp93.2.1, i32 %conv98.2.1, i32 %value.11.1.1
+ %and88.3.1 = and i64 %shl87.3.1, %b1.b2
+ %cmp93.3.1 = icmp eq i64 %and88.3.1, %shl87.3.1
+ %conv97.3.1 = sitofp i32 %value.11.2.1 to float
+ %77 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.3.1)
+ %conv98.3.1 = fptosi float %77 to i32
+ %value.11.3.1 = select i1 %cmp93.3.1, i32 %conv98.3.1, i32 %value.11.2.1
+ %and88.2552 = and i64 %shl87.2551, %b1.b2
+ %cmp93.2553 = icmp eq i64 %and88.2552, %shl87.2551
+ %conv97.2554 = sitofp i32 %value.11.3.1 to float
+ %78 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.2554)
+ %conv98.2555 = fptosi float %78 to i32
+ %value.11.2556 = select i1 %cmp93.2553, i32 %conv98.2555, i32 %value.11.3.1
+ %and88.1.2 = and i64 %shl87.1.2, %b1.b2
+ %cmp93.1.2 = icmp eq i64 %and88.1.2, %shl87.1.2
+ %conv97.1.2 = sitofp i32 %value.11.2556 to float
+ %79 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.1.2)
+ %conv98.1.2 = fptosi float %79 to i32
+ %value.11.1.2 = select i1 %cmp93.1.2, i32 %conv98.1.2, i32 %value.11.2556
+ %and88.2.2 = and i64 %shl87.2.2, %b1.b2
+ %cmp93.2.2 = icmp eq i64 %and88.2.2, %shl87.2.2
+ %conv97.2.2 = sitofp i32 %value.11.1.2 to float
+ %80 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.2.2)
+ %conv98.2.2 = fptosi float %80 to i32
+ %value.11.2.2 = select i1 %cmp93.2.2, i32 %conv98.2.2, i32 %value.11.1.2
+ %and88.3.2 = and i64 %shl87.3.2, %b1.b2
+ %cmp93.3.2 = icmp eq i64 %and88.3.2, %shl87.3.2
+ %conv97.3.2 = sitofp i32 %value.11.2.2 to float
+ %81 = tail call float @llvm.fmuladd.f32(float %add.add4, float 1.000000e+03, float %conv97.3.2)
+ %conv98.3.2 = fptosi float %81 to i32
+ %value.11.3.2 = select i1 %cmp93.3.2, i32 %conv98.3.2, i32 %value.11.2.2
+ %b2.b1 = select i1 %cmp1, i64 %b2, i64 %b1
+ %and112 = and i64 %4, %b1.b2
+ %cmp115 = icmp eq i64 %and112, %4
+ %and119 = and i64 %0, %b2.b1
+ %tobool.not = icmp eq i64 %and119, 0
+ %or.cond = select i1 %cmp115, i1 %tobool.not, i1 false
+ %conv122 = sitofp i32 %value.11.3.2 to float
+ %82 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122)
+ %conv123 = fptosi float %82 to i32
+ %value.13 = select i1 %or.cond, i32 %conv123, i32 %value.11.3.2
+ %and112.1 = and i64 %shl111.1, %b1.b2
+ %cmp115.1 = icmp eq i64 %and112.1, %shl111.1
+ %and119.1 = and i64 %shl.1, %b2.b1
+ %tobool.not.1 = icmp eq i64 %and119.1, 0
+ %or.cond685 = select i1 %cmp115.1, i1 %tobool.not.1, i1 false
+ %conv122.1 = sitofp i32 %value.13 to float
+ %83 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.1)
+ %conv123.1 = fptosi float %83 to i32
+ %value.13.1 = select i1 %or.cond685, i32 %conv123.1, i32 %value.13
+ %and112.2 = and i64 %shl111.2, %b1.b2
+ %cmp115.2 = icmp eq i64 %and112.2, %shl111.2
+ %and119.2 = and i64 %shl.2, %b2.b1
+ %tobool.not.2 = icmp eq i64 %and119.2, 0
+ %or.cond686 = select i1 %cmp115.2, i1 %tobool.not.2, i1 false
+ %conv122.2 = sitofp i32 %value.13.1 to float
+ %84 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.2)
+ %conv123.2 = fptosi float %84 to i32
+ %value.13.2 = select i1 %or.cond686, i32 %conv123.2, i32 %value.13.1
+ %and112.3 = and i64 %shl111.3, %b1.b2
+ %cmp115.3 = icmp eq i64 %and112.3, %shl111.3
+ %and119.3 = and i64 %shl.3, %b2.b1
+ %tobool.not.3 = icmp eq i64 %and119.3, 0
+ %or.cond687 = select i1 %cmp115.3, i1 %tobool.not.3, i1 false
+ %conv122.3 = sitofp i32 %value.13.2 to float
+ %85 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.3)
+ %conv123.3 = fptosi float %85 to i32
+ %value.13.3 = select i1 %or.cond687, i32 %conv123.3, i32 %value.13.2
+ %and112.4 = and i64 %shl111.4, %b1.b2
+ %cmp115.4 = icmp eq i64 %and112.4, %shl111.4
+ %and119.4 = and i64 %shl.4, %b2.b1
+ %tobool.not.4 = icmp eq i64 %and119.4, 0
+ %or.cond688 = select i1 %cmp115.4, i1 %tobool.not.4, i1 false
+ %conv122.4 = sitofp i32 %value.13.3 to float
+ %86 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.4)
+ %conv123.4 = fptosi float %86 to i32
+ %value.13.4 = select i1 %or.cond688, i32 %conv123.4, i32 %value.13.3
+ %and112.5 = and i64 %shl111.5, %b1.b2
+ %cmp115.5 = icmp eq i64 %and112.5, %shl111.5
+ %and119.5 = and i64 %shl.5, %b2.b1
+ %tobool.not.5 = icmp eq i64 %and119.5, 0
+ %or.cond689 = select i1 %cmp115.5, i1 %tobool.not.5, i1 false
+ %conv122.5 = sitofp i32 %value.13.4 to float
+ %87 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.5)
+ %conv123.5 = fptosi float %87 to i32
+ %value.13.5 = select i1 %or.cond689, i32 %conv123.5, i32 %value.13.4
+ %and112.6 = and i64 %shl111.6, %b1.b2
+ %cmp115.6 = icmp eq i64 %and112.6, %shl111.6
+ %and119.6 = and i64 %shl.6, %b2.b1
+ %tobool.not.6 = icmp eq i64 %and119.6, 0
+ %or.cond690 = select i1 %cmp115.6, i1 %tobool.not.6, i1 false
+ %conv122.6 = sitofp i32 %value.13.5 to float
+ %88 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.6)
+ %conv123.6 = fptosi float %88 to i32
+ %value.13.6 = select i1 %or.cond690, i32 %conv123.6, i32 %value.13.5
+ %and112.7 = and i64 %shl111.7, %b1.b2
+ %cmp115.7 = icmp eq i64 %and112.7, %shl111.7
+ %and119.7 = and i64 %shl.7, %b2.b1
+ %tobool.not.7 = icmp eq i64 %and119.7, 0
+ %or.cond691 = select i1 %cmp115.7, i1 %tobool.not.7, i1 false
+ %conv122.7 = sitofp i32 %value.13.6 to float
+ %89 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.7)
+ %conv123.7 = fptosi float %89 to i32
+ %value.13.7 = select i1 %or.cond691, i32 %conv123.7, i32 %value.13.6
+ %and112.8 = and i64 %shl111.8, %b1.b2
+ %cmp115.8 = icmp eq i64 %and112.8, %shl111.8
+ %and119.8 = and i64 %shl.8, %b2.b1
+ %tobool.not.8 = icmp eq i64 %and119.8, 0
+ %or.cond692 = select i1 %cmp115.8, i1 %tobool.not.8, i1 false
+ %conv122.8 = sitofp i32 %value.13.7 to float
+ %90 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.8)
+ %conv123.8 = fptosi float %90 to i32
+ %value.13.8 = select i1 %or.cond692, i32 %conv123.8, i32 %value.13.7
+ %and112.9 = and i64 %shl111.9, %b1.b2
+ %cmp115.9 = icmp eq i64 %and112.9, %shl111.9
+ %and119.9 = and i64 %shl.9, %b2.b1
+ %tobool.not.9 = icmp eq i64 %and119.9, 0
+ %or.cond693 = select i1 %cmp115.9, i1 %tobool.not.9, i1 false
+ %conv122.9 = sitofp i32 %value.13.8 to float
+ %91 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.9)
+ %conv123.9 = fptosi float %91 to i32
+ %value.13.9 = select i1 %or.cond693, i32 %conv123.9, i32 %value.13.8
+ %and112.10 = and i64 %shl111.10, %b1.b2
+ %cmp115.10 = icmp eq i64 %and112.10, %shl111.10
+ %and119.10 = and i64 %shl.10, %b2.b1
+ %tobool.not.10 = icmp eq i64 %and119.10, 0
+ %or.cond694 = select i1 %cmp115.10, i1 %tobool.not.10, i1 false
+ %conv122.10 = sitofp i32 %value.13.9 to float
+ %92 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.10)
+ %conv123.10 = fptosi float %92 to i32
+ %value.13.10 = select i1 %or.cond694, i32 %conv123.10, i32 %value.13.9
+ %and112.11 = and i64 %shl111.11, %b1.b2
+ %cmp115.11 = icmp eq i64 %and112.11, %shl111.11
+ %and119.11 = and i64 %shl.11, %b2.b1
+ %tobool.not.11 = icmp eq i64 %and119.11, 0
+ %or.cond695 = select i1 %cmp115.11, i1 %tobool.not.11, i1 false
+ %conv122.11 = sitofp i32 %value.13.10 to float
+ %93 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.11)
+ %conv123.11 = fptosi float %93 to i32
+ %value.13.11 = select i1 %or.cond695, i32 %conv123.11, i32 %value.13.10
+ %and112.12 = and i64 %shl111.12, %b1.b2
+ %cmp115.12 = icmp eq i64 %and112.12, %shl111.12
+ %and119.12 = and i64 %shl.12, %b2.b1
+ %tobool.not.12 = icmp eq i64 %and119.12, 0
+ %or.cond696 = select i1 %cmp115.12, i1 %tobool.not.12, i1 false
+ %conv122.12 = sitofp i32 %value.13.11 to float
+ %94 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.12)
+ %conv123.12 = fptosi float %94 to i32
+ %value.13.12 = select i1 %or.cond696, i32 %conv123.12, i32 %value.13.11
+ %and112.13 = and i64 %shl111.13, %b1.b2
+ %cmp115.13 = icmp eq i64 %and112.13, %shl111.13
+ %and119.13 = and i64 %shl.13, %b2.b1
+ %tobool.not.13 = icmp eq i64 %and119.13, 0
+ %or.cond697 = select i1 %cmp115.13, i1 %tobool.not.13, i1 false
+ %conv122.13 = sitofp i32 %value.13.12 to float
+ %95 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.13)
+ %conv123.13 = fptosi float %95 to i32
+ %value.13.13 = select i1 %or.cond697, i32 %conv123.13, i32 %value.13.12
+ %and112.14 = and i64 %shl111.14, %b1.b2
+ %cmp115.14 = icmp eq i64 %and112.14, %shl111.14
+ %and119.14 = and i64 %shl.14, %b2.b1
+ %tobool.not.14 = icmp eq i64 %and119.14, 0
+ %or.cond698 = select i1 %cmp115.14, i1 %tobool.not.14, i1 false
+ %conv122.14 = sitofp i32 %value.13.13 to float
+ %96 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.14)
+ %conv123.14 = fptosi float %96 to i32
+ %value.13.14 = select i1 %or.cond698, i32 %conv123.14, i32 %value.13.13
+ %and112.15 = and i64 %shl111.15, %b1.b2
+ %cmp115.15 = icmp eq i64 %and112.15, %shl111.15
+ %and119.15 = and i64 %shl.15, %b2.b1
+ %tobool.not.15 = icmp eq i64 %and119.15, 0
+ %or.cond699 = select i1 %cmp115.15, i1 %tobool.not.15, i1 false
+ %conv122.15 = sitofp i32 %value.13.14 to float
+ %97 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.15)
+ %conv123.15 = fptosi float %97 to i32
+ %value.13.15 = select i1 %or.cond699, i32 %conv123.15, i32 %value.13.14
+ %and112.16 = and i64 %shl111.16, %b1.b2
+ %cmp115.16 = icmp eq i64 %and112.16, %shl111.16
+ %and119.16 = and i64 %shl.16, %b2.b1
+ %tobool.not.16 = icmp eq i64 %and119.16, 0
+ %or.cond700 = select i1 %cmp115.16, i1 %tobool.not.16, i1 false
+ %conv122.16 = sitofp i32 %value.13.15 to float
+ %98 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.16)
+ %conv123.16 = fptosi float %98 to i32
+ %value.13.16 = select i1 %or.cond700, i32 %conv123.16, i32 %value.13.15
+ %and112.17 = and i64 %shl111.17, %b1.b2
+ %cmp115.17 = icmp eq i64 %and112.17, %shl111.17
+ %and119.17 = and i64 %shl.17, %b2.b1
+ %tobool.not.17 = icmp eq i64 %and119.17, 0
+ %or.cond701 = select i1 %cmp115.17, i1 %tobool.not.17, i1 false
+ %conv122.17 = sitofp i32 %value.13.16 to float
+ %99 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.17)
+ %conv123.17 = fptosi float %99 to i32
+ %value.13.17 = select i1 %or.cond701, i32 %conv123.17, i32 %value.13.16
+ %and112.18 = and i64 %shl111.18, %b1.b2
+ %cmp115.18 = icmp eq i64 %and112.18, %shl111.18
+ %and119.18 = and i64 %shl.18, %b2.b1
+ %tobool.not.18 = icmp eq i64 %and119.18, 0
+ %or.cond702 = select i1 %cmp115.18, i1 %tobool.not.18, i1 false
+ %conv122.18 = sitofp i32 %value.13.17 to float
+ %100 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.18)
+ %conv123.18 = fptosi float %100 to i32
+ %value.13.18 = select i1 %or.cond702, i32 %conv123.18, i32 %value.13.17
+ %and112.19 = and i64 %shl111.19, %b1.b2
+ %cmp115.19 = icmp eq i64 %and112.19, %shl111.19
+ %and119.19 = and i64 %shl.19, %b2.b1
+ %tobool.not.19 = icmp eq i64 %and119.19, 0
+ %or.cond703 = select i1 %cmp115.19, i1 %tobool.not.19, i1 false
+ %conv122.19 = sitofp i32 %value.13.18 to float
+ %101 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.19)
+ %conv123.19 = fptosi float %101 to i32
+ %value.13.19 = select i1 %or.cond703, i32 %conv123.19, i32 %value.13.18
+ %and112.20 = and i64 %shl111.20, %b1.b2
+ %cmp115.20 = icmp eq i64 %and112.20, %shl111.20
+ %and119.20 = and i64 %shl.20, %b2.b1
+ %tobool.not.20 = icmp eq i64 %and119.20, 0
+ %or.cond704 = select i1 %cmp115.20, i1 %tobool.not.20, i1 false
+ %conv122.20 = sitofp i32 %value.13.19 to float
+ %102 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv122.20)
+ %conv123.20 = fptosi float %102 to i32
+ %value.13.20 = select i1 %or.cond704, i32 %conv123.20, i32 %value.13.19
+ %and140 = and i64 %5, %b1.b2
+ %cmp145 = icmp eq i64 %and140, %5
+ %conv149 = sitofp i32 %value.13.20 to float
+ %103 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149)
+ %conv150 = fptosi float %103 to i32
+ %value.16 = select i1 %cmp145, i32 %conv150, i32 %value.13.20
+ %and140.1 = and i64 %shl139.1, %b1.b2
+ %cmp145.1 = icmp eq i64 %and140.1, %shl139.1
+ %conv149.1 = sitofp i32 %value.16 to float
+ %104 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1)
+ %conv150.1 = fptosi float %104 to i32
+ %value.16.1 = select i1 %cmp145.1, i32 %conv150.1, i32 %value.16
+ %and140.2 = and i64 %shl139.2, %b1.b2
+ %cmp145.2 = icmp eq i64 %and140.2, %shl139.2
+ %conv149.2 = sitofp i32 %value.16.1 to float
+ %105 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2)
+ %conv150.2 = fptosi float %105 to i32
+ %value.16.2 = select i1 %cmp145.2, i32 %conv150.2, i32 %value.16.1
+ %and140.3 = and i64 %shl139.3, %b1.b2
+ %cmp145.3 = icmp eq i64 %and140.3, %shl139.3
+ %conv149.3 = sitofp i32 %value.16.2 to float
+ %106 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3)
+ %conv150.3 = fptosi float %106 to i32
+ %value.16.3 = select i1 %cmp145.3, i32 %conv150.3, i32 %value.16.2
+ %and140.4 = and i64 %shl139.4, %b1.b2
+ %cmp145.4 = icmp eq i64 %and140.4, %shl139.4
+ %conv149.4 = sitofp i32 %value.16.3 to float
+ %107 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4)
+ %conv150.4 = fptosi float %107 to i32
+ %value.16.4 = select i1 %cmp145.4, i32 %conv150.4, i32 %value.16.3
+ %and140.1563 = and i64 %shl139.1562, %b1.b2
+ %cmp145.1564 = icmp eq i64 %and140.1563, %shl139.1562
+ %conv149.1565 = sitofp i32 %value.16.4 to float
+ %108 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1565)
+ %conv150.1566 = fptosi float %108 to i32
+ %value.16.1567 = select i1 %cmp145.1564, i32 %conv150.1566, i32 %value.16.4
+ %and140.1.1 = and i64 %shl139.1.1, %b1.b2
+ %cmp145.1.1 = icmp eq i64 %and140.1.1, %shl139.1.1
+ %conv149.1.1 = sitofp i32 %value.16.1567 to float
+ %109 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1.1)
+ %conv150.1.1 = fptosi float %109 to i32
+ %value.16.1.1 = select i1 %cmp145.1.1, i32 %conv150.1.1, i32 %value.16.1567
+ %and140.2.1 = and i64 %shl139.2.1, %b1.b2
+ %cmp145.2.1 = icmp eq i64 %and140.2.1, %shl139.2.1
+ %conv149.2.1 = sitofp i32 %value.16.1.1 to float
+ %110 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2.1)
+ %conv150.2.1 = fptosi float %110 to i32
+ %value.16.2.1 = select i1 %cmp145.2.1, i32 %conv150.2.1, i32 %value.16.1.1
+ %and140.3.1 = and i64 %shl139.3.1, %b1.b2
+ %cmp145.3.1 = icmp eq i64 %and140.3.1, %shl139.3.1
+ %conv149.3.1 = sitofp i32 %value.16.2.1 to float
+ %111 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3.1)
+ %conv150.3.1 = fptosi float %111 to i32
+ %value.16.3.1 = select i1 %cmp145.3.1, i32 %conv150.3.1, i32 %value.16.2.1
+ %and140.4.1 = and i64 %shl139.4.1, %b1.b2
+ %cmp145.4.1 = icmp eq i64 %and140.4.1, %shl139.4.1
+ %conv149.4.1 = sitofp i32 %value.16.3.1 to float
+ %112 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4.1)
+ %conv150.4.1 = fptosi float %112 to i32
+ %value.16.4.1 = select i1 %cmp145.4.1, i32 %conv150.4.1, i32 %value.16.3.1
+ %and140.2569 = and i64 %shl139.2568, %b1.b2
+ %cmp145.2570 = icmp eq i64 %and140.2569, %shl139.2568
+ %conv149.2571 = sitofp i32 %value.16.4.1 to float
+ %113 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2571)
+ %conv150.2572 = fptosi float %113 to i32
+ %value.16.2573 = select i1 %cmp145.2570, i32 %conv150.2572, i32 %value.16.4.1
+ %and140.1.2 = and i64 %shl139.1.2, %b1.b2
+ %cmp145.1.2 = icmp eq i64 %and140.1.2, %shl139.1.2
+ %conv149.1.2 = sitofp i32 %value.16.2573 to float
+ %114 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1.2)
+ %conv150.1.2 = fptosi float %114 to i32
+ %value.16.1.2 = select i1 %cmp145.1.2, i32 %conv150.1.2, i32 %value.16.2573
+ %and140.2.2 = and i64 %shl139.2.2, %b1.b2
+ %cmp145.2.2 = icmp eq i64 %and140.2.2, %shl139.2.2
+ %conv149.2.2 = sitofp i32 %value.16.1.2 to float
+ %115 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2.2)
+ %conv150.2.2 = fptosi float %115 to i32
+ %value.16.2.2 = select i1 %cmp145.2.2, i32 %conv150.2.2, i32 %value.16.1.2
+ %and140.3.2 = and i64 %shl139.3.2, %b1.b2
+ %cmp145.3.2 = icmp eq i64 %and140.3.2, %shl139.3.2
+ %conv149.3.2 = sitofp i32 %value.16.2.2 to float
+ %116 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3.2)
+ %conv150.3.2 = fptosi float %116 to i32
+ %value.16.3.2 = select i1 %cmp145.3.2, i32 %conv150.3.2, i32 %value.16.2.2
+ %and140.4.2 = and i64 %shl139.4.2, %b1.b2
+ %cmp145.4.2 = icmp eq i64 %and140.4.2, %shl139.4.2
+ %conv149.4.2 = sitofp i32 %value.16.3.2 to float
+ %117 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4.2)
+ %conv150.4.2 = fptosi float %117 to i32
+ %value.16.4.2 = select i1 %cmp145.4.2, i32 %conv150.4.2, i32 %value.16.3.2
+ %and140.3575 = and i64 %shl139.3574, %b1.b2
+ %cmp145.3576 = icmp eq i64 %and140.3575, %shl139.3574
+ %conv149.3577 = sitofp i32 %value.16.4.2 to float
+ %118 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3577)
+ %conv150.3578 = fptosi float %118 to i32
+ %value.16.3579 = select i1 %cmp145.3576, i32 %conv150.3578, i32 %value.16.4.2
+ %and140.1.3 = and i64 %shl139.1.3, %b1.b2
+ %cmp145.1.3 = icmp eq i64 %and140.1.3, %shl139.1.3
+ %conv149.1.3 = sitofp i32 %value.16.3579 to float
+ %119 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1.3)
+ %conv150.1.3 = fptosi float %119 to i32
+ %value.16.1.3 = select i1 %cmp145.1.3, i32 %conv150.1.3, i32 %value.16.3579
+ %and140.2.3 = and i64 %shl139.2.3, %b1.b2
+ %cmp145.2.3 = icmp eq i64 %and140.2.3, %shl139.2.3
+ %conv149.2.3 = sitofp i32 %value.16.1.3 to float
+ %120 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2.3)
+ %conv150.2.3 = fptosi float %120 to i32
+ %value.16.2.3 = select i1 %cmp145.2.3, i32 %conv150.2.3, i32 %value.16.1.3
+ %and140.3.3 = and i64 %shl139.3.3, %b1.b2
+ %cmp145.3.3 = icmp eq i64 %and140.3.3, %shl139.3.3
+ %conv149.3.3 = sitofp i32 %value.16.2.3 to float
+ %121 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3.3)
+ %conv150.3.3 = fptosi float %121 to i32
+ %value.16.3.3 = select i1 %cmp145.3.3, i32 %conv150.3.3, i32 %value.16.2.3
+ %and140.4.3 = and i64 %shl139.4.3, %b1.b2
+ %cmp145.4.3 = icmp eq i64 %and140.4.3, %shl139.4.3
+ %conv149.4.3 = sitofp i32 %value.16.3.3 to float
+ %122 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4.3)
+ %conv150.4.3 = fptosi float %122 to i32
+ %value.16.4.3 = select i1 %cmp145.4.3, i32 %conv150.4.3, i32 %value.16.3.3
+ %and140.4581 = and i64 %shl139.4580, %b1.b2
+ %cmp145.4582 = icmp eq i64 %and140.4581, %shl139.4580
+ %conv149.4583 = sitofp i32 %value.16.4.3 to float
+ %123 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4583)
+ %conv150.4584 = fptosi float %123 to i32
+ %value.16.4585 = select i1 %cmp145.4582, i32 %conv150.4584, i32 %value.16.4.3
+ %and140.1.4 = and i64 %shl139.1.4, %b1.b2
+ %cmp145.1.4 = icmp eq i64 %and140.1.4, %shl139.1.4
+ %conv149.1.4 = sitofp i32 %value.16.4585 to float
+ %124 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1.4)
+ %conv150.1.4 = fptosi float %124 to i32
+ %value.16.1.4 = select i1 %cmp145.1.4, i32 %conv150.1.4, i32 %value.16.4585
+ %and140.2.4 = and i64 %shl139.2.4, %b1.b2
+ %cmp145.2.4 = icmp eq i64 %and140.2.4, %shl139.2.4
+ %conv149.2.4 = sitofp i32 %value.16.1.4 to float
+ %125 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2.4)
+ %conv150.2.4 = fptosi float %125 to i32
+ %value.16.2.4 = select i1 %cmp145.2.4, i32 %conv150.2.4, i32 %value.16.1.4
+ %and140.3.4 = and i64 %shl139.3.4, %b1.b2
+ %cmp145.3.4 = icmp eq i64 %and140.3.4, %shl139.3.4
+ %conv149.3.4 = sitofp i32 %value.16.2.4 to float
+ %126 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3.4)
+ %conv150.3.4 = fptosi float %126 to i32
+ %value.16.3.4 = select i1 %cmp145.3.4, i32 %conv150.3.4, i32 %value.16.2.4
+ %and140.4.4 = and i64 %shl139.4.4, %b1.b2
+ %cmp145.4.4 = icmp eq i64 %and140.4.4, %shl139.4.4
+ %conv149.4.4 = sitofp i32 %value.16.3.4 to float
+ %127 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4.4)
+ %conv150.4.4 = fptosi float %127 to i32
+ %value.16.4.4 = select i1 %cmp145.4.4, i32 %conv150.4.4, i32 %value.16.3.4
+ %and140.5 = and i64 %shl139.5, %b1.b2
+ %cmp145.5 = icmp eq i64 %and140.5, %shl139.5
+ %conv149.5 = sitofp i32 %value.16.4.4 to float
+ %128 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.5)
+ %conv150.5 = fptosi float %128 to i32
+ %value.16.5 = select i1 %cmp145.5, i32 %conv150.5, i32 %value.16.4.4
+ %and140.1.5 = and i64 %shl139.1.5, %b1.b2
+ %cmp145.1.5 = icmp eq i64 %and140.1.5, %shl139.1.5
+ %conv149.1.5 = sitofp i32 %value.16.5 to float
+ %129 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.1.5)
+ %conv150.1.5 = fptosi float %129 to i32
+ %value.16.1.5 = select i1 %cmp145.1.5, i32 %conv150.1.5, i32 %value.16.5
+ %and140.2.5 = and i64 %shl139.2.5, %b1.b2
+ %cmp145.2.5 = icmp eq i64 %and140.2.5, %shl139.2.5
+ %conv149.2.5 = sitofp i32 %value.16.1.5 to float
+ %130 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.2.5)
+ %conv150.2.5 = fptosi float %130 to i32
+ %value.16.2.5 = select i1 %cmp145.2.5, i32 %conv150.2.5, i32 %value.16.1.5
+ %and140.3.5 = and i64 %shl139.3.5, %b1.b2
+ %cmp145.3.5 = icmp eq i64 %and140.3.5, %shl139.3.5
+ %conv149.3.5 = sitofp i32 %value.16.2.5 to float
+ %131 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.3.5)
+ %conv150.3.5 = fptosi float %131 to i32
+ %value.16.3.5 = select i1 %cmp145.3.5, i32 %conv150.3.5, i32 %value.16.2.5
+ %and140.4.5 = and i64 %shl139.4.5, %b1.b2
+ %cmp145.4.5 = icmp eq i64 %and140.4.5, %shl139.4.5
+ %conv149.4.5 = sitofp i32 %value.16.3.5 to float
+ %132 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv149.4.5)
+ %conv150.4.5 = fptosi float %132 to i32
+ %value.16.4.5 = select i1 %cmp145.4.5, i32 %conv150.4.5, i32 %value.16.3.5
+ %and170 = and i64 %6, %b1.b2
+ %cmp175 = icmp eq i64 %and170, %6
+ %conv179 = sitofp i32 %value.16.4.5 to float
+ %133 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179)
+ %conv180 = fptosi float %133 to i32
+ %value.19 = select i1 %cmp175, i32 %conv180, i32 %value.16.4.5
+ %and170.1 = and i64 %shl169.1, %b1.b2
+ %cmp175.1 = icmp eq i64 %and170.1, %shl169.1
+ %conv179.1 = sitofp i32 %value.19 to float
+ %134 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.1)
+ %conv180.1 = fptosi float %134 to i32
+ %value.19.1 = select i1 %cmp175.1, i32 %conv180.1, i32 %value.19
+ %and170.2 = and i64 %shl169.2, %b1.b2
+ %cmp175.2 = icmp eq i64 %and170.2, %shl169.2
+ %conv179.2 = sitofp i32 %value.19.1 to float
+ %135 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.2)
+ %conv180.2 = fptosi float %135 to i32
+ %value.19.2 = select i1 %cmp175.2, i32 %conv180.2, i32 %value.19.1
+ %and170.3 = and i64 %shl169.3, %b1.b2
+ %cmp175.3 = icmp eq i64 %and170.3, %shl169.3
+ %conv179.3 = sitofp i32 %value.19.2 to float
+ %136 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.3)
+ %conv180.3 = fptosi float %136 to i32
+ %value.19.3 = select i1 %cmp175.3, i32 %conv180.3, i32 %value.19.2
+ %and170.1591 = and i64 %shl169.1590, %b1.b2
+ %cmp175.1592 = icmp eq i64 %and170.1591, %shl169.1590
+ %conv179.1593 = sitofp i32 %value.19.3 to float
+ %137 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.1593)
+ %conv180.1594 = fptosi float %137 to i32
+ %value.19.1595 = select i1 %cmp175.1592, i32 %conv180.1594, i32 %value.19.3
+ %and170.1.1 = and i64 %shl169.1.1, %b1.b2
+ %cmp175.1.1 = icmp eq i64 %and170.1.1, %shl169.1.1
+ %conv179.1.1 = sitofp i32 %value.19.1595 to float
+ %138 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.1.1)
+ %conv180.1.1 = fptosi float %138 to i32
+ %value.19.1.1 = select i1 %cmp175.1.1, i32 %conv180.1.1, i32 %value.19.1595
+ %and170.2.1 = and i64 %shl169.2.1, %b1.b2
+ %cmp175.2.1 = icmp eq i64 %and170.2.1, %shl169.2.1
+ %conv179.2.1 = sitofp i32 %value.19.1.1 to float
+ %139 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.2.1)
+ %conv180.2.1 = fptosi float %139 to i32
+ %value.19.2.1 = select i1 %cmp175.2.1, i32 %conv180.2.1, i32 %value.19.1.1
+ %and170.3.1 = and i64 %shl169.3.1, %b1.b2
+ %cmp175.3.1 = icmp eq i64 %and170.3.1, %shl169.3.1
+ %conv179.3.1 = sitofp i32 %value.19.2.1 to float
+ %140 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.3.1)
+ %conv180.3.1 = fptosi float %140 to i32
+ %value.19.3.1 = select i1 %cmp175.3.1, i32 %conv180.3.1, i32 %value.19.2.1
+ %and170.2597 = and i64 %shl169.2596, %b1.b2
+ %cmp175.2598 = icmp eq i64 %and170.2597, %shl169.2596
+ %conv179.2599 = sitofp i32 %value.19.3.1 to float
+ %141 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.2599)
+ %conv180.2600 = fptosi float %141 to i32
+ %value.19.2601 = select i1 %cmp175.2598, i32 %conv180.2600, i32 %value.19.3.1
+ %and170.1.2 = and i64 %shl169.1.2, %b1.b2
+ %cmp175.1.2 = icmp eq i64 %and170.1.2, %shl169.1.2
+ %conv179.1.2 = sitofp i32 %value.19.2601 to float
+ %142 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.1.2)
+ %conv180.1.2 = fptosi float %142 to i32
+ %value.19.1.2 = select i1 %cmp175.1.2, i32 %conv180.1.2, i32 %value.19.2601
+ %and170.2.2 = and i64 %shl169.2.2, %b1.b2
+ %cmp175.2.2 = icmp eq i64 %and170.2.2, %shl169.2.2
+ %conv179.2.2 = sitofp i32 %value.19.1.2 to float
+ %143 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.2.2)
+ %conv180.2.2 = fptosi float %143 to i32
+ %value.19.2.2 = select i1 %cmp175.2.2, i32 %conv180.2.2, i32 %value.19.1.2
+ %and170.3.2 = and i64 %shl169.3.2, %b1.b2
+ %cmp175.3.2 = icmp eq i64 %and170.3.2, %shl169.3.2
+ %conv179.3.2 = sitofp i32 %value.19.2.2 to float
+ %144 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv179.3.2)
+ %conv180.3.2 = fptosi float %144 to i32
+ %value.19.3.2 = select i1 %cmp175.3.2, i32 %conv180.3.2, i32 %value.19.2.2
+ %and200 = and i64 %7, %b1.b2
+ %cmp205 = icmp eq i64 %and200, %7
+ %conv209 = sitofp i32 %value.19.3.2 to float
+ %145 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209)
+ %conv210 = fptosi float %145 to i32
+ %value.22 = select i1 %cmp205, i32 %conv210, i32 %value.19.3.2
+ %and200.1 = and i64 %shl199.1, %b1.b2
+ %cmp205.1 = icmp eq i64 %and200.1, %shl199.1
+ %conv209.1 = sitofp i32 %value.22 to float
+ %146 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.1)
+ %conv210.1 = fptosi float %146 to i32
+ %value.22.1 = select i1 %cmp205.1, i32 %conv210.1, i32 %value.22
+ %and200.2 = and i64 %shl199.2, %b1.b2
+ %cmp205.2 = icmp eq i64 %and200.2, %shl199.2
+ %conv209.2 = sitofp i32 %value.22.1 to float
+ %147 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.2)
+ %conv210.2 = fptosi float %147 to i32
+ %value.22.2 = select i1 %cmp205.2, i32 %conv210.2, i32 %value.22.1
+ %and200.3 = and i64 %shl199.3, %b1.b2
+ %cmp205.3 = icmp eq i64 %and200.3, %shl199.3
+ %conv209.3 = sitofp i32 %value.22.2 to float
+ %148 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.3)
+ %conv210.3 = fptosi float %148 to i32
+ %value.22.3 = select i1 %cmp205.3, i32 %conv210.3, i32 %value.22.2
+ %and200.1607 = and i64 %shl199.1606, %b1.b2
+ %cmp205.1608 = icmp eq i64 %and200.1607, %shl199.1606
+ %conv209.1609 = sitofp i32 %value.22.3 to float
+ %149 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.1609)
+ %conv210.1610 = fptosi float %149 to i32
+ %value.22.1611 = select i1 %cmp205.1608, i32 %conv210.1610, i32 %value.22.3
+ %and200.1.1 = and i64 %shl199.1.1, %b1.b2
+ %cmp205.1.1 = icmp eq i64 %and200.1.1, %shl199.1.1
+ %conv209.1.1 = sitofp i32 %value.22.1611 to float
+ %150 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.1.1)
+ %conv210.1.1 = fptosi float %150 to i32
+ %value.22.1.1 = select i1 %cmp205.1.1, i32 %conv210.1.1, i32 %value.22.1611
+ %and200.2.1 = and i64 %shl199.2.1, %b1.b2
+ %cmp205.2.1 = icmp eq i64 %and200.2.1, %shl199.2.1
+ %conv209.2.1 = sitofp i32 %value.22.1.1 to float
+ %151 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.2.1)
+ %conv210.2.1 = fptosi float %151 to i32
+ %value.22.2.1 = select i1 %cmp205.2.1, i32 %conv210.2.1, i32 %value.22.1.1
+ %and200.3.1 = and i64 %shl199.3.1, %b1.b2
+ %cmp205.3.1 = icmp eq i64 %and200.3.1, %shl199.3.1
+ %conv209.3.1 = sitofp i32 %value.22.2.1 to float
+ %152 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.3.1)
+ %conv210.3.1 = fptosi float %152 to i32
+ %value.22.3.1 = select i1 %cmp205.3.1, i32 %conv210.3.1, i32 %value.22.2.1
+ %and200.2613 = and i64 %shl199.2612, %b1.b2
+ %cmp205.2614 = icmp eq i64 %and200.2613, %shl199.2612
+ %conv209.2615 = sitofp i32 %value.22.3.1 to float
+ %153 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.2615)
+ %conv210.2616 = fptosi float %153 to i32
+ %value.22.2617 = select i1 %cmp205.2614, i32 %conv210.2616, i32 %value.22.3.1
+ %and200.1.2 = and i64 %shl199.1.2, %b1.b2
+ %cmp205.1.2 = icmp eq i64 %and200.1.2, %shl199.1.2
+ %conv209.1.2 = sitofp i32 %value.22.2617 to float
+ %154 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.1.2)
+ %conv210.1.2 = fptosi float %154 to i32
+ %value.22.1.2 = select i1 %cmp205.1.2, i32 %conv210.1.2, i32 %value.22.2617
+ %and200.2.2 = and i64 %shl199.2.2, %b1.b2
+ %cmp205.2.2 = icmp eq i64 %and200.2.2, %shl199.2.2
+ %conv209.2.2 = sitofp i32 %value.22.1.2 to float
+ %155 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.2.2)
+ %conv210.2.2 = fptosi float %155 to i32
+ %value.22.2.2 = select i1 %cmp205.2.2, i32 %conv210.2.2, i32 %value.22.1.2
+ %and200.3.2 = and i64 %shl199.3.2, %b1.b2
+ %cmp205.3.2 = icmp eq i64 %and200.3.2, %shl199.3.2
+ %conv209.3.2 = sitofp i32 %value.22.2.2 to float
+ %156 = tail call float @llvm.fmuladd.f32(float %add.add4, float 2.000000e+01, float %conv209.3.2)
+ %conv210.3.2 = fptosi float %156 to i32
+ %value.22.3.2 = select i1 %cmp205.3.2, i32 %conv210.3.2, i32 %value.22.2.2
+ %and224 = and i64 %8, %b1.b2
+ %cmp227 = icmp eq i64 %and224, %8
+ %and232 = and i64 %0, %b2.b1
+ %tobool233.not = icmp eq i64 %and232, 0
+ %or.cond705 = select i1 %cmp227, i1 %tobool233.not, i1 false
+ %conv236 = sitofp i32 %value.22.3.2 to float
+ %157 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236)
+ %conv237 = fptosi float %157 to i32
+ %value.24 = select i1 %or.cond705, i32 %conv237, i32 %value.22.3.2
+ %and224.1 = and i64 %shl223.1, %b1.b2
+ %cmp227.1 = icmp eq i64 %and224.1, %shl223.1
+ %and232.1 = and i64 %shl.1, %b2.b1
+ %tobool233.not.1 = icmp eq i64 %and232.1, 0
+ %or.cond706 = select i1 %cmp227.1, i1 %tobool233.not.1, i1 false
+ %conv236.1 = sitofp i32 %value.24 to float
+ %158 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.1)
+ %conv237.1 = fptosi float %158 to i32
+ %value.24.1 = select i1 %or.cond706, i32 %conv237.1, i32 %value.24
+ %and224.2 = and i64 %shl223.2, %b1.b2
+ %cmp227.2 = icmp eq i64 %and224.2, %shl223.2
+ %and232.2 = and i64 %shl.2, %b2.b1
+ %tobool233.not.2 = icmp eq i64 %and232.2, 0
+ %or.cond707 = select i1 %cmp227.2, i1 %tobool233.not.2, i1 false
+ %conv236.2 = sitofp i32 %value.24.1 to float
+ %159 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.2)
+ %conv237.2 = fptosi float %159 to i32
+ %value.24.2 = select i1 %or.cond707, i32 %conv237.2, i32 %value.24.1
+ %and224.3 = and i64 %shl223.3, %b1.b2
+ %cmp227.3 = icmp eq i64 %and224.3, %shl223.3
+ %and232.3 = and i64 %shl.3, %b2.b1
+ %tobool233.not.3 = icmp eq i64 %and232.3, 0
+ %or.cond708 = select i1 %cmp227.3, i1 %tobool233.not.3, i1 false
+ %conv236.3 = sitofp i32 %value.24.2 to float
+ %160 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.3)
+ %conv237.3 = fptosi float %160 to i32
+ %value.24.3 = select i1 %or.cond708, i32 %conv237.3, i32 %value.24.2
+ %and224.4 = and i64 %shl223.4, %b1.b2
+ %cmp227.4 = icmp eq i64 %and224.4, %shl223.4
+ %and232.4 = and i64 %shl.4, %b2.b1
+ %tobool233.not.4 = icmp eq i64 %and232.4, 0
+ %or.cond709 = select i1 %cmp227.4, i1 %tobool233.not.4, i1 false
+ %conv236.4 = sitofp i32 %value.24.3 to float
+ %161 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.4)
+ %conv237.4 = fptosi float %161 to i32
+ %value.24.4 = select i1 %or.cond709, i32 %conv237.4, i32 %value.24.3
+ %and224.5 = and i64 %shl223.5, %b1.b2
+ %cmp227.5 = icmp eq i64 %and224.5, %shl223.5
+ %and232.5 = and i64 %shl.5, %b2.b1
+ %tobool233.not.5 = icmp eq i64 %and232.5, 0
+ %or.cond710 = select i1 %cmp227.5, i1 %tobool233.not.5, i1 false
+ %conv236.5 = sitofp i32 %value.24.4 to float
+ %162 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.5)
+ %conv237.5 = fptosi float %162 to i32
+ %value.24.5 = select i1 %or.cond710, i32 %conv237.5, i32 %value.24.4
+ %and224.6 = and i64 %shl223.6, %b1.b2
+ %cmp227.6 = icmp eq i64 %and224.6, %shl223.6
+ %and232.6 = and i64 %shl.6, %b2.b1
+ %tobool233.not.6 = icmp eq i64 %and232.6, 0
+ %or.cond711 = select i1 %cmp227.6, i1 %tobool233.not.6, i1 false
+ %conv236.6 = sitofp i32 %value.24.5 to float
+ %163 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.6)
+ %conv237.6 = fptosi float %163 to i32
+ %value.24.6 = select i1 %or.cond711, i32 %conv237.6, i32 %value.24.5
+ %and224.7 = and i64 %shl223.7, %b1.b2
+ %cmp227.7 = icmp eq i64 %and224.7, %shl223.7
+ %and232.7 = and i64 %shl.7, %b2.b1
+ %tobool233.not.7 = icmp eq i64 %and232.7, 0
+ %or.cond712 = select i1 %cmp227.7, i1 %tobool233.not.7, i1 false
+ %conv236.7 = sitofp i32 %value.24.6 to float
+ %164 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.7)
+ %conv237.7 = fptosi float %164 to i32
+ %value.24.7 = select i1 %or.cond712, i32 %conv237.7, i32 %value.24.6
+ %and224.8 = and i64 %shl223.8, %b1.b2
+ %cmp227.8 = icmp eq i64 %and224.8, %shl223.8
+ %and232.8 = and i64 %shl.8, %b2.b1
+ %tobool233.not.8 = icmp eq i64 %and232.8, 0
+ %or.cond713 = select i1 %cmp227.8, i1 %tobool233.not.8, i1 false
+ %conv236.8 = sitofp i32 %value.24.7 to float
+ %165 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.8)
+ %conv237.8 = fptosi float %165 to i32
+ %value.24.8 = select i1 %or.cond713, i32 %conv237.8, i32 %value.24.7
+ %and224.9 = and i64 %shl223.9, %b1.b2
+ %cmp227.9 = icmp eq i64 %and224.9, %shl223.9
+ %and232.9 = and i64 %shl.9, %b2.b1
+ %tobool233.not.9 = icmp eq i64 %and232.9, 0
+ %or.cond714 = select i1 %cmp227.9, i1 %tobool233.not.9, i1 false
+ %conv236.9 = sitofp i32 %value.24.8 to float
+ %166 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.9)
+ %conv237.9 = fptosi float %166 to i32
+ %value.24.9 = select i1 %or.cond714, i32 %conv237.9, i32 %value.24.8
+ %and224.10 = and i64 %shl223.10, %b1.b2
+ %cmp227.10 = icmp eq i64 %and224.10, %shl223.10
+ %and232.10 = and i64 %shl.10, %b2.b1
+ %tobool233.not.10 = icmp eq i64 %and232.10, 0
+ %or.cond715 = select i1 %cmp227.10, i1 %tobool233.not.10, i1 false
+ %conv236.10 = sitofp i32 %value.24.9 to float
+ %167 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.10)
+ %conv237.10 = fptosi float %167 to i32
+ %value.24.10 = select i1 %or.cond715, i32 %conv237.10, i32 %value.24.9
+ %and224.11 = and i64 %shl223.11, %b1.b2
+ %cmp227.11 = icmp eq i64 %and224.11, %shl223.11
+ %and232.11 = and i64 %shl.11, %b2.b1
+ %tobool233.not.11 = icmp eq i64 %and232.11, 0
+ %or.cond716 = select i1 %cmp227.11, i1 %tobool233.not.11, i1 false
+ %conv236.11 = sitofp i32 %value.24.10 to float
+ %168 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.11)
+ %conv237.11 = fptosi float %168 to i32
+ %value.24.11 = select i1 %or.cond716, i32 %conv237.11, i32 %value.24.10
+ %and224.12 = and i64 %shl223.12, %b1.b2
+ %cmp227.12 = icmp eq i64 %and224.12, %shl223.12
+ %and232.12 = and i64 %shl.12, %b2.b1
+ %tobool233.not.12 = icmp eq i64 %and232.12, 0
+ %or.cond717 = select i1 %cmp227.12, i1 %tobool233.not.12, i1 false
+ %conv236.12 = sitofp i32 %value.24.11 to float
+ %169 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.12)
+ %conv237.12 = fptosi float %169 to i32
+ %value.24.12 = select i1 %or.cond717, i32 %conv237.12, i32 %value.24.11
+ %and224.13 = and i64 %shl223.13, %b1.b2
+ %cmp227.13 = icmp eq i64 %and224.13, %shl223.13
+ %and232.13 = and i64 %shl.13, %b2.b1
+ %tobool233.not.13 = icmp eq i64 %and232.13, 0
+ %or.cond718 = select i1 %cmp227.13, i1 %tobool233.not.13, i1 false
+ %conv236.13 = sitofp i32 %value.24.12 to float
+ %170 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.13)
+ %conv237.13 = fptosi float %170 to i32
+ %value.24.13 = select i1 %or.cond718, i32 %conv237.13, i32 %value.24.12
+ %and224.14 = and i64 %shl223.14, %b1.b2
+ %cmp227.14 = icmp eq i64 %and224.14, %shl223.14
+ %and232.14 = and i64 %shl.14, %b2.b1
+ %tobool233.not.14 = icmp eq i64 %and232.14, 0
+ %or.cond719 = select i1 %cmp227.14, i1 %tobool233.not.14, i1 false
+ %conv236.14 = sitofp i32 %value.24.13 to float
+ %171 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.14)
+ %conv237.14 = fptosi float %171 to i32
+ %value.24.14 = select i1 %or.cond719, i32 %conv237.14, i32 %value.24.13
+ %and224.15 = and i64 %shl223.15, %b1.b2
+ %cmp227.15 = icmp eq i64 %and224.15, %shl223.15
+ %and232.15 = and i64 %shl.15, %b2.b1
+ %tobool233.not.15 = icmp eq i64 %and232.15, 0
+ %or.cond720 = select i1 %cmp227.15, i1 %tobool233.not.15, i1 false
+ %conv236.15 = sitofp i32 %value.24.14 to float
+ %172 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.15)
+ %conv237.15 = fptosi float %172 to i32
+ %value.24.15 = select i1 %or.cond720, i32 %conv237.15, i32 %value.24.14
+ %and224.16 = and i64 %shl223.16, %b1.b2
+ %cmp227.16 = icmp eq i64 %and224.16, %shl223.16
+ %and232.16 = and i64 %shl.16, %b2.b1
+ %tobool233.not.16 = icmp eq i64 %and232.16, 0
+ %or.cond721 = select i1 %cmp227.16, i1 %tobool233.not.16, i1 false
+ %conv236.16 = sitofp i32 %value.24.15 to float
+ %173 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.16)
+ %conv237.16 = fptosi float %173 to i32
+ %value.24.16 = select i1 %or.cond721, i32 %conv237.16, i32 %value.24.15
+ %and224.17 = and i64 %shl223.17, %b1.b2
+ %cmp227.17 = icmp eq i64 %and224.17, %shl223.17
+ %and232.17 = and i64 %shl.17, %b2.b1
+ %tobool233.not.17 = icmp eq i64 %and232.17, 0
+ %or.cond722 = select i1 %cmp227.17, i1 %tobool233.not.17, i1 false
+ %conv236.17 = sitofp i32 %value.24.16 to float
+ %174 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.17)
+ %conv237.17 = fptosi float %174 to i32
+ %value.24.17 = select i1 %or.cond722, i32 %conv237.17, i32 %value.24.16
+ %and224.18 = and i64 %shl223.18, %b1.b2
+ %cmp227.18 = icmp eq i64 %and224.18, %shl223.18
+ %and232.18 = and i64 %shl.18, %b2.b1
+ %tobool233.not.18 = icmp eq i64 %and232.18, 0
+ %or.cond723 = select i1 %cmp227.18, i1 %tobool233.not.18, i1 false
+ %conv236.18 = sitofp i32 %value.24.17 to float
+ %175 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.18)
+ %conv237.18 = fptosi float %175 to i32
+ %value.24.18 = select i1 %or.cond723, i32 %conv237.18, i32 %value.24.17
+ %and224.19 = and i64 %shl223.19, %b1.b2
+ %cmp227.19 = icmp eq i64 %and224.19, %shl223.19
+ %and232.19 = and i64 %shl.19, %b2.b1
+ %tobool233.not.19 = icmp eq i64 %and232.19, 0
+ %or.cond724 = select i1 %cmp227.19, i1 %tobool233.not.19, i1 false
+ %conv236.19 = sitofp i32 %value.24.18 to float
+ %176 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.19)
+ %conv237.19 = fptosi float %176 to i32
+ %value.24.19 = select i1 %or.cond724, i32 %conv237.19, i32 %value.24.18
+ %and224.20 = and i64 %shl223.20, %b1.b2
+ %cmp227.20 = icmp eq i64 %and224.20, %shl223.20
+ %and232.20 = and i64 %shl.20, %b2.b1
+ %tobool233.not.20 = icmp eq i64 %and232.20, 0
+ %or.cond725 = select i1 %cmp227.20, i1 %tobool233.not.20, i1 false
+ %conv236.20 = sitofp i32 %value.24.19 to float
+ %177 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv236.20)
+ %conv237.20 = fptosi float %177 to i32
+ %value.24.20 = select i1 %or.cond725, i32 %conv237.20, i32 %value.24.19
+ %and254 = and i64 %9, %b1.b2
+ %cmp259 = icmp eq i64 %and254, %9
+ %conv263 = sitofp i32 %value.24.20 to float
+ %178 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263)
+ %conv264 = fptosi float %178 to i32
+ %value.27 = select i1 %cmp259, i32 %conv264, i32 %value.24.20
+ %and254.1 = and i64 %shl253.1, %b1.b2
+ %cmp259.1 = icmp eq i64 %and254.1, %shl253.1
+ %conv263.1 = sitofp i32 %value.27 to float
+ %179 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1)
+ %conv264.1 = fptosi float %179 to i32
+ %value.27.1 = select i1 %cmp259.1, i32 %conv264.1, i32 %value.27
+ %and254.2 = and i64 %shl253.2, %b1.b2
+ %cmp259.2 = icmp eq i64 %and254.2, %shl253.2
+ %conv263.2 = sitofp i32 %value.27.1 to float
+ %180 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2)
+ %conv264.2 = fptosi float %180 to i32
+ %value.27.2 = select i1 %cmp259.2, i32 %conv264.2, i32 %value.27.1
+ %and254.3 = and i64 %shl253.3, %b1.b2
+ %cmp259.3 = icmp eq i64 %and254.3, %shl253.3
+ %conv263.3 = sitofp i32 %value.27.2 to float
+ %181 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3)
+ %conv264.3 = fptosi float %181 to i32
+ %value.27.3 = select i1 %cmp259.3, i32 %conv264.3, i32 %value.27.2
+ %and254.4 = and i64 %shl253.4, %b1.b2
+ %cmp259.4 = icmp eq i64 %and254.4, %shl253.4
+ %conv263.4 = sitofp i32 %value.27.3 to float
+ %182 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4)
+ %conv264.4 = fptosi float %182 to i32
+ %value.27.4 = select i1 %cmp259.4, i32 %conv264.4, i32 %value.27.3
+ %and254.5 = and i64 %shl253.5, %b1.b2
+ %cmp259.5 = icmp eq i64 %and254.5, %shl253.5
+ %conv263.5 = sitofp i32 %value.27.4 to float
+ %183 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5)
+ %conv264.5 = fptosi float %183 to i32
+ %value.27.5 = select i1 %cmp259.5, i32 %conv264.5, i32 %value.27.4
+ %and254.1624 = and i64 %shl253.1623, %b1.b2
+ %cmp259.1625 = icmp eq i64 %and254.1624, %shl253.1623
+ %conv263.1626 = sitofp i32 %value.27.5 to float
+ %184 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1626)
+ %conv264.1627 = fptosi float %184 to i32
+ %value.27.1628 = select i1 %cmp259.1625, i32 %conv264.1627, i32 %value.27.5
+ %and254.1.1 = and i64 %shl253.1.1, %b1.b2
+ %cmp259.1.1 = icmp eq i64 %and254.1.1, %shl253.1.1
+ %conv263.1.1 = sitofp i32 %value.27.1628 to float
+ %185 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1.1)
+ %conv264.1.1 = fptosi float %185 to i32
+ %value.27.1.1 = select i1 %cmp259.1.1, i32 %conv264.1.1, i32 %value.27.1628
+ %and254.2.1 = and i64 %shl253.2.1, %b1.b2
+ %cmp259.2.1 = icmp eq i64 %and254.2.1, %shl253.2.1
+ %conv263.2.1 = sitofp i32 %value.27.1.1 to float
+ %186 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2.1)
+ %conv264.2.1 = fptosi float %186 to i32
+ %value.27.2.1 = select i1 %cmp259.2.1, i32 %conv264.2.1, i32 %value.27.1.1
+ %and254.3.1 = and i64 %shl253.3.1, %b1.b2
+ %cmp259.3.1 = icmp eq i64 %and254.3.1, %shl253.3.1
+ %conv263.3.1 = sitofp i32 %value.27.2.1 to float
+ %187 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3.1)
+ %conv264.3.1 = fptosi float %187 to i32
+ %value.27.3.1 = select i1 %cmp259.3.1, i32 %conv264.3.1, i32 %value.27.2.1
+ %and254.4.1 = and i64 %shl253.4.1, %b1.b2
+ %cmp259.4.1 = icmp eq i64 %and254.4.1, %shl253.4.1
+ %conv263.4.1 = sitofp i32 %value.27.3.1 to float
+ %188 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4.1)
+ %conv264.4.1 = fptosi float %188 to i32
+ %value.27.4.1 = select i1 %cmp259.4.1, i32 %conv264.4.1, i32 %value.27.3.1
+ %and254.5.1 = and i64 %shl253.5.1, %b1.b2
+ %cmp259.5.1 = icmp eq i64 %and254.5.1, %shl253.5.1
+ %conv263.5.1 = sitofp i32 %value.27.4.1 to float
+ %189 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5.1)
+ %conv264.5.1 = fptosi float %189 to i32
+ %value.27.5.1 = select i1 %cmp259.5.1, i32 %conv264.5.1, i32 %value.27.4.1
+ %and254.2630 = and i64 %shl253.2629, %b1.b2
+ %cmp259.2631 = icmp eq i64 %and254.2630, %shl253.2629
+ %conv263.2632 = sitofp i32 %value.27.5.1 to float
+ %190 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2632)
+ %conv264.2633 = fptosi float %190 to i32
+ %value.27.2634 = select i1 %cmp259.2631, i32 %conv264.2633, i32 %value.27.5.1
+ %and254.1.2 = and i64 %shl253.1.2, %b1.b2
+ %cmp259.1.2 = icmp eq i64 %and254.1.2, %shl253.1.2
+ %conv263.1.2 = sitofp i32 %value.27.2634 to float
+ %191 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1.2)
+ %conv264.1.2 = fptosi float %191 to i32
+ %value.27.1.2 = select i1 %cmp259.1.2, i32 %conv264.1.2, i32 %value.27.2634
+ %and254.2.2 = and i64 %shl253.2.2, %b1.b2
+ %cmp259.2.2 = icmp eq i64 %and254.2.2, %shl253.2.2
+ %conv263.2.2 = sitofp i32 %value.27.1.2 to float
+ %192 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2.2)
+ %conv264.2.2 = fptosi float %192 to i32
+ %value.27.2.2 = select i1 %cmp259.2.2, i32 %conv264.2.2, i32 %value.27.1.2
+ %and254.3.2 = and i64 %shl253.3.2, %b1.b2
+ %cmp259.3.2 = icmp eq i64 %and254.3.2, %shl253.3.2
+ %conv263.3.2 = sitofp i32 %value.27.2.2 to float
+ %193 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3.2)
+ %conv264.3.2 = fptosi float %193 to i32
+ %value.27.3.2 = select i1 %cmp259.3.2, i32 %conv264.3.2, i32 %value.27.2.2
+ %and254.4.2 = and i64 %shl253.4.2, %b1.b2
+ %cmp259.4.2 = icmp eq i64 %and254.4.2, %shl253.4.2
+ %conv263.4.2 = sitofp i32 %value.27.3.2 to float
+ %194 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4.2)
+ %conv264.4.2 = fptosi float %194 to i32
+ %value.27.4.2 = select i1 %cmp259.4.2, i32 %conv264.4.2, i32 %value.27.3.2
+ %and254.5.2 = and i64 %shl253.5.2, %b1.b2
+ %cmp259.5.2 = icmp eq i64 %and254.5.2, %shl253.5.2
+ %conv263.5.2 = sitofp i32 %value.27.4.2 to float
+ %195 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5.2)
+ %conv264.5.2 = fptosi float %195 to i32
+ %value.27.5.2 = select i1 %cmp259.5.2, i32 %conv264.5.2, i32 %value.27.4.2
+ %and254.3636 = and i64 %shl253.3635, %b1.b2
+ %cmp259.3637 = icmp eq i64 %and254.3636, %shl253.3635
+ %conv263.3638 = sitofp i32 %value.27.5.2 to float
+ %196 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3638)
+ %conv264.3639 = fptosi float %196 to i32
+ %value.27.3640 = select i1 %cmp259.3637, i32 %conv264.3639, i32 %value.27.5.2
+ %and254.1.3 = and i64 %shl253.1.3, %b1.b2
+ %cmp259.1.3 = icmp eq i64 %and254.1.3, %shl253.1.3
+ %conv263.1.3 = sitofp i32 %value.27.3640 to float
+ %197 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1.3)
+ %conv264.1.3 = fptosi float %197 to i32
+ %value.27.1.3 = select i1 %cmp259.1.3, i32 %conv264.1.3, i32 %value.27.3640
+ %and254.2.3 = and i64 %shl253.2.3, %b1.b2
+ %cmp259.2.3 = icmp eq i64 %and254.2.3, %shl253.2.3
+ %conv263.2.3 = sitofp i32 %value.27.1.3 to float
+ %198 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2.3)
+ %conv264.2.3 = fptosi float %198 to i32
+ %value.27.2.3 = select i1 %cmp259.2.3, i32 %conv264.2.3, i32 %value.27.1.3
+ %and254.3.3 = and i64 %shl253.3.3, %b1.b2
+ %cmp259.3.3 = icmp eq i64 %and254.3.3, %shl253.3.3
+ %conv263.3.3 = sitofp i32 %value.27.2.3 to float
+ %199 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3.3)
+ %conv264.3.3 = fptosi float %199 to i32
+ %value.27.3.3 = select i1 %cmp259.3.3, i32 %conv264.3.3, i32 %value.27.2.3
+ %and254.4.3 = and i64 %shl253.4.3, %b1.b2
+ %cmp259.4.3 = icmp eq i64 %and254.4.3, %shl253.4.3
+ %conv263.4.3 = sitofp i32 %value.27.3.3 to float
+ %200 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4.3)
+ %conv264.4.3 = fptosi float %200 to i32
+ %value.27.4.3 = select i1 %cmp259.4.3, i32 %conv264.4.3, i32 %value.27.3.3
+ %and254.5.3 = and i64 %shl253.5.3, %b1.b2
+ %cmp259.5.3 = icmp eq i64 %and254.5.3, %shl253.5.3
+ %conv263.5.3 = sitofp i32 %value.27.4.3 to float
+ %201 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5.3)
+ %conv264.5.3 = fptosi float %201 to i32
+ %value.27.5.3 = select i1 %cmp259.5.3, i32 %conv264.5.3, i32 %value.27.4.3
+ %and254.4642 = and i64 %shl253.4641, %b1.b2
+ %cmp259.4643 = icmp eq i64 %and254.4642, %shl253.4641
+ %conv263.4644 = sitofp i32 %value.27.5.3 to float
+ %202 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4644)
+ %conv264.4645 = fptosi float %202 to i32
+ %value.27.4646 = select i1 %cmp259.4643, i32 %conv264.4645, i32 %value.27.5.3
+ %and254.1.4 = and i64 %shl253.1.4, %b1.b2
+ %cmp259.1.4 = icmp eq i64 %and254.1.4, %shl253.1.4
+ %conv263.1.4 = sitofp i32 %value.27.4646 to float
+ %203 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1.4)
+ %conv264.1.4 = fptosi float %203 to i32
+ %value.27.1.4 = select i1 %cmp259.1.4, i32 %conv264.1.4, i32 %value.27.4646
+ %and254.2.4 = and i64 %shl253.2.4, %b1.b2
+ %cmp259.2.4 = icmp eq i64 %and254.2.4, %shl253.2.4
+ %conv263.2.4 = sitofp i32 %value.27.1.4 to float
+ %204 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2.4)
+ %conv264.2.4 = fptosi float %204 to i32
+ %value.27.2.4 = select i1 %cmp259.2.4, i32 %conv264.2.4, i32 %value.27.1.4
+ %and254.3.4 = and i64 %shl253.3.4, %b1.b2
+ %cmp259.3.4 = icmp eq i64 %and254.3.4, %shl253.3.4
+ %conv263.3.4 = sitofp i32 %value.27.2.4 to float
+ %205 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3.4)
+ %conv264.3.4 = fptosi float %205 to i32
+ %value.27.3.4 = select i1 %cmp259.3.4, i32 %conv264.3.4, i32 %value.27.2.4
+ %and254.4.4 = and i64 %shl253.4.4, %b1.b2
+ %cmp259.4.4 = icmp eq i64 %and254.4.4, %shl253.4.4
+ %conv263.4.4 = sitofp i32 %value.27.3.4 to float
+ %206 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4.4)
+ %conv264.4.4 = fptosi float %206 to i32
+ %value.27.4.4 = select i1 %cmp259.4.4, i32 %conv264.4.4, i32 %value.27.3.4
+ %and254.5.4 = and i64 %shl253.5.4, %b1.b2
+ %cmp259.5.4 = icmp eq i64 %and254.5.4, %shl253.5.4
+ %conv263.5.4 = sitofp i32 %value.27.4.4 to float
+ %207 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5.4)
+ %conv264.5.4 = fptosi float %207 to i32
+ %value.27.5.4 = select i1 %cmp259.5.4, i32 %conv264.5.4, i32 %value.27.4.4
+ %and254.5648 = and i64 %shl253.5647, %b1.b2
+ %cmp259.5649 = icmp eq i64 %and254.5648, %shl253.5647
+ %conv263.5650 = sitofp i32 %value.27.5.4 to float
+ %208 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5650)
+ %conv264.5651 = fptosi float %208 to i32
+ %value.27.5652 = select i1 %cmp259.5649, i32 %conv264.5651, i32 %value.27.5.4
+ %and254.1.5 = and i64 %shl253.1.5, %b1.b2
+ %cmp259.1.5 = icmp eq i64 %and254.1.5, %shl253.1.5
+ %conv263.1.5 = sitofp i32 %value.27.5652 to float
+ %209 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.1.5)
+ %conv264.1.5 = fptosi float %209 to i32
+ %value.27.1.5 = select i1 %cmp259.1.5, i32 %conv264.1.5, i32 %value.27.5652
+ %and254.2.5 = and i64 %shl253.2.5, %b1.b2
+ %cmp259.2.5 = icmp eq i64 %and254.2.5, %shl253.2.5
+ %conv263.2.5 = sitofp i32 %value.27.1.5 to float
+ %210 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.2.5)
+ %conv264.2.5 = fptosi float %210 to i32
+ %value.27.2.5 = select i1 %cmp259.2.5, i32 %conv264.2.5, i32 %value.27.1.5
+ %and254.3.5 = and i64 %shl253.3.5, %b1.b2
+ %cmp259.3.5 = icmp eq i64 %and254.3.5, %shl253.3.5
+ %conv263.3.5 = sitofp i32 %value.27.2.5 to float
+ %211 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.3.5)
+ %conv264.3.5 = fptosi float %211 to i32
+ %value.27.3.5 = select i1 %cmp259.3.5, i32 %conv264.3.5, i32 %value.27.2.5
+ %and254.4.5 = and i64 %shl253.4.5, %b1.b2
+ %cmp259.4.5 = icmp eq i64 %and254.4.5, %shl253.4.5
+ %conv263.4.5 = sitofp i32 %value.27.3.5 to float
+ %212 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.4.5)
+ %conv264.4.5 = fptosi float %212 to i32
+ %value.27.4.5 = select i1 %cmp259.4.5, i32 %conv264.4.5, i32 %value.27.3.5
+ %and254.5.5 = and i64 %shl253.5.5, %b1.b2
+ %cmp259.5.5 = icmp eq i64 %and254.5.5, %shl253.5.5
+ %conv263.5.5 = sitofp i32 %value.27.4.5 to float
+ %213 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv263.5.5)
+ %conv264.5.5 = fptosi float %213 to i32
+ %value.27.5.5 = select i1 %cmp259.5.5, i32 %conv264.5.5, i32 %value.27.4.5
+ %and284 = and i64 %10, %b1.b2
+ %cmp289 = icmp eq i64 %and284, %10
+ %conv293 = sitofp i32 %value.27.5.5 to float
+ %214 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293)
+ %conv294 = fptosi float %214 to i32
+ %value.30 = select i1 %cmp289, i32 %conv294, i32 %value.27.5.5
+ %and284.1 = and i64 %shl283.1, %b1.b2
+ %cmp289.1 = icmp eq i64 %and284.1, %shl283.1
+ %conv293.1 = sitofp i32 %value.30 to float
+ %215 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.1)
+ %conv294.1 = fptosi float %215 to i32
+ %value.30.1 = select i1 %cmp289.1, i32 %conv294.1, i32 %value.30
+ %and284.2 = and i64 %shl283.2, %b1.b2
+ %cmp289.2 = icmp eq i64 %and284.2, %shl283.2
+ %conv293.2 = sitofp i32 %value.30.1 to float
+ %216 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.2)
+ %conv294.2 = fptosi float %216 to i32
+ %value.30.2 = select i1 %cmp289.2, i32 %conv294.2, i32 %value.30.1
+ %and284.3 = and i64 %shl283.3, %b1.b2
+ %cmp289.3 = icmp eq i64 %and284.3, %shl283.3
+ %conv293.3 = sitofp i32 %value.30.2 to float
+ %217 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.3)
+ %conv294.3 = fptosi float %217 to i32
+ %value.30.3 = select i1 %cmp289.3, i32 %conv294.3, i32 %value.30.2
+ %and284.1658 = and i64 %shl283.1657, %b1.b2
+ %cmp289.1659 = icmp eq i64 %and284.1658, %shl283.1657
+ %conv293.1660 = sitofp i32 %value.30.3 to float
+ %218 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.1660)
+ %conv294.1661 = fptosi float %218 to i32
+ %value.30.1662 = select i1 %cmp289.1659, i32 %conv294.1661, i32 %value.30.3
+ %and284.1.1 = and i64 %shl283.1.1, %b1.b2
+ %cmp289.1.1 = icmp eq i64 %and284.1.1, %shl283.1.1
+ %conv293.1.1 = sitofp i32 %value.30.1662 to float
+ %219 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.1.1)
+ %conv294.1.1 = fptosi float %219 to i32
+ %value.30.1.1 = select i1 %cmp289.1.1, i32 %conv294.1.1, i32 %value.30.1662
+ %and284.2.1 = and i64 %shl283.2.1, %b1.b2
+ %cmp289.2.1 = icmp eq i64 %and284.2.1, %shl283.2.1
+ %conv293.2.1 = sitofp i32 %value.30.1.1 to float
+ %220 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.2.1)
+ %conv294.2.1 = fptosi float %220 to i32
+ %value.30.2.1 = select i1 %cmp289.2.1, i32 %conv294.2.1, i32 %value.30.1.1
+ %and284.3.1 = and i64 %shl283.3.1, %b1.b2
+ %cmp289.3.1 = icmp eq i64 %and284.3.1, %shl283.3.1
+ %conv293.3.1 = sitofp i32 %value.30.2.1 to float
+ %221 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.3.1)
+ %conv294.3.1 = fptosi float %221 to i32
+ %value.30.3.1 = select i1 %cmp289.3.1, i32 %conv294.3.1, i32 %value.30.2.1
+ %and284.2664 = and i64 %shl283.2663, %b1.b2
+ %cmp289.2665 = icmp eq i64 %and284.2664, %shl283.2663
+ %conv293.2666 = sitofp i32 %value.30.3.1 to float
+ %222 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.2666)
+ %conv294.2667 = fptosi float %222 to i32
+ %value.30.2668 = select i1 %cmp289.2665, i32 %conv294.2667, i32 %value.30.3.1
+ %and284.1.2 = and i64 %shl283.1.2, %b1.b2
+ %cmp289.1.2 = icmp eq i64 %and284.1.2, %shl283.1.2
+ %conv293.1.2 = sitofp i32 %value.30.2668 to float
+ %223 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.1.2)
+ %conv294.1.2 = fptosi float %223 to i32
+ %value.30.1.2 = select i1 %cmp289.1.2, i32 %conv294.1.2, i32 %value.30.2668
+ %and284.2.2 = and i64 %shl283.2.2, %b1.b2
+ %cmp289.2.2 = icmp eq i64 %and284.2.2, %shl283.2.2
+ %conv293.2.2 = sitofp i32 %value.30.1.2 to float
+ %224 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.2.2)
+ %conv294.2.2 = fptosi float %224 to i32
+ %value.30.2.2 = select i1 %cmp289.2.2, i32 %conv294.2.2, i32 %value.30.1.2
+ %and284.3.2 = and i64 %shl283.3.2, %b1.b2
+ %cmp289.3.2 = icmp eq i64 %and284.3.2, %shl283.3.2
+ %conv293.3.2 = sitofp i32 %value.30.2.2 to float
+ %225 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv293.3.2)
+ %conv294.3.2 = fptosi float %225 to i32
+ %value.30.3.2 = select i1 %cmp289.3.2, i32 %conv294.3.2, i32 %value.30.2.2
+ %and314 = and i64 %11, %b1.b2
+ %cmp319 = icmp eq i64 %and314, %11
+ %conv323 = sitofp i32 %value.30.3.2 to float
+ %226 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323)
+ %conv324 = fptosi float %226 to i32
+ %value.33 = select i1 %cmp319, i32 %conv324, i32 %value.30.3.2
+ %and314.1 = and i64 %shl313.1, %b1.b2
+ %cmp319.1 = icmp eq i64 %and314.1, %shl313.1
+ %conv323.1 = sitofp i32 %value.33 to float
+ %227 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.1)
+ %conv324.1 = fptosi float %227 to i32
+ %value.33.1 = select i1 %cmp319.1, i32 %conv324.1, i32 %value.33
+ %and314.2 = and i64 %shl313.2, %b1.b2
+ %cmp319.2 = icmp eq i64 %and314.2, %shl313.2
+ %conv323.2 = sitofp i32 %value.33.1 to float
+ %228 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.2)
+ %conv324.2 = fptosi float %228 to i32
+ %value.33.2 = select i1 %cmp319.2, i32 %conv324.2, i32 %value.33.1
+ %and314.3 = and i64 %shl313.3, %b1.b2
+ %cmp319.3 = icmp eq i64 %and314.3, %shl313.3
+ %conv323.3 = sitofp i32 %value.33.2 to float
+ %229 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.3)
+ %conv324.3 = fptosi float %229 to i32
+ %value.33.3 = select i1 %cmp319.3, i32 %conv324.3, i32 %value.33.2
+ %and314.1674 = and i64 %shl313.1673, %b1.b2
+ %cmp319.1675 = icmp eq i64 %and314.1674, %shl313.1673
+ %conv323.1676 = sitofp i32 %value.33.3 to float
+ %230 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.1676)
+ %conv324.1677 = fptosi float %230 to i32
+ %value.33.1678 = select i1 %cmp319.1675, i32 %conv324.1677, i32 %value.33.3
+ %and314.1.1 = and i64 %shl313.1.1, %b1.b2
+ %cmp319.1.1 = icmp eq i64 %and314.1.1, %shl313.1.1
+ %conv323.1.1 = sitofp i32 %value.33.1678 to float
+ %231 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.1.1)
+ %conv324.1.1 = fptosi float %231 to i32
+ %value.33.1.1 = select i1 %cmp319.1.1, i32 %conv324.1.1, i32 %value.33.1678
+ %and314.2.1 = and i64 %shl313.2.1, %b1.b2
+ %cmp319.2.1 = icmp eq i64 %and314.2.1, %shl313.2.1
+ %conv323.2.1 = sitofp i32 %value.33.1.1 to float
+ %232 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.2.1)
+ %conv324.2.1 = fptosi float %232 to i32
+ %value.33.2.1 = select i1 %cmp319.2.1, i32 %conv324.2.1, i32 %value.33.1.1
+ %and314.3.1 = and i64 %shl313.3.1, %b1.b2
+ %cmp319.3.1 = icmp eq i64 %and314.3.1, %shl313.3.1
+ %conv323.3.1 = sitofp i32 %value.33.2.1 to float
+ %233 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.3.1)
+ %conv324.3.1 = fptosi float %233 to i32
+ %value.33.3.1 = select i1 %cmp319.3.1, i32 %conv324.3.1, i32 %value.33.2.1
+ %and314.2680 = and i64 %shl313.2679, %b1.b2
+ %cmp319.2681 = icmp eq i64 %and314.2680, %shl313.2679
+ %conv323.2682 = sitofp i32 %value.33.3.1 to float
+ %234 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.2682)
+ %conv324.2683 = fptosi float %234 to i32
+ %value.33.2684 = select i1 %cmp319.2681, i32 %conv324.2683, i32 %value.33.3.1
+ %and314.1.2 = and i64 %shl313.1.2, %b1.b2
+ %cmp319.1.2 = icmp eq i64 %and314.1.2, %shl313.1.2
+ %conv323.1.2 = sitofp i32 %value.33.2684 to float
+ %235 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.1.2)
+ %conv324.1.2 = fptosi float %235 to i32
+ %value.33.1.2 = select i1 %cmp319.1.2, i32 %conv324.1.2, i32 %value.33.2684
+ %and314.2.2 = and i64 %shl313.2.2, %b1.b2
+ %cmp319.2.2 = icmp eq i64 %and314.2.2, %shl313.2.2
+ %conv323.2.2 = sitofp i32 %value.33.1.2 to float
+ %236 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.2.2)
+ %conv324.2.2 = fptosi float %236 to i32
+ %value.33.2.2 = select i1 %cmp319.2.2, i32 %conv324.2.2, i32 %value.33.1.2
+ %and314.3.2 = and i64 %shl313.3.2, %b1.b2
+ %cmp319.3.2 = icmp eq i64 %and314.3.2, %shl313.3.2
+ %conv323.3.2 = sitofp i32 %value.33.2.2 to float
+ %237 = tail call float @llvm.fmuladd.f32(float %add.add4, float 5.000000e+00, float %conv323.3.2)
+ %conv324.3.2 = fptosi float %237 to i32
+ %value.33.3.2 = select i1 %cmp319.3.2, i32 %conv324.3.2, i32 %value.33.2.2
+ br i1 %cmp1, label %for.body, label %for.end334
+
+for.end334: ; preds = %for.body
+ ret i32 %value.33.3.2
+}
diff --git a/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir b/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir
new file mode 100644
index 0000000000000..a87a5c951b01b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir
@@ -0,0 +1,509 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - | FileCheck %s
+
+---
+# Fold a sequence of 32 stores to pairs by materializing the base
+# register to make the remaining offset fit the immediate operand.
+name: test0
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test0
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 89 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 88 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 87 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 86 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 85 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 84 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 83 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 82 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 81 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 80 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 79 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 78 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 77 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 76 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 75 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 74 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 73 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 72 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 95 :: (store (s32))
+ STRXui $xzr, $sp, 94 :: (store (s32))
+ STRXui $xzr, $sp, 93 :: (store (s32))
+ STRXui $xzr, $sp, 92 :: (store (s32))
+ STRXui $xzr, $sp, 91 :: (store (s32))
+ STRXui $xzr, $sp, 90 :: (store (s32))
+ STRXui $xzr, $sp, 89 :: (store (s32))
+ STRXui $xzr, $sp, 88 :: (store (s32))
+ STRXui $xzr, $sp, 87 :: (store (s32))
+ STRXui $xzr, $sp, 86 :: (store (s32))
+ STRXui $xzr, $sp, 85 :: (store (s32))
+ STRXui $xzr, $sp, 84 :: (store (s32))
+ STRXui $xzr, $sp, 83 :: (store (s32))
+ STRXui $xzr, $sp, 82 :: (store (s32))
+ STRXui $xzr, $sp, 81 :: (store (s32))
+ STRXui $xzr, $sp, 80 :: (store (s32))
+ STRXui $xzr, $sp, 79 :: (store (s32))
+ STRXui $xzr, $sp, 78 :: (store (s32))
+ STRXui $xzr, $sp, 77 :: (store (s32))
+ STRXui $xzr, $sp, 76 :: (store (s32))
+ STRXui $xzr, $sp, 75 :: (store (s32))
+ STRXui $xzr, $sp, 74 :: (store (s32))
+ STRXui $xzr, $sp, 73 :: (store (s32))
+ STRXui $xzr, $sp, 72 :: (store (s32))
+ STRXui $xzr, $sp, 71 :: (store (s32))
+ STRXui $xzr, $sp, 70 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+ RET undef $lr
+...
+---
+# Same as test0, but there are 2 more store instructions.
+# The optimization has an arbitrary limit of 32 instructions.
+# Longer sequences often call memset instead.
+name: test1
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test1
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 97 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 96 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 89 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 88 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 87 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 86 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 85 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 84 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 83 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 82 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 81 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 80 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 79 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 78 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 77 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 76 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 75 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 74 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 73 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 72 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 97 :: (store (s32))
+ STRXui $xzr, $sp, 96 :: (store (s32))
+ STRXui $xzr, $sp, 95 :: (store (s32))
+ STRXui $xzr, $sp, 94 :: (store (s32))
+ STRXui $xzr, $sp, 93 :: (store (s32))
+ STRXui $xzr, $sp, 92 :: (store (s32))
+ STRXui $xzr, $sp, 91 :: (store (s32))
+ STRXui $xzr, $sp, 90 :: (store (s32))
+ STRXui $xzr, $sp, 89 :: (store (s32))
+ STRXui $xzr, $sp, 88 :: (store (s32))
+ STRXui $xzr, $sp, 87 :: (store (s32))
+ STRXui $xzr, $sp, 86 :: (store (s32))
+ STRXui $xzr, $sp, 85 :: (store (s32))
+ STRXui $xzr, $sp, 84 :: (store (s32))
+ STRXui $xzr, $sp, 83 :: (store (s32))
+ STRXui $xzr, $sp, 82 :: (store (s32))
+ STRXui $xzr, $sp, 81 :: (store (s32))
+ STRXui $xzr, $sp, 80 :: (store (s32))
+ STRXui $xzr, $sp, 79 :: (store (s32))
+ STRXui $xzr, $sp, 78 :: (store (s32))
+ STRXui $xzr, $sp, 77 :: (store (s32))
+ STRXui $xzr, $sp, 76 :: (store (s32))
+ STRXui $xzr, $sp, 75 :: (store (s32))
+ STRXui $xzr, $sp, 74 :: (store (s32))
+ STRXui $xzr, $sp, 73 :: (store (s32))
+ STRXui $xzr, $sp, 72 :: (store (s32))
+ STRXui $xzr, $sp, 71 :: (store (s32))
+ STRXui $xzr, $sp, 70 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+ RET undef $lr
+...
+---
+# Only STRXui and LDRXui instructions are handled. Other instructions
+# mixed into the sequence stop the search.
+name: test2
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp, $x2
+
+ ; CHECK-LABEL: name: test2
+ ; CHECK: liveins: $lr, $fp, $sp, $x2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 97 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 96 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
+ ; CHECK-NEXT: $x2 = ADDXri $x2, 1, 0
+ ; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 97 :: (store (s32))
+ STRXui $xzr, $sp, 96 :: (store (s32))
+ STRXui $xzr, $sp, 95 :: (store (s32))
+ STRXui $xzr, $sp, 94 :: (store (s32))
+ STRXui $xzr, $sp, 93 :: (store (s32))
+ STRXui $xzr, $sp, 92 :: (store (s32))
+ $x2 = ADDXri $x2, 1, 0
+ STRXui $xzr, $sp, 91 :: (store (s32))
+ STRXui $xzr, $sp, 90 :: (store (s32))
+ RET undef $lr
+...
+---
+# All instructions in a sequence must share the same base pointer.
+name: test3
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test3
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 97 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 96 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $fp, 93 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $fp, 92 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 89 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $fp, 88 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 87 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 86 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 97 :: (store (s32))
+ STRXui $xzr, $sp, 96 :: (store (s32))
+ STRXui $xzr, $sp, 95 :: (store (s32))
+ STRXui $xzr, $sp, 94 :: (store (s32))
+ STRXui $xzr, $sp, 93 :: (store (s32))
+ STRXui $xzr, $sp, 92 :: (store (s32))
+ STRXui $xzr, $fp, 93 :: (store (s32))
+ STRXui $xzr, $fp, 92 :: (store (s32))
+ STRXui $xzr, $sp, 91 :: (store (s32))
+ STRXui $xzr, $sp, 90 :: (store (s32))
+ STRXui $xzr, $sp, 89 :: (store (s32))
+ STRXui $xzr, $fp, 88 :: (store (s32))
+ STRXui $xzr, $sp, 87 :: (store (s32))
+ STRXui $xzr, $sp, 86 :: (store (s32))
+
+ RET undef $lr
+...
+---
+# Offset must fit the immediate operand of each instruction.
+name: test4
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test4
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 130 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 129 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 128 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 127 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 130 :: (store (s32))
+ STRXui $xzr, $sp, 129 :: (store (s32))
+ STRXui $xzr, $sp, 128 :: (store (s32))
+ STRXui $xzr, $sp, 127 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+
+ RET undef $lr
+...
+---
+# Minimum offset must fit immediate of ADDXri.
+name: test5
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test5
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 521 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 520 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 519 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 518 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 517 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 516 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 515 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 514 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 513 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 512 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 521 :: (store (s32))
+ STRXui $xzr, $sp, 520 :: (store (s32))
+ STRXui $xzr, $sp, 519 :: (store (s32))
+ STRXui $xzr, $sp, 518 :: (store (s32))
+ STRXui $xzr, $sp, 517 :: (store (s32))
+ STRXui $xzr, $sp, 516 :: (store (s32))
+ STRXui $xzr, $sp, 515 :: (store (s32))
+ STRXui $xzr, $sp, 514 :: (store (s32))
+ STRXui $xzr, $sp, 513 :: (store (s32))
+ STRXui $xzr, $sp, 512 :: (store (s32))
+
+ RET undef $lr
+...
+---
+# There must be at least 1 free register. Here X0 is free.
+name: test6
+body: |
+ bb.0.entry:
+ liveins: $lr, $sp, $fp, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28
+
+ ; CHECK-LABEL: name: test6
+ ; CHECK: liveins: $lr, $sp, $fp, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 71 :: (store (s32))
+ STRXui $xzr, $sp, 70 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+
+ RET undef $lr
+...
+---
+# Bail out if all registers are allocated.
+name: test7
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28
+
+ ; CHECK-LABEL: name: test7
+ ; CHECK: liveins: $lr, $fp, $sp, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $x2, 1, 0
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 71 :: (store (s32))
+ STRXui $xzr, $sp, 70 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ $x0 = ADDXri $x2, 1, 0
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+
+ RET undef $lr
+...
+---
+# Fold a sequence of loads.
+name: test8
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test8
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 95 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 94 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 93 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 92 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 91 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 90 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 89 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 88 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 87 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 86 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 85 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 84 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 83 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 82 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 81 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 80 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 79 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 78 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 77 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 76 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 75 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 74 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 73 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 72 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 71 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 70 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 69 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 68 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 67 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 66 :: (load (s32))
+ ; CHECK-NEXT: $x0 = LDRXui $sp, 65 :: (load (s32))
+ ; CHECK-NEXT: $x1 = LDRXui $sp, 64 :: (load (s32))
+ ; CHECK-NEXT: RET undef $lr
+ $x0 = LDRXui $sp, 95 :: (load (s32))
+ $x1 = LDRXui $sp, 94 :: (load (s32))
+ $x0 = LDRXui $sp, 93 :: (load (s32))
+ $x1 = LDRXui $sp, 92 :: (load (s32))
+ $x0 = LDRXui $sp, 91 :: (load (s32))
+ $x1 = LDRXui $sp, 90 :: (load (s32))
+ $x0 = LDRXui $sp, 89 :: (load (s32))
+ $x1 = LDRXui $sp, 88 :: (load (s32))
+ $x0 = LDRXui $sp, 87 :: (load (s32))
+ $x1 = LDRXui $sp, 86 :: (load (s32))
+ $x0 = LDRXui $sp, 85 :: (load (s32))
+ $x1 = LDRXui $sp, 84 :: (load (s32))
+ $x0 = LDRXui $sp, 83 :: (load (s32))
+ $x1 = LDRXui $sp, 82 :: (load (s32))
+ $x0 = LDRXui $sp, 81 :: (load (s32))
+ $x1 = LDRXui $sp, 80 :: (load (s32))
+ $x0 = LDRXui $sp, 79 :: (load (s32))
+ $x1 = LDRXui $sp, 78 :: (load (s32))
+ $x0 = LDRXui $sp, 77 :: (load (s32))
+ $x1 = LDRXui $sp, 76 :: (load (s32))
+ $x0 = LDRXui $sp, 75 :: (load (s32))
+ $x1 = LDRXui $sp, 74 :: (load (s32))
+ $x0 = LDRXui $sp, 73 :: (load (s32))
+ $x1 = LDRXui $sp, 72 :: (load (s32))
+ $x0 = LDRXui $sp, 71 :: (load (s32))
+ $x1 = LDRXui $sp, 70 :: (load (s32))
+ $x0 = LDRXui $sp, 69 :: (load (s32))
+ $x1 = LDRXui $sp, 68 :: (load (s32))
+ $x0 = LDRXui $sp, 67 :: (load (s32))
+ $x1 = LDRXui $sp, 66 :: (load (s32))
+ $x0 = LDRXui $sp, 65 :: (load (s32))
+ $x1 = LDRXui $sp, 64 :: (load (s32))
+ RET undef $lr
+...
+---
+# Continuous sequence with the minimum offset equal to zero.
+name: test9
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test9
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $sp, 0 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 71 :: (store (s32))
+ STRXui $xzr, $sp, 70 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+ STRXui $xzr, $sp, 1 :: (store (s32))
+ STRXui $xzr, $sp, 0 :: (store (s32))
+
+ RET undef $lr
+...
+---
+# Same as test9, but without the trailing stores that break the
+# sequence.
+name: test10
+body: |
+ bb.0.entry:
+ liveins: $lr, $fp, $sp
+
+ ; CHECK-LABEL: name: test10
+ ; CHECK: liveins: $lr, $fp, $sp
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr
+ STRXui $xzr, $sp, 71 :: (store (s32))
+ STRXui $xzr, $sp, 70 :: (store (s32))
+ STRXui $xzr, $sp, 69 :: (store (s32))
+ STRXui $xzr, $sp, 68 :: (store (s32))
+ STRXui $xzr, $sp, 67 :: (store (s32))
+ STRXui $xzr, $sp, 66 :: (store (s32))
+ STRXui $xzr, $sp, 65 :: (store (s32))
+ STRXui $xzr, $sp, 64 :: (store (s32))
+
+ RET undef $lr
+...
>From c90ab40f3af0bb632ee1c207e06791aa95ea4ede Mon Sep 17 00:00:00 2001
From: Andrew Savonichev <andrew.savonichev at gmail.com>
Date: Fri, 11 Sep 2026 01:16:57 +0900
Subject: [PATCH 2/2] [AArch64] Materialize a common offset for paired
load/store optimization
AArch64LoadStoreOptimizer used to not optimize loads/stores with an
offset greater than the range of LDP/STP.
The patch adds a fallback path to detect a chain of LDP/STP candidates
and materialize `base reg + offset` into a free register to allow the
existing optimization in tryToPairLdStInst to continue.
The optimization in tryToPairLdStInst handles a lot of cases of
load/store instructions: pre- and post-increments, scaled and unscaled
variants, etc. The new fallback path in tryToReduceSequenceOffset
avoids dealing with this complexity, and it only handles trivial
sequences of STRXui and LDRXui instructions.
The motivating example is large-stack-memset.ll, where the compiler
used to miss the optimization for a memset.
---
.../AArch64/AArch64LoadStoreOptimizer.cpp | 202 +++++++++++++++-
.../CodeGen/AArch64/large-stack-memset.ll | 51 ++---
.../test/CodeGen/AArch64/large-stack-spill.ll | 16 +-
.../AArch64/ldst-opt-reduce-offset.mir | 216 +++++++-----------
llvm/test/CodeGen/AArch64/stack-hazard.ll | 169 ++++++--------
5 files changed, 360 insertions(+), 294 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 13f11eb2a07f1..aee5d7148cdc7 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -217,6 +217,10 @@ struct AArch64LoadStoreOpt {
// Find and pair ldr/str instructions.
bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+ // Reduce offsets of an ldr/str sequence that starts with MBBI by
+ // materializing the base register + common offset.
+ bool tryToReduceSequenceOffset(MachineBasicBlock::iterator MBBI);
+
// Find and promote load instructions which read directly from store.
bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
@@ -1927,6 +1931,16 @@ static bool canRenameUntilSecondLoad(
return Success;
}
+// Checks if any sub- or super-register of PR is callee saved.
+static bool anySubOrSuperRegCalleePreserved(MCPhysReg PR,
+ const MachineFunction &MF,
+ const TargetRegisterInfo *TRI) {
+ return any_of(TRI->sub_and_superregs_inclusive(PR),
+ [&MF, TRI](MCPhysReg SubOrSuper) {
+ return TRI->isCalleeSavedPhysReg(SubOrSuper, MF);
+ });
+}
+
// Check if we can find a physical register for renaming \p Reg. This register
// must:
// * not be defined already in \p DefinedInBB; DefinedInBB must contain all
@@ -1941,14 +1955,6 @@ static std::optional<MCPhysReg> tryToFindRegisterToRename(
const TargetRegisterInfo *TRI) {
const MachineRegisterInfo &RegInfo = MF.getRegInfo();
- // Checks if any sub- or super-register of PR is callee saved.
- auto AnySubOrSuperRegCalleePreserved = [&MF, TRI](MCPhysReg PR) {
- return any_of(TRI->sub_and_superregs_inclusive(PR),
- [&MF, TRI](MCPhysReg SubOrSuper) {
- return TRI->isCalleeSavedPhysReg(SubOrSuper, MF);
- });
- };
-
// Check if PR or one of its sub- or super-registers can be used for all
// required register classes.
auto CanBeUsedForAllClasses = [&RequiredClasses, TRI](MCPhysReg PR) {
@@ -1962,7 +1968,8 @@ static std::optional<MCPhysReg> tryToFindRegisterToRename(
auto *RegClass = TRI->getMinimalPhysRegClass(Reg);
for (const MCPhysReg &PR : *RegClass) {
if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
- !RegInfo.isReserved(PR) && !AnySubOrSuperRegCalleePreserved(PR) &&
+ !RegInfo.isReserved(PR) &&
+ !anySubOrSuperRegCalleePreserved(PR, MF, TRI) &&
CanBeUsedForAllClasses(PR)) {
DefinedInBB.addReg(PR);
LLVM_DEBUG(dbgs() << "Found rename register " << printReg(PR, TRI)
@@ -2841,6 +2848,167 @@ bool AArch64LoadStoreOpt::tryToMergeZeroStInst(
return false;
}
+struct LdStPair {
+ MachineInstr *MI[2];
+ int Offset[2];
+ bool Skip;
+};
+
+bool AArch64LoadStoreOpt::tryToReduceSequenceOffset(
+ MachineBasicBlock::iterator MBBI) {
+ MachineInstr &RootMI = *MBBI;
+ MachineFunction &MF = *RootMI.getMF();
+ MachineBasicBlock &BB = *RootMI.getParent();
+ MachineBasicBlock::iterator E = BB.end();
+
+ // Find a sequence of pairable store instructions.
+ SmallVector<LdStPair, 32> Sequence;
+ int MinOffset = INT_MAX;
+ Register BaseReg = 0;
+
+ LiveRegUnits UsedInBetween;
+ UsedInBetween.init(*TRI);
+
+ MachineBasicBlock::iterator It = MBBI;
+ int MaxSeqLength = 16;
+ for (int i = 0; i < MaxSeqLength; ++i) {
+ // Iterate over pairs of instructions
+ if (It == E)
+ break;
+ MachineInstr &FirstMI = *It;
+ ++It;
+
+ if (It == E)
+ break;
+ MachineInstr &SecondMI = *It;
+ ++It;
+
+ // MachineScheduler tries to make a continuous sequence of
+ // loads/stores. Stop early if the sequence interrupted.
+ unsigned Opcode = FirstMI.getOpcode();
+ if (Opcode != SecondMI.getOpcode())
+ break;
+
+ // Only match basic 64 bit loads and stores. We must avoid
+ // changing instructions, unless they are definitely going to be
+ // paired later. Pairing logic is complicated, so by limiting
+ // scope to STRXui and LDRXui we avoid most of this complexity.
+ if (Opcode != AArch64::STRXui && Opcode != AArch64::LDRXui)
+ break;
+
+ Register FirstReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg();
+ Register SecondReg = AArch64InstrInfo::getLdStBaseOp(SecondMI).getReg();
+
+ // All load/store instructions in the sequence must have the same
+ // base register.
+
+ if (FirstReg != SecondReg)
+ break;
+
+ if (!BaseReg) {
+ BaseReg = FirstReg;
+ } else {
+ if (BaseReg != FirstReg)
+ break;
+ }
+
+ int FirstOffset = AArch64InstrInfo::getLdStOffsetOp(FirstMI).getImm();
+ int SecondOffset = AArch64InstrInfo::getLdStOffsetOp(SecondMI).getImm();
+
+ // Offsets of STRXui and LDRXui must be adjecent to pair them.
+ if (std::abs(FirstOffset - SecondOffset) != 1)
+ break;
+
+ assert(FirstOffset >= 0 && SecondOffset >= 0 &&
+ "offset of STRXui and LDRXui is unsigned");
+
+ MinOffset = std::min(FirstOffset, MinOffset);
+ MinOffset = std::min(SecondOffset, MinOffset);
+
+ UsedInBetween.accumulate(FirstMI);
+ UsedInBetween.accumulate(SecondMI);
+
+ Sequence.push_back(
+ LdStPair{{&FirstMI, &SecondMI}, {FirstOffset, SecondOffset}, false});
+ }
+
+ // Bail out if the sequence already starts with 0 offset.
+ if (!MinOffset)
+ return false;
+
+ // Reduce offsets by MinOffset for all pairs. Check that the
+ // remaining offsets fit the paired instruction.
+ unsigned Count = 0;
+ for (LdStPair &Pair : Sequence) {
+ Pair.Offset[0] -= MinOffset;
+ Pair.Offset[1] -= MinOffset;
+
+ // Skip pairs that do not fit.
+ int HeadOffset = std::min(Pair.Offset[0], Pair.Offset[1]);
+ if (!inBoundsForPair(/*IsUnscaled=*/false, HeadOffset,
+ /*OffsetStride=*/1)) {
+ Pair.Skip = true;
+ continue;
+ }
+ ++Count;
+ }
+
+ // Not profitable to change short sequences.
+ if (Count < 3)
+ return false;
+
+ // Avoid changing sequences that do not start with a pair we can
+ // handle. Otherwise we make a useless change here and it may goes
+ // out of sync with tryToPairLdStInst that actually folds the
+ // sequence.
+ if (Sequence[0].Skip)
+ return false;
+
+ // Find a free register to materialize the new base.
+ auto *RegClass = TRI->getRegClass(AArch64::GPR64spRegClassID);
+ if (!RegClass->contains(BaseReg))
+ return false;
+ const MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MCPhysReg NewBaseReg = 0;
+ for (const MCPhysReg &PR : *RegClass) {
+ if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
+ !RegInfo.isReserved(PR) &&
+ !anySubOrSuperRegCalleePreserved(PR, MF, TRI)) {
+ DefinedInBB.addReg(PR);
+ NewBaseReg = PR;
+ break;
+ }
+ }
+
+ if (!NewBaseReg)
+ return false;
+
+ // Scaled offset must fit into 12 bit immediate of ADDXri.
+ int ScaledMinOffset = TII->getMemScale(RootMI) * MinOffset;
+ if (ScaledMinOffset > 4095)
+ return false;
+ assert(ScaledMinOffset > 0 && "inconsistent offset");
+
+ // Materialize the new base: old base + scaled minimum (common) offset.
+ BuildMI(BB, MBBI, RootMI.getDebugLoc(), TII->get(AArch64::ADDXri), NewBaseReg)
+ .addReg(BaseReg)
+ .addImm(ScaledMinOffset)
+ .addImm(0);
+
+ // Update all pairs to use the new base and offset.
+ for (LdStPair &Pair : Sequence) {
+ if (Pair.Skip)
+ continue;
+
+ for (unsigned i = 0; i < 2; ++i) {
+ Pair.MI[i]->getOperand(1).setReg(NewBaseReg);
+ Pair.MI[i]->getOperand(2).setImm(Pair.Offset[i]);
+ }
+ }
+
+ return true;
+}
+
// Find loads and stores that can be merged into a single load or store pair
// instruction.
bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
@@ -2867,8 +3035,20 @@ bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
// Allow one more for offset.
if (Offset > 0)
Offset -= OffsetStride;
- if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
- return false;
+ if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride)) {
+ // Try to materialize (Base + Offset) to reduce the offset.
+ if (!tryToReduceSequenceOffset(MBBI))
+ return false;
+
+ // Check the offset again
+ Offset = AArch64InstrInfo::getLdStOffsetOp(MI).getImm();
+ if (Offset > 0)
+ Offset -= OffsetStride;
+ if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride)) {
+ assert(0 && "useless materialization");
+ return false;
+ }
+ }
// Look ahead up to LdStLimit instructions for a pairable instruction.
LdStPairFlags Flags;
diff --git a/llvm/test/CodeGen/AArch64/large-stack-memset.ll b/llvm/test/CodeGen/AArch64/large-stack-memset.ll
index 8572f4e3b827e..edda8d9998eac 100644
--- a/llvm/test/CodeGen/AArch64/large-stack-memset.ll
+++ b/llvm/test/CodeGen/AArch64/large-stack-memset.ll
@@ -28,41 +28,26 @@ define void @test1() #1 {
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: sub sp, sp, #768
; CHECK-NEXT: .cfi_def_cfa_offset 784
-; CHECK-NEXT: mov x0, sp
+; CHECK-NEXT: add x0, sp, #512
; CHECK-NEXT: mov w1, wzr
; CHECK-NEXT: mov w2, #512 // =0x200
-; CHECK-NEXT: str xzr, [sp, #760]
-; CHECK-NEXT: str xzr, [sp, #752]
-; CHECK-NEXT: str xzr, [sp, #744]
-; CHECK-NEXT: str xzr, [sp, #736]
-; CHECK-NEXT: str xzr, [sp, #728]
-; CHECK-NEXT: str xzr, [sp, #720]
-; CHECK-NEXT: str xzr, [sp, #712]
-; CHECK-NEXT: str xzr, [sp, #704]
-; CHECK-NEXT: str xzr, [sp, #696]
-; CHECK-NEXT: str xzr, [sp, #688]
-; CHECK-NEXT: str xzr, [sp, #680]
-; CHECK-NEXT: str xzr, [sp, #672]
-; CHECK-NEXT: str xzr, [sp, #664]
-; CHECK-NEXT: str xzr, [sp, #656]
-; CHECK-NEXT: str xzr, [sp, #648]
-; CHECK-NEXT: str xzr, [sp, #640]
-; CHECK-NEXT: str xzr, [sp, #632]
-; CHECK-NEXT: str xzr, [sp, #624]
-; CHECK-NEXT: str xzr, [sp, #616]
-; CHECK-NEXT: str xzr, [sp, #608]
-; CHECK-NEXT: str xzr, [sp, #600]
-; CHECK-NEXT: str xzr, [sp, #592]
-; CHECK-NEXT: str xzr, [sp, #584]
-; CHECK-NEXT: str xzr, [sp, #576]
-; CHECK-NEXT: str xzr, [sp, #568]
-; CHECK-NEXT: str xzr, [sp, #560]
-; CHECK-NEXT: str xzr, [sp, #552]
-; CHECK-NEXT: str xzr, [sp, #544]
-; CHECK-NEXT: str xzr, [sp, #536]
-; CHECK-NEXT: str xzr, [sp, #528]
-; CHECK-NEXT: str xzr, [sp, #520]
-; CHECK-NEXT: str xzr, [sp, #512]
+; CHECK-NEXT: stp xzr, xzr, [x0, #240]
+; CHECK-NEXT: stp xzr, xzr, [x0, #224]
+; CHECK-NEXT: stp xzr, xzr, [x0, #208]
+; CHECK-NEXT: stp xzr, xzr, [x0, #192]
+; CHECK-NEXT: stp xzr, xzr, [x0, #176]
+; CHECK-NEXT: stp xzr, xzr, [x0, #160]
+; CHECK-NEXT: stp xzr, xzr, [x0, #144]
+; CHECK-NEXT: stp xzr, xzr, [x0, #128]
+; CHECK-NEXT: stp xzr, xzr, [x0, #112]
+; CHECK-NEXT: stp xzr, xzr, [x0, #96]
+; CHECK-NEXT: stp xzr, xzr, [x0, #80]
+; CHECK-NEXT: stp xzr, xzr, [x0, #64]
+; CHECK-NEXT: stp xzr, xzr, [x0, #48]
+; CHECK-NEXT: stp xzr, xzr, [x0, #32]
+; CHECK-NEXT: stp xzr, xzr, [x0, #16]
+; CHECK-NEXT: stp xzr, xzr, [x0]
+; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: bl memset
; CHECK-NEXT: add x0, sp, #512
; CHECK-NEXT: mov x1, sp
diff --git a/llvm/test/CodeGen/AArch64/large-stack-spill.ll b/llvm/test/CodeGen/AArch64/large-stack-spill.ll
index c4d195cbe703d..5a20eff7c35c8 100644
--- a/llvm/test/CodeGen/AArch64/large-stack-spill.ll
+++ b/llvm/test/CodeGen/AArch64/large-stack-spill.ll
@@ -495,16 +495,12 @@ define dso_local i32 @value(i64 noundef %b1, i64 noundef %b2) {
; CHECK-NEXT: ldr x19, [sp, #1672] // 8-byte Reload
; CHECK-NEXT: fadd s6, s0, s6
; CHECK-NEXT: bics xzr, x0, x3
-; CHECK-NEXT: ldr x20, [sp, #1664] // 8-byte Reload
-; CHECK-NEXT: ldr x21, [sp, #1656] // 8-byte Reload
-; CHECK-NEXT: ldr x22, [sp, #1648] // 8-byte Reload
-; CHECK-NEXT: ldr x23, [sp, #1640] // 8-byte Reload
-; CHECK-NEXT: ldr x24, [sp, #1632] // 8-byte Reload
-; CHECK-NEXT: ldr x25, [sp, #1624] // 8-byte Reload
-; CHECK-NEXT: ldr x26, [sp, #1616] // 8-byte Reload
-; CHECK-NEXT: ldr x27, [sp, #1608] // 8-byte Reload
-; CHECK-NEXT: ldr x28, [sp, #1600] // 8-byte Reload
-; CHECK-NEXT: ldr x29, [sp, #1592] // 8-byte Reload
+; CHECK-NEXT: add x1, sp, #1592
+; CHECK-NEXT: ldp x21, x20, [x1, #64] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x23, x22, [x1, #48] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x25, x24, [x1, #32] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x27, x26, [x1, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldp x29, x28, [x1] // 16-byte Folded Reload
; CHECK-NEXT: fmadd s7, s6, s5, s7
; CHECK-NEXT: ldr x30, [sp, #1584] // 8-byte Reload
; CHECK-NEXT: ldr x11, [sp, #1576] // 8-byte Reload
diff --git a/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir b/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir
index a87a5c951b01b..0cf38349c1457 100644
--- a/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir
+++ b/llvm/test/CodeGen/AArch64/ldst-opt-reduce-offset.mir
@@ -12,38 +12,23 @@ body: |
; CHECK-LABEL: name: test0
; CHECK: liveins: $lr, $fp, $sp
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 89 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 88 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 87 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 86 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 85 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 84 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 83 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 82 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 81 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 80 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 79 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 78 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 77 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 76 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 75 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 74 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 73 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 72 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 512, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 30 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 28 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 26 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 24 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 22 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 20 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 18 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 16 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 14 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 12 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 10 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 8 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 6 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
STRXui $xzr, $sp, 95 :: (store (s32))
STRXui $xzr, $sp, 94 :: (store (s32))
@@ -91,38 +76,23 @@ body: |
; CHECK-LABEL: name: test1
; CHECK: liveins: $lr, $fp, $sp
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, $sp, 97 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 96 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 89 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 88 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 87 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 86 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 85 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 84 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 83 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 82 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 81 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 80 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 79 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 78 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 77 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 76 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 75 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 74 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 73 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 72 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 528, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 30 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 28 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 26 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 24 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 22 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 20 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 18 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 16 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 14 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 12 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 10 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 8 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 6 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
; CHECK-NEXT: RET undef $lr
@@ -173,12 +143,10 @@ body: |
; CHECK-LABEL: name: test2
; CHECK: liveins: $lr, $fp, $sp, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, $sp, 97 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 96 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 736, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: $x2 = ADDXri $x2, 1, 0
; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $sp, 90 :: (store (s32))
@@ -204,12 +172,10 @@ body: |
; CHECK-LABEL: name: test3
; CHECK: liveins: $lr, $fp, $sp
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, $sp, 97 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 96 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 95 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 94 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 93 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 92 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 736, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $fp, 93 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $fp, 92 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $sp, 91 :: (store (s32))
@@ -248,14 +214,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: STRXui $xzr, $sp, 130 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $sp, 129 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 128 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 127 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 512, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 63 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
STRXui $xzr, $sp, 130 :: (store (s32))
STRXui $xzr, $sp, 129 :: (store (s32))
@@ -314,14 +277,11 @@ body: |
; CHECK-LABEL: name: test6
; CHECK: liveins: $lr, $sp, $fp, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 512, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 6 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
STRXui $xzr, $sp, 71 :: (store (s32))
STRXui $xzr, $sp, 70 :: (store (s32))
@@ -376,38 +336,23 @@ body: |
; CHECK-LABEL: name: test8
; CHECK: liveins: $lr, $fp, $sp
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $x0 = LDRXui $sp, 95 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 94 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 93 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 92 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 91 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 90 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 89 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 88 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 87 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 86 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 85 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 84 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 83 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 82 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 81 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 80 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 79 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 78 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 77 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 76 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 75 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 74 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 73 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 72 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 71 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 70 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 69 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 68 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 67 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 66 :: (load (s32))
- ; CHECK-NEXT: $x0 = LDRXui $sp, 65 :: (load (s32))
- ; CHECK-NEXT: $x1 = LDRXui $sp, 64 :: (load (s32))
+ ; CHECK-NEXT: $x2 = ADDXri $sp, 512, 0
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 30 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 28 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 26 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 24 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 22 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 20 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 18 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 16 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 14 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 12 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 10 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 8 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 6 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 4 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 2 :: (load (s32))
+ ; CHECK-NEXT: $x1, $x0 = LDPXi $x2, 0 :: (load (s32))
; CHECK-NEXT: RET undef $lr
$x0 = LDRXui $sp, 95 :: (load (s32))
$x1 = LDRXui $sp, 94 :: (load (s32))
@@ -454,12 +399,10 @@ body: |
; CHECK: liveins: $lr, $fp, $sp
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 520, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
; CHECK-NEXT: STPXi $xzr, $xzr, $sp, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
@@ -487,14 +430,11 @@ body: |
; CHECK-LABEL: name: test10
; CHECK: liveins: $lr, $fp, $sp
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: STRXui $xzr, $sp, 71 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 70 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 69 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 68 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 67 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 66 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 65 :: (store (s32))
- ; CHECK-NEXT: STRXui $xzr, $sp, 64 :: (store (s32))
+ ; CHECK-NEXT: $x0 = ADDXri $sp, 512, 0
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 6 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 4 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: STPXi $xzr, $xzr, $x0, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
STRXui $xzr, $sp, 71 :: (store (s32))
STRXui $xzr, $sp, 70 :: (store (s32))
diff --git a/llvm/test/CodeGen/AArch64/stack-hazard.ll b/llvm/test/CodeGen/AArch64/stack-hazard.ll
index bbb171d4fa885..ffb5adc6b105c 100644
--- a/llvm/test/CodeGen/AArch64/stack-hazard.ll
+++ b/llvm/test/CodeGen/AArch64/stack-hazard.ll
@@ -549,18 +549,15 @@ define i32 @csr_x18_25_d8_15_allocdi64(i64 %d, double %e) "aarch64_pstate_sm_com
; CHECK1024-LABEL: csr_x18_25_d8_15_allocdi64:
; CHECK1024: // %bb.0: // %entry
; CHECK1024-NEXT: sub sp, sp, #1152
+; CHECK1024-NEXT: add x1, sp, #1088
; CHECK1024-NEXT: stp d15, d14, [sp] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
-; CHECK1024-NEXT: str x29, [sp, #1088] // 8-byte Spill
-; CHECK1024-NEXT: str x25, [sp, #1096] // 8-byte Spill
-; CHECK1024-NEXT: str x24, [sp, #1104] // 8-byte Spill
-; CHECK1024-NEXT: str x23, [sp, #1112] // 8-byte Spill
-; CHECK1024-NEXT: str x22, [sp, #1120] // 8-byte Spill
-; CHECK1024-NEXT: str x21, [sp, #1128] // 8-byte Spill
-; CHECK1024-NEXT: str x20, [sp, #1136] // 8-byte Spill
-; CHECK1024-NEXT: str x19, [sp, #1144] // 8-byte Spill
+; CHECK1024-NEXT: stp x29, x25, [x1] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x24, x23, [x1, #16] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x22, x21, [x1, #32] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x20, x19, [x1, #48] // 16-byte Folded Spill
; CHECK1024-NEXT: sub sp, sp, #1056
; CHECK1024-NEXT: .cfi_def_cfa_offset 2208
; CHECK1024-NEXT: .cfi_offset w19, -8
@@ -588,16 +585,13 @@ define i32 @csr_x18_25_d8_15_allocdi64(i64 %d, double %e) "aarch64_pstate_sm_com
; CHECK1024-NEXT: str x8, [sp, #8]
; CHECK1024-NEXT: str d0, [sp, #1048]
; CHECK1024-NEXT: add sp, sp, #1056
+; CHECK1024-NEXT: add x2, sp, #1088
; CHECK1024-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
-; CHECK1024-NEXT: ldr x19, [sp, #1144] // 8-byte Reload
+; CHECK1024-NEXT: ldp x20, x19, [x2, #48] // 16-byte Folded Reload
+; CHECK1024-NEXT: ldp x22, x21, [x2, #32] // 16-byte Folded Reload
+; CHECK1024-NEXT: ldp x24, x23, [x2, #16] // 16-byte Folded Reload
+; CHECK1024-NEXT: ldp x29, x25, [x2] // 16-byte Folded Reload
; CHECK1024-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK1024-NEXT: ldr x20, [sp, #1136] // 8-byte Reload
-; CHECK1024-NEXT: ldr x21, [sp, #1128] // 8-byte Reload
-; CHECK1024-NEXT: ldr x22, [sp, #1120] // 8-byte Reload
-; CHECK1024-NEXT: ldr x23, [sp, #1112] // 8-byte Reload
-; CHECK1024-NEXT: ldr x24, [sp, #1104] // 8-byte Reload
-; CHECK1024-NEXT: ldr x25, [sp, #1096] // 8-byte Reload
-; CHECK1024-NEXT: ldr x29, [sp, #1088] // 8-byte Reload
; CHECK1024-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
; CHECK1024-NEXT: ldp d15, d14, [sp] // 16-byte Folded Reload
; CHECK1024-NEXT: add sp, sp, #1152
@@ -766,20 +760,17 @@ define i32 @csr_x18_25_d8_15_allocdi64_locallystreaming(i64 %d, double %e) "aarc
; CHECK1024-NEXT: sub sp, sp, #1168
; CHECK1024-NEXT: .cfi_def_cfa_offset 1168
; CHECK1024-NEXT: cntd x9
+; CHECK1024-NEXT: add x1, sp, #1104
; CHECK1024-NEXT: stp d15, d14, [sp] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
; CHECK1024-NEXT: str x29, [sp, #1088] // 8-byte Spill
; CHECK1024-NEXT: str x30, [sp, #1096] // 8-byte Spill
-; CHECK1024-NEXT: str x9, [sp, #1104] // 8-byte Spill
-; CHECK1024-NEXT: str x25, [sp, #1112] // 8-byte Spill
-; CHECK1024-NEXT: str x24, [sp, #1120] // 8-byte Spill
-; CHECK1024-NEXT: str x23, [sp, #1128] // 8-byte Spill
-; CHECK1024-NEXT: str x22, [sp, #1136] // 8-byte Spill
-; CHECK1024-NEXT: str x21, [sp, #1144] // 8-byte Spill
-; CHECK1024-NEXT: str x20, [sp, #1152] // 8-byte Spill
-; CHECK1024-NEXT: str x19, [sp, #1160] // 8-byte Spill
+; CHECK1024-NEXT: stp x9, x25, [x1] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x24, x23, [x1, #16] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x22, x21, [x1, #32] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x20, x19, [x1, #48] // 16-byte Folded Spill
; CHECK1024-NEXT: .cfi_offset w19, -8
; CHECK1024-NEXT: .cfi_offset w20, -16
; CHECK1024-NEXT: .cfi_offset w21, -24
@@ -813,17 +804,15 @@ define i32 @csr_x18_25_d8_15_allocdi64_locallystreaming(i64 %d, double %e) "aarc
; CHECK1024-NEXT: mov w0, wzr
; CHECK1024-NEXT: add sp, sp, #1056
; CHECK1024-NEXT: .cfi_def_cfa_offset 1168
+; CHECK1024-NEXT: add x2, sp, #1120
; CHECK1024-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
-; CHECK1024-NEXT: ldr x19, [sp, #1160] // 8-byte Reload
-; CHECK1024-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK1024-NEXT: ldr x20, [sp, #1152] // 8-byte Reload
-; CHECK1024-NEXT: ldr x21, [sp, #1144] // 8-byte Reload
-; CHECK1024-NEXT: ldr x22, [sp, #1136] // 8-byte Reload
-; CHECK1024-NEXT: ldr x23, [sp, #1128] // 8-byte Reload
-; CHECK1024-NEXT: ldr x24, [sp, #1120] // 8-byte Reload
+; CHECK1024-NEXT: ldp x20, x19, [x2, #32] // 16-byte Folded Reload
; CHECK1024-NEXT: ldr x25, [sp, #1112] // 8-byte Reload
+; CHECK1024-NEXT: ldp x22, x21, [x2, #16] // 16-byte Folded Reload
; CHECK1024-NEXT: ldr x30, [sp, #1096] // 8-byte Reload
; CHECK1024-NEXT: ldr x29, [sp, #1088] // 8-byte Reload
+; CHECK1024-NEXT: ldp x24, x23, [x2] // 16-byte Folded Reload
+; CHECK1024-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
; CHECK1024-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
; CHECK1024-NEXT: ldp d15, d14, [sp] // 16-byte Folded Reload
; CHECK1024-NEXT: add sp, sp, #1168
@@ -1531,14 +1520,11 @@ define i32 @svecc_csr_x18_25_d8_15_allocdi64(i64 %d, double %e, <vscale x 4 x i3
; CHECK1024-NOSPLITSVE-LABEL: svecc_csr_x18_25_d8_15_allocdi64:
; CHECK1024-NOSPLITSVE: // %bb.0: // %entry
; CHECK1024-NOSPLITSVE-NEXT: sub sp, sp, #1088
-; CHECK1024-NOSPLITSVE-NEXT: str x29, [sp, #1024] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x25, [sp, #1032] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x24, [sp, #1040] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x23, [sp, #1048] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x22, [sp, #1056] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x21, [sp, #1064] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x20, [sp, #1072] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x19, [sp, #1080] // 8-byte Spill
+; CHECK1024-NOSPLITSVE-NEXT: add x1, sp, #1024
+; CHECK1024-NOSPLITSVE-NEXT: stp x29, x25, [x1] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x24, x23, [x1, #16] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x22, x21, [x1, #32] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x20, x19, [x1, #48] // 16-byte Folded Spill
; CHECK1024-NOSPLITSVE-NEXT: addvl sp, sp, #-8
; CHECK1024-NOSPLITSVE-NEXT: str z15, [sp] // 16-byte Folded Spill
; CHECK1024-NOSPLITSVE-NEXT: str z14, [sp, #1, mul vl] // 16-byte Folded Spill
@@ -1584,14 +1570,11 @@ define i32 @svecc_csr_x18_25_d8_15_allocdi64(i64 %d, double %e, <vscale x 4 x i3
; CHECK1024-NOSPLITSVE-NEXT: ldr z9, [sp, #6, mul vl] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: ldr z8, [sp, #7, mul vl] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: addvl sp, sp, #8
-; CHECK1024-NOSPLITSVE-NEXT: ldr x19, [sp, #1080] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x20, [sp, #1072] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x21, [sp, #1064] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x22, [sp, #1056] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x23, [sp, #1048] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x24, [sp, #1040] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x25, [sp, #1032] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x29, [sp, #1024] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: add x2, sp, #1024
+; CHECK1024-NOSPLITSVE-NEXT: ldp x20, x19, [x2, #48] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x22, x21, [x2, #32] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x24, x23, [x2, #16] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x29, x25, [x2] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: add sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: ret
;
@@ -1857,18 +1840,16 @@ define i32 @f128_libcall(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32
; CHECK1024-NEXT: sub sp, sp, #1152
; CHECK1024-NEXT: .cfi_def_cfa_offset 1152
; CHECK1024-NEXT: cntd x9
+; CHECK1024-NEXT: add x2, sp, #1104
; CHECK1024-NEXT: stp d15, d14, [sp] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
; CHECK1024-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
; CHECK1024-NEXT: str x29, [sp, #1088] // 8-byte Spill
; CHECK1024-NEXT: str x30, [sp, #1096] // 8-byte Spill
-; CHECK1024-NEXT: str x9, [sp, #1104] // 8-byte Spill
-; CHECK1024-NEXT: str x28, [sp, #1112] // 8-byte Spill
-; CHECK1024-NEXT: str x22, [sp, #1120] // 8-byte Spill
-; CHECK1024-NEXT: str x21, [sp, #1128] // 8-byte Spill
-; CHECK1024-NEXT: str x20, [sp, #1136] // 8-byte Spill
-; CHECK1024-NEXT: str x19, [sp, #1144] // 8-byte Spill
+; CHECK1024-NEXT: stp x9, x28, [x2] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x22, x21, [x2, #16] // 16-byte Folded Spill
+; CHECK1024-NEXT: stp x20, x19, [x2, #32] // 16-byte Folded Spill
; CHECK1024-NEXT: .cfi_offset w19, -8
; CHECK1024-NEXT: .cfi_offset w20, -16
; CHECK1024-NEXT: .cfi_offset w21, -24
@@ -1915,15 +1896,13 @@ define i32 @f128_libcall(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32
; CHECK1024-NEXT: csel w0, w20, w19, mi
; CHECK1024-NEXT: add sp, sp, #1088
; CHECK1024-NEXT: .cfi_def_cfa_offset 1152
+; CHECK1024-NEXT: add x1, sp, #1088
; CHECK1024-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
+; CHECK1024-NEXT: ldp x21, x20, [x1, #40] // 16-byte Folded Reload
; CHECK1024-NEXT: ldr x19, [sp, #1144] // 8-byte Reload
+; CHECK1024-NEXT: ldp x28, x22, [x1, #24] // 16-byte Folded Reload
+; CHECK1024-NEXT: ldp x29, x30, [x1] // 16-byte Folded Reload
; CHECK1024-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
-; CHECK1024-NEXT: ldr x20, [sp, #1136] // 8-byte Reload
-; CHECK1024-NEXT: ldr x21, [sp, #1128] // 8-byte Reload
-; CHECK1024-NEXT: ldr x22, [sp, #1120] // 8-byte Reload
-; CHECK1024-NEXT: ldr x28, [sp, #1112] // 8-byte Reload
-; CHECK1024-NEXT: ldr x30, [sp, #1096] // 8-byte Reload
-; CHECK1024-NEXT: ldr x29, [sp, #1088] // 8-byte Reload
; CHECK1024-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
; CHECK1024-NEXT: ldp d15, d14, [sp] // 16-byte Folded Reload
; CHECK1024-NEXT: add sp, sp, #1152
@@ -2325,12 +2304,10 @@ define i32 @svecc_call(<4 x i16> %P0, ptr %P1, i32 %P2, <vscale x 16 x i8> %P3,
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore z14
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore z15
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa wsp, 1088
-; CHECK1024-NOSPLITSVE-NEXT: ldr x19, [sp, #1072] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x26, [sp, #1064] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x27, [sp, #1056] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x28, [sp, #1048] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x30, [sp, #1032] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x29, [sp, #1024] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: add x1, sp, #1024
+; CHECK1024-NOSPLITSVE-NEXT: ldp x26, x19, [x1, #40] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x28, x27, [x1, #24] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x29, x30, [x1] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: add sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa_offset 0
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore w19
@@ -2848,12 +2825,10 @@ define i32 @svecc_alloca_call(<4 x i16> %P0, ptr %P1, i32 %P2, <vscale x 16 x i8
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore z14
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore z15
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa wsp, 1088
-; CHECK1024-NOSPLITSVE-NEXT: ldr x19, [sp, #1072] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x26, [sp, #1064] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x27, [sp, #1056] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x28, [sp, #1048] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x30, [sp, #1032] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x29, [sp, #1024] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: add x1, sp, #1024
+; CHECK1024-NOSPLITSVE-NEXT: ldp x26, x19, [x1, #40] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x28, x27, [x1, #24] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x29, x30, [x1] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: add sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa_offset 0
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore w19
@@ -3795,14 +3770,12 @@ define i32 @svecc_call_dynamic_alloca(<4 x i16> %P0, i32 %P1, i32 %P2, <vscale x
; CHECK1024-NOSPLITSVE-NEXT: sub sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa_offset 1088
; CHECK1024-NOSPLITSVE-NEXT: cntd x9
+; CHECK1024-NOSPLITSVE-NEXT: add x2, sp, #1040
; CHECK1024-NOSPLITSVE-NEXT: str x29, [sp, #1024] // 8-byte Spill
; CHECK1024-NOSPLITSVE-NEXT: str x30, [sp, #1032] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x9, [sp, #1040] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x28, [sp, #1048] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x27, [sp, #1056] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x26, [sp, #1064] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x20, [sp, #1072] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x19, [sp, #1080] // 8-byte Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x9, x28, [x2] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x27, x26, [x2, #16] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x20, x19, [x2, #32] // 16-byte Folded Spill
; CHECK1024-NOSPLITSVE-NEXT: add x29, sp, #1024
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa w29, 64
; CHECK1024-NOSPLITSVE-NEXT: .cfi_offset w19, -8
@@ -3917,13 +3890,11 @@ define i32 @svecc_call_dynamic_alloca(<4 x i16> %P0, i32 %P1, i32 %P2, <vscale x
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore z15
; CHECK1024-NOSPLITSVE-NEXT: sub sp, x29, #1024
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa wsp, 1088
+; CHECK1024-NOSPLITSVE-NEXT: add x1, sp, #1024
; CHECK1024-NOSPLITSVE-NEXT: ldr x19, [sp, #1080] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x20, [sp, #1072] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x26, [sp, #1064] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x27, [sp, #1056] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x28, [sp, #1048] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x30, [sp, #1032] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x29, [sp, #1024] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x26, x20, [x1, #40] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x28, x27, [x1, #24] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x29, x30, [x1] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: add sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa_offset 0
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore w19
@@ -4458,12 +4429,10 @@ define i32 @svecc_call_realign(<4 x i16> %P0, i32 %P1, i32 %P2, <vscale x 16 x i
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore z15
; CHECK1024-NOSPLITSVE-NEXT: sub sp, x29, #1024
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa wsp, 1088
-; CHECK1024-NOSPLITSVE-NEXT: ldr x19, [sp, #1072] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x26, [sp, #1064] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x27, [sp, #1056] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x28, [sp, #1048] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x30, [sp, #1032] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x29, [sp, #1024] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: add x1, sp, #1024
+; CHECK1024-NOSPLITSVE-NEXT: ldp x26, x19, [x1, #40] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x28, x27, [x1, #24] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x29, x30, [x1] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: add sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: .cfi_def_cfa_offset 0
; CHECK1024-NOSPLITSVE-NEXT: .cfi_restore w19
@@ -4837,14 +4806,12 @@ define i32 @svecc_call_dynamic_and_scalable_alloca(<4 x i16> %P0, i32 %P1, i32 %
; CHECK1024-NOSPLITSVE-LABEL: svecc_call_dynamic_and_scalable_alloca:
; CHECK1024-NOSPLITSVE: // %bb.0: // %entry
; CHECK1024-NOSPLITSVE-NEXT: sub sp, sp, #1088
-; CHECK1024-NOSPLITSVE-NEXT: str x29, [sp, #1024] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: add x29, sp, #1024
-; CHECK1024-NOSPLITSVE-NEXT: str x30, [sp, #1032] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x28, [sp, #1040] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x27, [sp, #1048] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x26, [sp, #1056] // 8-byte Spill
-; CHECK1024-NOSPLITSVE-NEXT: str x20, [sp, #1064] // 8-byte Spill
+; CHECK1024-NOSPLITSVE-NEXT: add x1, sp, #1024
; CHECK1024-NOSPLITSVE-NEXT: str x19, [sp, #1072] // 8-byte Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x29, x30, [x1] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: add x29, sp, #1024
+; CHECK1024-NOSPLITSVE-NEXT: stp x28, x27, [x1, #16] // 16-byte Folded Spill
+; CHECK1024-NOSPLITSVE-NEXT: stp x26, x20, [x1, #32] // 16-byte Folded Spill
; CHECK1024-NOSPLITSVE-NEXT: addvl sp, sp, #-18
; CHECK1024-NOSPLITSVE-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill
; CHECK1024-NOSPLITSVE-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill
@@ -4942,13 +4909,11 @@ define i32 @svecc_call_dynamic_and_scalable_alloca(<4 x i16> %P0, i32 %P1, i32 %
; CHECK1024-NOSPLITSVE-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload
; CHECK1024-NOSPLITSVE-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload
; CHECK1024-NOSPLITSVE-NEXT: sub sp, x29, #1024
-; CHECK1024-NOSPLITSVE-NEXT: ldr x19, [sp, #1072] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x20, [sp, #1064] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x26, [sp, #1056] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x27, [sp, #1048] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x28, [sp, #1040] // 8-byte Reload
-; CHECK1024-NOSPLITSVE-NEXT: ldr x30, [sp, #1032] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: add x2, sp, #1032
; CHECK1024-NOSPLITSVE-NEXT: ldr x29, [sp, #1024] // 8-byte Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x20, x19, [x2, #32] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x27, x26, [x2, #16] // 16-byte Folded Reload
+; CHECK1024-NOSPLITSVE-NEXT: ldp x30, x28, [x2] // 16-byte Folded Reload
; CHECK1024-NOSPLITSVE-NEXT: add sp, sp, #1088
; CHECK1024-NOSPLITSVE-NEXT: ret
;
More information about the llvm-commits
mailing list