[llvm] [AArch64] Enable quad variant st1b/ld1b for callee-saved spills (PR #225100)

[Kieran B via llvm-commits]

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@@ -4,51 +4,46 @@
 define aarch64_sve_vector_pcs void @pair() nounwind {
 ; CHECK-LABEL: pair:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    addvl sp, sp, #-5
+; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    str p8, [sp] // 2-byte Spill
 ; CHECK-NEXT:    ptrue pn8.b
 ; CHECK-NEXT:    str z9, [sp, #1, mul vl] // 16-byte Folded Spill
 ; CHECK-NEXT:    st1b { z10.b, z11.b }, pn8, [sp, #2, mul vl] // 32-byte Folded Spill
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kieroxide wrote:

I forgot to update the test checks last commit. I confirmed this extra z11 in the test checks does not happen anymore for this case! I had to change the test to ensure quad/pair do generate. 

https://github.com/llvm/llvm-project/pull/225100