[llvm] [AArch64] Enable quad variant st1b/ld1b for callee-saved spills (PR #225100)

[Kieran B via llvm-commits]

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@@ -1847,74 +1901,85 @@ void computeCalleeSaveRegisterPairs(const AArch64FrameLowering &AFL,
     //
     // The order of the registers in the list is controlled by
     // getCalleeSavedRegs(), so they will always be in-order, as well.
-    assert((!RPI.isPaired() ||
+    assert((!RGI.isPaired() ||
             (CSI[i].getFrameIdx() + RegInc == CSI[i + RegInc].getFrameIdx())) &&
            "Out of order callee saved regs!");
 
-    assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg2 != AArch64::FP ||
-            RPI.Reg1 == AArch64::LR) &&
+    assert((!RGI.isQuad() ||
+            ((CSI[i].getFrameIdx() + RegInc == CSI[i + RegInc].getFrameIdx()) &&
+             (CSI[i + RegInc].getFrameIdx() + RegInc ==
+              CSI[i + RegInc * 2].getFrameIdx()) &&
+             (CSI[i + RegInc * 2].getFrameIdx() + RegInc ==
+              CSI[i + RegInc * 3].getFrameIdx()))) &&
+           "Out of order callee saved regs!");
+
+    assert((!RGI.isQuad() || RGI.Type == RegGroupInfo::ZPR) &&
+           "Currently only ZPR's support four-register spills");
+
+    assert((!RGI.isPaired() || !NeedsFrameRecord || RGI.Reg2 != AArch64::FP ||
+            RGI.Reg1 == AArch64::LR) &&
            "FrameRecord must be allocated together with LR");
 
     // Windows AAPCS has FP and LR reversed.
-    assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg1 != AArch64::FP ||
-            RPI.Reg2 == AArch64::LR) &&
+    assert((!RGI.isPaired() || !NeedsFrameRecord || RGI.Reg1 != AArch64::FP ||
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kieroxide wrote:

Yes, I have done this now and added that method. 

https://github.com/llvm/llvm-project/pull/225100