[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)

[Jay Foad via llvm-commits]

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@@ -1514,21 +1514,21 @@ bool SIFoldOperandsImpl::foldOperand(
       //
       // Excerpt from AMDGPUGenRegisterInfoEnums.inc
       // NoSubRegister, //0
-      // hi16, // 1
-      // lo16, // 2
+      // lo16, // 1
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jayfoad wrote:

#226082 should remove the need for any changes in this file.

https://github.com/llvm/llvm-project/pull/225809