[llvm] [NVPTX][TTI] Fix v4i8 scalarization cost (PR #226071)

[via llvm-commits]

https://github.com/wenhu1024 created https://github.com/llvm/llvm-project/pull/226071

Handle v4i8 before the generic packed 32-bit vector case so its dedicated scalarization cost is reachable. Accumulate the cost in the outer variable and add a cost-model regression test.

>From 27945fbbd937b40a97889985ba9f86f5e8b0cf63 Mon Sep 17 00:00:00 2001
From: wenhu1024 <1340773297 at qq.com>
Date: Thu, 24 Sep 2026 16:40:47 +0800
Subject: [PATCH] [NVPTX][TTI] Fix v4i8 scalarization cost

Handle v4i8 before the generic packed 32-bit vector case so its dedicated scalarization cost is reachable. Accumulate the cost in the outer variable and add a cost-model regression test.
---
 .../lib/Target/NVPTX/NVPTXTargetTransformInfo.h | 14 +++++++-------
 .../CostModel/NVPTX/v4i8-scalarization.ll       | 17 +++++++++++++++++
 2 files changed, 24 insertions(+), 7 deletions(-)
 create mode 100644 llvm/test/Analysis/CostModel/NVPTX/v4i8-scalarization.ll

diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
index c6313a5a0fb518..1d1b5bdebd7e17 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
@@ -151,18 +151,18 @@ class NVPTXTTIImpl final : public BasicTTIImplBase<NVPTXTTIImpl> {
         Insert = false;
       }
     }
-    if (Insert && NVPTX::isPackedVectorTy(VT) && VT.is32BitVector()) {
-      // Can be built in a single 32-bit mov (64-bit regs are emulated in SASS
-      // with 2x 32-bit regs)
-      Cost += 1;
-      Insert = false;
-    }
     if (Insert && VT == MVT::v4i8) {
-      InstructionCost Cost = 3; // 3 x PRMT
+      Cost += 3; // 3 x PRMT
       for (auto Idx : seq(NumElements))
         if (DemandedElts[Idx])
           Cost += 1; // zext operand to i32
       Insert = false;
+    } else if (Insert && NVPTX::isPackedVectorTy(VT) &&
+               VT.is32BitVector()) {
+      // Can be built in a single 32-bit mov (64-bit regs are emulated in SASS
+      // with 2x 32-bit regs)
+      Cost += 1;
+      Insert = false;
     }
     return Cost + BaseT::getScalarizationOverhead(InTy, DemandedElts, Insert,
                                                   Extract, CostKind,
diff --git a/llvm/test/Analysis/CostModel/NVPTX/v4i8-scalarization.ll b/llvm/test/Analysis/CostModel/NVPTX/v4i8-scalarization.ll
new file mode 100644
index 00000000000000..c557ea96a017fe
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/NVPTX/v4i8-scalarization.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt -passes="print<cost-model>" -disable-output < %s 2>&1 | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+; ADD is expanded for v4i8, so BasicTTI includes getScalarizationOverhead() in
+; its cost. The total is four scalar adds, four extracts, and seven to construct
+; the result (three PRMTs and four extensions). The construction was previously
+; miscosted as one, resulting in a total cost of nine.
+define <4 x i8> @scalarized_add_v4i8(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: 'scalarized_add_v4i8'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %add = add <4 x i8> %x, %y
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i8> %add
+;
+  %add = add <4 x i8> %x, %y
+  ret <4 x i8> %add
+}