[llvm] [AMDGPU] Split wide constant address space stores (PR #226069)

[Keshav Vinayak Jha via llvm-commits]

https://github.com/keshavvinayak01 created https://github.com/llvm/llvm-project/pull/226069

Wide stores to addrspace(4) can reach AMDGPU SelectionDAG instruction selection without being split, causing `Cannot select` on a 256-bit store. Include AS4 in the existing global/flat wide-store split so the resulting 128-bit stores use the global-store patterns added by llvm/llvm-project#153835.

The reproducer came from fuzzer-generated IR where the AS4 store is undefined behavior. This change prevents the codegen crash without defining that store's runtime behavior.

Tests: `llc -O0 -global-isel=false` on gfx90a and gfx1201; the original bitcode now compiles.


>From 8189ff8b57a45bf6cac2cd932074d53a2bc0bdf7 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Thu, 24 Sep 2026 08:19:15 +0000
Subject: [PATCH] [AMDGPU] Split wide constant address space stores

Co-authored-by: GPT-5 <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp          |  3 ++-
 llvm/test/CodeGen/AMDGPU/store-to-constant-wide.ll | 11 +++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/store-to-constant-wide.ll

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e47dd0e788796..676294053975b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -14287,7 +14287,8 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
              : AMDGPUAS::GLOBAL_ADDRESS;
 
   unsigned NumElements = VT.getVectorNumElements();
-  if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
+  if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::CONSTANT_ADDRESS ||
+      AS == AMDGPUAS::FLAT_ADDRESS) {
     if (NumElements > 4)
       return SplitVectorStore(Op, DAG);
     // v3 stores not supported on SI.
diff --git a/llvm/test/CodeGen/AMDGPU/store-to-constant-wide.ll b/llvm/test/CodeGen/AMDGPU/store-to-constant-wide.ll
new file mode 100644
index 0000000000000..26cc3eb5943cb
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/store-to-constant-wide.ll
@@ -0,0 +1,11 @@
+; RUN: llc -O0 -global-isel=false -mtriple=amdgpu9.0a-amd-amdhsa %s -o - | FileCheck %s --check-prefix=GFX90A
+; RUN: llc -O0 -global-isel=false -mtriple=amdgpu12.01-amd-amdhsa %s -o - | FileCheck %s --check-prefix=GFX12
+
+define amdgpu_kernel void @store_as4_v4i64(ptr addrspace(4) %dst, <4 x i64> %value) {
+; GFX90A-LABEL: store_as4_v4i64:
+; GFX90A-COUNT-2: global_store_dwordx4
+; GFX12-LABEL: store_as4_v4i64:
+; GFX12-COUNT-2: global_store_b128
+  store <4 x i64> %value, ptr addrspace(4) %dst, align 32
+  ret void
+}