[llvm] [LoongArch] Add scheduler definitions for LoongArch with schedule model for LA464/LA664 (PR #226064)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 01:15:28 PDT 2026
https://github.com/lrzlin created https://github.com/llvm/llvm-project/pull/226064
This patch adds full scheduler definitions for LoongArch backend and schedule models for LA464/LA664, covering basic instructions and LSX/LASX SIMD instructions, along with a series of `llvm-mca` tests.
The model are base on a Chip and Cheese microarchitecture analysis article, [Loongson 3A6000: A Star among Chinese CPUs](https://chipsandcheese.com/p/loongson-3a6000-a-star-among-chinese-cpus/), which has a detailed analysis for LA464/LA664 microarchitecture. The latency/throughput numbers were measured from actual machine, so many of them depend on estimate.
`PostRAScheduler` was not set because we found that it will cause regression on SPEC CPU2006 470.lbm testcase. `MispredictPenalty` is also based on a raw guess. Besides, even if `LoopMicroOpBufferSize` will have a positive impact on performance due to loop unrolling, these microarchitecture details is still unknown, so I would perfer override the `getUnrollingPreferences` in future TTI patches, or waiting for more informations about this.
For the performance metrics, we run SPEC CPU2006 with `-mtune=la664 -O3 -mlsx` on a Loongson 3B6000, which has 16 LA664 cores running on 2.1GHz, here are the results.
## CINT2006
| benchmark | sched time (s) | nosched time (s) | sched ratio | nosched ratio | delta |
|---|---:|---:|---:|---:|---:|
| 400.perlbench | 358 | 374 | 27.3 | 26.1 | **+4.6 %** |
| 401.bzip2 | 521 | 519 | 18.5 | 18.6 | -0.5 % |
| 403.gcc | 314 | 315 | 25.6 | 25.5 | +0.4 % |
| 429.mcf | 256 | 254 | 35.6 | 35.9 | -0.8 % |
| 445.gobmk | 461 | 464 | 22.8 | 22.6 | +0.9 % |
| 456.hmmer | 456 | 456 | 20.5 | 20.5 | +0.0 % |
| 458.sjeng | 512 | 515 | 23.6 | 23.5 | +0.4 % |
| 462.libquantum | 630 | 642 | 32.9 | 32.3 | **+1.9 %** |
| 464.h264ref | 597 | 598 | 37.1 | 37.0 | +0.3 % |
| 471.omnetpp | 178 | 180 | 35.0 | 34.7 | +0.9 % |
| 473.astar | 365 | 363 | 19.3 | 19.4 | -0.5 % |
| 483.xalancbmk | 219 | 218 | 31.5 | 31.6 | -0.3 % |
| **SPECint_base2006** | | | **26.7** | **26.6** | **+0.58 %** |
## CFP2006
| benchmark | sched time (s) | nosched time (s) | sched ratio | nosched ratio | delta |
|---|---:|---:|---:|---:|---:|
| 410.bwaves | 341 | 343 | 39.9 | 39.7 | +0.5 % |
| 416.gamess | 605 | 613 | 32.4 | 31.9 | **+1.6 %** |
| 433.milc | 362 | 361 | 25.3 | 25.5 | -0.8 % |
| 434.zeusmp | 257 | 257 | 35.4 | 35.4 | +0.0 % |
| 435.gromacs | 467 | 469 | 15.3 | 15.2 | +0.7 % |
| 436.cactusADM | 206 | 205 | 58.0 | 58.3 | -0.5 % |
| 437.leslie3d | 269 | 278 | 35.0 | 33.8 | **+3.6 %** |
| 444.namd | 342 | 351 | 23.5 | 22.8 | **+3.1 %** |
| 447.dealII | 317 | 314 | 36.1 | 36.4 | -0.8 % |
| 450.soplex | 237 | 279 | 35.2 | 29.9 | **+17.7 %** |
| 453.povray | 153 | 154 | 34.8 | 34.6 | +0.6 % |
| 454.calculix | 912 | 907 | 9.1 | 9.1 | -0.5 % |
| 459.GemsFDTD | 323 | 321 | 32.8 | 33.1 | -0.9 % |
| 465.tonto | 312 | 313 | 31.5 | 31.5 | +0.0 % |
| 470.lbm | 305 | 304 | 45.1 | 45.2 | -0.2 % |
| 481.wrf | 237 | 237 | 47.2 | 47.2 | +0.0 % |
| 482.sphinx3 | 561 | 551 | 34.7 | 35.4 | **-2.0 %** |
| **SPECfp_base2006** | | | **31.2** | **30.9** | **+1.20 %** |
The SPEC CPU2006 results show a slightly improment on both CINT and CFP, consider it introducing possibilities for optimization passes like `MachineCombiner` and `EarlyIfConvertion`, the performance could futher improve IMO.
>From bc94bf5861908e64b93b93fd13b4165f1272ba71 Mon Sep 17 00:00:00 2001
From: Lin Runze <lrzlin at 163.com>
Date: Fri, 10 Jul 2026 15:30:22 +0800
Subject: [PATCH] [LoongArch] Add scheduler definitions for LoongArch with
schedule model for LA464/LA664
---
llvm/lib/Target/LoongArch/LoongArch.td | 14 +-
.../LoongArch/LoongArchFloat32InstrInfo.td | 231 +-
.../LoongArch/LoongArchFloat64InstrInfo.td | 247 +-
.../Target/LoongArch/LoongArchInstrInfo.td | 561 ++--
.../LoongArch/LoongArchLASXInstrInfo.td | 2292 +++++++++++------
.../Target/LoongArch/LoongArchLSXInstrInfo.td | 2202 ++++++++++------
.../Target/LoongArch/LoongArchSchedLA464.td | 1080 ++++++++
.../Target/LoongArch/LoongArchSchedLA664.td | 1138 ++++++++
.../lib/Target/LoongArch/LoongArchSchedule.td | 520 ++++
.../Target/LoongArch/LoongArchScheduleV.td | 1291 ++++++++++
.../LoongArch/Inputs/floating-point.s | 27 +
.../tools/llvm-mca/LoongArch/Inputs/integer.s | 22 +
.../tools/llvm-mca/LoongArch/Inputs/lasx.s | 27 +
.../tools/llvm-mca/LoongArch/Inputs/lsx.s | 41 +
.../tools/llvm-mca/LoongArch/Inputs/memory.s | 22 +
.../tools/llvm-mca/LoongArch/Inputs/mul-div.s | 9 +
.../LoongArch/LA464/floating-point.test | 88 +
.../llvm-mca/LoongArch/LA464/integer.test | 78 +
.../tools/llvm-mca/LoongArch/LA464/lasx.test | 88 +
.../tools/llvm-mca/LoongArch/LA464/lsx.test | 116 +
.../llvm-mca/LoongArch/LA464/memory.test | 78 +
.../llvm-mca/LoongArch/LA464/mul-div.test | 52 +
.../LoongArch/LA664/floating-point.test | 93 +
.../llvm-mca/LoongArch/LA664/integer.test | 83 +
.../tools/llvm-mca/LoongArch/LA664/lasx.test | 93 +
.../tools/llvm-mca/LoongArch/LA664/lsx.test | 121 +
.../llvm-mca/LoongArch/LA664/memory.test | 83 +
.../llvm-mca/LoongArch/LA664/mul-div.test | 57 +
.../tools/llvm-mca/LoongArch/lit.local.cfg | 2 +
29 files changed, 8743 insertions(+), 2013 deletions(-)
create mode 100644 llvm/lib/Target/LoongArch/LoongArchSchedLA464.td
create mode 100644 llvm/lib/Target/LoongArch/LoongArchSchedLA664.td
create mode 100644 llvm/lib/Target/LoongArch/LoongArchSchedule.td
create mode 100644 llvm/lib/Target/LoongArch/LoongArchScheduleV.td
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/Inputs/floating-point.s
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/Inputs/integer.s
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/Inputs/lasx.s
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/Inputs/lsx.s
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/Inputs/memory.s
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/Inputs/mul-div.s
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA464/floating-point.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA464/integer.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA464/lasx.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA464/lsx.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA464/memory.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA464/mul-div.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA664/floating-point.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA664/integer.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA664/lasx.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA664/lsx.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA664/memory.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/LA664/mul-div.test
create mode 100644 llvm/test/tools/llvm-mca/LoongArch/lit.local.cfg
diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td
index 577dcbed48eea..0514e36a96563 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.td
+++ b/llvm/lib/Target/LoongArch/LoongArch.td
@@ -155,13 +155,21 @@ def TunePreferWInst
"Prefer instructions with W suffix">;
//===----------------------------------------------------------------------===//
-// Registers, instruction descriptions ...
+// Schedule, Registers, instruction descriptions ...
//===----------------------------------------------------------------------===//
+include "LoongArchSchedule.td"
include "LoongArchRegisterInfo.td"
include "LoongArchCallingConv.td"
include "LoongArchInstrInfo.td"
+//===----------------------------------------------------------------------===//
+// LoongArch Scheduling Models.
+//===----------------------------------------------------------------------===//
+
+include "LoongArchSchedLA464.td"
+include "LoongArchSchedLA664.td"
+
//===----------------------------------------------------------------------===//
// LoongArch processors supported.
//===----------------------------------------------------------------------===//
@@ -183,13 +191,13 @@ def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit,
// to change to the appropriate la32/la64 version.
def : ProcessorModel<"generic", NoSchedModel, []>;
-def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
+def : ProcessorModel<"la464", LA464Model, [Feature64Bit,
FeatureUAL,
FeatureExtLASX,
FeatureExtLVZ,
FeatureExtLBT]>;
-def : ProcessorModel<"la664", NoSchedModel, [Feature64Bit,
+def : ProcessorModel<"la664", LA664Model, [Feature64Bit,
FeatureUAL,
FeatureExtLASX,
FeatureExtLVZ,
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
index 27d5fa1fab62a..3c5635942ca8c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
@@ -54,112 +54,189 @@ def loongarch_sitof : SDNode<"LoongArchISD::SITOF", SDT_LoongArchITOF>;
let Predicates = [HasBasicF] in {
// Arithmetic Operation Instructions
-def FADD_S : FP_ALU_3R<0x01008000>;
-def FSUB_S : FP_ALU_3R<0x01028000>;
-def FMUL_S : FP_ALU_3R<0x01048000>;
-def FDIV_S : FP_ALU_3R<0x01068000>;
-def FMADD_S : FP_ALU_4R<0x08100000>;
-def FMSUB_S : FP_ALU_4R<0x08500000>;
-def FNMADD_S : FP_ALU_4R<0x08900000>;
-def FNMSUB_S : FP_ALU_4R<0x08d00000>;
-def FMAX_S : FP_ALU_3R<0x01088000>;
-def FMIN_S : FP_ALU_3R<0x010a8000>;
-def FMAXA_S : FP_ALU_3R<0x010c8000>;
-def FMINA_S : FP_ALU_3R<0x010e8000>;
-def FABS_S : FP_ALU_2R<0x01140400>;
-def FNEG_S : FP_ALU_2R<0x01141400>;
-def FSQRT_S : FP_ALU_2R<0x01144400>;
-def FRECIP_S : FP_ALU_2R<0x01145400>;
-def FRSQRT_S : FP_ALU_2R<0x01146400>;
-def FRECIPE_S : FP_ALU_2R<0x01147400>;
-def FRSQRTE_S : FP_ALU_2R<0x01148400>;
-def FSCALEB_S : FP_ALU_3R<0x01108000>;
-def FLOGB_S : FP_ALU_2R<0x01142400>;
-def FCOPYSIGN_S : FP_ALU_3R<0x01128000>;
-def FCLASS_S : FP_ALU_2R<0x01143400>;
+def FADD_S : FP_ALU_3R<0x01008000>,
+ Sched<[WriteFADD, ReadFADD, ReadFADD]>;
+def FSUB_S : FP_ALU_3R<0x01028000>,
+ Sched<[WriteFADD, ReadFADD, ReadFADD]>;
+def FMUL_S : FP_ALU_3R<0x01048000>,
+ Sched<[WriteFMUL, ReadFMUL, ReadFMUL]>;
+def FDIV_S : FP_ALU_3R<0x01068000>,
+ Sched<[WriteFDIV32, ReadFDIV32, ReadFDIV32]>;
+def FMADD_S : FP_ALU_4R<0x08100000>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FMSUB_S : FP_ALU_4R<0x08500000>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FNMADD_S : FP_ALU_4R<0x08900000>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FNMSUB_S : FP_ALU_4R<0x08d00000>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FMAX_S : FP_ALU_3R<0x01088000>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FMIN_S : FP_ALU_3R<0x010a8000>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FMAXA_S : FP_ALU_3R<0x010c8000>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FMINA_S : FP_ALU_3R<0x010e8000>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FABS_S : FP_ALU_2R<0x01140400>,
+ Sched<[WriteFABS, ReadFABS]>;
+def FNEG_S : FP_ALU_2R<0x01141400>,
+ Sched<[WriteFNEG, ReadFNEG]>;
+def FSQRT_S : FP_ALU_2R<0x01144400>,
+ Sched<[WriteFSQRT32, ReadFSQRT32]>;
+def FRECIP_S : FP_ALU_2R<0x01145400>,
+ Sched<[WriteFRECIP32, ReadFRECIP32]>;
+def FRSQRT_S : FP_ALU_2R<0x01146400>,
+ Sched<[WriteFRSQRT32, ReadFRSQRT32]>;
+def FRECIPE_S : FP_ALU_2R<0x01147400>,
+ Sched<[WriteFRECIPE, ReadFRECIPE]>;
+def FRSQRTE_S : FP_ALU_2R<0x01148400>,
+ Sched<[WriteFRSQRTE, ReadFRSQRTE]>;
+def FSCALEB_S : FP_ALU_3R<0x01108000>,
+ Sched<[WriteFSCALEB, ReadFSCALEB, ReadFSCALEB]>;
+def FLOGB_S : FP_ALU_2R<0x01142400>,
+ Sched<[WriteFLOGB, ReadFLOGB]>;
+def FCOPYSIGN_S : FP_ALU_3R<0x01128000>,
+ Sched<[WriteFCOPYSIGN, ReadFCOPYSIGN, ReadFCOPYSIGN]>;
+def FCLASS_S : FP_ALU_2R<0x01143400>,
+ Sched<[WriteFCLASS, ReadFCLASS]>;
// Comparison Instructions
-def FCMP_CAF_S : FP_CMP<0x0c100000>;
-def FCMP_CUN_S : FP_CMP<0x0c140000>;
-def FCMP_CEQ_S : FP_CMP<0x0c120000>;
-def FCMP_CUEQ_S : FP_CMP<0x0c160000>;
-def FCMP_CLT_S : FP_CMP<0x0c110000>;
-def FCMP_CULT_S : FP_CMP<0x0c150000>;
-def FCMP_CLE_S : FP_CMP<0x0c130000>;
-def FCMP_CULE_S : FP_CMP<0x0c170000>;
-def FCMP_CNE_S : FP_CMP<0x0c180000>;
-def FCMP_COR_S : FP_CMP<0x0c1a0000>;
-def FCMP_CUNE_S : FP_CMP<0x0c1c0000>;
-def FCMP_SAF_S : FP_CMP<0x0c108000>;
-def FCMP_SUN_S : FP_CMP<0x0c148000>;
-def FCMP_SEQ_S : FP_CMP<0x0c128000>;
-def FCMP_SUEQ_S : FP_CMP<0x0c168000>;
-def FCMP_SLT_S : FP_CMP<0x0c118000>;
-def FCMP_SULT_S : FP_CMP<0x0c158000>;
-def FCMP_SLE_S : FP_CMP<0x0c138000>;
-def FCMP_SULE_S : FP_CMP<0x0c178000>;
-def FCMP_SNE_S : FP_CMP<0x0c188000>;
-def FCMP_SOR_S : FP_CMP<0x0c1a8000>;
-def FCMP_SUNE_S : FP_CMP<0x0c1c8000>;
+def FCMP_CAF_S : FP_CMP<0x0c100000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CUN_S : FP_CMP<0x0c140000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CEQ_S : FP_CMP<0x0c120000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CUEQ_S : FP_CMP<0x0c160000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CLT_S : FP_CMP<0x0c110000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CULT_S : FP_CMP<0x0c150000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CLE_S : FP_CMP<0x0c130000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CULE_S : FP_CMP<0x0c170000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CNE_S : FP_CMP<0x0c180000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_COR_S : FP_CMP<0x0c1a0000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CUNE_S : FP_CMP<0x0c1c0000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SAF_S : FP_CMP<0x0c108000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SUN_S : FP_CMP<0x0c148000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SEQ_S : FP_CMP<0x0c128000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SUEQ_S : FP_CMP<0x0c168000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SLT_S : FP_CMP<0x0c118000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SULT_S : FP_CMP<0x0c158000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SLE_S : FP_CMP<0x0c138000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SULE_S : FP_CMP<0x0c178000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SNE_S : FP_CMP<0x0c188000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SOR_S : FP_CMP<0x0c1a8000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SUNE_S : FP_CMP<0x0c1c8000>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
// Conversion Instructions
-def FFINT_S_W : FP_CONV<0x011d1000>;
-def FTINT_W_S : FP_CONV<0x011b0400>;
-def FTINTRM_W_S : FP_CONV<0x011a0400>;
-def FTINTRP_W_S : FP_CONV<0x011a4400>;
-def FTINTRZ_W_S : FP_CONV<0x011a8400>;
-def FTINTRNE_W_S : FP_CONV<0x011ac400>;
-def FRINT_S : FP_CONV<0x011e4400>;
+def FFINT_S_W : FP_CONV<0x011d1000>,
+ Sched<[WriteFCvtStoW, ReadFCvtStoW]>;
+def FTINT_W_S : FP_CONV<0x011b0400>,
+ Sched<[WriteFCvtWtoS, ReadFCvtWtoS]>;
+def FTINTRM_W_S : FP_CONV<0x011a0400>,
+ Sched<[WriteFCvtWtoS_RM, ReadFCvtWtoS_RM]>;
+def FTINTRP_W_S : FP_CONV<0x011a4400>,
+ Sched<[WriteFCvtWtoS_RP, ReadFCvtWtoS_RP]>;
+def FTINTRZ_W_S : FP_CONV<0x011a8400>,
+ Sched<[WriteFCvtWtoS_RZ, ReadFCvtWtoS_RZ]>;
+def FTINTRNE_W_S : FP_CONV<0x011ac400>,
+ Sched<[WriteFCvtWtoS_RNE, ReadFCvtWtoS_RNE]>;
+def FRINT_S : FP_CONV<0x011e4400>,
+ Sched<[WriteFCvtFStoIS, ReadFCvtFStoIS]>;
// Move Instructions
-def FSEL_xS : FP_SEL<0x0d000000>;
-def FMOV_S : FP_MOV<0x01149400>;
-def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>;
-def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>;
+def FSEL_xS : FP_SEL<0x0d000000>,
+ Sched<[WriteFSEL, ReadFSEL, ReadFSEL, ReadFSEL]>;
+def FMOV_S : FP_MOV<0x01149400>,
+ Sched<[WriteFMovS, ReadFMovS]>;
+def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>,
+ Sched<[WriteFMovGRtoFRW, ReadFMovGRtoFRW]>;
+def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>,
+ Sched<[WriteFMovFRtoGRS, ReadFMovFRtoGRS]>;
let hasSideEffects = 1 in {
-def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>;
-def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>;
+def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>,
+ Sched<[WriteFMovGRtoFCSR, ReadFMovGRtoFCSR]>;
+def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>,
+ Sched<[WriteFMovFCSRtoGR, ReadFMovFCSRtoGR]>;
} // hasSideEffects = 1
-def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>;
-def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>;
-def MOVGR2CF : FP_MOV<0x0114d800, CFR, GPR>;
-def MOVCF2GR : FP_MOV<0x0114dc00, GPR, CFR>;
+def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>,
+ Sched<[WriteFMoveFRtoCF, ReadFMoveFRtoCF]>;
+def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>,
+ Sched<[WriteFMoveCFtoFR, ReadFMoveCFtoFR]>;
+def MOVGR2CF : FP_MOV<0x0114d800, CFR, GPR>,
+ Sched<[WriteFMoveGRtoCF, ReadFMoveGRtoCF]>;
+def MOVCF2GR : FP_MOV<0x0114dc00, GPR, CFR>,
+ Sched<[WriteFMoveCFtoGR, ReadFMoveCFtoGR]>;
// Branch Instructions
-def BCEQZ : FP_BRANCH<0x48000000>;
-def BCNEZ : FP_BRANCH<0x48000100>;
+def BCEQZ : FP_BRANCH<0x48000000>,
+ Sched<[WriteFJump, ReadFJump]>;
+def BCNEZ : FP_BRANCH<0x48000100>,
+ Sched<[WriteFJump, ReadFJump]>;
// Common Memory Access Instructions
-def FLD_S : FP_LOAD_2RI12<0x2b000000>;
-def FST_S : FP_STORE_2RI12<0x2b400000>;
-def FLDX_S : FP_LOAD_3R<0x38300000>;
-def FSTX_S : FP_STORE_3R<0x38380000>;
+def FLD_S : FP_LOAD_2RI12<0x2b000000>,
+ Sched<[WriteFLD, ReadFMemBase]>;
+def FST_S : FP_STORE_2RI12<0x2b400000>,
+ Sched<[WriteFST, ReadFSTData, ReadFMemBase]>;
+def FLDX_S : FP_LOAD_3R<0x38300000>,
+ Sched<[WriteFLDX, ReadFMemBase, ReadFMemOffset]>;
+def FSTX_S : FP_STORE_3R<0x38380000>,
+ Sched<[WriteFSTX, ReadFSTData, ReadFMemBase, ReadFMemOffset]>;
// Bound Check Memory Access Instructions
-def FLDGT_S : FP_LOAD_3R<0x38740000>;
-def FLDLE_S : FP_LOAD_3R<0x38750000>;
-def FSTGT_S : FP_STORE_3R<0x38760000>;
-def FSTLE_S : FP_STORE_3R<0x38770000>;
+def FLDGT_S : FP_LOAD_3R<0x38740000>,
+ Sched<[WriteFLDGT, ReadFMemBase, ReadFMemCmp]>;
+def FLDLE_S : FP_LOAD_3R<0x38750000>,
+ Sched<[WriteFLDLE, ReadFMemBase, ReadFMemCmp]>;
+def FSTGT_S : FP_STORE_3R<0x38760000>,
+ Sched<[WriteFSTGT, ReadFSTData, ReadFMemBase, ReadFMemCmp]>;
+def FSTLE_S : FP_STORE_3R<0x38770000>,
+ Sched<[WriteFSTLE, ReadFSTData, ReadFMemBase, ReadFMemCmp]>;
// Pseudo instructions for spill/reload CFRs.
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
def PseudoST_CFR : Pseudo<(outs),
- (ins CFR:$ccd, GPR:$rj, grlenimm:$imm)>;
+ (ins CFR:$ccd, GPR:$rj, grlenimm:$imm)>,
+ Sched<[WritePseudo, ReadPseudo, ReadPseudo]>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
def PseudoLD_CFR : Pseudo<(outs CFR:$ccd),
- (ins GPR:$rj, grlenimm:$imm)>;
+ (ins GPR:$rj, grlenimm:$imm)>,
+ Sched<[WritePseudo, ReadPseudo]>;
// SET_CFR_{FALSE,TRUE}
// These instructions are defined in order to avoid expensive check error if
// regular instruction patterns are used.
// fcmp.caf.s $dst, $fa0, $fa0
-def SET_CFR_FALSE : SET_CFR<0x0c100000, "fcmp.caf.s">;
+def SET_CFR_FALSE : SET_CFR<0x0c100000, "fcmp.caf.s">,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
// fcmp.cueq.s $dst, $fa0, $fa0
-def SET_CFR_TRUE : SET_CFR<0x0c160000, "fcmp.cueq.s">;
+def SET_CFR_TRUE : SET_CFR<0x0c160000, "fcmp.cueq.s">,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
// Pseudo instruction for copying CFRs.
-def PseudoCopyCFR : Pseudo<(outs CFR:$dst), (ins CFR:$src)> {
+def PseudoCopyCFR : Pseudo<(outs CFR:$dst), (ins CFR:$src)>,
+ Sched<[WritePseudo, ReadPseudo]> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
index 6eb9398b4d34a..398884397469f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
@@ -33,113 +33,196 @@ def loongarch_movgr2fr_d_lo_hi
let Predicates = [HasBasicD] in {
// Arithmetic Operation Instructions
-def FADD_D : FP_ALU_3R<0x01010000, FPR64>;
-def FSUB_D : FP_ALU_3R<0x01030000, FPR64>;
-def FMUL_D : FP_ALU_3R<0x01050000, FPR64>;
-def FDIV_D : FP_ALU_3R<0x01070000, FPR64>;
-def FMADD_D : FP_ALU_4R<0x08200000, FPR64>;
-def FMSUB_D : FP_ALU_4R<0x08600000, FPR64>;
-def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>;
-def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>;
-def FMAX_D : FP_ALU_3R<0x01090000, FPR64>;
-def FMIN_D : FP_ALU_3R<0x010b0000, FPR64>;
-def FMAXA_D : FP_ALU_3R<0x010d0000, FPR64>;
-def FMINA_D : FP_ALU_3R<0x010f0000, FPR64>;
-def FABS_D : FP_ALU_2R<0x01140800, FPR64>;
-def FNEG_D : FP_ALU_2R<0x01141800, FPR64>;
-def FSQRT_D : FP_ALU_2R<0x01144800, FPR64>;
-def FRECIP_D : FP_ALU_2R<0x01145800, FPR64>;
-def FRSQRT_D : FP_ALU_2R<0x01146800, FPR64>;
-def FRECIPE_D : FP_ALU_2R<0x01147800, FPR64>;
-def FRSQRTE_D : FP_ALU_2R<0x01148800, FPR64>;
-def FSCALEB_D : FP_ALU_3R<0x01110000, FPR64>;
-def FLOGB_D : FP_ALU_2R<0x01142800, FPR64>;
-def FCOPYSIGN_D : FP_ALU_3R<0x01130000, FPR64>;
-def FCLASS_D : FP_ALU_2R<0x01143800, FPR64>;
+def FADD_D : FP_ALU_3R<0x01010000, FPR64>,
+ Sched<[WriteFADD, ReadFADD, ReadFADD]>;
+def FSUB_D : FP_ALU_3R<0x01030000, FPR64>,
+ Sched<[WriteFADD, ReadFADD, ReadFADD]>;
+def FMUL_D : FP_ALU_3R<0x01050000, FPR64>,
+ Sched<[WriteFMUL, ReadFMUL, ReadFMUL]>;
+def FDIV_D : FP_ALU_3R<0x01070000, FPR64>,
+ Sched<[WriteFDIV, ReadFDIV, ReadFDIV]>;
+def FMADD_D : FP_ALU_4R<0x08200000, FPR64>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FMSUB_D : FP_ALU_4R<0x08600000, FPR64>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>,
+ Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>;
+def FMAX_D : FP_ALU_3R<0x01090000, FPR64>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FMIN_D : FP_ALU_3R<0x010b0000, FPR64>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FMAXA_D : FP_ALU_3R<0x010d0000, FPR64>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FMINA_D : FP_ALU_3R<0x010f0000, FPR64>,
+ Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>;
+def FABS_D : FP_ALU_2R<0x01140800, FPR64>,
+ Sched<[WriteFABS, ReadFABS]>;
+def FNEG_D : FP_ALU_2R<0x01141800, FPR64>,
+ Sched<[WriteFNEG, ReadFNEG]>;
+def FSQRT_D : FP_ALU_2R<0x01144800, FPR64>,
+ Sched<[WriteFSQRT, ReadFSQRT]>;
+def FRECIP_D : FP_ALU_2R<0x01145800, FPR64>,
+ Sched<[WriteFRECIP, ReadFRECIP]>;
+def FRSQRT_D : FP_ALU_2R<0x01146800, FPR64>,
+ Sched<[WriteFRSQRT, ReadFRSQRT]>;
+def FRECIPE_D : FP_ALU_2R<0x01147800, FPR64>,
+ Sched<[WriteFRECIPE, ReadFRECIPE]>;
+def FRSQRTE_D : FP_ALU_2R<0x01148800, FPR64>,
+ Sched<[WriteFRSQRTE, ReadFRSQRTE]>;
+def FSCALEB_D : FP_ALU_3R<0x01110000, FPR64>,
+ Sched<[WriteFSCALEB, ReadFSCALEB, ReadFSCALEB]>;
+def FLOGB_D : FP_ALU_2R<0x01142800, FPR64>,
+ Sched<[WriteFLOGB, ReadFLOGB]>;
+def FCOPYSIGN_D : FP_ALU_3R<0x01130000, FPR64>,
+ Sched<[WriteFCOPYSIGN, ReadFCOPYSIGN, ReadFCOPYSIGN]>;
+def FCLASS_D : FP_ALU_2R<0x01143800, FPR64>,
+ Sched<[WriteFCLASS, ReadFCLASS]>;
// Comparison Instructions
-def FCMP_CAF_D : FP_CMP<0x0c200000, FPR64>;
-def FCMP_CUN_D : FP_CMP<0x0c240000, FPR64>;
-def FCMP_CEQ_D : FP_CMP<0x0c220000, FPR64>;
-def FCMP_CUEQ_D : FP_CMP<0x0c260000, FPR64>;
-def FCMP_CLT_D : FP_CMP<0x0c210000, FPR64>;
-def FCMP_CULT_D : FP_CMP<0x0c250000, FPR64>;
-def FCMP_CLE_D : FP_CMP<0x0c230000, FPR64>;
-def FCMP_CULE_D : FP_CMP<0x0c270000, FPR64>;
-def FCMP_CNE_D : FP_CMP<0x0c280000, FPR64>;
-def FCMP_COR_D : FP_CMP<0x0c2a0000, FPR64>;
-def FCMP_CUNE_D : FP_CMP<0x0c2c0000, FPR64>;
-def FCMP_SAF_D : FP_CMP<0x0c208000, FPR64>;
-def FCMP_SUN_D : FP_CMP<0x0c248000, FPR64>;
-def FCMP_SEQ_D : FP_CMP<0x0c228000, FPR64>;
-def FCMP_SUEQ_D : FP_CMP<0x0c268000, FPR64>;
-def FCMP_SLT_D : FP_CMP<0x0c218000, FPR64>;
-def FCMP_SULT_D : FP_CMP<0x0c258000, FPR64>;
-def FCMP_SLE_D : FP_CMP<0x0c238000, FPR64>;
-def FCMP_SULE_D : FP_CMP<0x0c278000, FPR64>;
-def FCMP_SNE_D : FP_CMP<0x0c288000, FPR64>;
-def FCMP_SOR_D : FP_CMP<0x0c2a8000, FPR64>;
-def FCMP_SUNE_D : FP_CMP<0x0c2c8000, FPR64>;
+def FCMP_CAF_D : FP_CMP<0x0c200000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CUN_D : FP_CMP<0x0c240000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CEQ_D : FP_CMP<0x0c220000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CUEQ_D : FP_CMP<0x0c260000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CLT_D : FP_CMP<0x0c210000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CULT_D : FP_CMP<0x0c250000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CLE_D : FP_CMP<0x0c230000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CULE_D : FP_CMP<0x0c270000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CNE_D : FP_CMP<0x0c280000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_COR_D : FP_CMP<0x0c2a0000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_CUNE_D : FP_CMP<0x0c2c0000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SAF_D : FP_CMP<0x0c208000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SUN_D : FP_CMP<0x0c248000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SEQ_D : FP_CMP<0x0c228000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SUEQ_D : FP_CMP<0x0c268000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SLT_D : FP_CMP<0x0c218000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SULT_D : FP_CMP<0x0c258000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SLE_D : FP_CMP<0x0c238000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SULE_D : FP_CMP<0x0c278000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SNE_D : FP_CMP<0x0c288000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SOR_D : FP_CMP<0x0c2a8000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
+def FCMP_SUNE_D : FP_CMP<0x0c2c8000, FPR64>,
+ Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>;
// Conversion Instructions
-def FFINT_S_L : FP_CONV<0x011d1800, FPR32, FPR64>;
-def FTINT_L_S : FP_CONV<0x011b2400, FPR64, FPR32>;
-def FTINTRM_L_S : FP_CONV<0x011a2400, FPR64, FPR32>;
-def FTINTRP_L_S : FP_CONV<0x011a6400, FPR64, FPR32>;
-def FTINTRZ_L_S : FP_CONV<0x011aa400, FPR64, FPR32>;
-def FTINTRNE_L_S : FP_CONV<0x011ae400, FPR64, FPR32>;
-def FCVT_S_D : FP_CONV<0x01191800, FPR32, FPR64>;
-def FCVT_D_S : FP_CONV<0x01192400, FPR64, FPR32>;
-def FFINT_D_W : FP_CONV<0x011d2000, FPR64, FPR32>;
-def FFINT_D_L : FP_CONV<0x011d2800, FPR64, FPR64>;
-def FTINT_W_D : FP_CONV<0x011b0800, FPR32, FPR64>;
-def FTINT_L_D : FP_CONV<0x011b2800, FPR64, FPR64>;
-def FTINTRM_W_D : FP_CONV<0x011a0800, FPR32, FPR64>;
-def FTINTRM_L_D : FP_CONV<0x011a2800, FPR64, FPR64>;
-def FTINTRP_W_D : FP_CONV<0x011a4800, FPR32, FPR64>;
-def FTINTRP_L_D : FP_CONV<0x011a6800, FPR64, FPR64>;
-def FTINTRZ_W_D : FP_CONV<0x011a8800, FPR32, FPR64>;
-def FTINTRZ_L_D : FP_CONV<0x011aa800, FPR64, FPR64>;
-def FTINTRNE_W_D : FP_CONV<0x011ac800, FPR32, FPR64>;
-def FTINTRNE_L_D : FP_CONV<0x011ae800, FPR64, FPR64>;
-def FRINT_D : FP_CONV<0x011e4800, FPR64, FPR64>;
+def FFINT_S_L : FP_CONV<0x011d1800, FPR32, FPR64>,
+ Sched<[WriteFCvtStoL, ReadFCvtStoL]>;
+def FTINT_L_S : FP_CONV<0x011b2400, FPR64, FPR32>,
+ Sched<[WriteFCvtLtoS, ReadFCvtLtoS]>;
+def FTINTRM_L_S : FP_CONV<0x011a2400, FPR64, FPR32>,
+ Sched<[WriteFCvtLtoS_RM, ReadFCvtLtoS_RM]>;
+def FTINTRP_L_S : FP_CONV<0x011a6400, FPR64, FPR32>,
+ Sched<[WriteFCvtLtoS_RP, ReadFCvtLtoS_RP]>;
+def FTINTRZ_L_S : FP_CONV<0x011aa400, FPR64, FPR32>,
+ Sched<[WriteFCvtLtoS_RZ, ReadFCvtLtoS_RZ]>;
+def FTINTRNE_L_S : FP_CONV<0x011ae400, FPR64, FPR32>,
+ Sched<[WriteFCvtLtoS_RNE, ReadFCvtLtoS_RNE]>;
+def FCVT_S_D : FP_CONV<0x01191800, FPR32, FPR64>,
+ Sched<[WriteFCvtStoD, ReadFCvtStoD]>;
+def FCVT_D_S : FP_CONV<0x01192400, FPR64, FPR32>,
+ Sched<[WriteFCvtDtoS, ReadFCvtDtoS]>;
+def FFINT_D_W : FP_CONV<0x011d2000, FPR64, FPR32>,
+ Sched<[WriteFCvtDtoW, ReadFCvtDtoW]>;
+def FFINT_D_L : FP_CONV<0x011d2800, FPR64, FPR64>,
+ Sched<[WriteFCvtDtoL, ReadFCvtDtoL]>;
+def FTINT_W_D : FP_CONV<0x011b0800, FPR32, FPR64>,
+ Sched<[WriteFCvtWtoD, ReadFCvtWtoD]>;
+def FTINT_L_D : FP_CONV<0x011b2800, FPR64, FPR64>,
+ Sched<[WriteFCvtLtoD, ReadFCvtLtoD]>;
+def FTINTRM_W_D : FP_CONV<0x011a0800, FPR32, FPR64>,
+ Sched<[WriteFCvtWtoD_RM, ReadFCvtWtoD_RM]>;
+def FTINTRM_L_D : FP_CONV<0x011a2800, FPR64, FPR64>,
+ Sched<[WriteFCvtLtoD_RM, ReadFCvtLtoD_RM]>;
+def FTINTRP_W_D : FP_CONV<0x011a4800, FPR32, FPR64>,
+ Sched<[WriteFCvtWtoD_RP, ReadFCvtWtoD_RP]>;
+def FTINTRP_L_D : FP_CONV<0x011a6800, FPR64, FPR64>,
+ Sched<[WriteFCvtLtoD_RP, ReadFCvtLtoD_RP]>;
+def FTINTRZ_W_D : FP_CONV<0x011a8800, FPR32, FPR64>,
+ Sched<[WriteFCvtWtoD_RZ, ReadFCvtWtoD_RZ]>;
+def FTINTRZ_L_D : FP_CONV<0x011aa800, FPR64, FPR64>,
+ Sched<[WriteFCvtLtoD_RZ, ReadFCvtLtoD_RZ]>;
+def FTINTRNE_W_D : FP_CONV<0x011ac800, FPR32, FPR64>,
+ Sched<[WriteFCvtWtoD_RNE, ReadFCvtWtoD_RNE]>;
+def FTINTRNE_L_D : FP_CONV<0x011ae800, FPR64, FPR64>,
+ Sched<[WriteFCvtLtoD_RNE, ReadFCvtLtoD_RNE]>;
+def FRINT_D : FP_CONV<0x011e4800, FPR64, FPR64>,
+ Sched<[WriteFCvtFDtoID, ReadFCvtFDtoID]>;
+
// Move Instructions
-def FMOV_D : FP_MOV<0x01149800, FPR64, FPR64>;
-def MOVFRH2GR_S : FP_MOV<0x0114bc00, GPR, FPR64>;
+def FMOV_D : FP_MOV<0x01149800, FPR64, FPR64>,
+ Sched<[WriteFMovD, ReadFMovD]>;
+def MOVFRH2GR_S : FP_MOV<0x0114bc00, GPR, FPR64>,
+ Sched<[WriteFMovFRHtoGRS, ReadFMovFRHtoGRS]>;
let isCodeGenOnly = 1 in {
-def MOVFR2GR_S_64 : FP_MOV<0x0114b400, GPR, FPR64>;
-def FSEL_xD : FP_SEL<0x0d000000, FPR64>;
+def MOVFR2GR_S_64 : FP_MOV<0x0114b400, GPR, FPR64>,
+ Sched<[WriteFMovFRtoGRS, ReadFMovFRtoGRS]>;
+def FSEL_xD : FP_SEL<0x0d000000, FPR64>,
+ Sched<[WriteFSEL, ReadFSEL, ReadFSEL, ReadFSEL]>;
} // isCodeGenOnly = 1
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" in {
def MOVGR2FRH_W : FPFmtMOV<0x0114ac00, (outs FPR64:$out),
(ins FPR64:$dst, GPR:$src),
- "$dst, $src">;
+ "$dst, $src">,
+ Sched<[WriteFMovGRtoFRHW, ReadFMovGRtoFRHW]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out"
// Common Memory Access Instructions
-def FLD_D : FP_LOAD_2RI12<0x2b800000, FPR64>;
-def FST_D : FP_STORE_2RI12<0x2bc00000, FPR64>;
-def FLDX_D : FP_LOAD_3R<0x38340000, FPR64>;
-def FSTX_D : FP_STORE_3R<0x383c0000, FPR64>;
+def FLD_D : FP_LOAD_2RI12<0x2b800000, FPR64>,
+ Sched<[WriteFLD, ReadFMemBase]>;
+def FST_D : FP_STORE_2RI12<0x2bc00000, FPR64>,
+ Sched<[WriteFST, ReadFSTData, ReadFMemBase]>;
+def FLDX_D : FP_LOAD_3R<0x38340000, FPR64>,
+ Sched<[WriteFLDX, ReadFMemBase, ReadFMemOffset]>;
+def FSTX_D : FP_STORE_3R<0x383c0000, FPR64>,
+ Sched<[WriteFSTX, ReadFSTData, ReadFMemBase, ReadFMemOffset]>;
// Bound Check Memory Access Instructions
-def FLDGT_D : FP_LOAD_3R<0x38748000, FPR64>;
-def FLDLE_D : FP_LOAD_3R<0x38758000, FPR64>;
-def FSTGT_D : FP_STORE_3R<0x38768000, FPR64>;
-def FSTLE_D : FP_STORE_3R<0x38778000, FPR64>;
+def FLDGT_D : FP_LOAD_3R<0x38748000, FPR64>,
+ Sched<[WriteFLDGT, ReadFMemBase, ReadFMemCmp]>;
+def FLDLE_D : FP_LOAD_3R<0x38758000, FPR64>,
+ Sched<[WriteFLDLE, ReadFMemBase, ReadFMemCmp]>;
+def FSTGT_D : FP_STORE_3R<0x38768000, FPR64>,
+ Sched<[WriteFSTGT, ReadFSTData, ReadFMemBase, ReadFMemCmp]>;
+def FSTLE_D : FP_STORE_3R<0x38778000, FPR64>,
+ Sched<[WriteFSTLE, ReadFSTData, ReadFMemBase, ReadFMemCmp]>;
} // Predicates = [HasBasicD]
// Instructions only available on LA64
let Predicates = [HasBasicD, IsLA64] in {
-def MOVGR2FR_D : FP_MOV<0x0114a800, FPR64, GPR>;
-def MOVFR2GR_D : FP_MOV<0x0114b800, GPR, FPR64>;
+def MOVGR2FR_D : FP_MOV<0x0114a800, FPR64, GPR>,
+ Sched<[WriteFMovGRtoFRD, ReadFMovGRtoFRD]>;
+def MOVFR2GR_D : FP_MOV<0x0114b800, GPR, FPR64>,
+ Sched<[WriteFMovFRtoGRD, ReadFMovFRtoGRD]>;
} // Predicates = [HasBasicD, IsLA64]
// Instructions only available on LA32
let Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 in {
-def MOVGR2FR_W_64 : FP_MOV<0x0114a400, FPR64, GPR>;
+def MOVGR2FR_W_64 : FP_MOV<0x0114a400, FPR64, GPR>,
+ Sched<[WriteFMovGRtoFRW, ReadFMovGRtoFRW]>;
} // Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index 5e9c7d8a7b2ec..2c6d94e075ff6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -776,18 +776,21 @@ class RDTIME_2R<bits<32> op>
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
class BrCC_2RI16<bits<32> op>
: Fmt2RI16<op, (outs), (ins GPR:$rj, GPR:$rd, simm16_lsl2_br:$imm16),
- "$rj, $rd, $imm16"> {
+ "$rj, $rd, $imm16">,
+ Sched<[WriteIJump, ReadIJump, ReadIJump]> {
let isBranch = 1;
let isTerminator = 1;
}
class BrCCZ_1RI21<bits<32> op>
: Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2_br:$imm21),
- "$rj, $imm21"> {
+ "$rj, $imm21">,
+ Sched<[WriteIJump, ReadIJump]> {
let isBranch = 1;
let isTerminator = 1;
}
class Br_I26<bits<32> op>
- : FmtI26<op, (outs), (ins simm26_b:$imm26), "$imm26"> {
+ : FmtI26<op, (outs), (ins simm26_b:$imm26), "$imm26">,
+ Sched<[WriteIJump]> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
@@ -799,10 +802,12 @@ class LOAD_3R<bits<32> op>
: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), "$rd, $rj, $rk">;
class LOAD_2RI12<bits<32> op>
: Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12_addlike:$imm12),
- "$rd, $rj, $imm12">;
+ "$rd, $rj, $imm12">,
+ Sched<[WriteLD, ReadMemBase]>;
class LOAD_2RI14<bits<32> op>
: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
- "$rd, $rj, $imm14">;
+ "$rd, $rj, $imm14">,
+ Sched<[WriteLDPTR, ReadMemBase]>;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
@@ -811,10 +816,12 @@ class STORE_3R<bits<32> op>
"$rd, $rj, $rk">;
class STORE_2RI12<bits<32> op>
: Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12_addlike:$imm12),
- "$rd, $rj, $imm12">;
+ "$rd, $rj, $imm12">,
+ Sched<[WriteST, ReadSTData, ReadMemBase]>;
class STORE_2RI14<bits<32> op>
: Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
- "$rd, $rj, $imm14">;
+ "$rd, $rj, $imm14">,
+ Sched<[WriteSTPTR, ReadSTData, ReadMemBase]>;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
let hasSideEffects = 0, mayLoad = 1, mayStore = 1,
@@ -870,45 +877,74 @@ class IOCSRWR<bits<32> op>
//===----------------------------------------------------------------------===//
// Arithmetic Operation Instructions
-def ADD_W : ALU_3R<0x00100000>;
-def SUB_W : ALU_3R<0x00110000>;
-def ADDI_W : ALU_2RI12<0x02800000, simm12_addlike>;
+def ADD_W : ALU_3R<0x00100000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def SUB_W : ALU_3R<0x00110000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def ADDI_W : ALU_2RI12<0x02800000, simm12_addlike>,
+ Sched<[WriteIALU, ReadIALU]>;
let isReMaterializable = 1 in {
-def LU12I_W : ALU_1RI20<0x14000000, simm20_lu12iw>;
-}
-def SLT : ALU_3R<0x00120000>;
-def SLTU : ALU_3R<0x00128000>;
-def SLTI : ALU_2RI12<0x02000000, simm12>;
-def SLTUI : ALU_2RI12<0x02400000, simm12>;
-def PCADDU12I : ALU_1RI20<0x1c000000, simm20_pcaddu12i>;
-def AND : ALU_3R<0x00148000>;
-def OR : ALU_3R<0x00150000>;
-def NOR : ALU_3R<0x00140000>;
-def XOR : ALU_3R<0x00158000>;
-def ANDI : ALU_2RI12<0x03400000, uimm12>;
+def LU12I_W : ALU_1RI20<0x14000000, simm20_lu12iw>,
+ Sched<[WriteIALU]>;
+}
+def SLT : ALU_3R<0x00120000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def SLTU : ALU_3R<0x00128000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def SLTI : ALU_2RI12<0x02000000, simm12>,
+ Sched<[WriteIALU, ReadIALU]>;
+def SLTUI : ALU_2RI12<0x02400000, simm12>,
+ Sched<[WriteIALU, ReadIALU]>;
+def PCADDU12I : ALU_1RI20<0x1c000000, simm20_pcaddu12i>,
+ Sched<[WriteIPCAdd]>;
+def AND : ALU_3R<0x00148000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def OR : ALU_3R<0x00150000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def NOR : ALU_3R<0x00140000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def XOR : ALU_3R<0x00158000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def ANDI : ALU_2RI12<0x03400000, uimm12>,
+ Sched<[WriteIALU, ReadIALU]>;
// See LoongArchInstrInfo::isAsCheapAsAMove for more details.
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
-def ORI : ALU_2RI12<0x03800000, uimm12_ori>;
-def XORI : ALU_2RI12<0x03c00000, uimm12>;
-}
-def MUL_W : ALU_3R<0x001c0000>;
-def MULH_W : ALU_3R<0x001c8000>;
-def MULH_WU : ALU_3R<0x001d0000>;
+def ORI : ALU_2RI12<0x03800000, uimm12_ori>,
+ Sched<[WriteIALU, ReadIALU]>;
+def XORI : ALU_2RI12<0x03c00000, uimm12>,
+ Sched<[WriteIALU, ReadIALU]>;
+}
+def MUL_W : ALU_3R<0x001c0000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
+def MULH_W : ALU_3R<0x001c8000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
+def MULH_WU : ALU_3R<0x001d0000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
let usesCustomInserter = true in {
-def DIV_W : ALU_3R<0x00200000>;
-def MOD_W : ALU_3R<0x00208000>;
-def DIV_WU : ALU_3R<0x00210000>;
-def MOD_WU : ALU_3R<0x00218000>;
+def DIV_W : ALU_3R<0x00200000>,
+ Sched<[WriteIDIV32, ReadIDIV32, ReadIDIV32]>;
+def MOD_W : ALU_3R<0x00208000>,
+ Sched<[WriteIDIV32, ReadIDIV32, ReadIDIV32]>;
+def DIV_WU : ALU_3R<0x00210000>,
+ Sched<[WriteIDIV32, ReadIDIV32, ReadIDIV32]>;
+def MOD_WU : ALU_3R<0x00218000>,
+ Sched<[WriteIDIV32, ReadIDIV32, ReadIDIV32]>;
} // usesCustomInserter = true
// Bit-shift Instructions
-def SLL_W : ALU_3R<0x00170000>;
-def SRL_W : ALU_3R<0x00178000>;
-def SRA_W : ALU_3R<0x00180000>;
-
-def SLLI_W : ALU_2RI5<0x00408000, uimm5>;
-def SRLI_W : ALU_2RI5<0x00448000, uimm5>;
-def SRAI_W : ALU_2RI5<0x00488000, uimm5>;
+def SLL_W : ALU_3R<0x00170000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def SRL_W : ALU_3R<0x00178000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def SRA_W : ALU_3R<0x00180000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+
+def SLLI_W : ALU_2RI5<0x00408000, uimm5>,
+ Sched<[WriteIShift, ReadIShift]>;
+def SRLI_W : ALU_2RI5<0x00448000, uimm5>,
+ Sched<[WriteIShift, ReadIShift]>;
+def SRAI_W : ALU_2RI5<0x00488000, uimm5>,
+ Sched<[WriteIShift, ReadIShift]>;
// Branch Instructions
def BEQ : BrCC_2RI16<0x58000000>;
@@ -920,10 +956,12 @@ def BGEU : BrCC_2RI16<0x6c000000>;
def B : Br_I26<0x50000000>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, Defs=[R1] in
-def BL : FmtI26<0x54000000, (outs), (ins simm26_symbol:$imm26), "$imm26">;
+def BL : FmtI26<0x54000000, (outs), (ins simm26_symbol:$imm26), "$imm26">,
+ Sched<[WriteIJump]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def JIRL : Fmt2RI16<0x4c000000, (outs GPR:$rd),
- (ins GPR:$rj, simm16_lsl2:$imm16), "$rd, $rj, $imm16">;
+ (ins GPR:$rj, simm16_lsl2:$imm16), "$rd, $rj, $imm16">,
+ Sched<[WriteIJump, ReadIJump]>;
// Common Memory Access Instructions
def LD_B : LOAD_2RI12<0x28000000>;
@@ -936,68 +974,93 @@ def ST_H : STORE_2RI12<0x29400000>;
def ST_W : STORE_2RI12<0x29800000>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12),
- "$imm5, $rj, $imm12">;
+ "$imm5, $rj, $imm12">,
+ Sched<[]>;
// Atomic Memory Access Instructions
-def LL_W : LLBase<0x20000000>;
-def SC_W : SCBase<0x21000000>;
+def LL_W : LLBase<0x20000000>,
+ Sched<[WriteAtomic]>;
+def SC_W : SCBase<0x21000000>,
+ Sched<[WriteAtomic]>;
// Barrier Instructions
-def DBAR : MISC_I15<0x38720000>;
-def IBAR : MISC_I15<0x38728000>;
+def DBAR : MISC_I15<0x38720000>, Sched<[]>;
+def IBAR : MISC_I15<0x38728000>, Sched<[]>;
// Other Miscellaneous Instructions
-def SYSCALL : MISC_I15<0x002b0000>;
-def BREAK : MISC_I15<0x002a0000>;
-def RDTIMEL_W : RDTIME_2R<0x00006000>;
-def RDTIMEH_W : RDTIME_2R<0x00006400>;
+def SYSCALL : MISC_I15<0x002b0000>, Sched<[]>;
+def BREAK : MISC_I15<0x002a0000>, Sched<[]>;
+def RDTIMEL_W : RDTIME_2R<0x00006000>, Sched<[]>;
+def RDTIMEH_W : RDTIME_2R<0x00006400>, Sched<[]>;
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
-def UD : FmtUD<(outs), (ins uimm5:$imm5), "$imm5">;
+def UD : FmtUD<(outs), (ins uimm5:$imm5), "$imm5">, Sched<[]>;
// The CPUCFG instruction offers a reliable way to probing CPU features.
// Although support is not guaranteed on LA32R, having compiler support
// nevertheless enables applications to rely on its presence, potentially
// via kernel emulation if not available natively.
-def CPUCFG : ALU_2R<0x00006c00>;
+def CPUCFG : ALU_2R<0x00006c00>, Sched<[]>;
// Cache Maintenance Instructions
def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12),
- "$op, $rj, $imm12">;
+ "$op, $rj, $imm12">,
+ Sched<[]>;
let Predicates = [Has32S] in {
// Arithmetic Operation Instructions
-def ALSL_W : ALU_3RI2<0x00040000, uimm2_plus1>;
-def ANDN : ALU_3R<0x00168000>;
-def ORN : ALU_3R<0x00160000>;
-def PCADDI : ALU_1RI20<0x18000000, simm20_pcaddi>;
-def PCALAU12I : ALU_1RI20<0x1a000000, simm20_pcalau12i>;
+def ALSL_W : ALU_3RI2<0x00040000, uimm2_plus1>,
+ Sched<[WriteIALSL, ReadIALSL, ReadIALSL]>;
+def ANDN : ALU_3R<0x00168000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def ORN : ALU_3R<0x00160000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def PCADDI : ALU_1RI20<0x18000000, simm20_pcaddi>,
+ Sched<[WriteIPCAdd]>;
+def PCALAU12I : ALU_1RI20<0x1a000000, simm20_pcalau12i>,
+ Sched<[WriteIPCAdd]>;
// Bit-shift Instructions
-def ROTR_W : ALU_3R<0x001b0000>;
-def ROTRI_W : ALU_2RI5<0x004c8000, uimm5>;
+def ROTR_W : ALU_3R<0x001b0000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def ROTRI_W : ALU_2RI5<0x004c8000, uimm5>,
+ Sched<[WriteIShift, ReadIShift]>;
// Bit-manipulation Instructions
-def EXT_W_B : ALU_2R<0x00005c00>;
-def EXT_W_H : ALU_2R<0x00005800>;
-def CLO_W : ALU_2R<0x00001000>;
-def CLZ_W : ALU_2R<0x00001400>;
-def CTO_W : ALU_2R<0x00001800>;
-def CTZ_W : ALU_2R<0x00001c00>;
-def BYTEPICK_W : ALU_3RI2<0x00080000, uimm2>;
-def REVB_2H : ALU_2R<0x00003000>;
-def BITREV_4B : ALU_2R<0x00004800>;
-def BITREV_W : ALU_2R<0x00005000>;
+def EXT_W_B : ALU_2R<0x00005c00>,
+ Sched<[WriteIEXT, ReadIEXT]>;
+def EXT_W_H : ALU_2R<0x00005800>,
+ Sched<[WriteIEXT, ReadIEXT]>;
+def CLO_W : ALU_2R<0x00001000>,
+ Sched<[WriteICL, ReadICL]>;
+def CLZ_W : ALU_2R<0x00001400>,
+ Sched<[WriteICL, ReadICL]>;
+def CTO_W : ALU_2R<0x00001800>,
+ Sched<[WriteICT, ReadICT]>;
+def CTZ_W : ALU_2R<0x00001c00>,
+ Sched<[WriteICT, ReadICT]>;
+def BYTEPICK_W : ALU_3RI2<0x00080000, uimm2>,
+ Sched<[WriteIBytePick, ReadIBytePick, ReadIBytePick]>;
+def REVB_2H : ALU_2R<0x00003000>,
+ Sched<[WriteIRev, ReadIRev]>;
+def BITREV_4B : ALU_2R<0x00004800>,
+ Sched<[WriteIBitRev, ReadIBitRev]>;
+def BITREV_W : ALU_2R<0x00005000>,
+ Sched<[WriteIBitRev, ReadIBitRev]>;
let Constraints = "$rd = $dst" in {
def BSTRINS_W : FmtBSTR_W<0x00600000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
- "$rd, $rj, $msbw, $lsbw">;
+ "$rd, $rj, $msbw, $lsbw">,
+ Sched<[WriteIBstrins, ReadIBstrins]>;
}
def BSTRPICK_W : FmtBSTR_W<0x00608000, (outs GPR:$rd),
(ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
- "$rd, $rj, $msbw, $lsbw">;
-def MASKEQZ : ALU_3R<0x00130000>;
-def MASKNEZ : ALU_3R<0x00138000>;
+ "$rd, $rj, $msbw, $lsbw">,
+ Sched<[WriteIBstrPick, ReadIBstrPick]>;
+def MASKEQZ : ALU_3R<0x00130000>,
+ Sched<[WriteIMASK, ReadIMASK]>;
+def MASKNEZ : ALU_3R<0x00138000>,
+ Sched<[WriteIMASK, ReadIMASK]>;
// Branch Instructions
def BEQZ : BrCCZ_1RI21<0x40000000>;
@@ -1009,190 +1072,260 @@ def BNEZ : BrCCZ_1RI21<0x44000000>;
let Predicates = [IsLA64] in {
// Arithmetic Operation Instructions for 64-bits
-def ADD_D : ALU_3R<0x00108000>;
-def SUB_D : ALU_3R<0x00118000>;
+def ADD_D : ALU_3R<0x00108000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def SUB_D : ALU_3R<0x00118000>,
+ Sched<[WriteIALU, ReadIALU, ReadIALU]>;
// ADDI_D isn't always rematerializable, but isReMaterializable will be used as
// a hint which is verified in isReMaterializableImpl.
// See LoongArchInstrInfo::isAsCheapAsAMove for more details.
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
-def ADDI_D : ALU_2RI12<0x02c00000, simm12_addlike>;
-}
-def ADDU16I_D : ALU_2RI16<0x10000000, simm16>;
-def ALSL_WU : ALU_3RI2<0x00060000, uimm2_plus1>;
-def ALSL_D : ALU_3RI2<0x002c0000, uimm2_plus1>;
+def ADDI_D : ALU_2RI12<0x02c00000, simm12_addlike>,
+ Sched<[WriteIALU, ReadIALU]>;
+}
+def ADDU16I_D : ALU_2RI16<0x10000000, simm16>,
+ Sched<[WriteIALU, ReadIALU]>;
+def ALSL_WU : ALU_3RI2<0x00060000, uimm2_plus1>,
+ Sched<[WriteIALSL, ReadIALSL, ReadIALSL]>;
+def ALSL_D : ALU_3RI2<0x002c0000, uimm2_plus1>,
+ Sched<[WriteIALSL, ReadIALSL, ReadIALSL]>;
let Constraints = "$rd = $dst" in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
isReMaterializable = 1 in
def LU32I_D : Fmt1RI20<0x16000000, (outs GPR:$dst),
(ins GPR:$rd, simm20_lu32id:$imm20),
- "$rd, $imm20">;
+ "$rd, $imm20">,
+ Sched<[WriteIALU]>;
}
let isReMaterializable = 1 in {
-def LU52I_D : ALU_2RI12<0x03000000, simm12_lu52id>;
-}
-def PCADDU18I : ALU_1RI20<0x1e000000, simm20_pcaddu18i>;
-def MUL_D : ALU_3R<0x001d8000>;
-def MULH_D : ALU_3R<0x001e0000>;
-def MULH_DU : ALU_3R<0x001e8000>;
-def MULW_D_W : ALU_3R<0x001f0000>;
-def MULW_D_WU : ALU_3R<0x001f8000>;
+def LU52I_D : ALU_2RI12<0x03000000, simm12_lu52id>,
+ Sched<[WriteIALU, ReadIALU]>;
+}
+def PCADDU18I : ALU_1RI20<0x1e000000, simm20_pcaddu18i>,
+ Sched<[WriteIPCAdd]>;
+def MUL_D : ALU_3R<0x001d8000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
+def MULH_D : ALU_3R<0x001e0000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
+def MULH_DU : ALU_3R<0x001e8000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
+def MULW_D_W : ALU_3R<0x001f0000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
+def MULW_D_WU : ALU_3R<0x001f8000>,
+ Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>;
let usesCustomInserter = true in {
-def DIV_D : ALU_3R<0x00220000>;
-def MOD_D : ALU_3R<0x00228000>;
-def DIV_DU : ALU_3R<0x00230000>;
-def MOD_DU : ALU_3R<0x00238000>;
+def DIV_D : ALU_3R<0x00220000>,
+ Sched<[WriteIDIV, ReadIDIV, ReadIDIV]>;
+def MOD_D : ALU_3R<0x00228000>,
+ Sched<[WriteIDIV, ReadIDIV, ReadIDIV]>;
+def DIV_DU : ALU_3R<0x00230000>,
+ Sched<[WriteIDIV, ReadIDIV, ReadIDIV]>;
+def MOD_DU : ALU_3R<0x00238000>,
+ Sched<[WriteIDIV, ReadIDIV, ReadIDIV]>;
} // usesCustomInserter = true
// Bit-shift Instructions for 64-bits
-def SLL_D : ALU_3R<0x00188000>;
-def SRL_D : ALU_3R<0x00190000>;
-def SRA_D : ALU_3R<0x00198000>;
-def ROTR_D : ALU_3R<0x001b8000>;
-def SLLI_D : ALU_2RI6<0x00410000, uimm6>;
-def SRLI_D : ALU_2RI6<0x00450000, uimm6>;
-def SRAI_D : ALU_2RI6<0x00490000, uimm6>;
-def ROTRI_D : ALU_2RI6<0x004d0000, uimm6>;
+def SLL_D : ALU_3R<0x00188000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def SRL_D : ALU_3R<0x00190000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def SRA_D : ALU_3R<0x00198000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def ROTR_D : ALU_3R<0x001b8000>,
+ Sched<[WriteIShift, ReadIShift, ReadIShift]>;
+def SLLI_D : ALU_2RI6<0x00410000, uimm6>,
+ Sched<[WriteIShift, ReadIShift]>;
+def SRLI_D : ALU_2RI6<0x00450000, uimm6>,
+ Sched<[WriteIShift, ReadIShift]>;
+def SRAI_D : ALU_2RI6<0x00490000, uimm6>,
+ Sched<[WriteIShift, ReadIShift]>;
+def ROTRI_D : ALU_2RI6<0x004d0000, uimm6>,
+ Sched<[WriteIShift, ReadIShift]>;
// Bit-manipulation Instructions for 64-bits
-def CLO_D : ALU_2R<0x00002000>;
-def CLZ_D : ALU_2R<0x00002400>;
-def CTO_D : ALU_2R<0x00002800>;
-def CTZ_D : ALU_2R<0x00002c00>;
-def BYTEPICK_D : ALU_3RI3<0x000c0000, uimm3>;
-def REVB_4H : ALU_2R<0x00003400>;
-def REVB_2W : ALU_2R<0x00003800>;
-def REVB_D : ALU_2R<0x00003c00>;
-def REVH_2W : ALU_2R<0x00004000>;
-def REVH_D : ALU_2R<0x00004400>;
-def BITREV_8B : ALU_2R<0x00004c00>;
-def BITREV_D : ALU_2R<0x00005400>;
+def CLO_D : ALU_2R<0x00002000>,
+ Sched<[WriteICL, ReadICL]>;
+def CLZ_D : ALU_2R<0x00002400>,
+ Sched<[WriteICL, ReadICL]>;
+def CTO_D : ALU_2R<0x00002800>,
+ Sched<[WriteICT, ReadICT]>;
+def CTZ_D : ALU_2R<0x00002c00>,
+ Sched<[WriteICT, ReadICT]>;
+def BYTEPICK_D : ALU_3RI3<0x000c0000, uimm3>,
+ Sched<[WriteIBytePick, ReadIBytePick, ReadIBytePick]>;
+def REVB_4H : ALU_2R<0x00003400>,
+ Sched<[WriteIRev, ReadIRev]>;
+def REVB_2W : ALU_2R<0x00003800>,
+ Sched<[WriteIRev, ReadIRev]>;
+def REVB_D : ALU_2R<0x00003c00>,
+ Sched<[WriteIRev, ReadIRev]>;
+def REVH_2W : ALU_2R<0x00004000>,
+ Sched<[WriteIRev, ReadIRev]>;
+def REVH_D : ALU_2R<0x00004400>,
+ Sched<[WriteIRev, ReadIRev]>;
+def BITREV_8B : ALU_2R<0x00004c00>,
+ Sched<[WriteIBitRev, ReadIBitRev]>;
+def BITREV_D : ALU_2R<0x00005400>,
+ Sched<[WriteIBitRev, ReadIBitRev]>;
let Constraints = "$rd = $dst" in {
def BSTRINS_D : FmtBSTR_D<0x00800000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
- "$rd, $rj, $msbd, $lsbd">;
+ "$rd, $rj, $msbd, $lsbd">,
+ Sched<[WriteIBstrins, ReadIBstrins]>;
}
def BSTRPICK_D : FmtBSTR_D<0x00c00000, (outs GPR:$rd),
(ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
- "$rd, $rj, $msbd, $lsbd">;
+ "$rd, $rj, $msbd, $lsbd">,
+ Sched<[WriteIBstrPick, ReadIBstrPick]>;
// Common Memory Access Instructions for 64-bits
def LD_WU : LOAD_2RI12<0x2a800000>;
def LD_D : LOAD_2RI12<0x28c00000>;
def ST_D : STORE_2RI12<0x29c00000>;
-def LDX_B : LOAD_3R<0x38000000>;
-def LDX_H : LOAD_3R<0x38040000>;
-def LDX_W : LOAD_3R<0x38080000>;
-def LDX_D : LOAD_3R<0x380c0000>;
-def LDX_BU : LOAD_3R<0x38200000>;
-def LDX_HU : LOAD_3R<0x38240000>;
-def LDX_WU : LOAD_3R<0x38280000>;
-def STX_B : STORE_3R<0x38100000>;
-def STX_H : STORE_3R<0x38140000>;
-def STX_W : STORE_3R<0x38180000>;
-def STX_D : STORE_3R<0x381c0000>;
+def LDX_B : LOAD_3R<0x38000000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def LDX_H : LOAD_3R<0x38040000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def LDX_W : LOAD_3R<0x38080000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def LDX_D : LOAD_3R<0x380c0000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def LDX_BU : LOAD_3R<0x38200000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def LDX_HU : LOAD_3R<0x38240000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def LDX_WU : LOAD_3R<0x38280000>,
+ Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>;
+def STX_B : STORE_3R<0x38100000>,
+ Sched<[WriteSTX, ReadSTData, ReadMemBase, ReadMemOffset]>;
+def STX_H : STORE_3R<0x38140000>,
+ Sched<[WriteSTX, ReadSTData, ReadMemBase, ReadMemOffset]>;
+def STX_W : STORE_3R<0x38180000>,
+ Sched<[WriteSTX, ReadSTData, ReadMemBase, ReadMemOffset]>;
+def STX_D : STORE_3R<0x381c0000>,
+ Sched<[WriteSTX, ReadSTData, ReadMemBase, ReadMemOffset]>;
def LDPTR_W : LOAD_2RI14<0x24000000>;
def LDPTR_D : LOAD_2RI14<0x26000000>;
def STPTR_W : STORE_2RI14<0x25000000>;
def STPTR_D : STORE_2RI14<0x27000000>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk),
- "$imm5, $rj, $rk">;
+ "$imm5, $rj, $rk">,
+ Sched<[]>;
// Bound Check Memory Access Instructions
-def LDGT_B : LOAD_3R<0x38780000>;
-def LDGT_H : LOAD_3R<0x38788000>;
-def LDGT_W : LOAD_3R<0x38790000>;
-def LDGT_D : LOAD_3R<0x38798000>;
-def LDLE_B : LOAD_3R<0x387a0000>;
-def LDLE_H : LOAD_3R<0x387a8000>;
-def LDLE_W : LOAD_3R<0x387b0000>;
-def LDLE_D : LOAD_3R<0x387b8000>;
-def STGT_B : STORE_3R<0x387c0000>;
-def STGT_H : STORE_3R<0x387c8000>;
-def STGT_W : STORE_3R<0x387d0000>;
-def STGT_D : STORE_3R<0x387d8000>;
-def STLE_B : STORE_3R<0x387e0000>;
-def STLE_H : STORE_3R<0x387e8000>;
-def STLE_W : STORE_3R<0x387f0000>;
-def STLE_D : STORE_3R<0x387f8000>;
+def LDGT_B : LOAD_3R<0x38780000>,
+ Sched<[WriteLDGT, ReadMemBase, ReadMemCmp]>;
+def LDGT_H : LOAD_3R<0x38788000>,
+ Sched<[WriteLDGT, ReadMemBase, ReadMemCmp]>;
+def LDGT_W : LOAD_3R<0x38790000>,
+ Sched<[WriteLDGT, ReadMemBase, ReadMemCmp]>;
+def LDGT_D : LOAD_3R<0x38798000>,
+ Sched<[WriteLDGT, ReadMemBase, ReadMemCmp]>;
+def LDLE_B : LOAD_3R<0x387a0000>,
+ Sched<[WriteLDLE, ReadMemBase, ReadMemCmp]>;
+def LDLE_H : LOAD_3R<0x387a8000>,
+ Sched<[WriteLDLE, ReadMemBase, ReadMemCmp]>;
+def LDLE_W : LOAD_3R<0x387b0000>,
+ Sched<[WriteLDLE, ReadMemBase, ReadMemCmp]>;
+def LDLE_D : LOAD_3R<0x387b8000>,
+ Sched<[WriteLDLE, ReadMemBase, ReadMemCmp]>;
+def STGT_B : STORE_3R<0x387c0000>,
+ Sched<[WriteSTGT, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STGT_H : STORE_3R<0x387c8000>,
+ Sched<[WriteSTGT, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STGT_W : STORE_3R<0x387d0000>,
+ Sched<[WriteSTGT, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STGT_D : STORE_3R<0x387d8000>,
+ Sched<[WriteSTGT, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STLE_B : STORE_3R<0x387e0000>,
+ Sched<[WriteSTLE, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STLE_H : STORE_3R<0x387e8000>,
+ Sched<[WriteSTLE, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STLE_W : STORE_3R<0x387f0000>,
+ Sched<[WriteSTLE, ReadSTData, ReadMemBase, ReadMemCmp]>;
+def STLE_D : STORE_3R<0x387f8000>,
+ Sched<[WriteSTLE, ReadSTData, ReadMemBase, ReadMemCmp]>;
// Atomic Memory Access Instructions for 64-bits
-def AMSWAP_B : AM_3R<0x385c0000>;
-def AMSWAP_H : AM_3R<0x385c8000>;
-def AMSWAP_W : AU_3R<0x38600000>;
-def AMSWAP_D : AM_3R<0x38608000>;
-def AMADD_B : AM_3R<0x385d0000>;
-def AMADD_H : AM_3R<0x385d8000>;
-def AMADD_W : AM_3R<0x38610000>;
-def AMADD_D : AM_3R<0x38618000>;
-def AMAND_W : AM_3R<0x38620000>;
-def AMAND_D : AM_3R<0x38628000>;
-def AMOR_W : AM_3R<0x38630000>;
-def AMOR_D : AM_3R<0x38638000>;
-def AMXOR_W : AM_3R<0x38640000>;
-def AMXOR_D : AM_3R<0x38648000>;
-def AMMAX_W : AM_3R<0x38650000>;
-def AMMAX_D : AM_3R<0x38658000>;
-def AMMIN_W : AM_3R<0x38660000>;
-def AMMIN_D : AM_3R<0x38668000>;
-def AMMAX_WU : AM_3R<0x38670000>;
-def AMMAX_DU : AM_3R<0x38678000>;
-def AMMIN_WU : AM_3R<0x38680000>;
-def AMMIN_DU : AM_3R<0x38688000>;
-def AMSWAP__DB_B : AM_3R<0x385e0000>;
-def AMSWAP__DB_H : AM_3R<0x385e8000>;
-def AMSWAP__DB_W : AM_3R<0x38690000>;
-def AMSWAP__DB_D : AM_3R<0x38698000>;
-def AMADD__DB_B : AM_3R<0x385f0000>;
-def AMADD__DB_H : AM_3R<0x385f8000>;
-def AMADD__DB_W : AM_3R<0x386a0000>;
-def AMADD__DB_D : AM_3R<0x386a8000>;
-def AMAND__DB_W : AM_3R<0x386b0000>;
-def AMAND__DB_D : AM_3R<0x386b8000>;
-def AMOR__DB_W : AM_3R<0x386c0000>;
-def AMOR__DB_D : AM_3R<0x386c8000>;
-def AMXOR__DB_W : AM_3R<0x386d0000>;
-def AMXOR__DB_D : AM_3R<0x386d8000>;
-def AMMAX__DB_W : AM_3R<0x386e0000>;
-def AMMAX__DB_D : AM_3R<0x386e8000>;
-def AMMIN__DB_W : AM_3R<0x386f0000>;
-def AMMIN__DB_D : AM_3R<0x386f8000>;
-def AMMAX__DB_WU : AM_3R<0x38700000>;
-def AMMAX__DB_DU : AM_3R<0x38708000>;
-def AMMIN__DB_WU : AM_3R<0x38710000>;
-def AMMIN__DB_DU : AM_3R<0x38718000>;
-def AMCAS_B : AMCAS_3R<0x38580000>;
-def AMCAS_H : AMCAS_3R<0x38588000>;
-def AMCAS_W : AMCAS_3R<0x38590000>;
-def AMCAS_D : AMCAS_3R<0x38598000>;
-def AMCAS__DB_B : AMCAS_3R<0x385a0000>;
-def AMCAS__DB_H : AMCAS_3R<0x385a8000>;
-def AMCAS__DB_W : AMCAS_3R<0x385b0000>;
-def AMCAS__DB_D : AMCAS_3R<0x385b8000>;
-def LL_D : LLBase<0x22000000>;
-def SC_D : SCBase<0x23000000>;
-def SC_Q : SCBase_128<0x38570000>;
-def LLACQ_W : LLBase_ACQ<0x38578000>;
-def SCREL_W : SCBase_REL<0x38578400>;
-def LLACQ_D : LLBase_ACQ<0x38578800>;
-def SCREL_D : SCBase_REL<0x38578C00>;
+def AMSWAP_B : AM_3R<0x385c0000>, Sched<[WriteAtomic]>;
+def AMSWAP_H : AM_3R<0x385c8000>, Sched<[WriteAtomic]>;
+def AMSWAP_W : AU_3R<0x38600000>, Sched<[WriteAtomic]>;
+def AMSWAP_D : AM_3R<0x38608000>, Sched<[WriteAtomic]>;
+def AMADD_B : AM_3R<0x385d0000>, Sched<[WriteAtomic]>;
+def AMADD_H : AM_3R<0x385d8000>, Sched<[WriteAtomic]>;
+def AMADD_W : AM_3R<0x38610000>, Sched<[WriteAtomic]>;
+def AMADD_D : AM_3R<0x38618000>, Sched<[WriteAtomic]>;
+def AMAND_W : AM_3R<0x38620000>, Sched<[WriteAtomic]>;
+def AMAND_D : AM_3R<0x38628000>, Sched<[WriteAtomic]>;
+def AMOR_W : AM_3R<0x38630000>, Sched<[WriteAtomic]>;
+def AMOR_D : AM_3R<0x38638000>, Sched<[WriteAtomic]>;
+def AMXOR_W : AM_3R<0x38640000>, Sched<[WriteAtomic]>;
+def AMXOR_D : AM_3R<0x38648000>, Sched<[WriteAtomic]>;
+def AMMAX_W : AM_3R<0x38650000>, Sched<[WriteAtomic]>;
+def AMMAX_D : AM_3R<0x38658000>, Sched<[WriteAtomic]>;
+def AMMIN_W : AM_3R<0x38660000>, Sched<[WriteAtomic]>;
+def AMMIN_D : AM_3R<0x38668000>, Sched<[WriteAtomic]>;
+def AMMAX_WU : AM_3R<0x38670000>, Sched<[WriteAtomic]>;
+def AMMAX_DU : AM_3R<0x38678000>, Sched<[WriteAtomic]>;
+def AMMIN_WU : AM_3R<0x38680000>, Sched<[WriteAtomic]>;
+def AMMIN_DU : AM_3R<0x38688000>, Sched<[WriteAtomic]>;
+def AMSWAP__DB_B : AM_3R<0x385e0000>, Sched<[WriteAtomic]>;
+def AMSWAP__DB_H : AM_3R<0x385e8000>, Sched<[WriteAtomic]>;
+def AMSWAP__DB_W : AM_3R<0x38690000>, Sched<[WriteAtomic]>;
+def AMSWAP__DB_D : AM_3R<0x38698000>, Sched<[WriteAtomic]>;
+def AMADD__DB_B : AM_3R<0x385f0000>, Sched<[WriteAtomic]>;
+def AMADD__DB_H : AM_3R<0x385f8000>, Sched<[WriteAtomic]>;
+def AMADD__DB_W : AM_3R<0x386a0000>, Sched<[WriteAtomic]>;
+def AMADD__DB_D : AM_3R<0x386a8000>, Sched<[WriteAtomic]>;
+def AMAND__DB_W : AM_3R<0x386b0000>, Sched<[WriteAtomic]>;
+def AMAND__DB_D : AM_3R<0x386b8000>, Sched<[WriteAtomic]>;
+def AMOR__DB_W : AM_3R<0x386c0000>, Sched<[WriteAtomic]>;
+def AMOR__DB_D : AM_3R<0x386c8000>, Sched<[WriteAtomic]>;
+def AMXOR__DB_W : AM_3R<0x386d0000>, Sched<[WriteAtomic]>;
+def AMXOR__DB_D : AM_3R<0x386d8000>, Sched<[WriteAtomic]>;
+def AMMAX__DB_W : AM_3R<0x386e0000>, Sched<[WriteAtomic]>;
+def AMMAX__DB_D : AM_3R<0x386e8000>, Sched<[WriteAtomic]>;
+def AMMIN__DB_W : AM_3R<0x386f0000>, Sched<[WriteAtomic]>;
+def AMMIN__DB_D : AM_3R<0x386f8000>, Sched<[WriteAtomic]>;
+def AMMAX__DB_WU : AM_3R<0x38700000>, Sched<[WriteAtomic]>;
+def AMMAX__DB_DU : AM_3R<0x38708000>, Sched<[WriteAtomic]>;
+def AMMIN__DB_WU : AM_3R<0x38710000>, Sched<[WriteAtomic]>;
+def AMMIN__DB_DU : AM_3R<0x38718000>, Sched<[WriteAtomic]>;
+def AMCAS_B : AMCAS_3R<0x38580000>, Sched<[WriteAtomic]>;
+def AMCAS_H : AMCAS_3R<0x38588000>, Sched<[WriteAtomic]>;
+def AMCAS_W : AMCAS_3R<0x38590000>, Sched<[WriteAtomic]>;
+def AMCAS_D : AMCAS_3R<0x38598000>, Sched<[WriteAtomic]>;
+def AMCAS__DB_B : AMCAS_3R<0x385a0000>, Sched<[WriteAtomic]>;
+def AMCAS__DB_H : AMCAS_3R<0x385a8000>, Sched<[WriteAtomic]>;
+def AMCAS__DB_W : AMCAS_3R<0x385b0000>, Sched<[WriteAtomic]>;
+def AMCAS__DB_D : AMCAS_3R<0x385b8000>, Sched<[WriteAtomic]>;
+def LL_D : LLBase<0x22000000>, Sched<[WriteAtomic]>;
+def SC_D : SCBase<0x23000000>, Sched<[WriteAtomic]>;
+def SC_Q : SCBase_128<0x38570000>, Sched<[WriteAtomic]>;
+def LLACQ_W : LLBase_ACQ<0x38578000>, Sched<[WriteAtomic]>;
+def SCREL_W : SCBase_REL<0x38578400>, Sched<[WriteAtomic]>;
+def LLACQ_D : LLBase_ACQ<0x38578800>, Sched<[WriteAtomic]>;
+def SCREL_D : SCBase_REL<0x38578C00>, Sched<[WriteAtomic]>;
// CRC Check Instructions
-def CRC_W_B_W : ALU_3R<0x00240000>;
-def CRC_W_H_W : ALU_3R<0x00248000>;
-def CRC_W_W_W : ALU_3R<0x00250000>;
-def CRC_W_D_W : ALU_3R<0x00258000>;
-def CRCC_W_B_W : ALU_3R<0x00260000>;
-def CRCC_W_H_W : ALU_3R<0x00268000>;
-def CRCC_W_W_W : ALU_3R<0x00270000>;
-def CRCC_W_D_W : ALU_3R<0x00278000>;
+def CRC_W_B_W : ALU_3R<0x00240000>, Sched<[]>;
+def CRC_W_H_W : ALU_3R<0x00248000>, Sched<[]>;
+def CRC_W_W_W : ALU_3R<0x00250000>, Sched<[]>;
+def CRC_W_D_W : ALU_3R<0x00258000>, Sched<[]>;
+def CRCC_W_B_W : ALU_3R<0x00260000>, Sched<[]>;
+def CRCC_W_H_W : ALU_3R<0x00268000>, Sched<[]>;
+def CRCC_W_W_W : ALU_3R<0x00270000>, Sched<[]>;
+def CRCC_W_D_W : ALU_3R<0x00278000>, Sched<[]>;
// Other Miscellaneous Instructions for 64-bits
def ASRTLE_D : FmtASRT<0x00010000, (outs), (ins GPR:$rj, GPR:$rk),
- "$rj, $rk">;
+ "$rj, $rk">,
+ Sched<[]>;
def ASRTGT_D : FmtASRT<0x00018000, (outs), (ins GPR:$rj, GPR:$rk),
- "$rj, $rk">;
-def RDTIME_D : RDTIME_2R<0x00006800>;
+ "$rj, $rk">,
+ Sched<[]>;
+def RDTIME_D : RDTIME_2R<0x00006800>, Sched<[]>;
} // Predicates = [IsLA64]
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index f3f19264ce3d3..374467ae063d4 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -224,848 +224,1476 @@ class LASX3R_Store<bits<32> op>
let hasSideEffects = 0, Predicates = [HasExtLASX] in {
let mayLoad = 0, mayStore = 0 in {
-def XVADD_B : LASX3R_XXX<0x740a0000>;
-def XVADD_H : LASX3R_XXX<0x740a8000>;
-def XVADD_W : LASX3R_XXX<0x740b0000>;
-def XVADD_D : LASX3R_XXX<0x740b8000>;
-def XVADD_Q : LASX3R_XXX<0x752d0000>;
-
-def XVSUB_B : LASX3R_XXX<0x740c0000>;
-def XVSUB_H : LASX3R_XXX<0x740c8000>;
-def XVSUB_W : LASX3R_XXX<0x740d0000>;
-def XVSUB_D : LASX3R_XXX<0x740d8000>;
-def XVSUB_Q : LASX3R_XXX<0x752d8000>;
-
-def XVADDI_BU : LASX2RI5_XXI<0x768a0000>;
-def XVADDI_HU : LASX2RI5_XXI<0x768a8000>;
-def XVADDI_WU : LASX2RI5_XXI<0x768b0000>;
-def XVADDI_DU : LASX2RI5_XXI<0x768b8000>;
-
-def XVSUBI_BU : LASX2RI5_XXI<0x768c0000>;
-def XVSUBI_HU : LASX2RI5_XXI<0x768c8000>;
-def XVSUBI_WU : LASX2RI5_XXI<0x768d0000>;
-def XVSUBI_DU : LASX2RI5_XXI<0x768d8000>;
-
-def XVNEG_B : LASX2R_XX<0x769c3000>;
-def XVNEG_H : LASX2R_XX<0x769c3400>;
-def XVNEG_W : LASX2R_XX<0x769c3800>;
-def XVNEG_D : LASX2R_XX<0x769c3c00>;
-
-def XVSADD_B : LASX3R_XXX<0x74460000>;
-def XVSADD_H : LASX3R_XXX<0x74468000>;
-def XVSADD_W : LASX3R_XXX<0x74470000>;
-def XVSADD_D : LASX3R_XXX<0x74478000>;
-def XVSADD_BU : LASX3R_XXX<0x744a0000>;
-def XVSADD_HU : LASX3R_XXX<0x744a8000>;
-def XVSADD_WU : LASX3R_XXX<0x744b0000>;
-def XVSADD_DU : LASX3R_XXX<0x744b8000>;
-
-def XVSSUB_B : LASX3R_XXX<0x74480000>;
-def XVSSUB_H : LASX3R_XXX<0x74488000>;
-def XVSSUB_W : LASX3R_XXX<0x74490000>;
-def XVSSUB_D : LASX3R_XXX<0x74498000>;
-def XVSSUB_BU : LASX3R_XXX<0x744c0000>;
-def XVSSUB_HU : LASX3R_XXX<0x744c8000>;
-def XVSSUB_WU : LASX3R_XXX<0x744d0000>;
-def XVSSUB_DU : LASX3R_XXX<0x744d8000>;
-
-def XVHADDW_H_B : LASX3R_XXX<0x74540000>;
-def XVHADDW_W_H : LASX3R_XXX<0x74548000>;
-def XVHADDW_D_W : LASX3R_XXX<0x74550000>;
-def XVHADDW_Q_D : LASX3R_XXX<0x74558000>;
-def XVHADDW_HU_BU : LASX3R_XXX<0x74580000>;
-def XVHADDW_WU_HU : LASX3R_XXX<0x74588000>;
-def XVHADDW_DU_WU : LASX3R_XXX<0x74590000>;
-def XVHADDW_QU_DU : LASX3R_XXX<0x74598000>;
-
-def XVHSUBW_H_B : LASX3R_XXX<0x74560000>;
-def XVHSUBW_W_H : LASX3R_XXX<0x74568000>;
-def XVHSUBW_D_W : LASX3R_XXX<0x74570000>;
-def XVHSUBW_Q_D : LASX3R_XXX<0x74578000>;
-def XVHSUBW_HU_BU : LASX3R_XXX<0x745a0000>;
-def XVHSUBW_WU_HU : LASX3R_XXX<0x745a8000>;
-def XVHSUBW_DU_WU : LASX3R_XXX<0x745b0000>;
-def XVHSUBW_QU_DU : LASX3R_XXX<0x745b8000>;
-
-def XVADDWEV_H_B : LASX3R_XXX<0x741e0000>;
-def XVADDWEV_W_H : LASX3R_XXX<0x741e8000>;
-def XVADDWEV_D_W : LASX3R_XXX<0x741f0000>;
-def XVADDWEV_Q_D : LASX3R_XXX<0x741f8000>;
-def XVADDWOD_H_B : LASX3R_XXX<0x74220000>;
-def XVADDWOD_W_H : LASX3R_XXX<0x74228000>;
-def XVADDWOD_D_W : LASX3R_XXX<0x74230000>;
-def XVADDWOD_Q_D : LASX3R_XXX<0x74238000>;
-
-def XVSUBWEV_H_B : LASX3R_XXX<0x74200000>;
-def XVSUBWEV_W_H : LASX3R_XXX<0x74208000>;
-def XVSUBWEV_D_W : LASX3R_XXX<0x74210000>;
-def XVSUBWEV_Q_D : LASX3R_XXX<0x74218000>;
-def XVSUBWOD_H_B : LASX3R_XXX<0x74240000>;
-def XVSUBWOD_W_H : LASX3R_XXX<0x74248000>;
-def XVSUBWOD_D_W : LASX3R_XXX<0x74250000>;
-def XVSUBWOD_Q_D : LASX3R_XXX<0x74258000>;
-
-def XVADDWEV_H_BU : LASX3R_XXX<0x742e0000>;
-def XVADDWEV_W_HU : LASX3R_XXX<0x742e8000>;
-def XVADDWEV_D_WU : LASX3R_XXX<0x742f0000>;
-def XVADDWEV_Q_DU : LASX3R_XXX<0x742f8000>;
-def XVADDWOD_H_BU : LASX3R_XXX<0x74320000>;
-def XVADDWOD_W_HU : LASX3R_XXX<0x74328000>;
-def XVADDWOD_D_WU : LASX3R_XXX<0x74330000>;
-def XVADDWOD_Q_DU : LASX3R_XXX<0x74338000>;
-
-def XVSUBWEV_H_BU : LASX3R_XXX<0x74300000>;
-def XVSUBWEV_W_HU : LASX3R_XXX<0x74308000>;
-def XVSUBWEV_D_WU : LASX3R_XXX<0x74310000>;
-def XVSUBWEV_Q_DU : LASX3R_XXX<0x74318000>;
-def XVSUBWOD_H_BU : LASX3R_XXX<0x74340000>;
-def XVSUBWOD_W_HU : LASX3R_XXX<0x74348000>;
-def XVSUBWOD_D_WU : LASX3R_XXX<0x74350000>;
-def XVSUBWOD_Q_DU : LASX3R_XXX<0x74358000>;
-
-def XVADDWEV_H_BU_B : LASX3R_XXX<0x743e0000>;
-def XVADDWEV_W_HU_H : LASX3R_XXX<0x743e8000>;
-def XVADDWEV_D_WU_W : LASX3R_XXX<0x743f0000>;
-def XVADDWEV_Q_DU_D : LASX3R_XXX<0x743f8000>;
-def XVADDWOD_H_BU_B : LASX3R_XXX<0x74400000>;
-def XVADDWOD_W_HU_H : LASX3R_XXX<0x74408000>;
-def XVADDWOD_D_WU_W : LASX3R_XXX<0x74410000>;
-def XVADDWOD_Q_DU_D : LASX3R_XXX<0x74418000>;
-
-def XVAVG_B : LASX3R_XXX<0x74640000>;
-def XVAVG_H : LASX3R_XXX<0x74648000>;
-def XVAVG_W : LASX3R_XXX<0x74650000>;
-def XVAVG_D : LASX3R_XXX<0x74658000>;
-def XVAVG_BU : LASX3R_XXX<0x74660000>;
-def XVAVG_HU : LASX3R_XXX<0x74668000>;
-def XVAVG_WU : LASX3R_XXX<0x74670000>;
-def XVAVG_DU : LASX3R_XXX<0x74678000>;
-def XVAVGR_B : LASX3R_XXX<0x74680000>;
-def XVAVGR_H : LASX3R_XXX<0x74688000>;
-def XVAVGR_W : LASX3R_XXX<0x74690000>;
-def XVAVGR_D : LASX3R_XXX<0x74698000>;
-def XVAVGR_BU : LASX3R_XXX<0x746a0000>;
-def XVAVGR_HU : LASX3R_XXX<0x746a8000>;
-def XVAVGR_WU : LASX3R_XXX<0x746b0000>;
-def XVAVGR_DU : LASX3R_XXX<0x746b8000>;
-
-def XVABSD_B : LASX3R_XXX<0x74600000>;
-def XVABSD_H : LASX3R_XXX<0x74608000>;
-def XVABSD_W : LASX3R_XXX<0x74610000>;
-def XVABSD_D : LASX3R_XXX<0x74618000>;
-def XVABSD_BU : LASX3R_XXX<0x74620000>;
-def XVABSD_HU : LASX3R_XXX<0x74628000>;
-def XVABSD_WU : LASX3R_XXX<0x74630000>;
-def XVABSD_DU : LASX3R_XXX<0x74638000>;
-
-def XVADDA_B : LASX3R_XXX<0x745c0000>;
-def XVADDA_H : LASX3R_XXX<0x745c8000>;
-def XVADDA_W : LASX3R_XXX<0x745d0000>;
-def XVADDA_D : LASX3R_XXX<0x745d8000>;
-
-def XVMAX_B : LASX3R_XXX<0x74700000>;
-def XVMAX_H : LASX3R_XXX<0x74708000>;
-def XVMAX_W : LASX3R_XXX<0x74710000>;
-def XVMAX_D : LASX3R_XXX<0x74718000>;
-def XVMAXI_B : LASX2RI5_XXI<0x76900000, simm5>;
-def XVMAXI_H : LASX2RI5_XXI<0x76908000, simm5>;
-def XVMAXI_W : LASX2RI5_XXI<0x76910000, simm5>;
-def XVMAXI_D : LASX2RI5_XXI<0x76918000, simm5>;
-def XVMAX_BU : LASX3R_XXX<0x74740000>;
-def XVMAX_HU : LASX3R_XXX<0x74748000>;
-def XVMAX_WU : LASX3R_XXX<0x74750000>;
-def XVMAX_DU : LASX3R_XXX<0x74758000>;
-def XVMAXI_BU : LASX2RI5_XXI<0x76940000>;
-def XVMAXI_HU : LASX2RI5_XXI<0x76948000>;
-def XVMAXI_WU : LASX2RI5_XXI<0x76950000>;
-def XVMAXI_DU : LASX2RI5_XXI<0x76958000>;
-
-def XVMIN_B : LASX3R_XXX<0x74720000>;
-def XVMIN_H : LASX3R_XXX<0x74728000>;
-def XVMIN_W : LASX3R_XXX<0x74730000>;
-def XVMIN_D : LASX3R_XXX<0x74738000>;
-def XVMINI_B : LASX2RI5_XXI<0x76920000, simm5>;
-def XVMINI_H : LASX2RI5_XXI<0x76928000, simm5>;
-def XVMINI_W : LASX2RI5_XXI<0x76930000, simm5>;
-def XVMINI_D : LASX2RI5_XXI<0x76938000, simm5>;
-def XVMIN_BU : LASX3R_XXX<0x74760000>;
-def XVMIN_HU : LASX3R_XXX<0x74768000>;
-def XVMIN_WU : LASX3R_XXX<0x74770000>;
-def XVMIN_DU : LASX3R_XXX<0x74778000>;
-def XVMINI_BU : LASX2RI5_XXI<0x76960000>;
-def XVMINI_HU : LASX2RI5_XXI<0x76968000>;
-def XVMINI_WU : LASX2RI5_XXI<0x76970000>;
-def XVMINI_DU : LASX2RI5_XXI<0x76978000>;
-
-def XVMUL_B : LASX3R_XXX<0x74840000>;
-def XVMUL_H : LASX3R_XXX<0x74848000>;
-def XVMUL_W : LASX3R_XXX<0x74850000>;
-def XVMUL_D : LASX3R_XXX<0x74858000>;
-
-def XVMUH_B : LASX3R_XXX<0x74860000>;
-def XVMUH_H : LASX3R_XXX<0x74868000>;
-def XVMUH_W : LASX3R_XXX<0x74870000>;
-def XVMUH_D : LASX3R_XXX<0x74878000>;
-def XVMUH_BU : LASX3R_XXX<0x74880000>;
-def XVMUH_HU : LASX3R_XXX<0x74888000>;
-def XVMUH_WU : LASX3R_XXX<0x74890000>;
-def XVMUH_DU : LASX3R_XXX<0x74898000>;
-
-def XVMULWEV_H_B : LASX3R_XXX<0x74900000>;
-def XVMULWEV_W_H : LASX3R_XXX<0x74908000>;
-def XVMULWEV_D_W : LASX3R_XXX<0x74910000>;
-def XVMULWEV_Q_D : LASX3R_XXX<0x74918000>;
-def XVMULWOD_H_B : LASX3R_XXX<0x74920000>;
-def XVMULWOD_W_H : LASX3R_XXX<0x74928000>;
-def XVMULWOD_D_W : LASX3R_XXX<0x74930000>;
-def XVMULWOD_Q_D : LASX3R_XXX<0x74938000>;
-def XVMULWEV_H_BU : LASX3R_XXX<0x74980000>;
-def XVMULWEV_W_HU : LASX3R_XXX<0x74988000>;
-def XVMULWEV_D_WU : LASX3R_XXX<0x74990000>;
-def XVMULWEV_Q_DU : LASX3R_XXX<0x74998000>;
-def XVMULWOD_H_BU : LASX3R_XXX<0x749a0000>;
-def XVMULWOD_W_HU : LASX3R_XXX<0x749a8000>;
-def XVMULWOD_D_WU : LASX3R_XXX<0x749b0000>;
-def XVMULWOD_Q_DU : LASX3R_XXX<0x749b8000>;
-def XVMULWEV_H_BU_B : LASX3R_XXX<0x74a00000>;
-def XVMULWEV_W_HU_H : LASX3R_XXX<0x74a08000>;
-def XVMULWEV_D_WU_W : LASX3R_XXX<0x74a10000>;
-def XVMULWEV_Q_DU_D : LASX3R_XXX<0x74a18000>;
-def XVMULWOD_H_BU_B : LASX3R_XXX<0x74a20000>;
-def XVMULWOD_W_HU_H : LASX3R_XXX<0x74a28000>;
-def XVMULWOD_D_WU_W : LASX3R_XXX<0x74a30000>;
-def XVMULWOD_Q_DU_D : LASX3R_XXX<0x74a38000>;
-
-def XVMADD_B : LASX3R_XXXX<0x74a80000>;
-def XVMADD_H : LASX3R_XXXX<0x74a88000>;
-def XVMADD_W : LASX3R_XXXX<0x74a90000>;
-def XVMADD_D : LASX3R_XXXX<0x74a98000>;
-
-def XVMSUB_B : LASX3R_XXXX<0x74aa0000>;
-def XVMSUB_H : LASX3R_XXXX<0x74aa8000>;
-def XVMSUB_W : LASX3R_XXXX<0x74ab0000>;
-def XVMSUB_D : LASX3R_XXXX<0x74ab8000>;
-
-def XVMADDWEV_H_B : LASX3R_XXXX<0x74ac0000>;
-def XVMADDWEV_W_H : LASX3R_XXXX<0x74ac8000>;
-def XVMADDWEV_D_W : LASX3R_XXXX<0x74ad0000>;
-def XVMADDWEV_Q_D : LASX3R_XXXX<0x74ad8000>;
-def XVMADDWOD_H_B : LASX3R_XXXX<0x74ae0000>;
-def XVMADDWOD_W_H : LASX3R_XXXX<0x74ae8000>;
-def XVMADDWOD_D_W : LASX3R_XXXX<0x74af0000>;
-def XVMADDWOD_Q_D : LASX3R_XXXX<0x74af8000>;
-def XVMADDWEV_H_BU : LASX3R_XXXX<0x74b40000>;
-def XVMADDWEV_W_HU : LASX3R_XXXX<0x74b48000>;
-def XVMADDWEV_D_WU : LASX3R_XXXX<0x74b50000>;
-def XVMADDWEV_Q_DU : LASX3R_XXXX<0x74b58000>;
-def XVMADDWOD_H_BU : LASX3R_XXXX<0x74b60000>;
-def XVMADDWOD_W_HU : LASX3R_XXXX<0x74b68000>;
-def XVMADDWOD_D_WU : LASX3R_XXXX<0x74b70000>;
-def XVMADDWOD_Q_DU : LASX3R_XXXX<0x74b78000>;
-def XVMADDWEV_H_BU_B : LASX3R_XXXX<0x74bc0000>;
-def XVMADDWEV_W_HU_H : LASX3R_XXXX<0x74bc8000>;
-def XVMADDWEV_D_WU_W : LASX3R_XXXX<0x74bd0000>;
-def XVMADDWEV_Q_DU_D : LASX3R_XXXX<0x74bd8000>;
-def XVMADDWOD_H_BU_B : LASX3R_XXXX<0x74be0000>;
-def XVMADDWOD_W_HU_H : LASX3R_XXXX<0x74be8000>;
-def XVMADDWOD_D_WU_W : LASX3R_XXXX<0x74bf0000>;
-def XVMADDWOD_Q_DU_D : LASX3R_XXXX<0x74bf8000>;
-
-def XVDIV_B : LASX3R_XXX<0x74e00000>;
-def XVDIV_H : LASX3R_XXX<0x74e08000>;
-def XVDIV_W : LASX3R_XXX<0x74e10000>;
-def XVDIV_D : LASX3R_XXX<0x74e18000>;
-def XVDIV_BU : LASX3R_XXX<0x74e40000>;
-def XVDIV_HU : LASX3R_XXX<0x74e48000>;
-def XVDIV_WU : LASX3R_XXX<0x74e50000>;
-def XVDIV_DU : LASX3R_XXX<0x74e58000>;
-
-def XVMOD_B : LASX3R_XXX<0x74e20000>;
-def XVMOD_H : LASX3R_XXX<0x74e28000>;
-def XVMOD_W : LASX3R_XXX<0x74e30000>;
-def XVMOD_D : LASX3R_XXX<0x74e38000>;
-def XVMOD_BU : LASX3R_XXX<0x74e60000>;
-def XVMOD_HU : LASX3R_XXX<0x74e68000>;
-def XVMOD_WU : LASX3R_XXX<0x74e70000>;
-def XVMOD_DU : LASX3R_XXX<0x74e78000>;
-
-def XVSAT_B : LASX2RI3_XXI<0x77242000>;
-def XVSAT_H : LASX2RI4_XXI<0x77244000>;
-def XVSAT_W : LASX2RI5_XXI<0x77248000>;
-def XVSAT_D : LASX2RI6_XXI<0x77250000>;
-def XVSAT_BU : LASX2RI3_XXI<0x77282000>;
-def XVSAT_HU : LASX2RI4_XXI<0x77284000>;
-def XVSAT_WU : LASX2RI5_XXI<0x77288000>;
-def XVSAT_DU : LASX2RI6_XXI<0x77290000>;
-
-def XVEXTH_H_B : LASX2R_XX<0x769ee000>;
-def XVEXTH_W_H : LASX2R_XX<0x769ee400>;
-def XVEXTH_D_W : LASX2R_XX<0x769ee800>;
-def XVEXTH_Q_D : LASX2R_XX<0x769eec00>;
-def XVEXTH_HU_BU : LASX2R_XX<0x769ef000>;
-def XVEXTH_WU_HU : LASX2R_XX<0x769ef400>;
-def XVEXTH_DU_WU : LASX2R_XX<0x769ef800>;
-def XVEXTH_QU_DU : LASX2R_XX<0x769efc00>;
-
-def VEXT2XV_H_B : LASX2R_XX<0x769f1000>;
-def VEXT2XV_W_B : LASX2R_XX<0x769f1400>;
-def VEXT2XV_D_B : LASX2R_XX<0x769f1800>;
-def VEXT2XV_W_H : LASX2R_XX<0x769f1c00>;
-def VEXT2XV_D_H : LASX2R_XX<0x769f2000>;
-def VEXT2XV_D_W : LASX2R_XX<0x769f2400>;
-def VEXT2XV_HU_BU : LASX2R_XX<0x769f2800>;
-def VEXT2XV_WU_BU : LASX2R_XX<0x769f2c00>;
-def VEXT2XV_DU_BU : LASX2R_XX<0x769f3000>;
-def VEXT2XV_WU_HU : LASX2R_XX<0x769f3400>;
-def VEXT2XV_DU_HU : LASX2R_XX<0x769f3800>;
-def VEXT2XV_DU_WU : LASX2R_XX<0x769f3c00>;
-
-def XVHSELI_D : LASX2RI5_XXI<0x769f8000>;
-
-def XVSIGNCOV_B : LASX3R_XXX<0x752e0000>;
-def XVSIGNCOV_H : LASX3R_XXX<0x752e8000>;
-def XVSIGNCOV_W : LASX3R_XXX<0x752f0000>;
-def XVSIGNCOV_D : LASX3R_XXX<0x752f8000>;
-
-def XVMSKLTZ_B : LASX2R_XX<0x769c4000>;
-def XVMSKLTZ_H : LASX2R_XX<0x769c4400>;
-def XVMSKLTZ_W : LASX2R_XX<0x769c4800>;
-def XVMSKLTZ_D : LASX2R_XX<0x769c4c00>;
-
-def XVMSKGEZ_B : LASX2R_XX<0x769c5000>;
-
-def XVMSKNZ_B : LASX2R_XX<0x769c6000>;
-
-def XVLDI : LASX1RI13_XI<0x77e00000>;
-
-def XVAND_V : LASX3R_XXX<0x75260000>;
-def XVOR_V : LASX3R_XXX<0x75268000>;
-def XVXOR_V : LASX3R_XXX<0x75270000>;
-def XVNOR_V : LASX3R_XXX<0x75278000>;
-def XVANDN_V : LASX3R_XXX<0x75280000>;
-def XVORN_V : LASX3R_XXX<0x75288000>;
-
-def XVANDI_B : LASX2RI8_XXI<0x77d00000>;
-def XVORI_B : LASX2RI8_XXI<0x77d40000>;
-def XVXORI_B : LASX2RI8_XXI<0x77d80000>;
-def XVNORI_B : LASX2RI8_XXI<0x77dc0000>;
-
-def XVSLL_B : LASX3R_XXX<0x74e80000>;
-def XVSLL_H : LASX3R_XXX<0x74e88000>;
-def XVSLL_W : LASX3R_XXX<0x74e90000>;
-def XVSLL_D : LASX3R_XXX<0x74e98000>;
-def XVSLLI_B : LASX2RI3_XXI<0x772c2000>;
-def XVSLLI_H : LASX2RI4_XXI<0x772c4000>;
-def XVSLLI_W : LASX2RI5_XXI<0x772c8000>;
-def XVSLLI_D : LASX2RI6_XXI<0x772d0000>;
-
-def XVSRL_B : LASX3R_XXX<0x74ea0000>;
-def XVSRL_H : LASX3R_XXX<0x74ea8000>;
-def XVSRL_W : LASX3R_XXX<0x74eb0000>;
-def XVSRL_D : LASX3R_XXX<0x74eb8000>;
-def XVSRLI_B : LASX2RI3_XXI<0x77302000>;
-def XVSRLI_H : LASX2RI4_XXI<0x77304000>;
-def XVSRLI_W : LASX2RI5_XXI<0x77308000>;
-def XVSRLI_D : LASX2RI6_XXI<0x77310000>;
-
-def XVSRA_B : LASX3R_XXX<0x74ec0000>;
-def XVSRA_H : LASX3R_XXX<0x74ec8000>;
-def XVSRA_W : LASX3R_XXX<0x74ed0000>;
-def XVSRA_D : LASX3R_XXX<0x74ed8000>;
-def XVSRAI_B : LASX2RI3_XXI<0x77342000>;
-def XVSRAI_H : LASX2RI4_XXI<0x77344000>;
-def XVSRAI_W : LASX2RI5_XXI<0x77348000>;
-def XVSRAI_D : LASX2RI6_XXI<0x77350000>;
-
-def XVROTR_B : LASX3R_XXX<0x74ee0000>;
-def XVROTR_H : LASX3R_XXX<0x74ee8000>;
-def XVROTR_W : LASX3R_XXX<0x74ef0000>;
-def XVROTR_D : LASX3R_XXX<0x74ef8000>;
-def XVROTRI_B : LASX2RI3_XXI<0x76a02000>;
-def XVROTRI_H : LASX2RI4_XXI<0x76a04000>;
-def XVROTRI_W : LASX2RI5_XXI<0x76a08000>;
-def XVROTRI_D : LASX2RI6_XXI<0x76a10000>;
-
-def XVSLLWIL_H_B : LASX2RI3_XXI<0x77082000>;
-def XVSLLWIL_W_H : LASX2RI4_XXI<0x77084000>;
-def XVSLLWIL_D_W : LASX2RI5_XXI<0x77088000>;
-def XVEXTL_Q_D : LASX2R_XX<0x77090000>;
-def XVSLLWIL_HU_BU : LASX2RI3_XXI<0x770c2000>;
-def XVSLLWIL_WU_HU : LASX2RI4_XXI<0x770c4000>;
-def XVSLLWIL_DU_WU : LASX2RI5_XXI<0x770c8000>;
-def XVEXTL_QU_DU : LASX2R_XX<0x770d0000>;
-
-def XVSRLR_B : LASX3R_XXX<0x74f00000>;
-def XVSRLR_H : LASX3R_XXX<0x74f08000>;
-def XVSRLR_W : LASX3R_XXX<0x74f10000>;
-def XVSRLR_D : LASX3R_XXX<0x74f18000>;
-def XVSRLRI_B : LASX2RI3_XXI<0x76a42000>;
-def XVSRLRI_H : LASX2RI4_XXI<0x76a44000>;
-def XVSRLRI_W : LASX2RI5_XXI<0x76a48000>;
-def XVSRLRI_D : LASX2RI6_XXI<0x76a50000>;
-
-def XVSRAR_B : LASX3R_XXX<0x74f20000>;
-def XVSRAR_H : LASX3R_XXX<0x74f28000>;
-def XVSRAR_W : LASX3R_XXX<0x74f30000>;
-def XVSRAR_D : LASX3R_XXX<0x74f38000>;
-def XVSRARI_B : LASX2RI3_XXI<0x76a82000>;
-def XVSRARI_H : LASX2RI4_XXI<0x76a84000>;
-def XVSRARI_W : LASX2RI5_XXI<0x76a88000>;
-def XVSRARI_D : LASX2RI6_XXI<0x76a90000>;
-
-def XVSRLN_B_H : LASX3R_XXX<0x74f48000>;
-def XVSRLN_H_W : LASX3R_XXX<0x74f50000>;
-def XVSRLN_W_D : LASX3R_XXX<0x74f58000>;
-def XVSRAN_B_H : LASX3R_XXX<0x74f68000>;
-def XVSRAN_H_W : LASX3R_XXX<0x74f70000>;
-def XVSRAN_W_D : LASX3R_XXX<0x74f78000>;
-
-def XVSRLNI_B_H : LASX2RI4_XXXI<0x77404000>;
-def XVSRLNI_H_W : LASX2RI5_XXXI<0x77408000>;
-def XVSRLNI_W_D : LASX2RI6_XXXI<0x77410000>;
-def XVSRLNI_D_Q : LASX2RI7_XXXI<0x77420000>;
-def XVSRANI_B_H : LASX2RI4_XXXI<0x77584000>;
-def XVSRANI_H_W : LASX2RI5_XXXI<0x77588000>;
-def XVSRANI_W_D : LASX2RI6_XXXI<0x77590000>;
-def XVSRANI_D_Q : LASX2RI7_XXXI<0x775a0000>;
-
-def XVSRLRN_B_H : LASX3R_XXX<0x74f88000>;
-def XVSRLRN_H_W : LASX3R_XXX<0x74f90000>;
-def XVSRLRN_W_D : LASX3R_XXX<0x74f98000>;
-def XVSRARN_B_H : LASX3R_XXX<0x74fa8000>;
-def XVSRARN_H_W : LASX3R_XXX<0x74fb0000>;
-def XVSRARN_W_D : LASX3R_XXX<0x74fb8000>;
-
-def XVSRLRNI_B_H : LASX2RI4_XXXI<0x77444000>;
-def XVSRLRNI_H_W : LASX2RI5_XXXI<0x77448000>;
-def XVSRLRNI_W_D : LASX2RI6_XXXI<0x77450000>;
-def XVSRLRNI_D_Q : LASX2RI7_XXXI<0x77460000>;
-def XVSRARNI_B_H : LASX2RI4_XXXI<0x775c4000>;
-def XVSRARNI_H_W : LASX2RI5_XXXI<0x775c8000>;
-def XVSRARNI_W_D : LASX2RI6_XXXI<0x775d0000>;
-def XVSRARNI_D_Q : LASX2RI7_XXXI<0x775e0000>;
-
-def XVSSRLN_B_H : LASX3R_XXX<0x74fc8000>;
-def XVSSRLN_H_W : LASX3R_XXX<0x74fd0000>;
-def XVSSRLN_W_D : LASX3R_XXX<0x74fd8000>;
-def XVSSRAN_B_H : LASX3R_XXX<0x74fe8000>;
-def XVSSRAN_H_W : LASX3R_XXX<0x74ff0000>;
-def XVSSRAN_W_D : LASX3R_XXX<0x74ff8000>;
-def XVSSRLN_BU_H : LASX3R_XXX<0x75048000>;
-def XVSSRLN_HU_W : LASX3R_XXX<0x75050000>;
-def XVSSRLN_WU_D : LASX3R_XXX<0x75058000>;
-def XVSSRAN_BU_H : LASX3R_XXX<0x75068000>;
-def XVSSRAN_HU_W : LASX3R_XXX<0x75070000>;
-def XVSSRAN_WU_D : LASX3R_XXX<0x75078000>;
-
-def XVSSRLNI_B_H : LASX2RI4_XXXI<0x77484000>;
-def XVSSRLNI_H_W : LASX2RI5_XXXI<0x77488000>;
-def XVSSRLNI_W_D : LASX2RI6_XXXI<0x77490000>;
-def XVSSRLNI_D_Q : LASX2RI7_XXXI<0x774a0000>;
-def XVSSRANI_B_H : LASX2RI4_XXXI<0x77604000>;
-def XVSSRANI_H_W : LASX2RI5_XXXI<0x77608000>;
-def XVSSRANI_W_D : LASX2RI6_XXXI<0x77610000>;
-def XVSSRANI_D_Q : LASX2RI7_XXXI<0x77620000>;
-def XVSSRLNI_BU_H : LASX2RI4_XXXI<0x774c4000>;
-def XVSSRLNI_HU_W : LASX2RI5_XXXI<0x774c8000>;
-def XVSSRLNI_WU_D : LASX2RI6_XXXI<0x774d0000>;
-def XVSSRLNI_DU_Q : LASX2RI7_XXXI<0x774e0000>;
-def XVSSRANI_BU_H : LASX2RI4_XXXI<0x77644000>;
-def XVSSRANI_HU_W : LASX2RI5_XXXI<0x77648000>;
-def XVSSRANI_WU_D : LASX2RI6_XXXI<0x77650000>;
-def XVSSRANI_DU_Q : LASX2RI7_XXXI<0x77660000>;
-
-def XVSSRLRN_B_H : LASX3R_XXX<0x75008000>;
-def XVSSRLRN_H_W : LASX3R_XXX<0x75010000>;
-def XVSSRLRN_W_D : LASX3R_XXX<0x75018000>;
-def XVSSRARN_B_H : LASX3R_XXX<0x75028000>;
-def XVSSRARN_H_W : LASX3R_XXX<0x75030000>;
-def XVSSRARN_W_D : LASX3R_XXX<0x75038000>;
-def XVSSRLRN_BU_H : LASX3R_XXX<0x75088000>;
-def XVSSRLRN_HU_W : LASX3R_XXX<0x75090000>;
-def XVSSRLRN_WU_D : LASX3R_XXX<0x75098000>;
-def XVSSRARN_BU_H : LASX3R_XXX<0x750a8000>;
-def XVSSRARN_HU_W : LASX3R_XXX<0x750b0000>;
-def XVSSRARN_WU_D : LASX3R_XXX<0x750b8000>;
-
-def XVSSRLRNI_B_H : LASX2RI4_XXXI<0x77504000>;
-def XVSSRLRNI_H_W : LASX2RI5_XXXI<0x77508000>;
-def XVSSRLRNI_W_D : LASX2RI6_XXXI<0x77510000>;
-def XVSSRLRNI_D_Q : LASX2RI7_XXXI<0x77520000>;
-def XVSSRARNI_B_H : LASX2RI4_XXXI<0x77684000>;
-def XVSSRARNI_H_W : LASX2RI5_XXXI<0x77688000>;
-def XVSSRARNI_W_D : LASX2RI6_XXXI<0x77690000>;
-def XVSSRARNI_D_Q : LASX2RI7_XXXI<0x776a0000>;
-def XVSSRLRNI_BU_H : LASX2RI4_XXXI<0x77544000>;
-def XVSSRLRNI_HU_W : LASX2RI5_XXXI<0x77548000>;
-def XVSSRLRNI_WU_D : LASX2RI6_XXXI<0x77550000>;
-def XVSSRLRNI_DU_Q : LASX2RI7_XXXI<0x77560000>;
-def XVSSRARNI_BU_H : LASX2RI4_XXXI<0x776c4000>;
-def XVSSRARNI_HU_W : LASX2RI5_XXXI<0x776c8000>;
-def XVSSRARNI_WU_D : LASX2RI6_XXXI<0x776d0000>;
-def XVSSRARNI_DU_Q : LASX2RI7_XXXI<0x776e0000>;
-
-def XVCLO_B : LASX2R_XX<0x769c0000>;
-def XVCLO_H : LASX2R_XX<0x769c0400>;
-def XVCLO_W : LASX2R_XX<0x769c0800>;
-def XVCLO_D : LASX2R_XX<0x769c0c00>;
-def XVCLZ_B : LASX2R_XX<0x769c1000>;
-def XVCLZ_H : LASX2R_XX<0x769c1400>;
-def XVCLZ_W : LASX2R_XX<0x769c1800>;
-def XVCLZ_D : LASX2R_XX<0x769c1c00>;
-
-def XVPCNT_B : LASX2R_XX<0x769c2000>;
-def XVPCNT_H : LASX2R_XX<0x769c2400>;
-def XVPCNT_W : LASX2R_XX<0x769c2800>;
-def XVPCNT_D : LASX2R_XX<0x769c2c00>;
-
-def XVBITCLR_B : LASX3R_XXX<0x750c0000>;
-def XVBITCLR_H : LASX3R_XXX<0x750c8000>;
-def XVBITCLR_W : LASX3R_XXX<0x750d0000>;
-def XVBITCLR_D : LASX3R_XXX<0x750d8000>;
-def XVBITCLRI_B : LASX2RI3_XXI<0x77102000>;
-def XVBITCLRI_H : LASX2RI4_XXI<0x77104000>;
-def XVBITCLRI_W : LASX2RI5_XXI<0x77108000>;
-def XVBITCLRI_D : LASX2RI6_XXI<0x77110000>;
-
-def XVBITSET_B : LASX3R_XXX<0x750e0000>;
-def XVBITSET_H : LASX3R_XXX<0x750e8000>;
-def XVBITSET_W : LASX3R_XXX<0x750f0000>;
-def XVBITSET_D : LASX3R_XXX<0x750f8000>;
-def XVBITSETI_B : LASX2RI3_XXI<0x77142000>;
-def XVBITSETI_H : LASX2RI4_XXI<0x77144000>;
-def XVBITSETI_W : LASX2RI5_XXI<0x77148000>;
-def XVBITSETI_D : LASX2RI6_XXI<0x77150000>;
-
-def XVBITREV_B : LASX3R_XXX<0x75100000>;
-def XVBITREV_H : LASX3R_XXX<0x75108000>;
-def XVBITREV_W : LASX3R_XXX<0x75110000>;
-def XVBITREV_D : LASX3R_XXX<0x75118000>;
-def XVBITREVI_B : LASX2RI3_XXI<0x77182000>;
-def XVBITREVI_H : LASX2RI4_XXI<0x77184000>;
-def XVBITREVI_W : LASX2RI5_XXI<0x77188000>;
-def XVBITREVI_D : LASX2RI6_XXI<0x77190000>;
-
-def XVFRSTP_B : LASX3R_XXXX<0x752b0000>;
-def XVFRSTP_H : LASX3R_XXXX<0x752b8000>;
-def XVFRSTPI_B : LASX2RI5_XXXI<0x769a0000>;
-def XVFRSTPI_H : LASX2RI5_XXXI<0x769a8000>;
-
-def XVFADD_S : LASX3R_XXX<0x75308000>;
-def XVFADD_D : LASX3R_XXX<0x75310000>;
-def XVFSUB_S : LASX3R_XXX<0x75328000>;
-def XVFSUB_D : LASX3R_XXX<0x75330000>;
-def XVFMUL_S : LASX3R_XXX<0x75388000>;
-def XVFMUL_D : LASX3R_XXX<0x75390000>;
-def XVFDIV_S : LASX3R_XXX<0x753a8000>;
-def XVFDIV_D : LASX3R_XXX<0x753b0000>;
-
-def XVFMADD_S : LASX4R_XXXX<0x0a100000>;
-def XVFMADD_D : LASX4R_XXXX<0x0a200000>;
-def XVFMSUB_S : LASX4R_XXXX<0x0a500000>;
-def XVFMSUB_D : LASX4R_XXXX<0x0a600000>;
-def XVFNMADD_S : LASX4R_XXXX<0x0a900000>;
-def XVFNMADD_D : LASX4R_XXXX<0x0aa00000>;
-def XVFNMSUB_S : LASX4R_XXXX<0x0ad00000>;
-def XVFNMSUB_D : LASX4R_XXXX<0x0ae00000>;
-
-def XVFMAX_S : LASX3R_XXX<0x753c8000>;
-def XVFMAX_D : LASX3R_XXX<0x753d0000>;
-def XVFMIN_S : LASX3R_XXX<0x753e8000>;
-def XVFMIN_D : LASX3R_XXX<0x753f0000>;
-
-def XVFMAXA_S : LASX3R_XXX<0x75408000>;
-def XVFMAXA_D : LASX3R_XXX<0x75410000>;
-def XVFMINA_S : LASX3R_XXX<0x75428000>;
-def XVFMINA_D : LASX3R_XXX<0x75430000>;
-
-def XVFLOGB_S : LASX2R_XX<0x769cc400>;
-def XVFLOGB_D : LASX2R_XX<0x769cc800>;
-
-def XVFCLASS_S : LASX2R_XX<0x769cd400>;
-def XVFCLASS_D : LASX2R_XX<0x769cd800>;
-
-def XVFSQRT_S : LASX2R_XX<0x769ce400>;
-def XVFSQRT_D : LASX2R_XX<0x769ce800>;
-def XVFRECIP_S : LASX2R_XX<0x769cf400>;
-def XVFRECIP_D : LASX2R_XX<0x769cf800>;
-def XVFRSQRT_S : LASX2R_XX<0x769d0400>;
-def XVFRSQRT_D : LASX2R_XX<0x769d0800>;
-def XVFRECIPE_S : LASX2R_XX<0x769d1400>;
-def XVFRECIPE_D : LASX2R_XX<0x769d1800>;
-def XVFRSQRTE_S : LASX2R_XX<0x769d2400>;
-def XVFRSQRTE_D : LASX2R_XX<0x769d2800>;
-
-def XVFCVTL_S_H : LASX2R_XX<0x769de800>;
-def XVFCVTH_S_H : LASX2R_XX<0x769dec00>;
-def XVFCVTL_D_S : LASX2R_XX<0x769df000>;
-def XVFCVTH_D_S : LASX2R_XX<0x769df400>;
-def XVFCVT_H_S : LASX3R_XXX<0x75460000>;
-def XVFCVT_S_D : LASX3R_XXX<0x75468000>;
-
-def XVFRINTRNE_S : LASX2R_XX<0x769d7400>;
-def XVFRINTRNE_D : LASX2R_XX<0x769d7800>;
-def XVFRINTRZ_S : LASX2R_XX<0x769d6400>;
-def XVFRINTRZ_D : LASX2R_XX<0x769d6800>;
-def XVFRINTRP_S : LASX2R_XX<0x769d5400>;
-def XVFRINTRP_D : LASX2R_XX<0x769d5800>;
-def XVFRINTRM_S : LASX2R_XX<0x769d4400>;
-def XVFRINTRM_D : LASX2R_XX<0x769d4800>;
-def XVFRINT_S : LASX2R_XX<0x769d3400>;
-def XVFRINT_D : LASX2R_XX<0x769d3800>;
-
-def XVFTINTRNE_W_S : LASX2R_XX<0x769e5000>;
-def XVFTINTRNE_L_D : LASX2R_XX<0x769e5400>;
-def XVFTINTRZ_W_S : LASX2R_XX<0x769e4800>;
-def XVFTINTRZ_L_D : LASX2R_XX<0x769e4c00>;
-def XVFTINTRP_W_S : LASX2R_XX<0x769e4000>;
-def XVFTINTRP_L_D : LASX2R_XX<0x769e4400>;
-def XVFTINTRM_W_S : LASX2R_XX<0x769e3800>;
-def XVFTINTRM_L_D : LASX2R_XX<0x769e3c00>;
-def XVFTINT_W_S : LASX2R_XX<0x769e3000>;
-def XVFTINT_L_D : LASX2R_XX<0x769e3400>;
-def XVFTINTRZ_WU_S : LASX2R_XX<0x769e7000>;
-def XVFTINTRZ_LU_D : LASX2R_XX<0x769e7400>;
-def XVFTINT_WU_S : LASX2R_XX<0x769e5800>;
-def XVFTINT_LU_D : LASX2R_XX<0x769e5c00>;
-
-def XVFTINTRNE_W_D : LASX3R_XXX<0x754b8000>;
-def XVFTINTRZ_W_D : LASX3R_XXX<0x754b0000>;
-def XVFTINTRP_W_D : LASX3R_XXX<0x754a8000>;
-def XVFTINTRM_W_D : LASX3R_XXX<0x754a0000>;
-def XVFTINT_W_D : LASX3R_XXX<0x75498000>;
-
-def XVFTINTRNEL_L_S : LASX2R_XX<0x769ea000>;
-def XVFTINTRNEH_L_S : LASX2R_XX<0x769ea400>;
-def XVFTINTRZL_L_S : LASX2R_XX<0x769e9800>;
-def XVFTINTRZH_L_S : LASX2R_XX<0x769e9c00>;
-def XVFTINTRPL_L_S : LASX2R_XX<0x769e9000>;
-def XVFTINTRPH_L_S : LASX2R_XX<0x769e9400>;
-def XVFTINTRML_L_S : LASX2R_XX<0x769e8800>;
-def XVFTINTRMH_L_S : LASX2R_XX<0x769e8c00>;
-def XVFTINTL_L_S : LASX2R_XX<0x769e8000>;
-def XVFTINTH_L_S : LASX2R_XX<0x769e8400>;
-
-def XVFFINT_S_W : LASX2R_XX<0x769e0000>;
-def XVFFINT_D_L : LASX2R_XX<0x769e0800>;
-def XVFFINT_S_WU : LASX2R_XX<0x769e0400>;
-def XVFFINT_D_LU : LASX2R_XX<0x769e0c00>;
-def XVFFINTL_D_W : LASX2R_XX<0x769e1000>;
-def XVFFINTH_D_W : LASX2R_XX<0x769e1400>;
-def XVFFINT_S_L : LASX3R_XXX<0x75480000>;
-
-def XVSEQ_B : LASX3R_XXX<0x74000000>;
-def XVSEQ_H : LASX3R_XXX<0x74008000>;
-def XVSEQ_W : LASX3R_XXX<0x74010000>;
-def XVSEQ_D : LASX3R_XXX<0x74018000>;
-def XVSEQI_B : LASX2RI5_XXI<0x76800000, simm5>;
-def XVSEQI_H : LASX2RI5_XXI<0x76808000, simm5>;
-def XVSEQI_W : LASX2RI5_XXI<0x76810000, simm5>;
-def XVSEQI_D : LASX2RI5_XXI<0x76818000, simm5>;
-
-def XVSLE_B : LASX3R_XXX<0x74020000>;
-def XVSLE_H : LASX3R_XXX<0x74028000>;
-def XVSLE_W : LASX3R_XXX<0x74030000>;
-def XVSLE_D : LASX3R_XXX<0x74038000>;
-def XVSLEI_B : LASX2RI5_XXI<0x76820000, simm5>;
-def XVSLEI_H : LASX2RI5_XXI<0x76828000, simm5>;
-def XVSLEI_W : LASX2RI5_XXI<0x76830000, simm5>;
-def XVSLEI_D : LASX2RI5_XXI<0x76838000, simm5>;
-
-def XVSLE_BU : LASX3R_XXX<0x74040000>;
-def XVSLE_HU : LASX3R_XXX<0x74048000>;
-def XVSLE_WU : LASX3R_XXX<0x74050000>;
-def XVSLE_DU : LASX3R_XXX<0x74058000>;
-def XVSLEI_BU : LASX2RI5_XXI<0x76840000>;
-def XVSLEI_HU : LASX2RI5_XXI<0x76848000>;
-def XVSLEI_WU : LASX2RI5_XXI<0x76850000>;
-def XVSLEI_DU : LASX2RI5_XXI<0x76858000>;
-
-def XVSLT_B : LASX3R_XXX<0x74060000>;
-def XVSLT_H : LASX3R_XXX<0x74068000>;
-def XVSLT_W : LASX3R_XXX<0x74070000>;
-def XVSLT_D : LASX3R_XXX<0x74078000>;
-def XVSLTI_B : LASX2RI5_XXI<0x76860000, simm5>;
-def XVSLTI_H : LASX2RI5_XXI<0x76868000, simm5>;
-def XVSLTI_W : LASX2RI5_XXI<0x76870000, simm5>;
-def XVSLTI_D : LASX2RI5_XXI<0x76878000, simm5>;
-
-def XVSLT_BU : LASX3R_XXX<0x74080000>;
-def XVSLT_HU : LASX3R_XXX<0x74088000>;
-def XVSLT_WU : LASX3R_XXX<0x74090000>;
-def XVSLT_DU : LASX3R_XXX<0x74098000>;
-def XVSLTI_BU : LASX2RI5_XXI<0x76880000>;
-def XVSLTI_HU : LASX2RI5_XXI<0x76888000>;
-def XVSLTI_WU : LASX2RI5_XXI<0x76890000>;
-def XVSLTI_DU : LASX2RI5_XXI<0x76898000>;
-
-def XVFCMP_CAF_S : LASX3R_XXX<0x0c900000>;
-def XVFCMP_SAF_S : LASX3R_XXX<0x0c908000>;
-def XVFCMP_CLT_S : LASX3R_XXX<0x0c910000>;
-def XVFCMP_SLT_S : LASX3R_XXX<0x0c918000>;
-def XVFCMP_CEQ_S : LASX3R_XXX<0x0c920000>;
-def XVFCMP_SEQ_S : LASX3R_XXX<0x0c928000>;
-def XVFCMP_CLE_S : LASX3R_XXX<0x0c930000>;
-def XVFCMP_SLE_S : LASX3R_XXX<0x0c938000>;
-def XVFCMP_CUN_S : LASX3R_XXX<0x0c940000>;
-def XVFCMP_SUN_S : LASX3R_XXX<0x0c948000>;
-def XVFCMP_CULT_S : LASX3R_XXX<0x0c950000>;
-def XVFCMP_SULT_S : LASX3R_XXX<0x0c958000>;
-def XVFCMP_CUEQ_S : LASX3R_XXX<0x0c960000>;
-def XVFCMP_SUEQ_S : LASX3R_XXX<0x0c968000>;
-def XVFCMP_CULE_S : LASX3R_XXX<0x0c970000>;
-def XVFCMP_SULE_S : LASX3R_XXX<0x0c978000>;
-def XVFCMP_CNE_S : LASX3R_XXX<0x0c980000>;
-def XVFCMP_SNE_S : LASX3R_XXX<0x0c988000>;
-def XVFCMP_COR_S : LASX3R_XXX<0x0c9a0000>;
-def XVFCMP_SOR_S : LASX3R_XXX<0x0c9a8000>;
-def XVFCMP_CUNE_S : LASX3R_XXX<0x0c9c0000>;
-def XVFCMP_SUNE_S : LASX3R_XXX<0x0c9c8000>;
-
-def XVFCMP_CAF_D : LASX3R_XXX<0x0ca00000>;
-def XVFCMP_SAF_D : LASX3R_XXX<0x0ca08000>;
-def XVFCMP_CLT_D : LASX3R_XXX<0x0ca10000>;
-def XVFCMP_SLT_D : LASX3R_XXX<0x0ca18000>;
-def XVFCMP_CEQ_D : LASX3R_XXX<0x0ca20000>;
-def XVFCMP_SEQ_D : LASX3R_XXX<0x0ca28000>;
-def XVFCMP_CLE_D : LASX3R_XXX<0x0ca30000>;
-def XVFCMP_SLE_D : LASX3R_XXX<0x0ca38000>;
-def XVFCMP_CUN_D : LASX3R_XXX<0x0ca40000>;
-def XVFCMP_SUN_D : LASX3R_XXX<0x0ca48000>;
-def XVFCMP_CULT_D : LASX3R_XXX<0x0ca50000>;
-def XVFCMP_SULT_D : LASX3R_XXX<0x0ca58000>;
-def XVFCMP_CUEQ_D : LASX3R_XXX<0x0ca60000>;
-def XVFCMP_SUEQ_D : LASX3R_XXX<0x0ca68000>;
-def XVFCMP_CULE_D : LASX3R_XXX<0x0ca70000>;
-def XVFCMP_SULE_D : LASX3R_XXX<0x0ca78000>;
-def XVFCMP_CNE_D : LASX3R_XXX<0x0ca80000>;
-def XVFCMP_SNE_D : LASX3R_XXX<0x0ca88000>;
-def XVFCMP_COR_D : LASX3R_XXX<0x0caa0000>;
-def XVFCMP_SOR_D : LASX3R_XXX<0x0caa8000>;
-def XVFCMP_CUNE_D : LASX3R_XXX<0x0cac0000>;
-def XVFCMP_SUNE_D : LASX3R_XXX<0x0cac8000>;
-
-def XVBITSEL_V : LASX4R_XXXX<0x0d200000>;
-
-def XVBITSELI_B : LASX2RI8_XXXI<0x77c40000>;
-
-def XVSETEQZ_V : LASX2R_CX<0x769c9800>;
-def XVSETNEZ_V : LASX2R_CX<0x769c9c00>;
-def XVSETANYEQZ_B : LASX2R_CX<0x769ca000>;
-def XVSETANYEQZ_H : LASX2R_CX<0x769ca400>;
-def XVSETANYEQZ_W : LASX2R_CX<0x769ca800>;
-def XVSETANYEQZ_D : LASX2R_CX<0x769cac00>;
-def XVSETALLNEZ_B : LASX2R_CX<0x769cb000>;
-def XVSETALLNEZ_H : LASX2R_CX<0x769cb400>;
-def XVSETALLNEZ_W : LASX2R_CX<0x769cb800>;
-def XVSETALLNEZ_D : LASX2R_CX<0x769cbc00>;
-
-def XVINSGR2VR_W : LASX2RI3_XXRI<0x76ebc000>;
-def XVINSGR2VR_D : LASX2RI2_XXRI<0x76ebe000>;
-def XVPICKVE2GR_W : LASX2RI3_RXI<0x76efc000>;
-def XVPICKVE2GR_D : LASX2RI2_RXI<0x76efe000>;
-def XVPICKVE2GR_WU : LASX2RI3_RXI<0x76f3c000>;
-def XVPICKVE2GR_DU : LASX2RI2_RXI<0x76f3e000>;
+def XVADD_B : LASX3R_XXX<0x740a0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVADD_H : LASX3R_XXX<0x740a8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVADD_W : LASX3R_XXX<0x740b0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVADD_D : LASX3R_XXX<0x740b8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVADD_Q : LASX3R_XXX<0x752d0000>,
+ Sched<[WriteVALUQ256, ReadVALUQ256, ReadVALUQ256]>;
+
+def XVSUB_B : LASX3R_XXX<0x740c0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSUB_H : LASX3R_XXX<0x740c8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSUB_W : LASX3R_XXX<0x740d0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSUB_D : LASX3R_XXX<0x740d8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSUB_Q : LASX3R_XXX<0x752d8000>,
+ Sched<[WriteVALUQ256, ReadVALUQ256, ReadVALUQ256]>;
+
+def XVADDI_BU : LASX2RI5_XXI<0x768a0000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVADDI_HU : LASX2RI5_XXI<0x768a8000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVADDI_WU : LASX2RI5_XXI<0x768b0000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVADDI_DU : LASX2RI5_XXI<0x768b8000>, Sched<[WriteVALU256, ReadVALU256]>;
+
+def XVSUBI_BU : LASX2RI5_XXI<0x768c0000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVSUBI_HU : LASX2RI5_XXI<0x768c8000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVSUBI_WU : LASX2RI5_XXI<0x768d0000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVSUBI_DU : LASX2RI5_XXI<0x768d8000>, Sched<[WriteVALU256, ReadVALU256]>;
+
+def XVNEG_B : LASX2R_XX<0x769c3000>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVNEG_H : LASX2R_XX<0x769c3400>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVNEG_W : LASX2R_XX<0x769c3800>, Sched<[WriteVALU256, ReadVALU256]>;
+def XVNEG_D : LASX2R_XX<0x769c3c00>, Sched<[WriteVALU256, ReadVALU256]>;
+
+def XVSADD_B : LASX3R_XXX<0x74460000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_H : LASX3R_XXX<0x74468000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_W : LASX3R_XXX<0x74470000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_D : LASX3R_XXX<0x74478000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_BU : LASX3R_XXX<0x744a0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_HU : LASX3R_XXX<0x744a8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_WU : LASX3R_XXX<0x744b0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSADD_DU : LASX3R_XXX<0x744b8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+
+def XVSSUB_B : LASX3R_XXX<0x74480000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_H : LASX3R_XXX<0x74488000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_W : LASX3R_XXX<0x74490000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_D : LASX3R_XXX<0x74498000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_BU : LASX3R_XXX<0x744c0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_HU : LASX3R_XXX<0x744c8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_WU : LASX3R_XXX<0x744d0000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+def XVSSUB_DU : LASX3R_XXX<0x744d8000>,
+ Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>;
+
+def XVHADDW_H_B : LASX3R_XXX<0x74540000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHADDW_W_H : LASX3R_XXX<0x74548000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHADDW_D_W : LASX3R_XXX<0x74550000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHADDW_Q_D : LASX3R_XXX<0x74558000>,
+ Sched<[WriteVHADDWQ256, ReadVHADDWQ256, ReadVHADDWQ256]>;
+def XVHADDW_HU_BU : LASX3R_XXX<0x74580000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHADDW_WU_HU : LASX3R_XXX<0x74588000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHADDW_DU_WU : LASX3R_XXX<0x74590000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHADDW_QU_DU : LASX3R_XXX<0x74598000>,
+ Sched<[WriteVHADDWQ256, ReadVHADDWQ256, ReadVHADDWQ256]>;
+
+def XVHSUBW_H_B : LASX3R_XXX<0x74560000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHSUBW_W_H : LASX3R_XXX<0x74568000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHSUBW_D_W : LASX3R_XXX<0x74570000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHSUBW_Q_D : LASX3R_XXX<0x74578000>,
+ Sched<[WriteVHADDWQ256, ReadVHADDWQ256, ReadVHADDWQ256]>;
+def XVHSUBW_HU_BU : LASX3R_XXX<0x745a0000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHSUBW_WU_HU : LASX3R_XXX<0x745a8000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHSUBW_DU_WU : LASX3R_XXX<0x745b0000>,
+ Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>;
+def XVHSUBW_QU_DU : LASX3R_XXX<0x745b8000>,
+ Sched<[WriteVHADDWQ256, ReadVHADDWQ256, ReadVHADDWQ256]>;
+
+def XVADDWEV_H_B : LASX3R_XXX<0x741e0000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_W_H : LASX3R_XXX<0x741e8000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_D_W : LASX3R_XXX<0x741f0000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_Q_D : LASX3R_XXX<0x741f8000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+def XVADDWOD_H_B : LASX3R_XXX<0x74220000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_W_H : LASX3R_XXX<0x74228000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_D_W : LASX3R_XXX<0x74230000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_Q_D : LASX3R_XXX<0x74238000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+
+def XVSUBWEV_H_B : LASX3R_XXX<0x74200000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWEV_W_H : LASX3R_XXX<0x74208000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWEV_D_W : LASX3R_XXX<0x74210000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWEV_Q_D : LASX3R_XXX<0x74218000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+def XVSUBWOD_H_B : LASX3R_XXX<0x74240000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWOD_W_H : LASX3R_XXX<0x74248000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWOD_D_W : LASX3R_XXX<0x74250000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWOD_Q_D : LASX3R_XXX<0x74258000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+
+def XVADDWEV_H_BU : LASX3R_XXX<0x742e0000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_W_HU : LASX3R_XXX<0x742e8000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_D_WU : LASX3R_XXX<0x742f0000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_Q_DU : LASX3R_XXX<0x742f8000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+def XVADDWOD_H_BU : LASX3R_XXX<0x74320000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_W_HU : LASX3R_XXX<0x74328000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_D_WU : LASX3R_XXX<0x74330000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_Q_DU : LASX3R_XXX<0x74338000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+
+def XVSUBWEV_H_BU : LASX3R_XXX<0x74300000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWEV_W_HU : LASX3R_XXX<0x74308000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWEV_D_WU : LASX3R_XXX<0x74310000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWEV_Q_DU : LASX3R_XXX<0x74318000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+def XVSUBWOD_H_BU : LASX3R_XXX<0x74340000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWOD_W_HU : LASX3R_XXX<0x74348000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWOD_D_WU : LASX3R_XXX<0x74350000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVSUBWOD_Q_DU : LASX3R_XXX<0x74358000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+
+def XVADDWEV_H_BU_B : LASX3R_XXX<0x743e0000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_W_HU_H : LASX3R_XXX<0x743e8000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_D_WU_W : LASX3R_XXX<0x743f0000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWEV_Q_DU_D : LASX3R_XXX<0x743f8000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+def XVADDWOD_H_BU_B : LASX3R_XXX<0x74400000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_W_HU_H : LASX3R_XXX<0x74408000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_D_WU_W : LASX3R_XXX<0x74410000>,
+ Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>;
+def XVADDWOD_Q_DU_D : LASX3R_XXX<0x74418000>,
+ Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>;
+
+def XVAVG_B : LASX3R_XXX<0x74640000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVG_H : LASX3R_XXX<0x74648000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVG_W : LASX3R_XXX<0x74650000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVG_D : LASX3R_XXX<0x74658000>,
+ Sched<[WriteVAVGD256, ReadVAVGD256, ReadVAVGD256]>;
+def XVAVG_BU : LASX3R_XXX<0x74660000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVG_HU : LASX3R_XXX<0x74668000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVG_WU : LASX3R_XXX<0x74670000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVG_DU : LASX3R_XXX<0x74678000>,
+ Sched<[WriteVAVGD256, ReadVAVGD256, ReadVAVGD256]>;
+def XVAVGR_B : LASX3R_XXX<0x74680000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVGR_H : LASX3R_XXX<0x74688000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVGR_W : LASX3R_XXX<0x74690000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVGR_D : LASX3R_XXX<0x74698000>,
+ Sched<[WriteVAVGD256, ReadVAVGD256, ReadVAVGD256]>;
+def XVAVGR_BU : LASX3R_XXX<0x746a0000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVGR_HU : LASX3R_XXX<0x746a8000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVGR_WU : LASX3R_XXX<0x746b0000>,
+ Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>;
+def XVAVGR_DU : LASX3R_XXX<0x746b8000>,
+ Sched<[WriteVAVGD256, ReadVAVGD256, ReadVAVGD256]>;
+
+def XVABSD_B : LASX3R_XXX<0x74600000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_H : LASX3R_XXX<0x74608000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_W : LASX3R_XXX<0x74610000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_D : LASX3R_XXX<0x74618000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_BU : LASX3R_XXX<0x74620000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_HU : LASX3R_XXX<0x74628000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_WU : LASX3R_XXX<0x74630000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+def XVABSD_DU : LASX3R_XXX<0x74638000>,
+ Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>;
+
+def XVADDA_B : LASX3R_XXX<0x745c0000>,
+ Sched<[WriteVADDA256, ReadVADDA256, ReadVADDA256]>;
+def XVADDA_H : LASX3R_XXX<0x745c8000>,
+ Sched<[WriteVADDA256, ReadVADDA256, ReadVADDA256]>;
+def XVADDA_W : LASX3R_XXX<0x745d0000>,
+ Sched<[WriteVADDA256, ReadVADDA256, ReadVADDA256]>;
+def XVADDA_D : LASX3R_XXX<0x745d8000>,
+ Sched<[WriteVADDA256, ReadVADDA256, ReadVADDA256]>;
+
+def XVMAX_B : LASX3R_XXX<0x74700000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMAX_H : LASX3R_XXX<0x74708000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMAX_W : LASX3R_XXX<0x74710000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMAX_D : LASX3R_XXX<0x74718000>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256, ReadVMINMAXD256]>;
+def XVMAXI_B : LASX2RI5_XXI<0x76900000, simm5>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMAXI_H : LASX2RI5_XXI<0x76908000, simm5>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMAXI_W : LASX2RI5_XXI<0x76910000, simm5>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMAXI_D : LASX2RI5_XXI<0x76918000, simm5>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256]>;
+def XVMAX_BU : LASX3R_XXX<0x74740000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMAX_HU : LASX3R_XXX<0x74748000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMAX_WU : LASX3R_XXX<0x74750000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMAX_DU : LASX3R_XXX<0x74758000>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256, ReadVMINMAXD256]>;
+def XVMAXI_BU : LASX2RI5_XXI<0x76940000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMAXI_HU : LASX2RI5_XXI<0x76948000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMAXI_WU : LASX2RI5_XXI<0x76950000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMAXI_DU : LASX2RI5_XXI<0x76958000>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256]>;
+
+def XVMIN_B : LASX3R_XXX<0x74720000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMIN_H : LASX3R_XXX<0x74728000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMIN_W : LASX3R_XXX<0x74730000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMIN_D : LASX3R_XXX<0x74738000>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256, ReadVMINMAXD256]>;
+def XVMINI_B : LASX2RI5_XXI<0x76920000, simm5>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMINI_H : LASX2RI5_XXI<0x76928000, simm5>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMINI_W : LASX2RI5_XXI<0x76930000, simm5>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMINI_D : LASX2RI5_XXI<0x76938000, simm5>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256]>;
+def XVMIN_BU : LASX3R_XXX<0x74760000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMIN_HU : LASX3R_XXX<0x74768000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMIN_WU : LASX3R_XXX<0x74770000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>;
+def XVMIN_DU : LASX3R_XXX<0x74778000>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256, ReadVMINMAXD256]>;
+def XVMINI_BU : LASX2RI5_XXI<0x76960000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMINI_HU : LASX2RI5_XXI<0x76968000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMINI_WU : LASX2RI5_XXI<0x76970000>,
+ Sched<[WriteVMINMAX256, ReadVMINMAX256]>;
+def XVMINI_DU : LASX2RI5_XXI<0x76978000>,
+ Sched<[WriteVMINMAXD256, ReadVMINMAXD256]>;
+
+def XVMUL_B : LASX3R_XXX<0x74840000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUL_H : LASX3R_XXX<0x74848000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUL_W : LASX3R_XXX<0x74850000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUL_D : LASX3R_XXX<0x74858000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+
+def XVMUH_B : LASX3R_XXX<0x74860000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_H : LASX3R_XXX<0x74868000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_W : LASX3R_XXX<0x74870000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_D : LASX3R_XXX<0x74878000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_BU : LASX3R_XXX<0x74880000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_HU : LASX3R_XXX<0x74888000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_WU : LASX3R_XXX<0x74890000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMUH_DU : LASX3R_XXX<0x74898000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+
+def XVMULWEV_H_B : LASX3R_XXX<0x74900000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_W_H : LASX3R_XXX<0x74908000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_D_W : LASX3R_XXX<0x74910000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_Q_D : LASX3R_XXX<0x74918000>,
+ Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>;
+def XVMULWOD_H_B : LASX3R_XXX<0x74920000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_W_H : LASX3R_XXX<0x74928000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_D_W : LASX3R_XXX<0x74930000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_Q_D : LASX3R_XXX<0x74938000>,
+ Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>;
+def XVMULWEV_H_BU : LASX3R_XXX<0x74980000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_W_HU : LASX3R_XXX<0x74988000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_D_WU : LASX3R_XXX<0x74990000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_Q_DU : LASX3R_XXX<0x74998000>,
+ Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>;
+def XVMULWOD_H_BU : LASX3R_XXX<0x749a0000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_W_HU : LASX3R_XXX<0x749a8000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_D_WU : LASX3R_XXX<0x749b0000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_Q_DU : LASX3R_XXX<0x749b8000>,
+ Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>;
+def XVMULWEV_H_BU_B : LASX3R_XXX<0x74a00000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_W_HU_H : LASX3R_XXX<0x74a08000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_D_WU_W : LASX3R_XXX<0x74a10000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWEV_Q_DU_D : LASX3R_XXX<0x74a18000>,
+ Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>;
+def XVMULWOD_H_BU_B : LASX3R_XXX<0x74a20000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_W_HU_H : LASX3R_XXX<0x74a28000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_D_WU_W : LASX3R_XXX<0x74a30000>,
+ Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>;
+def XVMULWOD_Q_DU_D : LASX3R_XXX<0x74a38000>,
+ Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>;
+
+def XVMADD_B : LASX3R_XXXX<0x74a80000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADD_H : LASX3R_XXXX<0x74a88000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADD_W : LASX3R_XXXX<0x74a90000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADD_D : LASX3R_XXXX<0x74a98000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+
+def XVMSUB_B : LASX3R_XXXX<0x74aa0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMSUB_H : LASX3R_XXXX<0x74aa8000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMSUB_W : LASX3R_XXXX<0x74ab0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMSUB_D : LASX3R_XXXX<0x74ab8000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+
+def XVMADDWEV_H_B : LASX3R_XXXX<0x74ac0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_W_H : LASX3R_XXXX<0x74ac8000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_D_W : LASX3R_XXXX<0x74ad0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_Q_D : LASX3R_XXXX<0x74ad8000>,
+ Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>;
+def XVMADDWOD_H_B : LASX3R_XXXX<0x74ae0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_W_H : LASX3R_XXXX<0x74ae8000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_D_W : LASX3R_XXXX<0x74af0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_Q_D : LASX3R_XXXX<0x74af8000>,
+ Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>;
+def XVMADDWEV_H_BU : LASX3R_XXXX<0x74b40000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_W_HU : LASX3R_XXXX<0x74b48000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_D_WU : LASX3R_XXXX<0x74b50000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_Q_DU : LASX3R_XXXX<0x74b58000>,
+ Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>;
+def XVMADDWOD_H_BU : LASX3R_XXXX<0x74b60000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_W_HU : LASX3R_XXXX<0x74b68000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_D_WU : LASX3R_XXXX<0x74b70000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_Q_DU : LASX3R_XXXX<0x74b78000>,
+ Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>;
+def XVMADDWEV_H_BU_B : LASX3R_XXXX<0x74bc0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_W_HU_H : LASX3R_XXXX<0x74bc8000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_D_WU_W : LASX3R_XXXX<0x74bd0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWEV_Q_DU_D : LASX3R_XXXX<0x74bd8000>,
+ Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>;
+def XVMADDWOD_H_BU_B : LASX3R_XXXX<0x74be0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_W_HU_H : LASX3R_XXXX<0x74be8000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_D_WU_W : LASX3R_XXXX<0x74bf0000>,
+ Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>;
+def XVMADDWOD_Q_DU_D : LASX3R_XXXX<0x74bf8000>,
+ Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>;
+
+def XVDIV_B : LASX3R_XXX<0x74e00000>,
+ Sched<[WriteVDIVB256, ReadVDIVB256, ReadVDIVB256]>;
+def XVDIV_H : LASX3R_XXX<0x74e08000>,
+ Sched<[WriteVDIVH256, ReadVDIVH256, ReadVDIVH256]>;
+def XVDIV_W : LASX3R_XXX<0x74e10000>,
+ Sched<[WriteVDIVW256, ReadVDIVW256, ReadVDIVW256]>;
+def XVDIV_D : LASX3R_XXX<0x74e18000>,
+ Sched<[WriteVDIVD256, ReadVDIVD256, ReadVDIVD256]>;
+def XVDIV_BU : LASX3R_XXX<0x74e40000>,
+ Sched<[WriteVDIVB256, ReadVDIVB256, ReadVDIVB256]>;
+def XVDIV_HU : LASX3R_XXX<0x74e48000>,
+ Sched<[WriteVDIVH256, ReadVDIVH256, ReadVDIVH256]>;
+def XVDIV_WU : LASX3R_XXX<0x74e50000>,
+ Sched<[WriteVDIVW256, ReadVDIVW256, ReadVDIVW256]>;
+def XVDIV_DU : LASX3R_XXX<0x74e58000>,
+ Sched<[WriteVDIVD256, ReadVDIVD256, ReadVDIVD256]>;
+
+def XVMOD_B : LASX3R_XXX<0x74e20000>,
+ Sched<[WriteVDIVB256, ReadVDIVB256, ReadVDIVB256]>;
+def XVMOD_H : LASX3R_XXX<0x74e28000>,
+ Sched<[WriteVDIVH256, ReadVDIVH256, ReadVDIVH256]>;
+def XVMOD_W : LASX3R_XXX<0x74e30000>,
+ Sched<[WriteVDIVW256, ReadVDIVW256, ReadVDIVW256]>;
+def XVMOD_D : LASX3R_XXX<0x74e38000>,
+ Sched<[WriteVDIVD256, ReadVDIVD256, ReadVDIVD256]>;
+def XVMOD_BU : LASX3R_XXX<0x74e60000>,
+ Sched<[WriteVDIVB256, ReadVDIVB256, ReadVDIVB256]>;
+def XVMOD_HU : LASX3R_XXX<0x74e68000>,
+ Sched<[WriteVDIVH256, ReadVDIVH256, ReadVDIVH256]>;
+def XVMOD_WU : LASX3R_XXX<0x74e70000>,
+ Sched<[WriteVDIVW256, ReadVDIVW256, ReadVDIVW256]>;
+def XVMOD_DU : LASX3R_XXX<0x74e78000>,
+ Sched<[WriteVDIVD256, ReadVDIVD256, ReadVDIVD256]>;
+
+def XVSAT_B : LASX2RI3_XXI<0x77242000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_H : LASX2RI4_XXI<0x77244000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_W : LASX2RI5_XXI<0x77248000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_D : LASX2RI6_XXI<0x77250000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_BU : LASX2RI3_XXI<0x77282000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_HU : LASX2RI4_XXI<0x77284000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_WU : LASX2RI5_XXI<0x77288000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+def XVSAT_DU : LASX2RI6_XXI<0x77290000>, Sched<[WriteVSAT256, ReadVSAT256]>;
+
+def XVEXTH_H_B : LASX2R_XX<0x769ee000>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_W_H : LASX2R_XX<0x769ee400>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_D_W : LASX2R_XX<0x769ee800>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_Q_D : LASX2R_XX<0x769eec00>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_HU_BU : LASX2R_XX<0x769ef000>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_WU_HU : LASX2R_XX<0x769ef400>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_DU_WU : LASX2R_XX<0x769ef800>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+def XVEXTH_QU_DU : LASX2R_XX<0x769efc00>, Sched<[WriteVEXTH256, ReadVEXTH256]>;
+
+def VEXT2XV_H_B : LASX2R_XX<0x769f1000>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_W_B : LASX2R_XX<0x769f1400>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_D_B : LASX2R_XX<0x769f1800>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_W_H : LASX2R_XX<0x769f1c00>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_D_H : LASX2R_XX<0x769f2000>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_D_W : LASX2R_XX<0x769f2400>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_HU_BU : LASX2R_XX<0x769f2800>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_WU_BU : LASX2R_XX<0x769f2c00>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_DU_BU : LASX2R_XX<0x769f3000>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_WU_HU : LASX2R_XX<0x769f3400>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_DU_HU : LASX2R_XX<0x769f3800>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+def VEXT2XV_DU_WU : LASX2R_XX<0x769f3c00>,
+ Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>;
+
+def XVHSELI_D : LASX2RI5_XXI<0x769f8000>,
+ Sched<[WriteVHSELI256, ReadVHSELI256]>;
+
+def XVSIGNCOV_B : LASX3R_XXX<0x752e0000>,
+ Sched<[WriteVSIGNCOV256, ReadVSIGNCOV256, ReadVSIGNCOV256]>;
+def XVSIGNCOV_H : LASX3R_XXX<0x752e8000>,
+ Sched<[WriteVSIGNCOV256, ReadVSIGNCOV256, ReadVSIGNCOV256]>;
+def XVSIGNCOV_W : LASX3R_XXX<0x752f0000>,
+ Sched<[WriteVSIGNCOV256, ReadVSIGNCOV256, ReadVSIGNCOV256]>;
+def XVSIGNCOV_D : LASX3R_XXX<0x752f8000>,
+ Sched<[WriteVSIGNCOV256, ReadVSIGNCOV256, ReadVSIGNCOV256]>;
+
+def XVMSKLTZ_B : LASX2R_XX<0x769c4000>, Sched<[WriteVMSK256, ReadVMSK256]>;
+def XVMSKLTZ_H : LASX2R_XX<0x769c4400>, Sched<[WriteVMSK256, ReadVMSK256]>;
+def XVMSKLTZ_W : LASX2R_XX<0x769c4800>, Sched<[WriteVMSK256, ReadVMSK256]>;
+def XVMSKLTZ_D : LASX2R_XX<0x769c4c00>, Sched<[WriteVMSK256, ReadVMSK256]>;
+
+def XVMSKGEZ_B : LASX2R_XX<0x769c5000>, Sched<[WriteVMSK256, ReadVMSK256]>;
+
+def XVMSKNZ_B : LASX2R_XX<0x769c6000>, Sched<[WriteVMSK256, ReadVMSK256]>;
+
+def XVLDI : LASX1RI13_XI<0x77e00000>, Sched<[WriteVLDI256]>;
+
+def XVAND_V : LASX3R_XXX<0x75260000>,
+ Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>;
+def XVOR_V : LASX3R_XXX<0x75268000>,
+ Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>;
+def XVXOR_V : LASX3R_XXX<0x75270000>,
+ Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>;
+def XVNOR_V : LASX3R_XXX<0x75278000>,
+ Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>;
+def XVANDN_V : LASX3R_XXX<0x75280000>,
+ Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>;
+def XVORN_V : LASX3R_XXX<0x75288000>,
+ Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>;
+
+def XVANDI_B : LASX2RI8_XXI<0x77d00000>, Sched<[WriteVBIT256, ReadVBIT256]>;
+def XVORI_B : LASX2RI8_XXI<0x77d40000>, Sched<[WriteVBIT256, ReadVBIT256]>;
+def XVXORI_B : LASX2RI8_XXI<0x77d80000>, Sched<[WriteVBIT256, ReadVBIT256]>;
+def XVNORI_B : LASX2RI8_XXI<0x77dc0000>, Sched<[WriteVBIT256, ReadVBIT256]>;
+
+def XVSLL_B : LASX3R_XXX<0x74e80000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSLL_H : LASX3R_XXX<0x74e88000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSLL_W : LASX3R_XXX<0x74e90000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSLL_D : LASX3R_XXX<0x74e98000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSLLI_B : LASX2RI3_XXI<0x772c2000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSLLI_H : LASX2RI4_XXI<0x772c4000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSLLI_W : LASX2RI5_XXI<0x772c8000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSLLI_D : LASX2RI6_XXI<0x772d0000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+
+def XVSRL_B : LASX3R_XXX<0x74ea0000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRL_H : LASX3R_XXX<0x74ea8000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRL_W : LASX3R_XXX<0x74eb0000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRL_D : LASX3R_XXX<0x74eb8000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRLI_B : LASX2RI3_XXI<0x77302000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSRLI_H : LASX2RI4_XXI<0x77304000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSRLI_W : LASX2RI5_XXI<0x77308000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSRLI_D : LASX2RI6_XXI<0x77310000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+
+def XVSRA_B : LASX3R_XXX<0x74ec0000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRA_H : LASX3R_XXX<0x74ec8000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRA_W : LASX3R_XXX<0x74ed0000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRA_D : LASX3R_XXX<0x74ed8000>,
+ Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>;
+def XVSRAI_B : LASX2RI3_XXI<0x77342000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSRAI_H : LASX2RI4_XXI<0x77344000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSRAI_W : LASX2RI5_XXI<0x77348000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVSRAI_D : LASX2RI6_XXI<0x77350000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+
+def XVROTR_B : LASX3R_XXX<0x74ee0000>,
+ Sched<[WriteVROTR256, ReadVROTR256, ReadVROTR256]>;
+def XVROTR_H : LASX3R_XXX<0x74ee8000>,
+ Sched<[WriteVROTR256, ReadVROTR256, ReadVROTR256]>;
+def XVROTR_W : LASX3R_XXX<0x74ef0000>,
+ Sched<[WriteVROTR256, ReadVROTR256, ReadVROTR256]>;
+def XVROTR_D : LASX3R_XXX<0x74ef8000>,
+ Sched<[WriteVROTR256, ReadVROTR256, ReadVROTR256]>;
+def XVROTRI_B : LASX2RI3_XXI<0x76a02000>,
+ Sched<[WriteVROTR256, ReadVROTR256]>;
+def XVROTRI_H : LASX2RI4_XXI<0x76a04000>,
+ Sched<[WriteVROTR256, ReadVROTR256]>;
+def XVROTRI_W : LASX2RI5_XXI<0x76a08000>,
+ Sched<[WriteVROTR256, ReadVROTR256]>;
+def XVROTRI_D : LASX2RI6_XXI<0x76a10000>,
+ Sched<[WriteVROTR256, ReadVROTR256]>;
+
+def XVSLLWIL_H_B : LASX2RI3_XXI<0x77082000>,
+ Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>;
+def XVSLLWIL_W_H : LASX2RI4_XXI<0x77084000>,
+ Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>;
+def XVSLLWIL_D_W : LASX2RI5_XXI<0x77088000>,
+ Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>;
+def XVEXTL_Q_D : LASX2R_XX<0x77090000>, Sched<[WriteVEXTL256, ReadVEXTL256]>;
+def XVSLLWIL_HU_BU : LASX2RI3_XXI<0x770c2000>,
+ Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>;
+def XVSLLWIL_WU_HU : LASX2RI4_XXI<0x770c4000>,
+ Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>;
+def XVSLLWIL_DU_WU : LASX2RI5_XXI<0x770c8000>,
+ Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>;
+def XVEXTL_QU_DU : LASX2R_XX<0x770d0000>, Sched<[WriteVEXTL256, ReadVEXTL256]>;
+
+def XVSRLR_B : LASX3R_XXX<0x74f00000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLR_H : LASX3R_XXX<0x74f08000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLR_W : LASX3R_XXX<0x74f10000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLR_D : LASX3R_XXX<0x74f18000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLRI_B : LASX2RI3_XXI<0x76a42000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLRI_H : LASX2RI4_XXI<0x76a44000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLRI_W : LASX2RI5_XXI<0x76a48000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRLRI_D : LASX2RI6_XXI<0x76a50000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+
+def XVSRAR_B : LASX3R_XXX<0x74f20000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRAR_H : LASX3R_XXX<0x74f28000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRAR_W : LASX3R_XXX<0x74f30000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRAR_D : LASX3R_XXX<0x74f38000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRARI_B : LASX2RI3_XXI<0x76a82000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRARI_H : LASX2RI4_XXI<0x76a84000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRARI_W : LASX2RI5_XXI<0x76a88000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+def XVSRARI_D : LASX2RI6_XXI<0x76a90000>,
+ Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>;
+
+def XVSRLN_B_H : LASX3R_XXX<0x74f48000>,
+ Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>;
+def XVSRLN_H_W : LASX3R_XXX<0x74f50000>,
+ Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>;
+def XVSRLN_W_D : LASX3R_XXX<0x74f58000>,
+ Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>;
+def XVSRAN_B_H : LASX3R_XXX<0x74f68000>,
+ Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>;
+def XVSRAN_H_W : LASX3R_XXX<0x74f70000>,
+ Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>;
+def XVSRAN_W_D : LASX3R_XXX<0x74f78000>,
+ Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>;
+
+def XVSRLNI_B_H : LASX2RI4_XXXI<0x77404000>,
+ Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>;
+def XVSRLNI_H_W : LASX2RI5_XXXI<0x77408000>,
+ Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>;
+def XVSRLNI_W_D : LASX2RI6_XXXI<0x77410000>,
+ Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>;
+def XVSRLNI_D_Q : LASX2RI7_XXXI<0x77420000>,
+ Sched<[WriteVSHIFTNIQ256, ReadVSHIFTNIQ256, ReadVSHIFTNIQ256]>;
+def XVSRANI_B_H : LASX2RI4_XXXI<0x77584000>,
+ Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>;
+def XVSRANI_H_W : LASX2RI5_XXXI<0x77588000>,
+ Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>;
+def XVSRANI_W_D : LASX2RI6_XXXI<0x77590000>,
+ Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>;
+def XVSRANI_D_Q : LASX2RI7_XXXI<0x775a0000>,
+ Sched<[WriteVSHIFTNIQ256, ReadVSHIFTNIQ256, ReadVSHIFTNIQ256]>;
+
+def XVSRLRN_B_H : LASX3R_XXX<0x74f88000>,
+ Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>;
+def XVSRLRN_H_W : LASX3R_XXX<0x74f90000>,
+ Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>;
+def XVSRLRN_W_D : LASX3R_XXX<0x74f98000>,
+ Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>;
+def XVSRARN_B_H : LASX3R_XXX<0x74fa8000>,
+ Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>;
+def XVSRARN_H_W : LASX3R_XXX<0x74fb0000>,
+ Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>;
+def XVSRARN_W_D : LASX3R_XXX<0x74fb8000>,
+ Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>;
+
+def XVSRLRNI_B_H : LASX2RI4_XXXI<0x77444000>,
+ Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>;
+def XVSRLRNI_H_W : LASX2RI5_XXXI<0x77448000>,
+ Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>;
+def XVSRLRNI_W_D : LASX2RI6_XXXI<0x77450000>,
+ Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>;
+def XVSRLRNI_D_Q : LASX2RI7_XXXI<0x77460000>,
+ Sched<[WriteVSHIFTRNIQ256, ReadVSHIFTRNIQ256, ReadVSHIFTRNIQ256]>;
+def XVSRARNI_B_H : LASX2RI4_XXXI<0x775c4000>,
+ Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>;
+def XVSRARNI_H_W : LASX2RI5_XXXI<0x775c8000>,
+ Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>;
+def XVSRARNI_W_D : LASX2RI6_XXXI<0x775d0000>,
+ Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>;
+def XVSRARNI_D_Q : LASX2RI7_XXXI<0x775e0000>,
+ Sched<[WriteVSHIFTRNIQ256, ReadVSHIFTRNIQ256, ReadVSHIFTRNIQ256]>;
+
+def XVSSRLN_B_H : LASX3R_XXX<0x74fc8000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRLN_H_W : LASX3R_XXX<0x74fd0000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRLN_W_D : LASX3R_XXX<0x74fd8000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRAN_B_H : LASX3R_XXX<0x74fe8000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRAN_H_W : LASX3R_XXX<0x74ff0000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRAN_W_D : LASX3R_XXX<0x74ff8000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRLN_BU_H : LASX3R_XXX<0x75048000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRLN_HU_W : LASX3R_XXX<0x75050000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRLN_WU_D : LASX3R_XXX<0x75058000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRAN_BU_H : LASX3R_XXX<0x75068000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRAN_HU_W : LASX3R_XXX<0x75070000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+def XVSSRAN_WU_D : LASX3R_XXX<0x75078000>,
+ Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>;
+
+def XVSSRLNI_B_H : LASX2RI4_XXXI<0x77484000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRLNI_H_W : LASX2RI5_XXXI<0x77488000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRLNI_W_D : LASX2RI6_XXXI<0x77490000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRLNI_D_Q : LASX2RI7_XXXI<0x774a0000>,
+ Sched<[WriteVSHIFTNSIQ256, ReadVSHIFTNSIQ256, ReadVSHIFTNSIQ256]>;
+def XVSSRANI_B_H : LASX2RI4_XXXI<0x77604000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRANI_H_W : LASX2RI5_XXXI<0x77608000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRANI_W_D : LASX2RI6_XXXI<0x77610000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRANI_D_Q : LASX2RI7_XXXI<0x77620000>,
+ Sched<[WriteVSHIFTNSIQ256, ReadVSHIFTNSIQ256, ReadVSHIFTNSIQ256]>;
+def XVSSRLNI_BU_H : LASX2RI4_XXXI<0x774c4000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRLNI_HU_W : LASX2RI5_XXXI<0x774c8000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRLNI_WU_D : LASX2RI6_XXXI<0x774d0000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRLNI_DU_Q : LASX2RI7_XXXI<0x774e0000>,
+ Sched<[WriteVSHIFTNSIQ256, ReadVSHIFTNSIQ256, ReadVSHIFTNSIQ256]>;
+def XVSSRANI_BU_H : LASX2RI4_XXXI<0x77644000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRANI_HU_W : LASX2RI5_XXXI<0x77648000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRANI_WU_D : LASX2RI6_XXXI<0x77650000>,
+ Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>;
+def XVSSRANI_DU_Q : LASX2RI7_XXXI<0x77660000>,
+ Sched<[WriteVSHIFTNSIQ256, ReadVSHIFTNSIQ256, ReadVSHIFTNSIQ256]>;
+
+def XVSSRLRN_B_H : LASX3R_XXX<0x75008000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRLRN_H_W : LASX3R_XXX<0x75010000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRLRN_W_D : LASX3R_XXX<0x75018000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRARN_B_H : LASX3R_XXX<0x75028000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRARN_H_W : LASX3R_XXX<0x75030000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRARN_W_D : LASX3R_XXX<0x75038000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRLRN_BU_H : LASX3R_XXX<0x75088000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRLRN_HU_W : LASX3R_XXX<0x75090000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRLRN_WU_D : LASX3R_XXX<0x75098000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRARN_BU_H : LASX3R_XXX<0x750a8000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRARN_HU_W : LASX3R_XXX<0x750b0000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+def XVSSRARN_WU_D : LASX3R_XXX<0x750b8000>,
+ Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>;
+
+def XVSSRLRNI_B_H : LASX2RI4_XXXI<0x77504000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRLRNI_H_W : LASX2RI5_XXXI<0x77508000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRLRNI_W_D : LASX2RI6_XXXI<0x77510000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRLRNI_D_Q : LASX2RI7_XXXI<0x77520000>,
+ Sched<[WriteVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256]>;
+def XVSSRARNI_B_H : LASX2RI4_XXXI<0x77684000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRARNI_H_W : LASX2RI5_XXXI<0x77688000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRARNI_W_D : LASX2RI6_XXXI<0x77690000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRARNI_D_Q : LASX2RI7_XXXI<0x776a0000>,
+ Sched<[WriteVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256]>;
+def XVSSRLRNI_BU_H : LASX2RI4_XXXI<0x77544000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRLRNI_HU_W : LASX2RI5_XXXI<0x77548000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRLRNI_WU_D : LASX2RI6_XXXI<0x77550000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRLRNI_DU_Q : LASX2RI7_XXXI<0x77560000>,
+ Sched<[WriteVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256]>;
+def XVSSRARNI_BU_H : LASX2RI4_XXXI<0x776c4000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRARNI_HU_W : LASX2RI5_XXXI<0x776c8000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRARNI_WU_D : LASX2RI6_XXXI<0x776d0000>,
+ Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>;
+def XVSSRARNI_DU_Q : LASX2RI7_XXXI<0x776e0000>,
+ Sched<[WriteVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256]>;
+
+def XVCLO_B : LASX2R_XX<0x769c0000>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLO_H : LASX2R_XX<0x769c0400>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLO_W : LASX2R_XX<0x769c0800>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLO_D : LASX2R_XX<0x769c0c00>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLZ_B : LASX2R_XX<0x769c1000>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLZ_H : LASX2R_XX<0x769c1400>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLZ_W : LASX2R_XX<0x769c1800>, Sched<[WriteVCL256, ReadVCL256]>;
+def XVCLZ_D : LASX2R_XX<0x769c1c00>, Sched<[WriteVCL256, ReadVCL256]>;
+
+def XVPCNT_B : LASX2R_XX<0x769c2000>, Sched<[WriteVPCNT256, ReadVPCNT256]>;
+def XVPCNT_H : LASX2R_XX<0x769c2400>, Sched<[WriteVPCNT256, ReadVPCNT256]>;
+def XVPCNT_W : LASX2R_XX<0x769c2800>, Sched<[WriteVPCNT256, ReadVPCNT256]>;
+def XVPCNT_D : LASX2R_XX<0x769c2c00>, Sched<[WriteVPCNT256, ReadVPCNT256]>;
+
+def XVBITCLR_B : LASX3R_XXX<0x750c0000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLR_H : LASX3R_XXX<0x750c8000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLR_W : LASX3R_XXX<0x750d0000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLR_D : LASX3R_XXX<0x750d8000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLRI_B : LASX2RI3_XXI<0x77102000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLRI_H : LASX2RI4_XXI<0x77104000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLRI_W : LASX2RI5_XXI<0x77108000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITCLRI_D : LASX2RI6_XXI<0x77110000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+
+def XVBITSET_B : LASX3R_XXX<0x750e0000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITSET_H : LASX3R_XXX<0x750e8000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITSET_W : LASX3R_XXX<0x750f0000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITSET_D : LASX3R_XXX<0x750f8000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITSETI_B : LASX2RI3_XXI<0x77142000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITSETI_H : LASX2RI4_XXI<0x77144000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITSETI_W : LASX2RI5_XXI<0x77148000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITSETI_D : LASX2RI6_XXI<0x77150000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+
+def XVBITREV_B : LASX3R_XXX<0x75100000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITREV_H : LASX3R_XXX<0x75108000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITREV_W : LASX3R_XXX<0x75110000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITREV_D : LASX3R_XXX<0x75118000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>;
+def XVBITREVI_B : LASX2RI3_XXI<0x77182000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITREVI_H : LASX2RI4_XXI<0x77184000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITREVI_W : LASX2RI5_XXI<0x77188000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+def XVBITREVI_D : LASX2RI6_XXI<0x77190000>,
+ Sched<[WriteVBITOPS256, ReadVBITOPS256]>;
+
+def XVFRSTP_B : LASX3R_XXXX<0x752b0000>,
+ Sched<[WriteVFRSTP256, ReadVFRSTP256, ReadVFRSTP256, ReadVFRSTP256]>;
+def XVFRSTP_H : LASX3R_XXXX<0x752b8000>,
+ Sched<[WriteVFRSTP256, ReadVFRSTP256, ReadVFRSTP256, ReadVFRSTP256]>;
+def XVFRSTPI_B : LASX2RI5_XXXI<0x769a0000>,
+ Sched<[WriteVFRSTP256, ReadVFRSTP256, ReadVFRSTP256]>;
+def XVFRSTPI_H : LASX2RI5_XXXI<0x769a8000>,
+ Sched<[WriteVFRSTP256, ReadVFRSTP256, ReadVFRSTP256]>;
+
+def XVFADD_S : LASX3R_XXX<0x75308000>,
+ Sched<[WriteVFADD256, ReadVFADD256, ReadVFADD256]>;
+def XVFADD_D : LASX3R_XXX<0x75310000>,
+ Sched<[WriteVFADD256, ReadVFADD256, ReadVFADD256]>;
+def XVFSUB_S : LASX3R_XXX<0x75328000>,
+ Sched<[WriteVFADD256, ReadVFADD256, ReadVFADD256]>;
+def XVFSUB_D : LASX3R_XXX<0x75330000>,
+ Sched<[WriteVFADD256, ReadVFADD256, ReadVFADD256]>;
+def XVFMUL_S : LASX3R_XXX<0x75388000>,
+ Sched<[WriteVFMUL256, ReadVFMUL256, ReadVFMUL256]>;
+def XVFMUL_D : LASX3R_XXX<0x75390000>,
+ Sched<[WriteVFMUL256, ReadVFMUL256, ReadVFMUL256]>;
+def XVFDIV_S : LASX3R_XXX<0x753a8000>,
+ Sched<[WriteVFDIVS256, ReadVFDIVS256, ReadVFDIVS256]>;
+def XVFDIV_D : LASX3R_XXX<0x753b0000>,
+ Sched<[WriteVFDIVD256, ReadVFDIVD256, ReadVFDIVD256]>;
+
+def XVFMADD_S : LASX4R_XXXX<0x0a100000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFMADD_D : LASX4R_XXXX<0x0a200000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFMSUB_S : LASX4R_XXXX<0x0a500000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFMSUB_D : LASX4R_XXXX<0x0a600000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFNMADD_S : LASX4R_XXXX<0x0a900000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFNMADD_D : LASX4R_XXXX<0x0aa00000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFNMSUB_S : LASX4R_XXXX<0x0ad00000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+def XVFNMSUB_D : LASX4R_XXXX<0x0ae00000>,
+ Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>;
+
+def XVFMAX_S : LASX3R_XXX<0x753c8000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+def XVFMAX_D : LASX3R_XXX<0x753d0000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+def XVFMIN_S : LASX3R_XXX<0x753e8000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+def XVFMIN_D : LASX3R_XXX<0x753f0000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+
+def XVFMAXA_S : LASX3R_XXX<0x75408000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+def XVFMAXA_D : LASX3R_XXX<0x75410000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+def XVFMINA_S : LASX3R_XXX<0x75428000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+def XVFMINA_D : LASX3R_XXX<0x75430000>,
+ Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>;
+
+def XVFLOGB_S : LASX2R_XX<0x769cc400>, Sched<[WriteVFLOGB256, ReadVFLOGB256]>;
+def XVFLOGB_D : LASX2R_XX<0x769cc800>, Sched<[WriteVFLOGB256, ReadVFLOGB256]>;
+
+def XVFCLASS_S : LASX2R_XX<0x769cd400>,
+ Sched<[WriteVFCLASS256, ReadVFCLASS256]>;
+def XVFCLASS_D : LASX2R_XX<0x769cd800>,
+ Sched<[WriteVFCLASS256, ReadVFCLASS256]>;
+
+def XVFSQRT_S : LASX2R_XX<0x769ce400>, Sched<[WriteVFSQRTS256, ReadVFSQRTS256]>;
+def XVFSQRT_D : LASX2R_XX<0x769ce800>, Sched<[WriteVFSQRTD256, ReadVFSQRTD256]>;
+def XVFRECIP_S : LASX2R_XX<0x769cf400>,
+ Sched<[WriteVFRECIPS256, ReadVFRECIPS256]>;
+def XVFRECIP_D : LASX2R_XX<0x769cf800>,
+ Sched<[WriteVFRECIPD256, ReadVFRECIPD256]>;
+def XVFRSQRT_S : LASX2R_XX<0x769d0400>,
+ Sched<[WriteVFRSQRTS256, ReadVFRSQRTS256]>;
+def XVFRSQRT_D : LASX2R_XX<0x769d0800>,
+ Sched<[WriteVFRSQRTD256, ReadVFRSQRTD256]>;
+def XVFRECIPE_S : LASX2R_XX<0x769d1400>,
+ Sched<[WriteVFRECIPE256, ReadVFRECIPE256]>;
+def XVFRECIPE_D : LASX2R_XX<0x769d1800>,
+ Sched<[WriteVFRECIPE256, ReadVFRECIPE256]>;
+def XVFRSQRTE_S : LASX2R_XX<0x769d2400>,
+ Sched<[WriteVFRSQRTE256, ReadVFRSQRTE256]>;
+def XVFRSQRTE_D : LASX2R_XX<0x769d2800>,
+ Sched<[WriteVFRSQRTE256, ReadVFRSQRTE256]>;
+
+def XVFCVTL_S_H : LASX2R_XX<0x769de800>, Sched<[WriteVFCVT256, ReadVFCVT256]>;
+def XVFCVTH_S_H : LASX2R_XX<0x769dec00>, Sched<[WriteVFCVT256, ReadVFCVT256]>;
+def XVFCVTL_D_S : LASX2R_XX<0x769df000>, Sched<[WriteVFCVT256, ReadVFCVT256]>;
+def XVFCVTH_D_S : LASX2R_XX<0x769df400>, Sched<[WriteVFCVT256, ReadVFCVT256]>;
+def XVFCVT_H_S : LASX3R_XXX<0x75460000>,
+ Sched<[WriteVFCVT256, ReadVFCVT256, ReadVFCVT256]>;
+def XVFCVT_S_D : LASX3R_XXX<0x75468000>,
+ Sched<[WriteVFCVT256, ReadVFCVT256, ReadVFCVT256]>;
+
+def XVFRINTRNE_S : LASX2R_XX<0x769d7400>,
+ Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRNE_D : LASX2R_XX<0x769d7800>,
+ Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRZ_S : LASX2R_XX<0x769d6400>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRZ_D : LASX2R_XX<0x769d6800>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRP_S : LASX2R_XX<0x769d5400>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRP_D : LASX2R_XX<0x769d5800>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRM_S : LASX2R_XX<0x769d4400>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINTRM_D : LASX2R_XX<0x769d4800>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINT_S : LASX2R_XX<0x769d3400>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+def XVFRINT_D : LASX2R_XX<0x769d3800>, Sched<[WriteVFRINT256, ReadVFRINT256]>;
+
+def XVFTINTRNE_W_S : LASX2R_XX<0x769e5000>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRNE_L_D : LASX2R_XX<0x769e5400>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRZ_W_S : LASX2R_XX<0x769e4800>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRZ_L_D : LASX2R_XX<0x769e4c00>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRP_W_S : LASX2R_XX<0x769e4000>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRP_L_D : LASX2R_XX<0x769e4400>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRM_W_S : LASX2R_XX<0x769e3800>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRM_L_D : LASX2R_XX<0x769e3c00>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINT_W_S : LASX2R_XX<0x769e3000>, Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINT_L_D : LASX2R_XX<0x769e3400>, Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRZ_WU_S : LASX2R_XX<0x769e7000>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINTRZ_LU_D : LASX2R_XX<0x769e7400>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINT_WU_S : LASX2R_XX<0x769e5800>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+def XVFTINT_LU_D : LASX2R_XX<0x769e5c00>,
+ Sched<[WriteVFTINT256, ReadVFTINT256]>;
+
+def XVFTINTRNE_W_D : LASX3R_XXX<0x754b8000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRZ_W_D : LASX3R_XXX<0x754b0000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRP_W_D : LASX3R_XXX<0x754a8000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRM_W_D : LASX3R_XXX<0x754a0000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256, ReadVFTINTX256]>;
+def XVFTINT_W_D : LASX3R_XXX<0x75498000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256, ReadVFTINTX256]>;
+
+def XVFTINTRNEL_L_S : LASX2R_XX<0x769ea000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRNEH_L_S : LASX2R_XX<0x769ea400>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRZL_L_S : LASX2R_XX<0x769e9800>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRZH_L_S : LASX2R_XX<0x769e9c00>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRPL_L_S : LASX2R_XX<0x769e9000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRPH_L_S : LASX2R_XX<0x769e9400>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRML_L_S : LASX2R_XX<0x769e8800>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTRMH_L_S : LASX2R_XX<0x769e8c00>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTL_L_S : LASX2R_XX<0x769e8000>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+def XVFTINTH_L_S : LASX2R_XX<0x769e8400>,
+ Sched<[WriteVFTINTX256, ReadVFTINTX256]>;
+
+def XVFFINT_S_W : LASX2R_XX<0x769e0000>, Sched<[WriteVFFINT256, ReadVFFINT256]>;
+def XVFFINT_D_L : LASX2R_XX<0x769e0800>, Sched<[WriteVFFINT256, ReadVFFINT256]>;
+def XVFFINT_S_WU : LASX2R_XX<0x769e0400>,
+ Sched<[WriteVFFINT256, ReadVFFINT256]>;
+def XVFFINT_D_LU : LASX2R_XX<0x769e0c00>,
+ Sched<[WriteVFFINT256, ReadVFFINT256]>;
+def XVFFINTL_D_W : LASX2R_XX<0x769e1000>,
+ Sched<[WriteVFFINTX256, ReadVFFINTX256]>;
+def XVFFINTH_D_W : LASX2R_XX<0x769e1400>,
+ Sched<[WriteVFFINTX256, ReadVFFINTX256]>;
+def XVFFINT_S_L : LASX3R_XXX<0x75480000>,
+ Sched<[WriteVFFINTX256, ReadVFFINTX256, ReadVFFINTX256]>;
+
+def XVSEQ_B : LASX3R_XXX<0x74000000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSEQ_H : LASX3R_XXX<0x74008000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSEQ_W : LASX3R_XXX<0x74010000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSEQ_D : LASX3R_XXX<0x74018000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSEQI_B : LASX2RI5_XXI<0x76800000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSEQI_H : LASX2RI5_XXI<0x76808000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSEQI_W : LASX2RI5_XXI<0x76810000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSEQI_D : LASX2RI5_XXI<0x76818000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+
+def XVSLE_B : LASX3R_XXX<0x74020000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLE_H : LASX3R_XXX<0x74028000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLE_W : LASX3R_XXX<0x74030000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLE_D : LASX3R_XXX<0x74038000>,
+ Sched<[WriteVCMPD256, ReadVCMPD256, ReadVCMPD256]>;
+def XVSLEI_B : LASX2RI5_XXI<0x76820000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLEI_H : LASX2RI5_XXI<0x76828000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLEI_W : LASX2RI5_XXI<0x76830000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLEI_D : LASX2RI5_XXI<0x76838000, simm5>,
+ Sched<[WriteVCMPD256, ReadVCMPD256]>;
+
+def XVSLE_BU : LASX3R_XXX<0x74040000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLE_HU : LASX3R_XXX<0x74048000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLE_WU : LASX3R_XXX<0x74050000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLE_DU : LASX3R_XXX<0x74058000>,
+ Sched<[WriteVCMPD256, ReadVCMPD256, ReadVCMPD256]>;
+def XVSLEI_BU : LASX2RI5_XXI<0x76840000>, Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLEI_HU : LASX2RI5_XXI<0x76848000>, Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLEI_WU : LASX2RI5_XXI<0x76850000>, Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLEI_DU : LASX2RI5_XXI<0x76858000>, Sched<[WriteVCMPD256, ReadVCMPD256]>;
+
+def XVSLT_B : LASX3R_XXX<0x74060000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLT_H : LASX3R_XXX<0x74068000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLT_W : LASX3R_XXX<0x74070000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLT_D : LASX3R_XXX<0x74078000>,
+ Sched<[WriteVCMPD256, ReadVCMPD256, ReadVCMPD256]>;
+def XVSLTI_B : LASX2RI5_XXI<0x76860000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLTI_H : LASX2RI5_XXI<0x76868000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLTI_W : LASX2RI5_XXI<0x76870000, simm5>,
+ Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLTI_D : LASX2RI5_XXI<0x76878000, simm5>,
+ Sched<[WriteVCMPD256, ReadVCMPD256]>;
+
+def XVSLT_BU : LASX3R_XXX<0x74080000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLT_HU : LASX3R_XXX<0x74088000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLT_WU : LASX3R_XXX<0x74090000>,
+ Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>;
+def XVSLT_DU : LASX3R_XXX<0x74098000>,
+ Sched<[WriteVCMPD256, ReadVCMPD256, ReadVCMPD256]>;
+def XVSLTI_BU : LASX2RI5_XXI<0x76880000>, Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLTI_HU : LASX2RI5_XXI<0x76888000>, Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLTI_WU : LASX2RI5_XXI<0x76890000>, Sched<[WriteVCMP256, ReadVCMP256]>;
+def XVSLTI_DU : LASX2RI5_XXI<0x76898000>, Sched<[WriteVCMPD256, ReadVCMPD256]>;
+
+def XVFCMP_CAF_S : LASX3R_XXX<0x0c900000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SAF_S : LASX3R_XXX<0x0c908000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CLT_S : LASX3R_XXX<0x0c910000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SLT_S : LASX3R_XXX<0x0c918000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CEQ_S : LASX3R_XXX<0x0c920000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SEQ_S : LASX3R_XXX<0x0c928000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CLE_S : LASX3R_XXX<0x0c930000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SLE_S : LASX3R_XXX<0x0c938000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CUN_S : LASX3R_XXX<0x0c940000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SUN_S : LASX3R_XXX<0x0c948000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CULT_S : LASX3R_XXX<0x0c950000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SULT_S : LASX3R_XXX<0x0c958000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CUEQ_S : LASX3R_XXX<0x0c960000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SUEQ_S : LASX3R_XXX<0x0c968000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CULE_S : LASX3R_XXX<0x0c970000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SULE_S : LASX3R_XXX<0x0c978000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CNE_S : LASX3R_XXX<0x0c980000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SNE_S : LASX3R_XXX<0x0c988000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_COR_S : LASX3R_XXX<0x0c9a0000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SOR_S : LASX3R_XXX<0x0c9a8000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CUNE_S : LASX3R_XXX<0x0c9c0000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SUNE_S : LASX3R_XXX<0x0c9c8000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+
+def XVFCMP_CAF_D : LASX3R_XXX<0x0ca00000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SAF_D : LASX3R_XXX<0x0ca08000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CLT_D : LASX3R_XXX<0x0ca10000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SLT_D : LASX3R_XXX<0x0ca18000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CEQ_D : LASX3R_XXX<0x0ca20000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SEQ_D : LASX3R_XXX<0x0ca28000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CLE_D : LASX3R_XXX<0x0ca30000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SLE_D : LASX3R_XXX<0x0ca38000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CUN_D : LASX3R_XXX<0x0ca40000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SUN_D : LASX3R_XXX<0x0ca48000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CULT_D : LASX3R_XXX<0x0ca50000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SULT_D : LASX3R_XXX<0x0ca58000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CUEQ_D : LASX3R_XXX<0x0ca60000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SUEQ_D : LASX3R_XXX<0x0ca68000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CULE_D : LASX3R_XXX<0x0ca70000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SULE_D : LASX3R_XXX<0x0ca78000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CNE_D : LASX3R_XXX<0x0ca80000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SNE_D : LASX3R_XXX<0x0ca88000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_COR_D : LASX3R_XXX<0x0caa0000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SOR_D : LASX3R_XXX<0x0caa8000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_CUNE_D : LASX3R_XXX<0x0cac0000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+def XVFCMP_SUNE_D : LASX3R_XXX<0x0cac8000>,
+ Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>;
+
+def XVBITSEL_V : LASX4R_XXXX<0x0d200000>,
+ Sched<[WriteVBITSEL256, ReadVBITSEL256, ReadVBITSEL256, ReadVBITSEL256]>;
+
+def XVBITSELI_B : LASX2RI8_XXXI<0x77c40000>,
+ Sched<[WriteVBITSEL256, ReadVBITSEL256, ReadVBITSEL256]>;
+
+def XVSETEQZ_V : LASX2R_CX<0x769c9800>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETNEZ_V : LASX2R_CX<0x769c9c00>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETANYEQZ_B : LASX2R_CX<0x769ca000>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETANYEQZ_H : LASX2R_CX<0x769ca400>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETANYEQZ_W : LASX2R_CX<0x769ca800>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETANYEQZ_D : LASX2R_CX<0x769cac00>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETALLNEZ_B : LASX2R_CX<0x769cb000>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETALLNEZ_H : LASX2R_CX<0x769cb400>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETALLNEZ_W : LASX2R_CX<0x769cb800>, Sched<[WriteVSET256, ReadVSET256]>;
+def XVSETALLNEZ_D : LASX2R_CX<0x769cbc00>, Sched<[WriteVSET256, ReadVSET256]>;
+
+def XVINSGR2VR_W : LASX2RI3_XXRI<0x76ebc000>,
+ Sched<[WriteVINSGR2VR256, ReadVINSGR2VR256, ReadVINSGR2VR256]>;
+def XVINSGR2VR_D : LASX2RI2_XXRI<0x76ebe000>,
+ Sched<[WriteVINSGR2VR256, ReadVINSGR2VR256, ReadVINSGR2VR256]>;
+def XVPICKVE2GR_W : LASX2RI3_RXI<0x76efc000>,
+ Sched<[WriteVPICKVE2GR256, ReadVPICKVE2GR256]>;
+def XVPICKVE2GR_D : LASX2RI2_RXI<0x76efe000>,
+ Sched<[WriteVPICKVE2GR256, ReadVPICKVE2GR256]>;
+def XVPICKVE2GR_WU : LASX2RI3_RXI<0x76f3c000>,
+ Sched<[WriteVPICKVE2GR256, ReadVPICKVE2GR256]>;
+def XVPICKVE2GR_DU : LASX2RI2_RXI<0x76f3e000>,
+ Sched<[WriteVPICKVE2GR256, ReadVPICKVE2GR256]>;
let isReMaterializable = 1 in {
-def XVREPLGR2VR_B : LASX2R_XR<0x769f0000>;
-def XVREPLGR2VR_H : LASX2R_XR<0x769f0400>;
-def XVREPLGR2VR_W : LASX2R_XR<0x769f0800>;
-def XVREPLGR2VR_D : LASX2R_XR<0x769f0c00>;
+def XVREPLGR2VR_B : LASX2R_XR<0x769f0000>,
+ Sched<[WriteVREPLGR2VR256, ReadVREPLGR2VR256]>;
+def XVREPLGR2VR_H : LASX2R_XR<0x769f0400>,
+ Sched<[WriteVREPLGR2VR256, ReadVREPLGR2VR256]>;
+def XVREPLGR2VR_W : LASX2R_XR<0x769f0800>,
+ Sched<[WriteVREPLGR2VRWD256, ReadVREPLGR2VRWD256]>;
+def XVREPLGR2VR_D : LASX2R_XR<0x769f0c00>,
+ Sched<[WriteVREPLGR2VRWD256, ReadVREPLGR2VRWD256]>;
}
-def XVREPLVE_B : LASX3R_XXR<0x75220000>;
-def XVREPLVE_H : LASX3R_XXR<0x75228000>;
-def XVREPLVE_W : LASX3R_XXR<0x75230000>;
-def XVREPLVE_D : LASX3R_XXR<0x75238000>;
-def XVREPL128VEI_B : LASX2RI4_XXI<0x76f78000>;
-def XVREPL128VEI_H : LASX2RI3_XXI<0x76f7c000>;
-def XVREPL128VEI_W : LASX2RI2_XXI<0x76f7e000>;
-def XVREPL128VEI_D : LASX2RI1_XXI<0x76f7f000>;
-
-def XVREPLVE0_B : LASX2R_XX<0x77070000>;
-def XVREPLVE0_H : LASX2R_XX<0x77078000>;
-def XVREPLVE0_W : LASX2R_XX<0x7707c000>;
-def XVREPLVE0_D : LASX2R_XX<0x7707e000>;
-def XVREPLVE0_Q : LASX2R_XX<0x7707f000>;
-
-def XVINSVE0_W : LASX2RI3_XXXI<0x76ffc000>;
-def XVINSVE0_D : LASX2RI2_XXXI<0x76ffe000>;
-
-def XVPICKVE_W : LASX2RI3_XXI<0x7703c000>;
-def XVPICKVE_D : LASX2RI2_XXI<0x7703e000>;
-
-def XVBSLL_V : LASX2RI5_XXI<0x768e0000>;
-def XVBSRL_V : LASX2RI5_XXI<0x768e8000>;
-
-def XVPACKEV_B : LASX3R_XXX<0x75160000>;
-def XVPACKEV_H : LASX3R_XXX<0x75168000>;
-def XVPACKEV_W : LASX3R_XXX<0x75170000>;
-def XVPACKEV_D : LASX3R_XXX<0x75178000>;
-def XVPACKOD_B : LASX3R_XXX<0x75180000>;
-def XVPACKOD_H : LASX3R_XXX<0x75188000>;
-def XVPACKOD_W : LASX3R_XXX<0x75190000>;
-def XVPACKOD_D : LASX3R_XXX<0x75198000>;
-
-def XVPICKEV_B : LASX3R_XXX<0x751e0000>;
-def XVPICKEV_H : LASX3R_XXX<0x751e8000>;
-def XVPICKEV_W : LASX3R_XXX<0x751f0000>;
-def XVPICKEV_D : LASX3R_XXX<0x751f8000>;
-def XVPICKOD_B : LASX3R_XXX<0x75200000>;
-def XVPICKOD_H : LASX3R_XXX<0x75208000>;
-def XVPICKOD_W : LASX3R_XXX<0x75210000>;
-def XVPICKOD_D : LASX3R_XXX<0x75218000>;
-
-def XVILVL_B : LASX3R_XXX<0x751a0000>;
-def XVILVL_H : LASX3R_XXX<0x751a8000>;
-def XVILVL_W : LASX3R_XXX<0x751b0000>;
-def XVILVL_D : LASX3R_XXX<0x751b8000>;
-def XVILVH_B : LASX3R_XXX<0x751c0000>;
-def XVILVH_H : LASX3R_XXX<0x751c8000>;
-def XVILVH_W : LASX3R_XXX<0x751d0000>;
-def XVILVH_D : LASX3R_XXX<0x751d8000>;
-
-def XVSHUF_B : LASX4R_XXXX<0x0d600000>;
-
-def XVSHUF_H : LASX3R_XXXX<0x757a8000>;
-def XVSHUF_W : LASX3R_XXXX<0x757b0000>;
-def XVSHUF_D : LASX3R_XXXX<0x757b8000>;
-
-def XVPERM_W : LASX3R_XXX<0x757d0000>;
-
-def XVSHUF4I_B : LASX2RI8_XXI<0x77900000>;
-def XVSHUF4I_H : LASX2RI8_XXI<0x77940000>;
-def XVSHUF4I_W : LASX2RI8_XXI<0x77980000>;
-def XVSHUF4I_D : LASX2RI8_XXXI<0x779c0000>;
-
-def XVPERMI_W : LASX2RI8_XXXI<0x77e40000>;
-def XVPERMI_D : LASX2RI8_XXI<0x77e80000>;
-def XVPERMI_Q : LASX2RI8_XXXI<0x77ec0000>;
-
-def XVEXTRINS_D : LASX2RI8_XXXI<0x77800000>;
-def XVEXTRINS_W : LASX2RI8_XXXI<0x77840000>;
-def XVEXTRINS_H : LASX2RI8_XXXI<0x77880000>;
-def XVEXTRINS_B : LASX2RI8_XXXI<0x778c0000>;
+def XVREPLVE_B : LASX3R_XXR<0x75220000>,
+ Sched<[WriteVREPLVE256, ReadVREPLVE256, ReadVREPLVE256]>;
+def XVREPLVE_H : LASX3R_XXR<0x75228000>,
+ Sched<[WriteVREPLVE256, ReadVREPLVE256, ReadVREPLVE256]>;
+def XVREPLVE_W : LASX3R_XXR<0x75230000>,
+ Sched<[WriteVREPLVE256, ReadVREPLVE256, ReadVREPLVE256]>;
+def XVREPLVE_D : LASX3R_XXR<0x75238000>,
+ Sched<[WriteVREPLVE256, ReadVREPLVE256, ReadVREPLVE256]>;
+def XVREPL128VEI_B : LASX2RI4_XXI<0x76f78000>,
+ Sched<[WriteVREPLVEI256, ReadVREPLVEI256]>;
+def XVREPL128VEI_H : LASX2RI3_XXI<0x76f7c000>,
+ Sched<[WriteVREPLVEI256, ReadVREPLVEI256]>;
+def XVREPL128VEI_W : LASX2RI2_XXI<0x76f7e000>,
+ Sched<[WriteVREPLVEI256, ReadVREPLVEI256]>;
+def XVREPL128VEI_D : LASX2RI1_XXI<0x76f7f000>,
+ Sched<[WriteVREPLVEI256, ReadVREPLVEI256]>;
+
+def XVREPLVE0_B : LASX2R_XX<0x77070000>,
+ Sched<[WriteVREPLVE0256, ReadVREPLVE0256]>;
+def XVREPLVE0_H : LASX2R_XX<0x77078000>,
+ Sched<[WriteVREPLVE0256, ReadVREPLVE0256]>;
+def XVREPLVE0_W : LASX2R_XX<0x7707c000>,
+ Sched<[WriteVREPLVE0256, ReadVREPLVE0256]>;
+def XVREPLVE0_D : LASX2R_XX<0x7707e000>,
+ Sched<[WriteVREPLVE0256, ReadVREPLVE0256]>;
+def XVREPLVE0_Q : LASX2R_XX<0x7707f000>,
+ Sched<[WriteVREPLVE0256, ReadVREPLVE0256]>;
+
+def XVINSVE0_W : LASX2RI3_XXXI<0x76ffc000>,
+ Sched<[WriteVINSVE0256, ReadVINSVE0256, ReadVINSVE0256]>;
+def XVINSVE0_D : LASX2RI2_XXXI<0x76ffe000>,
+ Sched<[WriteVINSVE0256, ReadVINSVE0256, ReadVINSVE0256]>;
+
+def XVPICKVE_W : LASX2RI3_XXI<0x7703c000>,
+ Sched<[WriteVPICKVE256, ReadVPICKVE256]>;
+def XVPICKVE_D : LASX2RI2_XXI<0x7703e000>,
+ Sched<[WriteVPICKVE256, ReadVPICKVE256]>;
+
+def XVBSLL_V : LASX2RI5_XXI<0x768e0000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+def XVBSRL_V : LASX2RI5_XXI<0x768e8000>, Sched<[WriteVSHIFT256, ReadVSHIFT256]>;
+
+def XVPACKEV_B : LASX3R_XXX<0x75160000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKEV_H : LASX3R_XXX<0x75168000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKEV_W : LASX3R_XXX<0x75170000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKEV_D : LASX3R_XXX<0x75178000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKOD_B : LASX3R_XXX<0x75180000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKOD_H : LASX3R_XXX<0x75188000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKOD_W : LASX3R_XXX<0x75190000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPACKOD_D : LASX3R_XXX<0x75198000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+
+def XVPICKEV_B : LASX3R_XXX<0x751e0000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKEV_H : LASX3R_XXX<0x751e8000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKEV_W : LASX3R_XXX<0x751f0000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKEV_D : LASX3R_XXX<0x751f8000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKOD_B : LASX3R_XXX<0x75200000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKOD_H : LASX3R_XXX<0x75208000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKOD_W : LASX3R_XXX<0x75210000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVPICKOD_D : LASX3R_XXX<0x75218000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+
+def XVILVL_B : LASX3R_XXX<0x751a0000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVL_H : LASX3R_XXX<0x751a8000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVL_W : LASX3R_XXX<0x751b0000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVL_D : LASX3R_XXX<0x751b8000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVH_B : LASX3R_XXX<0x751c0000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVH_H : LASX3R_XXX<0x751c8000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVH_W : LASX3R_XXX<0x751d0000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+def XVILVH_D : LASX3R_XXX<0x751d8000>,
+ Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>;
+
+def XVSHUF_B : LASX4R_XXXX<0x0d600000>,
+ Sched<[WriteVSHUF256, ReadVSHUF256, ReadVSHUF256, ReadVSHUF256]>;
+
+def XVSHUF_H : LASX3R_XXXX<0x757a8000>,
+ Sched<[WriteVSHUF256, ReadVSHUF256, ReadVSHUF256, ReadVSHUF256]>;
+def XVSHUF_W : LASX3R_XXXX<0x757b0000>,
+ Sched<[WriteVSHUF256, ReadVSHUF256, ReadVSHUF256, ReadVSHUF256]>;
+def XVSHUF_D : LASX3R_XXXX<0x757b8000>,
+ Sched<[WriteVSHUF256, ReadVSHUF256, ReadVSHUF256, ReadVSHUF256]>;
+
+def XVPERM_W : LASX3R_XXX<0x757d0000>,
+ Sched<[WriteVPERM256, ReadVPERM256, ReadVPERM256]>;
+
+def XVSHUF4I_B : LASX2RI8_XXI<0x77900000>,
+ Sched<[WriteVSHUF4I256, ReadVSHUF4I256]>;
+def XVSHUF4I_H : LASX2RI8_XXI<0x77940000>,
+ Sched<[WriteVSHUF4I256, ReadVSHUF4I256]>;
+def XVSHUF4I_W : LASX2RI8_XXI<0x77980000>,
+ Sched<[WriteVSHUF4I256, ReadVSHUF4I256]>;
+def XVSHUF4I_D : LASX2RI8_XXXI<0x779c0000>,
+ Sched<[WriteVSHUF4I256, ReadVSHUF4I256, ReadVSHUF4I256]>;
+
+def XVPERMI_W : LASX2RI8_XXXI<0x77e40000>,
+ Sched<[WriteVPERMI256, ReadVPERMI256, ReadVPERMI256]>;
+def XVPERMI_D : LASX2RI8_XXI<0x77e80000>, Sched<[WriteVPERM256, ReadVPERM256]>;
+def XVPERMI_Q : LASX2RI8_XXXI<0x77ec0000>,
+ Sched<[WriteVPERM256, ReadVPERM256, ReadVPERM256]>;
+
+def XVEXTRINS_D : LASX2RI8_XXXI<0x77800000>,
+ Sched<[WriteVEXTRINS256, ReadVEXTRINS256, ReadVEXTRINS256]>;
+def XVEXTRINS_W : LASX2RI8_XXXI<0x77840000>,
+ Sched<[WriteVEXTRINS256, ReadVEXTRINS256, ReadVEXTRINS256]>;
+def XVEXTRINS_H : LASX2RI8_XXXI<0x77880000>,
+ Sched<[WriteVEXTRINS256, ReadVEXTRINS256, ReadVEXTRINS256]>;
+def XVEXTRINS_B : LASX2RI8_XXXI<0x778c0000>,
+ Sched<[WriteVEXTRINS256, ReadVEXTRINS256, ReadVEXTRINS256]>;
} // mayLoad = 0, mayStore = 0
let mayLoad = 1, mayStore = 0 in {
-def XVLD : LASX2RI12_Load<0x2c800000>;
-def XVLDX : LASX3R_Load<0x38480000>;
-
-def XVLDREPL_B : LASX2RI12_Load<0x32800000>;
-def XVLDREPL_H : LASX2RI11_Load<0x32400000>;
-def XVLDREPL_W : LASX2RI10_Load<0x32200000>;
-def XVLDREPL_D : LASX2RI9_Load<0x32100000>;
+def XVLD : LASX2RI12_Load<0x2c800000>, Sched<[WriteVLD256, ReadVMemBase256]>;
+def XVLDX : LASX3R_Load<0x38480000>,
+ Sched<[WriteVLDX256, ReadVMemBase256, ReadVMemOffset256]>;
+
+def XVLDREPL_B : LASX2RI12_Load<0x32800000>,
+ Sched<[WriteVLDREPL256, ReadVMemBase256]>;
+def XVLDREPL_H : LASX2RI11_Load<0x32400000>,
+ Sched<[WriteVLDREPL256, ReadVMemBase256]>;
+def XVLDREPL_W : LASX2RI10_Load<0x32200000>,
+ Sched<[WriteVLDREPL256, ReadVMemBase256]>;
+def XVLDREPL_D : LASX2RI9_Load<0x32100000>,
+ Sched<[WriteVLDREPL256, ReadVMemBase256]>;
} // mayLoad = 1, mayStore = 0
let mayLoad = 0, mayStore = 1 in {
-def XVST : LASX2RI12_Store<0x2cc00000>;
-def XVSTX : LASX3R_Store<0x384c0000>;
-
-def XVSTELM_B : LASX2RI8I5_XRII<0x33800000>;
-def XVSTELM_H : LASX2RI8I4_XRII<0x33400000, simm8_lsl1>;
-def XVSTELM_W : LASX2RI8I3_XRII<0x33200000, simm8_lsl2>;
-def XVSTELM_D : LASX2RI8I2_XRII<0x33100000, simm8_lsl3>;
+def XVST : LASX2RI12_Store<0x2cc00000>,
+ Sched<[WriteVST256, ReadVSTData256, ReadVMemBase256]>;
+def XVSTX : LASX3R_Store<0x384c0000>,
+ Sched<[WriteVSTX256, ReadVSTData256, ReadVMemBase256, ReadVMemOffset256]>;
+
+def XVSTELM_B : LASX2RI8I5_XRII<0x33800000>,
+ Sched<[WriteVSTELM256, ReadVSTData256, ReadVMemBase256]>;
+def XVSTELM_H : LASX2RI8I4_XRII<0x33400000, simm8_lsl1>,
+ Sched<[WriteVSTELM256, ReadVSTData256, ReadVMemBase256]>;
+def XVSTELM_W : LASX2RI8I3_XRII<0x33200000, simm8_lsl2>,
+ Sched<[WriteVSTELM256, ReadVSTData256, ReadVMemBase256]>;
+def XVSTELM_D : LASX2RI8I2_XRII<0x33100000, simm8_lsl3>,
+ Sched<[WriteVSTELM256, ReadVSTData256, ReadVMemBase256]>;
} // mayLoad = 0, mayStore = 1
} // hasSideEffects = 0, Predicates = [HasExtLASX]
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 351f0a4cf86d2..62ba038cfc309 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -488,825 +488,1417 @@ let hasSideEffects = 0, Predicates = [HasExtLSX] in {
let mayLoad = 0, mayStore = 0 in {
-def VADD_B : LSX3R_VVV<0x700a0000>;
-def VADD_H : LSX3R_VVV<0x700a8000>;
-def VADD_W : LSX3R_VVV<0x700b0000>;
-def VADD_D : LSX3R_VVV<0x700b8000>;
-def VADD_Q : LSX3R_VVV<0x712d0000>;
-
-def VSUB_B : LSX3R_VVV<0x700c0000>;
-def VSUB_H : LSX3R_VVV<0x700c8000>;
-def VSUB_W : LSX3R_VVV<0x700d0000>;
-def VSUB_D : LSX3R_VVV<0x700d8000>;
-def VSUB_Q : LSX3R_VVV<0x712d8000>;
-
-def VADDI_BU : LSX2RI5_VVI<0x728a0000>;
-def VADDI_HU : LSX2RI5_VVI<0x728a8000>;
-def VADDI_WU : LSX2RI5_VVI<0x728b0000>;
-def VADDI_DU : LSX2RI5_VVI<0x728b8000>;
-
-def VSUBI_BU : LSX2RI5_VVI<0x728c0000>;
-def VSUBI_HU : LSX2RI5_VVI<0x728c8000>;
-def VSUBI_WU : LSX2RI5_VVI<0x728d0000>;
-def VSUBI_DU : LSX2RI5_VVI<0x728d8000>;
-
-def VNEG_B : LSX2R_VV<0x729c3000>;
-def VNEG_H : LSX2R_VV<0x729c3400>;
-def VNEG_W : LSX2R_VV<0x729c3800>;
-def VNEG_D : LSX2R_VV<0x729c3c00>;
-
-def VSADD_B : LSX3R_VVV<0x70460000>;
-def VSADD_H : LSX3R_VVV<0x70468000>;
-def VSADD_W : LSX3R_VVV<0x70470000>;
-def VSADD_D : LSX3R_VVV<0x70478000>;
-def VSADD_BU : LSX3R_VVV<0x704a0000>;
-def VSADD_HU : LSX3R_VVV<0x704a8000>;
-def VSADD_WU : LSX3R_VVV<0x704b0000>;
-def VSADD_DU : LSX3R_VVV<0x704b8000>;
-
-def VSSUB_B : LSX3R_VVV<0x70480000>;
-def VSSUB_H : LSX3R_VVV<0x70488000>;
-def VSSUB_W : LSX3R_VVV<0x70490000>;
-def VSSUB_D : LSX3R_VVV<0x70498000>;
-def VSSUB_BU : LSX3R_VVV<0x704c0000>;
-def VSSUB_HU : LSX3R_VVV<0x704c8000>;
-def VSSUB_WU : LSX3R_VVV<0x704d0000>;
-def VSSUB_DU : LSX3R_VVV<0x704d8000>;
-
-def VHADDW_H_B : LSX3R_VVV<0x70540000>;
-def VHADDW_W_H : LSX3R_VVV<0x70548000>;
-def VHADDW_D_W : LSX3R_VVV<0x70550000>;
-def VHADDW_Q_D : LSX3R_VVV<0x70558000>;
-def VHADDW_HU_BU : LSX3R_VVV<0x70580000>;
-def VHADDW_WU_HU : LSX3R_VVV<0x70588000>;
-def VHADDW_DU_WU : LSX3R_VVV<0x70590000>;
-def VHADDW_QU_DU : LSX3R_VVV<0x70598000>;
-
-def VHSUBW_H_B : LSX3R_VVV<0x70560000>;
-def VHSUBW_W_H : LSX3R_VVV<0x70568000>;
-def VHSUBW_D_W : LSX3R_VVV<0x70570000>;
-def VHSUBW_Q_D : LSX3R_VVV<0x70578000>;
-def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>;
-def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>;
-def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>;
-def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>;
-
-def VADDWEV_H_B : LSX3R_VVV<0x701e0000>;
-def VADDWEV_W_H : LSX3R_VVV<0x701e8000>;
-def VADDWEV_D_W : LSX3R_VVV<0x701f0000>;
-def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>;
-def VADDWOD_H_B : LSX3R_VVV<0x70220000>;
-def VADDWOD_W_H : LSX3R_VVV<0x70228000>;
-def VADDWOD_D_W : LSX3R_VVV<0x70230000>;
-def VADDWOD_Q_D : LSX3R_VVV<0x70238000>;
-
-def VSUBWEV_H_B : LSX3R_VVV<0x70200000>;
-def VSUBWEV_W_H : LSX3R_VVV<0x70208000>;
-def VSUBWEV_D_W : LSX3R_VVV<0x70210000>;
-def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>;
-def VSUBWOD_H_B : LSX3R_VVV<0x70240000>;
-def VSUBWOD_W_H : LSX3R_VVV<0x70248000>;
-def VSUBWOD_D_W : LSX3R_VVV<0x70250000>;
-def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>;
-
-def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>;
-def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>;
-def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>;
-def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>;
-def VADDWOD_H_BU : LSX3R_VVV<0x70320000>;
-def VADDWOD_W_HU : LSX3R_VVV<0x70328000>;
-def VADDWOD_D_WU : LSX3R_VVV<0x70330000>;
-def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>;
-
-def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>;
-def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>;
-def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>;
-def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>;
-def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>;
-def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>;
-def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>;
-def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>;
-
-def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>;
-def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>;
-def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>;
-def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>;
-def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>;
-def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>;
-def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>;
-def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>;
-
-def VAVG_B : LSX3R_VVV<0x70640000>;
-def VAVG_H : LSX3R_VVV<0x70648000>;
-def VAVG_W : LSX3R_VVV<0x70650000>;
-def VAVG_D : LSX3R_VVV<0x70658000>;
-def VAVG_BU : LSX3R_VVV<0x70660000>;
-def VAVG_HU : LSX3R_VVV<0x70668000>;
-def VAVG_WU : LSX3R_VVV<0x70670000>;
-def VAVG_DU : LSX3R_VVV<0x70678000>;
-def VAVGR_B : LSX3R_VVV<0x70680000>;
-def VAVGR_H : LSX3R_VVV<0x70688000>;
-def VAVGR_W : LSX3R_VVV<0x70690000>;
-def VAVGR_D : LSX3R_VVV<0x70698000>;
-def VAVGR_BU : LSX3R_VVV<0x706a0000>;
-def VAVGR_HU : LSX3R_VVV<0x706a8000>;
-def VAVGR_WU : LSX3R_VVV<0x706b0000>;
-def VAVGR_DU : LSX3R_VVV<0x706b8000>;
-
-def VABSD_B : LSX3R_VVV<0x70600000>;
-def VABSD_H : LSX3R_VVV<0x70608000>;
-def VABSD_W : LSX3R_VVV<0x70610000>;
-def VABSD_D : LSX3R_VVV<0x70618000>;
-def VABSD_BU : LSX3R_VVV<0x70620000>;
-def VABSD_HU : LSX3R_VVV<0x70628000>;
-def VABSD_WU : LSX3R_VVV<0x70630000>;
-def VABSD_DU : LSX3R_VVV<0x70638000>;
-
-def VADDA_B : LSX3R_VVV<0x705c0000>;
-def VADDA_H : LSX3R_VVV<0x705c8000>;
-def VADDA_W : LSX3R_VVV<0x705d0000>;
-def VADDA_D : LSX3R_VVV<0x705d8000>;
-
-def VMAX_B : LSX3R_VVV<0x70700000>;
-def VMAX_H : LSX3R_VVV<0x70708000>;
-def VMAX_W : LSX3R_VVV<0x70710000>;
-def VMAX_D : LSX3R_VVV<0x70718000>;
-def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>;
-def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>;
-def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>;
-def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>;
-def VMAX_BU : LSX3R_VVV<0x70740000>;
-def VMAX_HU : LSX3R_VVV<0x70748000>;
-def VMAX_WU : LSX3R_VVV<0x70750000>;
-def VMAX_DU : LSX3R_VVV<0x70758000>;
-def VMAXI_BU : LSX2RI5_VVI<0x72940000>;
-def VMAXI_HU : LSX2RI5_VVI<0x72948000>;
-def VMAXI_WU : LSX2RI5_VVI<0x72950000>;
-def VMAXI_DU : LSX2RI5_VVI<0x72958000>;
-
-def VMIN_B : LSX3R_VVV<0x70720000>;
-def VMIN_H : LSX3R_VVV<0x70728000>;
-def VMIN_W : LSX3R_VVV<0x70730000>;
-def VMIN_D : LSX3R_VVV<0x70738000>;
-def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>;
-def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>;
-def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>;
-def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>;
-def VMIN_BU : LSX3R_VVV<0x70760000>;
-def VMIN_HU : LSX3R_VVV<0x70768000>;
-def VMIN_WU : LSX3R_VVV<0x70770000>;
-def VMIN_DU : LSX3R_VVV<0x70778000>;
-def VMINI_BU : LSX2RI5_VVI<0x72960000>;
-def VMINI_HU : LSX2RI5_VVI<0x72968000>;
-def VMINI_WU : LSX2RI5_VVI<0x72970000>;
-def VMINI_DU : LSX2RI5_VVI<0x72978000>;
-
-def VMUL_B : LSX3R_VVV<0x70840000>;
-def VMUL_H : LSX3R_VVV<0x70848000>;
-def VMUL_W : LSX3R_VVV<0x70850000>;
-def VMUL_D : LSX3R_VVV<0x70858000>;
-
-def VMUH_B : LSX3R_VVV<0x70860000>;
-def VMUH_H : LSX3R_VVV<0x70868000>;
-def VMUH_W : LSX3R_VVV<0x70870000>;
-def VMUH_D : LSX3R_VVV<0x70878000>;
-def VMUH_BU : LSX3R_VVV<0x70880000>;
-def VMUH_HU : LSX3R_VVV<0x70888000>;
-def VMUH_WU : LSX3R_VVV<0x70890000>;
-def VMUH_DU : LSX3R_VVV<0x70898000>;
-
-def VMULWEV_H_B : LSX3R_VVV<0x70900000>;
-def VMULWEV_W_H : LSX3R_VVV<0x70908000>;
-def VMULWEV_D_W : LSX3R_VVV<0x70910000>;
-def VMULWEV_Q_D : LSX3R_VVV<0x70918000>;
-def VMULWOD_H_B : LSX3R_VVV<0x70920000>;
-def VMULWOD_W_H : LSX3R_VVV<0x70928000>;
-def VMULWOD_D_W : LSX3R_VVV<0x70930000>;
-def VMULWOD_Q_D : LSX3R_VVV<0x70938000>;
-def VMULWEV_H_BU : LSX3R_VVV<0x70980000>;
-def VMULWEV_W_HU : LSX3R_VVV<0x70988000>;
-def VMULWEV_D_WU : LSX3R_VVV<0x70990000>;
-def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>;
-def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>;
-def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>;
-def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>;
-def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>;
-def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>;
-def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>;
-def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>;
-def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>;
-def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>;
-def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>;
-def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>;
-def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>;
-
-def VMADD_B : LSX3R_VVVV<0x70a80000>;
-def VMADD_H : LSX3R_VVVV<0x70a88000>;
-def VMADD_W : LSX3R_VVVV<0x70a90000>;
-def VMADD_D : LSX3R_VVVV<0x70a98000>;
-
-def VMSUB_B : LSX3R_VVVV<0x70aa0000>;
-def VMSUB_H : LSX3R_VVVV<0x70aa8000>;
-def VMSUB_W : LSX3R_VVVV<0x70ab0000>;
-def VMSUB_D : LSX3R_VVVV<0x70ab8000>;
-
-def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>;
-def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>;
-def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>;
-def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>;
-def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>;
-def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>;
-def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>;
-def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>;
-def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>;
-def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>;
-def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>;
-def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>;
-def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>;
-def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>;
-def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>;
-def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>;
-def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>;
-def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>;
-def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>;
-def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>;
-def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>;
-def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>;
-def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>;
-def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>;
-
-def VDIV_B : LSX3R_VVV<0x70e00000>;
-def VDIV_H : LSX3R_VVV<0x70e08000>;
-def VDIV_W : LSX3R_VVV<0x70e10000>;
-def VDIV_D : LSX3R_VVV<0x70e18000>;
-def VDIV_BU : LSX3R_VVV<0x70e40000>;
-def VDIV_HU : LSX3R_VVV<0x70e48000>;
-def VDIV_WU : LSX3R_VVV<0x70e50000>;
-def VDIV_DU : LSX3R_VVV<0x70e58000>;
-
-def VMOD_B : LSX3R_VVV<0x70e20000>;
-def VMOD_H : LSX3R_VVV<0x70e28000>;
-def VMOD_W : LSX3R_VVV<0x70e30000>;
-def VMOD_D : LSX3R_VVV<0x70e38000>;
-def VMOD_BU : LSX3R_VVV<0x70e60000>;
-def VMOD_HU : LSX3R_VVV<0x70e68000>;
-def VMOD_WU : LSX3R_VVV<0x70e70000>;
-def VMOD_DU : LSX3R_VVV<0x70e78000>;
-
-def VSAT_B : LSX2RI3_VVI<0x73242000>;
-def VSAT_H : LSX2RI4_VVI<0x73244000>;
-def VSAT_W : LSX2RI5_VVI<0x73248000>;
-def VSAT_D : LSX2RI6_VVI<0x73250000>;
-def VSAT_BU : LSX2RI3_VVI<0x73282000>;
-def VSAT_HU : LSX2RI4_VVI<0x73284000>;
-def VSAT_WU : LSX2RI5_VVI<0x73288000>;
-def VSAT_DU : LSX2RI6_VVI<0x73290000>;
-
-def VEXTH_H_B : LSX2R_VV<0x729ee000>;
-def VEXTH_W_H : LSX2R_VV<0x729ee400>;
-def VEXTH_D_W : LSX2R_VV<0x729ee800>;
-def VEXTH_Q_D : LSX2R_VV<0x729eec00>;
-def VEXTH_HU_BU : LSX2R_VV<0x729ef000>;
-def VEXTH_WU_HU : LSX2R_VV<0x729ef400>;
-def VEXTH_DU_WU : LSX2R_VV<0x729ef800>;
-def VEXTH_QU_DU : LSX2R_VV<0x729efc00>;
-
-def VSIGNCOV_B : LSX3R_VVV<0x712e0000>;
-def VSIGNCOV_H : LSX3R_VVV<0x712e8000>;
-def VSIGNCOV_W : LSX3R_VVV<0x712f0000>;
-def VSIGNCOV_D : LSX3R_VVV<0x712f8000>;
-
-def VMSKLTZ_B : LSX2R_VV<0x729c4000>;
-def VMSKLTZ_H : LSX2R_VV<0x729c4400>;
-def VMSKLTZ_W : LSX2R_VV<0x729c4800>;
-def VMSKLTZ_D : LSX2R_VV<0x729c4c00>;
-
-def VMSKGEZ_B : LSX2R_VV<0x729c5000>;
-
-def VMSKNZ_B : LSX2R_VV<0x729c6000>;
+def VADD_B : LSX3R_VVV<0x700a0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VADD_H : LSX3R_VVV<0x700a8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VADD_W : LSX3R_VVV<0x700b0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VADD_D : LSX3R_VVV<0x700b8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VADD_Q : LSX3R_VVV<0x712d0000>,
+ Sched<[WriteVALUQ128, ReadVALUQ128, ReadVALUQ128]>;
+
+def VSUB_B : LSX3R_VVV<0x700c0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSUB_H : LSX3R_VVV<0x700c8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSUB_W : LSX3R_VVV<0x700d0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSUB_D : LSX3R_VVV<0x700d8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSUB_Q : LSX3R_VVV<0x712d8000>,
+ Sched<[WriteVALUQ128, ReadVALUQ128, ReadVALUQ128]>;
+
+def VADDI_BU : LSX2RI5_VVI<0x728a0000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VADDI_HU : LSX2RI5_VVI<0x728a8000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VADDI_WU : LSX2RI5_VVI<0x728b0000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VADDI_DU : LSX2RI5_VVI<0x728b8000>, Sched<[WriteVALU128, ReadVALU128]>;
+
+def VSUBI_BU : LSX2RI5_VVI<0x728c0000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VSUBI_HU : LSX2RI5_VVI<0x728c8000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VSUBI_WU : LSX2RI5_VVI<0x728d0000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VSUBI_DU : LSX2RI5_VVI<0x728d8000>, Sched<[WriteVALU128, ReadVALU128]>;
+
+def VNEG_B : LSX2R_VV<0x729c3000>, Sched<[WriteVALU128, ReadVALU128]>;
+def VNEG_H : LSX2R_VV<0x729c3400>, Sched<[WriteVALU128, ReadVALU128]>;
+def VNEG_W : LSX2R_VV<0x729c3800>, Sched<[WriteVALU128, ReadVALU128]>;
+def VNEG_D : LSX2R_VV<0x729c3c00>, Sched<[WriteVALU128, ReadVALU128]>;
+
+def VSADD_B : LSX3R_VVV<0x70460000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_H : LSX3R_VVV<0x70468000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_W : LSX3R_VVV<0x70470000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_D : LSX3R_VVV<0x70478000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_BU : LSX3R_VVV<0x704a0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_HU : LSX3R_VVV<0x704a8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_WU : LSX3R_VVV<0x704b0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSADD_DU : LSX3R_VVV<0x704b8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+
+def VSSUB_B : LSX3R_VVV<0x70480000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_H : LSX3R_VVV<0x70488000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_W : LSX3R_VVV<0x70490000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_D : LSX3R_VVV<0x70498000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_BU : LSX3R_VVV<0x704c0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_HU : LSX3R_VVV<0x704c8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_WU : LSX3R_VVV<0x704d0000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+def VSSUB_DU : LSX3R_VVV<0x704d8000>,
+ Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>;
+
+def VHADDW_H_B : LSX3R_VVV<0x70540000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHADDW_W_H : LSX3R_VVV<0x70548000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHADDW_D_W : LSX3R_VVV<0x70550000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHADDW_Q_D : LSX3R_VVV<0x70558000>,
+ Sched<[WriteVHADDWQ128, ReadVHADDWQ128, ReadVHADDWQ128]>;
+def VHADDW_HU_BU : LSX3R_VVV<0x70580000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHADDW_WU_HU : LSX3R_VVV<0x70588000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHADDW_DU_WU : LSX3R_VVV<0x70590000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHADDW_QU_DU : LSX3R_VVV<0x70598000>,
+ Sched<[WriteVHADDWQ128, ReadVHADDWQ128, ReadVHADDWQ128]>;
+
+def VHSUBW_H_B : LSX3R_VVV<0x70560000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHSUBW_W_H : LSX3R_VVV<0x70568000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHSUBW_D_W : LSX3R_VVV<0x70570000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHSUBW_Q_D : LSX3R_VVV<0x70578000>,
+ Sched<[WriteVHADDWQ128, ReadVHADDWQ128, ReadVHADDWQ128]>;
+def VHSUBW_HU_BU : LSX3R_VVV<0x705a0000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHSUBW_WU_HU : LSX3R_VVV<0x705a8000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHSUBW_DU_WU : LSX3R_VVV<0x705b0000>,
+ Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>;
+def VHSUBW_QU_DU : LSX3R_VVV<0x705b8000>,
+ Sched<[WriteVHADDWQ128, ReadVHADDWQ128, ReadVHADDWQ128]>;
+
+def VADDWEV_H_B : LSX3R_VVV<0x701e0000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_W_H : LSX3R_VVV<0x701e8000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_D_W : LSX3R_VVV<0x701f0000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_Q_D : LSX3R_VVV<0x701f8000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+def VADDWOD_H_B : LSX3R_VVV<0x70220000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_W_H : LSX3R_VVV<0x70228000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_D_W : LSX3R_VVV<0x70230000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_Q_D : LSX3R_VVV<0x70238000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+
+def VSUBWEV_H_B : LSX3R_VVV<0x70200000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWEV_W_H : LSX3R_VVV<0x70208000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWEV_D_W : LSX3R_VVV<0x70210000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWEV_Q_D : LSX3R_VVV<0x70218000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+def VSUBWOD_H_B : LSX3R_VVV<0x70240000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWOD_W_H : LSX3R_VVV<0x70248000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWOD_D_W : LSX3R_VVV<0x70250000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWOD_Q_D : LSX3R_VVV<0x70258000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+
+def VADDWEV_H_BU : LSX3R_VVV<0x702e0000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_W_HU : LSX3R_VVV<0x702e8000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_D_WU : LSX3R_VVV<0x702f0000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_Q_DU : LSX3R_VVV<0x702f8000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+def VADDWOD_H_BU : LSX3R_VVV<0x70320000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_W_HU : LSX3R_VVV<0x70328000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_D_WU : LSX3R_VVV<0x70330000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_Q_DU : LSX3R_VVV<0x70338000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+
+def VSUBWEV_H_BU : LSX3R_VVV<0x70300000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWEV_W_HU : LSX3R_VVV<0x70308000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWEV_D_WU : LSX3R_VVV<0x70310000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWEV_Q_DU : LSX3R_VVV<0x70318000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+def VSUBWOD_H_BU : LSX3R_VVV<0x70340000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWOD_W_HU : LSX3R_VVV<0x70348000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWOD_D_WU : LSX3R_VVV<0x70350000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VSUBWOD_Q_DU : LSX3R_VVV<0x70358000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+
+def VADDWEV_H_BU_B : LSX3R_VVV<0x703e0000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_W_HU_H : LSX3R_VVV<0x703e8000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_D_WU_W : LSX3R_VVV<0x703f0000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWEV_Q_DU_D : LSX3R_VVV<0x703f8000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+def VADDWOD_H_BU_B : LSX3R_VVV<0x70400000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_W_HU_H : LSX3R_VVV<0x70408000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_D_WU_W : LSX3R_VVV<0x70410000>,
+ Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>;
+def VADDWOD_Q_DU_D : LSX3R_VVV<0x70418000>,
+ Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>;
+
+def VAVG_B : LSX3R_VVV<0x70640000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVG_H : LSX3R_VVV<0x70648000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVG_W : LSX3R_VVV<0x70650000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVG_D : LSX3R_VVV<0x70658000>,
+ Sched<[WriteVAVGD128, ReadVAVGD128, ReadVAVGD128]>;
+def VAVG_BU : LSX3R_VVV<0x70660000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVG_HU : LSX3R_VVV<0x70668000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVG_WU : LSX3R_VVV<0x70670000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVG_DU : LSX3R_VVV<0x70678000>,
+ Sched<[WriteVAVGD128, ReadVAVGD128, ReadVAVGD128]>;
+def VAVGR_B : LSX3R_VVV<0x70680000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVGR_H : LSX3R_VVV<0x70688000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVGR_W : LSX3R_VVV<0x70690000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVGR_D : LSX3R_VVV<0x70698000>,
+ Sched<[WriteVAVGD128, ReadVAVGD128, ReadVAVGD128]>;
+def VAVGR_BU : LSX3R_VVV<0x706a0000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVGR_HU : LSX3R_VVV<0x706a8000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVGR_WU : LSX3R_VVV<0x706b0000>,
+ Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>;
+def VAVGR_DU : LSX3R_VVV<0x706b8000>,
+ Sched<[WriteVAVGD128, ReadVAVGD128, ReadVAVGD128]>;
+
+def VABSD_B : LSX3R_VVV<0x70600000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_H : LSX3R_VVV<0x70608000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_W : LSX3R_VVV<0x70610000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_D : LSX3R_VVV<0x70618000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_BU : LSX3R_VVV<0x70620000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_HU : LSX3R_VVV<0x70628000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_WU : LSX3R_VVV<0x70630000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+def VABSD_DU : LSX3R_VVV<0x70638000>,
+ Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>;
+
+def VADDA_B : LSX3R_VVV<0x705c0000>,
+ Sched<[WriteVADDA128, ReadVADDA128, ReadVADDA128]>;
+def VADDA_H : LSX3R_VVV<0x705c8000>,
+ Sched<[WriteVADDA128, ReadVADDA128, ReadVADDA128]>;
+def VADDA_W : LSX3R_VVV<0x705d0000>,
+ Sched<[WriteVADDA128, ReadVADDA128, ReadVADDA128]>;
+def VADDA_D : LSX3R_VVV<0x705d8000>,
+ Sched<[WriteVADDA128, ReadVADDA128, ReadVADDA128]>;
+
+def VMAX_B : LSX3R_VVV<0x70700000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMAX_H : LSX3R_VVV<0x70708000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMAX_W : LSX3R_VVV<0x70710000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMAX_D : LSX3R_VVV<0x70718000>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128, ReadVMINMAXD128]>;
+def VMAXI_B : LSX2RI5_VVI<0x72900000, simm5>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMAXI_H : LSX2RI5_VVI<0x72908000, simm5>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMAXI_W : LSX2RI5_VVI<0x72910000, simm5>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMAXI_D : LSX2RI5_VVI<0x72918000, simm5>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128]>;
+def VMAX_BU : LSX3R_VVV<0x70740000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMAX_HU : LSX3R_VVV<0x70748000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMAX_WU : LSX3R_VVV<0x70750000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMAX_DU : LSX3R_VVV<0x70758000>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128, ReadVMINMAXD128]>;
+def VMAXI_BU : LSX2RI5_VVI<0x72940000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMAXI_HU : LSX2RI5_VVI<0x72948000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMAXI_WU : LSX2RI5_VVI<0x72950000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMAXI_DU : LSX2RI5_VVI<0x72958000>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128]>;
+
+def VMIN_B : LSX3R_VVV<0x70720000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMIN_H : LSX3R_VVV<0x70728000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMIN_W : LSX3R_VVV<0x70730000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMIN_D : LSX3R_VVV<0x70738000>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128, ReadVMINMAXD128]>;
+def VMINI_B : LSX2RI5_VVI<0x72920000, simm5>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMINI_H : LSX2RI5_VVI<0x72928000, simm5>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMINI_W : LSX2RI5_VVI<0x72930000, simm5>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMINI_D : LSX2RI5_VVI<0x72938000, simm5>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128]>;
+def VMIN_BU : LSX3R_VVV<0x70760000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMIN_HU : LSX3R_VVV<0x70768000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMIN_WU : LSX3R_VVV<0x70770000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>;
+def VMIN_DU : LSX3R_VVV<0x70778000>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128, ReadVMINMAXD128]>;
+def VMINI_BU : LSX2RI5_VVI<0x72960000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMINI_HU : LSX2RI5_VVI<0x72968000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMINI_WU : LSX2RI5_VVI<0x72970000>,
+ Sched<[WriteVMINMAX128, ReadVMINMAX128]>;
+def VMINI_DU : LSX2RI5_VVI<0x72978000>,
+ Sched<[WriteVMINMAXD128, ReadVMINMAXD128]>;
+
+def VMUL_B : LSX3R_VVV<0x70840000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUL_H : LSX3R_VVV<0x70848000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUL_W : LSX3R_VVV<0x70850000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUL_D : LSX3R_VVV<0x70858000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+
+def VMUH_B : LSX3R_VVV<0x70860000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_H : LSX3R_VVV<0x70868000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_W : LSX3R_VVV<0x70870000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_D : LSX3R_VVV<0x70878000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_BU : LSX3R_VVV<0x70880000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_HU : LSX3R_VVV<0x70888000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_WU : LSX3R_VVV<0x70890000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMUH_DU : LSX3R_VVV<0x70898000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+
+def VMULWEV_H_B : LSX3R_VVV<0x70900000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_W_H : LSX3R_VVV<0x70908000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_D_W : LSX3R_VVV<0x70910000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_Q_D : LSX3R_VVV<0x70918000>,
+ Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>;
+def VMULWOD_H_B : LSX3R_VVV<0x70920000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_W_H : LSX3R_VVV<0x70928000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_D_W : LSX3R_VVV<0x70930000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_Q_D : LSX3R_VVV<0x70938000>,
+ Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>;
+def VMULWEV_H_BU : LSX3R_VVV<0x70980000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_W_HU : LSX3R_VVV<0x70988000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_D_WU : LSX3R_VVV<0x70990000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_Q_DU : LSX3R_VVV<0x70998000>,
+ Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>;
+def VMULWOD_H_BU : LSX3R_VVV<0x709a0000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_W_HU : LSX3R_VVV<0x709a8000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_D_WU : LSX3R_VVV<0x709b0000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_Q_DU : LSX3R_VVV<0x709b8000>,
+ Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>;
+def VMULWEV_H_BU_B : LSX3R_VVV<0x70a00000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_W_HU_H : LSX3R_VVV<0x70a08000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_D_WU_W : LSX3R_VVV<0x70a10000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWEV_Q_DU_D : LSX3R_VVV<0x70a18000>,
+ Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>;
+def VMULWOD_H_BU_B : LSX3R_VVV<0x70a20000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_W_HU_H : LSX3R_VVV<0x70a28000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_D_WU_W : LSX3R_VVV<0x70a30000>,
+ Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>;
+def VMULWOD_Q_DU_D : LSX3R_VVV<0x70a38000>,
+ Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>;
+
+def VMADD_B : LSX3R_VVVV<0x70a80000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADD_H : LSX3R_VVVV<0x70a88000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADD_W : LSX3R_VVVV<0x70a90000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADD_D : LSX3R_VVVV<0x70a98000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+
+def VMSUB_B : LSX3R_VVVV<0x70aa0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMSUB_H : LSX3R_VVVV<0x70aa8000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMSUB_W : LSX3R_VVVV<0x70ab0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMSUB_D : LSX3R_VVVV<0x70ab8000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+
+def VMADDWEV_H_B : LSX3R_VVVV<0x70ac0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_W_H : LSX3R_VVVV<0x70ac8000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_D_W : LSX3R_VVVV<0x70ad0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_Q_D : LSX3R_VVVV<0x70ad8000>,
+ Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>;
+def VMADDWOD_H_B : LSX3R_VVVV<0x70ae0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_W_H : LSX3R_VVVV<0x70ae8000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_D_W : LSX3R_VVVV<0x70af0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_Q_D : LSX3R_VVVV<0x70af8000>,
+ Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>;
+def VMADDWEV_H_BU : LSX3R_VVVV<0x70b40000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_W_HU : LSX3R_VVVV<0x70b48000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_D_WU : LSX3R_VVVV<0x70b50000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_Q_DU : LSX3R_VVVV<0x70b58000>,
+ Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>;
+def VMADDWOD_H_BU : LSX3R_VVVV<0x70b60000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_W_HU : LSX3R_VVVV<0x70b68000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_D_WU : LSX3R_VVVV<0x70b70000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_Q_DU : LSX3R_VVVV<0x70b78000>,
+ Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>;
+def VMADDWEV_H_BU_B : LSX3R_VVVV<0x70bc0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_W_HU_H : LSX3R_VVVV<0x70bc8000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_D_WU_W : LSX3R_VVVV<0x70bd0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWEV_Q_DU_D : LSX3R_VVVV<0x70bd8000>,
+ Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>;
+def VMADDWOD_H_BU_B : LSX3R_VVVV<0x70be0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_W_HU_H : LSX3R_VVVV<0x70be8000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_D_WU_W : LSX3R_VVVV<0x70bf0000>,
+ Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>;
+def VMADDWOD_Q_DU_D : LSX3R_VVVV<0x70bf8000>,
+ Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>;
+
+def VDIV_B : LSX3R_VVV<0x70e00000>,
+ Sched<[WriteVDIVB128, ReadVDIVB128, ReadVDIVB128]>;
+def VDIV_H : LSX3R_VVV<0x70e08000>,
+ Sched<[WriteVDIVH128, ReadVDIVH128, ReadVDIVH128]>;
+def VDIV_W : LSX3R_VVV<0x70e10000>,
+ Sched<[WriteVDIVW128, ReadVDIVW128, ReadVDIVW128]>;
+def VDIV_D : LSX3R_VVV<0x70e18000>,
+ Sched<[WriteVDIVD128, ReadVDIVD128, ReadVDIVD128]>;
+def VDIV_BU : LSX3R_VVV<0x70e40000>,
+ Sched<[WriteVDIVB128, ReadVDIVB128, ReadVDIVB128]>;
+def VDIV_HU : LSX3R_VVV<0x70e48000>,
+ Sched<[WriteVDIVH128, ReadVDIVH128, ReadVDIVH128]>;
+def VDIV_WU : LSX3R_VVV<0x70e50000>,
+ Sched<[WriteVDIVW128, ReadVDIVW128, ReadVDIVW128]>;
+def VDIV_DU : LSX3R_VVV<0x70e58000>,
+ Sched<[WriteVDIVD128, ReadVDIVD128, ReadVDIVD128]>;
+
+def VMOD_B : LSX3R_VVV<0x70e20000>,
+ Sched<[WriteVDIVB128, ReadVDIVB128, ReadVDIVB128]>;
+def VMOD_H : LSX3R_VVV<0x70e28000>,
+ Sched<[WriteVDIVH128, ReadVDIVH128, ReadVDIVH128]>;
+def VMOD_W : LSX3R_VVV<0x70e30000>,
+ Sched<[WriteVDIVW128, ReadVDIVW128, ReadVDIVW128]>;
+def VMOD_D : LSX3R_VVV<0x70e38000>,
+ Sched<[WriteVDIVD128, ReadVDIVD128, ReadVDIVD128]>;
+def VMOD_BU : LSX3R_VVV<0x70e60000>,
+ Sched<[WriteVDIVB128, ReadVDIVB128, ReadVDIVB128]>;
+def VMOD_HU : LSX3R_VVV<0x70e68000>,
+ Sched<[WriteVDIVH128, ReadVDIVH128, ReadVDIVH128]>;
+def VMOD_WU : LSX3R_VVV<0x70e70000>,
+ Sched<[WriteVDIVW128, ReadVDIVW128, ReadVDIVW128]>;
+def VMOD_DU : LSX3R_VVV<0x70e78000>,
+ Sched<[WriteVDIVD128, ReadVDIVD128, ReadVDIVD128]>;
+
+def VSAT_B : LSX2RI3_VVI<0x73242000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_H : LSX2RI4_VVI<0x73244000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_W : LSX2RI5_VVI<0x73248000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_D : LSX2RI6_VVI<0x73250000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_BU : LSX2RI3_VVI<0x73282000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_HU : LSX2RI4_VVI<0x73284000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_WU : LSX2RI5_VVI<0x73288000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+def VSAT_DU : LSX2RI6_VVI<0x73290000>, Sched<[WriteVSAT128, ReadVSAT128]>;
+
+def VEXTH_H_B : LSX2R_VV<0x729ee000>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_W_H : LSX2R_VV<0x729ee400>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_D_W : LSX2R_VV<0x729ee800>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_Q_D : LSX2R_VV<0x729eec00>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_HU_BU : LSX2R_VV<0x729ef000>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_WU_HU : LSX2R_VV<0x729ef400>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_DU_WU : LSX2R_VV<0x729ef800>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+def VEXTH_QU_DU : LSX2R_VV<0x729efc00>, Sched<[WriteVEXTH128, ReadVEXTH128]>;
+
+def VSIGNCOV_B : LSX3R_VVV<0x712e0000>,
+ Sched<[WriteVSIGNCOV128, ReadVSIGNCOV128, ReadVSIGNCOV128]>;
+def VSIGNCOV_H : LSX3R_VVV<0x712e8000>,
+ Sched<[WriteVSIGNCOV128, ReadVSIGNCOV128, ReadVSIGNCOV128]>;
+def VSIGNCOV_W : LSX3R_VVV<0x712f0000>,
+ Sched<[WriteVSIGNCOV128, ReadVSIGNCOV128, ReadVSIGNCOV128]>;
+def VSIGNCOV_D : LSX3R_VVV<0x712f8000>,
+ Sched<[WriteVSIGNCOV128, ReadVSIGNCOV128, ReadVSIGNCOV128]>;
+
+def VMSKLTZ_B : LSX2R_VV<0x729c4000>, Sched<[WriteVMSK128, ReadVMSK128]>;
+def VMSKLTZ_H : LSX2R_VV<0x729c4400>, Sched<[WriteVMSK128, ReadVMSK128]>;
+def VMSKLTZ_W : LSX2R_VV<0x729c4800>, Sched<[WriteVMSK128, ReadVMSK128]>;
+def VMSKLTZ_D : LSX2R_VV<0x729c4c00>, Sched<[WriteVMSK128, ReadVMSK128]>;
+
+def VMSKGEZ_B : LSX2R_VV<0x729c5000>, Sched<[WriteVMSK128, ReadVMSK128]>;
+
+def VMSKNZ_B : LSX2R_VV<0x729c6000>, Sched<[WriteVMSK128, ReadVMSK128]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
-def VLDI : LSX1RI13_VI<0x73e00000>;
+def VLDI : LSX1RI13_VI<0x73e00000>, Sched<[WriteVLDI128]>;
}
-def VAND_V : LSX3R_VVV<0x71260000>;
-def VOR_V : LSX3R_VVV<0x71268000>;
-def VXOR_V : LSX3R_VVV<0x71270000>;
-def VNOR_V : LSX3R_VVV<0x71278000>;
-def VANDN_V : LSX3R_VVV<0x71280000>;
-def VORN_V : LSX3R_VVV<0x71288000>;
-
-def VANDI_B : LSX2RI8_VVI<0x73d00000>;
-def VORI_B : LSX2RI8_VVI<0x73d40000>;
-def VXORI_B : LSX2RI8_VVI<0x73d80000>;
-def VNORI_B : LSX2RI8_VVI<0x73dc0000>;
-
-def VSLL_B : LSX3R_VVV<0x70e80000>;
-def VSLL_H : LSX3R_VVV<0x70e88000>;
-def VSLL_W : LSX3R_VVV<0x70e90000>;
-def VSLL_D : LSX3R_VVV<0x70e98000>;
-def VSLLI_B : LSX2RI3_VVI<0x732c2000>;
-def VSLLI_H : LSX2RI4_VVI<0x732c4000>;
-def VSLLI_W : LSX2RI5_VVI<0x732c8000>;
-def VSLLI_D : LSX2RI6_VVI<0x732d0000>;
-
-def VSRL_B : LSX3R_VVV<0x70ea0000>;
-def VSRL_H : LSX3R_VVV<0x70ea8000>;
-def VSRL_W : LSX3R_VVV<0x70eb0000>;
-def VSRL_D : LSX3R_VVV<0x70eb8000>;
-def VSRLI_B : LSX2RI3_VVI<0x73302000>;
-def VSRLI_H : LSX2RI4_VVI<0x73304000>;
-def VSRLI_W : LSX2RI5_VVI<0x73308000>;
-def VSRLI_D : LSX2RI6_VVI<0x73310000>;
-
-def VSRA_B : LSX3R_VVV<0x70ec0000>;
-def VSRA_H : LSX3R_VVV<0x70ec8000>;
-def VSRA_W : LSX3R_VVV<0x70ed0000>;
-def VSRA_D : LSX3R_VVV<0x70ed8000>;
-def VSRAI_B : LSX2RI3_VVI<0x73342000>;
-def VSRAI_H : LSX2RI4_VVI<0x73344000>;
-def VSRAI_W : LSX2RI5_VVI<0x73348000>;
-def VSRAI_D : LSX2RI6_VVI<0x73350000>;
-
-def VROTR_B : LSX3R_VVV<0x70ee0000>;
-def VROTR_H : LSX3R_VVV<0x70ee8000>;
-def VROTR_W : LSX3R_VVV<0x70ef0000>;
-def VROTR_D : LSX3R_VVV<0x70ef8000>;
-def VROTRI_B : LSX2RI3_VVI<0x72a02000>;
-def VROTRI_H : LSX2RI4_VVI<0x72a04000>;
-def VROTRI_W : LSX2RI5_VVI<0x72a08000>;
-def VROTRI_D : LSX2RI6_VVI<0x72a10000>;
-
-def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>;
-def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>;
-def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>;
-def VEXTL_Q_D : LSX2R_VV<0x73090000>;
-def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>;
-def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>;
-def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>;
-def VEXTL_QU_DU : LSX2R_VV<0x730d0000>;
-
-def VSRLR_B : LSX3R_VVV<0x70f00000>;
-def VSRLR_H : LSX3R_VVV<0x70f08000>;
-def VSRLR_W : LSX3R_VVV<0x70f10000>;
-def VSRLR_D : LSX3R_VVV<0x70f18000>;
-def VSRLRI_B : LSX2RI3_VVI<0x72a42000>;
-def VSRLRI_H : LSX2RI4_VVI<0x72a44000>;
-def VSRLRI_W : LSX2RI5_VVI<0x72a48000>;
-def VSRLRI_D : LSX2RI6_VVI<0x72a50000>;
-
-def VSRAR_B : LSX3R_VVV<0x70f20000>;
-def VSRAR_H : LSX3R_VVV<0x70f28000>;
-def VSRAR_W : LSX3R_VVV<0x70f30000>;
-def VSRAR_D : LSX3R_VVV<0x70f38000>;
-def VSRARI_B : LSX2RI3_VVI<0x72a82000>;
-def VSRARI_H : LSX2RI4_VVI<0x72a84000>;
-def VSRARI_W : LSX2RI5_VVI<0x72a88000>;
-def VSRARI_D : LSX2RI6_VVI<0x72a90000>;
-
-def VSRLN_B_H : LSX3R_VVV<0x70f48000>;
-def VSRLN_H_W : LSX3R_VVV<0x70f50000>;
-def VSRLN_W_D : LSX3R_VVV<0x70f58000>;
-def VSRAN_B_H : LSX3R_VVV<0x70f68000>;
-def VSRAN_H_W : LSX3R_VVV<0x70f70000>;
-def VSRAN_W_D : LSX3R_VVV<0x70f78000>;
-
-def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>;
-def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>;
-def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>;
-def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>;
-def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>;
-def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>;
-def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>;
-def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>;
-
-def VSRLRN_B_H : LSX3R_VVV<0x70f88000>;
-def VSRLRN_H_W : LSX3R_VVV<0x70f90000>;
-def VSRLRN_W_D : LSX3R_VVV<0x70f98000>;
-def VSRARN_B_H : LSX3R_VVV<0x70fa8000>;
-def VSRARN_H_W : LSX3R_VVV<0x70fb0000>;
-def VSRARN_W_D : LSX3R_VVV<0x70fb8000>;
-
-def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>;
-def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>;
-def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>;
-def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>;
-def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>;
-def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>;
-def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>;
-def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>;
-
-def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>;
-def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>;
-def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>;
-def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>;
-def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>;
-def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>;
-def VSSRLN_BU_H : LSX3R_VVV<0x71048000>;
-def VSSRLN_HU_W : LSX3R_VVV<0x71050000>;
-def VSSRLN_WU_D : LSX3R_VVV<0x71058000>;
-def VSSRAN_BU_H : LSX3R_VVV<0x71068000>;
-def VSSRAN_HU_W : LSX3R_VVV<0x71070000>;
-def VSSRAN_WU_D : LSX3R_VVV<0x71078000>;
-
-def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>;
-def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>;
-def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>;
-def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>;
-def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>;
-def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>;
-def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>;
-def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>;
-def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>;
-def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>;
-def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>;
-def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>;
-def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>;
-def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>;
-def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>;
-def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>;
-
-def VSSRLRN_B_H : LSX3R_VVV<0x71008000>;
-def VSSRLRN_H_W : LSX3R_VVV<0x71010000>;
-def VSSRLRN_W_D : LSX3R_VVV<0x71018000>;
-def VSSRARN_B_H : LSX3R_VVV<0x71028000>;
-def VSSRARN_H_W : LSX3R_VVV<0x71030000>;
-def VSSRARN_W_D : LSX3R_VVV<0x71038000>;
-def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>;
-def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>;
-def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>;
-def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>;
-def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>;
-def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>;
-
-def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>;
-def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>;
-def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>;
-def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>;
-def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>;
-def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>;
-def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>;
-def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>;
-def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>;
-def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>;
-def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>;
-def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>;
-def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>;
-def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>;
-def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>;
-def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>;
-
-def VCLO_B : LSX2R_VV<0x729c0000>;
-def VCLO_H : LSX2R_VV<0x729c0400>;
-def VCLO_W : LSX2R_VV<0x729c0800>;
-def VCLO_D : LSX2R_VV<0x729c0c00>;
-def VCLZ_B : LSX2R_VV<0x729c1000>;
-def VCLZ_H : LSX2R_VV<0x729c1400>;
-def VCLZ_W : LSX2R_VV<0x729c1800>;
-def VCLZ_D : LSX2R_VV<0x729c1c00>;
-
-def VPCNT_B : LSX2R_VV<0x729c2000>;
-def VPCNT_H : LSX2R_VV<0x729c2400>;
-def VPCNT_W : LSX2R_VV<0x729c2800>;
-def VPCNT_D : LSX2R_VV<0x729c2c00>;
-
-def VBITCLR_B : LSX3R_VVV<0x710c0000>;
-def VBITCLR_H : LSX3R_VVV<0x710c8000>;
-def VBITCLR_W : LSX3R_VVV<0x710d0000>;
-def VBITCLR_D : LSX3R_VVV<0x710d8000>;
-def VBITCLRI_B : LSX2RI3_VVI<0x73102000>;
-def VBITCLRI_H : LSX2RI4_VVI<0x73104000>;
-def VBITCLRI_W : LSX2RI5_VVI<0x73108000>;
-def VBITCLRI_D : LSX2RI6_VVI<0x73110000>;
-
-def VBITSET_B : LSX3R_VVV<0x710e0000>;
-def VBITSET_H : LSX3R_VVV<0x710e8000>;
-def VBITSET_W : LSX3R_VVV<0x710f0000>;
-def VBITSET_D : LSX3R_VVV<0x710f8000>;
-def VBITSETI_B : LSX2RI3_VVI<0x73142000>;
-def VBITSETI_H : LSX2RI4_VVI<0x73144000>;
-def VBITSETI_W : LSX2RI5_VVI<0x73148000>;
-def VBITSETI_D : LSX2RI6_VVI<0x73150000>;
-
-def VBITREV_B : LSX3R_VVV<0x71100000>;
-def VBITREV_H : LSX3R_VVV<0x71108000>;
-def VBITREV_W : LSX3R_VVV<0x71110000>;
-def VBITREV_D : LSX3R_VVV<0x71118000>;
-def VBITREVI_B : LSX2RI3_VVI<0x73182000>;
-def VBITREVI_H : LSX2RI4_VVI<0x73184000>;
-def VBITREVI_W : LSX2RI5_VVI<0x73188000>;
-def VBITREVI_D : LSX2RI6_VVI<0x73190000>;
-
-def VFRSTP_B : LSX3R_VVVV<0x712b0000>;
-def VFRSTP_H : LSX3R_VVVV<0x712b8000>;
-def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>;
-def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>;
-
-def VFADD_S : LSX3R_VVV<0x71308000>;
-def VFADD_D : LSX3R_VVV<0x71310000>;
-def VFSUB_S : LSX3R_VVV<0x71328000>;
-def VFSUB_D : LSX3R_VVV<0x71330000>;
-def VFMUL_S : LSX3R_VVV<0x71388000>;
-def VFMUL_D : LSX3R_VVV<0x71390000>;
-def VFDIV_S : LSX3R_VVV<0x713a8000>;
-def VFDIV_D : LSX3R_VVV<0x713b0000>;
-
-def VFMADD_S : LSX4R_VVVV<0x09100000>;
-def VFMADD_D : LSX4R_VVVV<0x09200000>;
-def VFMSUB_S : LSX4R_VVVV<0x09500000>;
-def VFMSUB_D : LSX4R_VVVV<0x09600000>;
-def VFNMADD_S : LSX4R_VVVV<0x09900000>;
-def VFNMADD_D : LSX4R_VVVV<0x09a00000>;
-def VFNMSUB_S : LSX4R_VVVV<0x09d00000>;
-def VFNMSUB_D : LSX4R_VVVV<0x09e00000>;
-
-def VFMAX_S : LSX3R_VVV<0x713c8000>;
-def VFMAX_D : LSX3R_VVV<0x713d0000>;
-def VFMIN_S : LSX3R_VVV<0x713e8000>;
-def VFMIN_D : LSX3R_VVV<0x713f0000>;
-
-def VFMAXA_S : LSX3R_VVV<0x71408000>;
-def VFMAXA_D : LSX3R_VVV<0x71410000>;
-def VFMINA_S : LSX3R_VVV<0x71428000>;
-def VFMINA_D : LSX3R_VVV<0x71430000>;
-
-def VFLOGB_S : LSX2R_VV<0x729cc400>;
-def VFLOGB_D : LSX2R_VV<0x729cc800>;
-
-def VFCLASS_S : LSX2R_VV<0x729cd400>;
-def VFCLASS_D : LSX2R_VV<0x729cd800>;
-
-def VFSQRT_S : LSX2R_VV<0x729ce400>;
-def VFSQRT_D : LSX2R_VV<0x729ce800>;
-def VFRECIP_S : LSX2R_VV<0x729cf400>;
-def VFRECIP_D : LSX2R_VV<0x729cf800>;
-def VFRSQRT_S : LSX2R_VV<0x729d0400>;
-def VFRSQRT_D : LSX2R_VV<0x729d0800>;
-def VFRECIPE_S : LSX2R_VV<0x729d1400>;
-def VFRECIPE_D : LSX2R_VV<0x729d1800>;
-def VFRSQRTE_S : LSX2R_VV<0x729d2400>;
-def VFRSQRTE_D : LSX2R_VV<0x729d2800>;
-
-def VFCVTL_S_H : LSX2R_VV<0x729de800>;
-def VFCVTH_S_H : LSX2R_VV<0x729dec00>;
-def VFCVTL_D_S : LSX2R_VV<0x729df000>;
-def VFCVTH_D_S : LSX2R_VV<0x729df400>;
-def VFCVT_H_S : LSX3R_VVV<0x71460000>;
-def VFCVT_S_D : LSX3R_VVV<0x71468000>;
-
-def VFRINTRNE_S : LSX2R_VV<0x729d7400>;
-def VFRINTRNE_D : LSX2R_VV<0x729d7800>;
-def VFRINTRZ_S : LSX2R_VV<0x729d6400>;
-def VFRINTRZ_D : LSX2R_VV<0x729d6800>;
-def VFRINTRP_S : LSX2R_VV<0x729d5400>;
-def VFRINTRP_D : LSX2R_VV<0x729d5800>;
-def VFRINTRM_S : LSX2R_VV<0x729d4400>;
-def VFRINTRM_D : LSX2R_VV<0x729d4800>;
-def VFRINT_S : LSX2R_VV<0x729d3400>;
-def VFRINT_D : LSX2R_VV<0x729d3800>;
-
-def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>;
-def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>;
-def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>;
-def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>;
-def VFTINTRP_W_S : LSX2R_VV<0x729e4000>;
-def VFTINTRP_L_D : LSX2R_VV<0x729e4400>;
-def VFTINTRM_W_S : LSX2R_VV<0x729e3800>;
-def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>;
-def VFTINT_W_S : LSX2R_VV<0x729e3000>;
-def VFTINT_L_D : LSX2R_VV<0x729e3400>;
-def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>;
-def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>;
-def VFTINT_WU_S : LSX2R_VV<0x729e5800>;
-def VFTINT_LU_D : LSX2R_VV<0x729e5c00>;
-
-def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>;
-def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>;
-def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>;
-def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>;
-def VFTINT_W_D : LSX3R_VVV<0x71498000>;
-
-def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>;
-def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>;
-def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>;
-def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>;
-def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>;
-def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>;
-def VFTINTRML_L_S : LSX2R_VV<0x729e8800>;
-def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>;
-def VFTINTL_L_S : LSX2R_VV<0x729e8000>;
-def VFTINTH_L_S : LSX2R_VV<0x729e8400>;
-
-def VFFINT_S_W : LSX2R_VV<0x729e0000>;
-def VFFINT_D_L : LSX2R_VV<0x729e0800>;
-def VFFINT_S_WU : LSX2R_VV<0x729e0400>;
-def VFFINT_D_LU : LSX2R_VV<0x729e0c00>;
-def VFFINTL_D_W : LSX2R_VV<0x729e1000>;
-def VFFINTH_D_W : LSX2R_VV<0x729e1400>;
-def VFFINT_S_L : LSX3R_VVV<0x71480000>;
-
-def VSEQ_B : LSX3R_VVV<0x70000000>;
-def VSEQ_H : LSX3R_VVV<0x70008000>;
-def VSEQ_W : LSX3R_VVV<0x70010000>;
-def VSEQ_D : LSX3R_VVV<0x70018000>;
-def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>;
-def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>;
-def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>;
-def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>;
-
-def VSLE_B : LSX3R_VVV<0x70020000>;
-def VSLE_H : LSX3R_VVV<0x70028000>;
-def VSLE_W : LSX3R_VVV<0x70030000>;
-def VSLE_D : LSX3R_VVV<0x70038000>;
-def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>;
-def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>;
-def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>;
-def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>;
-
-def VSLE_BU : LSX3R_VVV<0x70040000>;
-def VSLE_HU : LSX3R_VVV<0x70048000>;
-def VSLE_WU : LSX3R_VVV<0x70050000>;
-def VSLE_DU : LSX3R_VVV<0x70058000>;
-def VSLEI_BU : LSX2RI5_VVI<0x72840000>;
-def VSLEI_HU : LSX2RI5_VVI<0x72848000>;
-def VSLEI_WU : LSX2RI5_VVI<0x72850000>;
-def VSLEI_DU : LSX2RI5_VVI<0x72858000>;
-
-def VSLT_B : LSX3R_VVV<0x70060000>;
-def VSLT_H : LSX3R_VVV<0x70068000>;
-def VSLT_W : LSX3R_VVV<0x70070000>;
-def VSLT_D : LSX3R_VVV<0x70078000>;
-def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>;
-def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>;
-def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>;
-def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>;
-
-def VSLT_BU : LSX3R_VVV<0x70080000>;
-def VSLT_HU : LSX3R_VVV<0x70088000>;
-def VSLT_WU : LSX3R_VVV<0x70090000>;
-def VSLT_DU : LSX3R_VVV<0x70098000>;
-def VSLTI_BU : LSX2RI5_VVI<0x72880000>;
-def VSLTI_HU : LSX2RI5_VVI<0x72888000>;
-def VSLTI_WU : LSX2RI5_VVI<0x72890000>;
-def VSLTI_DU : LSX2RI5_VVI<0x72898000>;
-
-def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>;
-def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>;
-def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>;
-def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>;
-def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>;
-def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>;
-def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>;
-def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>;
-def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>;
-def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>;
-def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>;
-def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>;
-def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>;
-def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>;
-def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>;
-def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>;
-def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>;
-def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>;
-def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>;
-def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>;
-def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>;
-def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>;
-
-def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>;
-def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>;
-def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>;
-def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>;
-def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>;
-def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>;
-def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>;
-def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>;
-def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>;
-def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>;
-def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>;
-def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>;
-def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>;
-def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>;
-def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>;
-def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>;
-def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>;
-def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>;
-def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>;
-def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>;
-def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>;
-def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>;
-
-def VBITSEL_V : LSX4R_VVVV<0x0d100000>;
-
-def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>;
-
-def VSETEQZ_V : LSX2R_CV<0x729c9800>;
-def VSETNEZ_V : LSX2R_CV<0x729c9c00>;
-def VSETANYEQZ_B : LSX2R_CV<0x729ca000>;
-def VSETANYEQZ_H : LSX2R_CV<0x729ca400>;
-def VSETANYEQZ_W : LSX2R_CV<0x729ca800>;
-def VSETANYEQZ_D : LSX2R_CV<0x729cac00>;
-def VSETALLNEZ_B : LSX2R_CV<0x729cb000>;
-def VSETALLNEZ_H : LSX2R_CV<0x729cb400>;
-def VSETALLNEZ_W : LSX2R_CV<0x729cb800>;
-def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>;
-
-def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>;
-def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>;
-def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>;
-def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>;
-def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>;
-def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>;
-def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>;
-def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>;
-def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>;
-def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>;
-def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>;
-def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>;
+def VAND_V : LSX3R_VVV<0x71260000>,
+ Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>;
+def VOR_V : LSX3R_VVV<0x71268000>,
+ Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>;
+def VXOR_V : LSX3R_VVV<0x71270000>,
+ Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>;
+def VNOR_V : LSX3R_VVV<0x71278000>,
+ Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>;
+def VANDN_V : LSX3R_VVV<0x71280000>,
+ Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>;
+def VORN_V : LSX3R_VVV<0x71288000>,
+ Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>;
+
+def VANDI_B : LSX2RI8_VVI<0x73d00000>, Sched<[WriteVBIT128, ReadVBIT128]>;
+def VORI_B : LSX2RI8_VVI<0x73d40000>, Sched<[WriteVBIT128, ReadVBIT128]>;
+def VXORI_B : LSX2RI8_VVI<0x73d80000>, Sched<[WriteVBIT128, ReadVBIT128]>;
+def VNORI_B : LSX2RI8_VVI<0x73dc0000>, Sched<[WriteVBIT128, ReadVBIT128]>;
+
+def VSLL_B : LSX3R_VVV<0x70e80000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSLL_H : LSX3R_VVV<0x70e88000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSLL_W : LSX3R_VVV<0x70e90000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSLL_D : LSX3R_VVV<0x70e98000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSLLI_B : LSX2RI3_VVI<0x732c2000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSLLI_H : LSX2RI4_VVI<0x732c4000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSLLI_W : LSX2RI5_VVI<0x732c8000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSLLI_D : LSX2RI6_VVI<0x732d0000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+
+def VSRL_B : LSX3R_VVV<0x70ea0000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRL_H : LSX3R_VVV<0x70ea8000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRL_W : LSX3R_VVV<0x70eb0000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRL_D : LSX3R_VVV<0x70eb8000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRLI_B : LSX2RI3_VVI<0x73302000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSRLI_H : LSX2RI4_VVI<0x73304000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSRLI_W : LSX2RI5_VVI<0x73308000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSRLI_D : LSX2RI6_VVI<0x73310000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+
+def VSRA_B : LSX3R_VVV<0x70ec0000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRA_H : LSX3R_VVV<0x70ec8000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRA_W : LSX3R_VVV<0x70ed0000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRA_D : LSX3R_VVV<0x70ed8000>,
+ Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>;
+def VSRAI_B : LSX2RI3_VVI<0x73342000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSRAI_H : LSX2RI4_VVI<0x73344000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSRAI_W : LSX2RI5_VVI<0x73348000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VSRAI_D : LSX2RI6_VVI<0x73350000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+
+def VROTR_B : LSX3R_VVV<0x70ee0000>,
+ Sched<[WriteVROTR128, ReadVROTR128, ReadVROTR128]>;
+def VROTR_H : LSX3R_VVV<0x70ee8000>,
+ Sched<[WriteVROTR128, ReadVROTR128, ReadVROTR128]>;
+def VROTR_W : LSX3R_VVV<0x70ef0000>,
+ Sched<[WriteVROTR128, ReadVROTR128, ReadVROTR128]>;
+def VROTR_D : LSX3R_VVV<0x70ef8000>,
+ Sched<[WriteVROTR128, ReadVROTR128, ReadVROTR128]>;
+def VROTRI_B : LSX2RI3_VVI<0x72a02000>, Sched<[WriteVROTR128, ReadVROTR128]>;
+def VROTRI_H : LSX2RI4_VVI<0x72a04000>, Sched<[WriteVROTR128, ReadVROTR128]>;
+def VROTRI_W : LSX2RI5_VVI<0x72a08000>, Sched<[WriteVROTR128, ReadVROTR128]>;
+def VROTRI_D : LSX2RI6_VVI<0x72a10000>, Sched<[WriteVROTR128, ReadVROTR128]>;
+
+def VSLLWIL_H_B : LSX2RI3_VVI<0x73082000>,
+ Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>;
+def VSLLWIL_W_H : LSX2RI4_VVI<0x73084000>,
+ Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>;
+def VSLLWIL_D_W : LSX2RI5_VVI<0x73088000>,
+ Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>;
+def VEXTL_Q_D : LSX2R_VV<0x73090000>, Sched<[WriteVEXTL128, ReadVEXTL128]>;
+def VSLLWIL_HU_BU : LSX2RI3_VVI<0x730c2000>,
+ Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>;
+def VSLLWIL_WU_HU : LSX2RI4_VVI<0x730c4000>,
+ Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>;
+def VSLLWIL_DU_WU : LSX2RI5_VVI<0x730c8000>,
+ Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>;
+def VEXTL_QU_DU : LSX2R_VV<0x730d0000>, Sched<[WriteVEXTL128, ReadVEXTL128]>;
+
+def VSRLR_B : LSX3R_VVV<0x70f00000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLR_H : LSX3R_VVV<0x70f08000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLR_W : LSX3R_VVV<0x70f10000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLR_D : LSX3R_VVV<0x70f18000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLRI_B : LSX2RI3_VVI<0x72a42000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLRI_H : LSX2RI4_VVI<0x72a44000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLRI_W : LSX2RI5_VVI<0x72a48000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+def VSRLRI_D : LSX2RI6_VVI<0x72a50000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+
+def VSRAR_B : LSX3R_VVV<0x70f20000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRAR_H : LSX3R_VVV<0x70f28000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRAR_W : LSX3R_VVV<0x70f30000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRAR_D : LSX3R_VVV<0x70f38000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>;
+def VSRARI_B : LSX2RI3_VVI<0x72a82000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+def VSRARI_H : LSX2RI4_VVI<0x72a84000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+def VSRARI_W : LSX2RI5_VVI<0x72a88000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+def VSRARI_D : LSX2RI6_VVI<0x72a90000>,
+ Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>;
+
+def VSRLN_B_H : LSX3R_VVV<0x70f48000>,
+ Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>;
+def VSRLN_H_W : LSX3R_VVV<0x70f50000>,
+ Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>;
+def VSRLN_W_D : LSX3R_VVV<0x70f58000>,
+ Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>;
+def VSRAN_B_H : LSX3R_VVV<0x70f68000>,
+ Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>;
+def VSRAN_H_W : LSX3R_VVV<0x70f70000>,
+ Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>;
+def VSRAN_W_D : LSX3R_VVV<0x70f78000>,
+ Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>;
+
+def VSRLNI_B_H : LSX2RI4_VVVI<0x73404000>,
+ Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>;
+def VSRLNI_H_W : LSX2RI5_VVVI<0x73408000>,
+ Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>;
+def VSRLNI_W_D : LSX2RI6_VVVI<0x73410000>,
+ Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>;
+def VSRLNI_D_Q : LSX2RI7_VVVI<0x73420000>,
+ Sched<[WriteVSHIFTNIQ128, ReadVSHIFTNIQ128, ReadVSHIFTNIQ128]>;
+def VSRANI_B_H : LSX2RI4_VVVI<0x73584000>,
+ Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>;
+def VSRANI_H_W : LSX2RI5_VVVI<0x73588000>,
+ Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>;
+def VSRANI_W_D : LSX2RI6_VVVI<0x73590000>,
+ Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>;
+def VSRANI_D_Q : LSX2RI7_VVVI<0x735a0000>,
+ Sched<[WriteVSHIFTNIQ128, ReadVSHIFTNIQ128, ReadVSHIFTNIQ128]>;
+
+def VSRLRN_B_H : LSX3R_VVV<0x70f88000>,
+ Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>;
+def VSRLRN_H_W : LSX3R_VVV<0x70f90000>,
+ Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>;
+def VSRLRN_W_D : LSX3R_VVV<0x70f98000>,
+ Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>;
+def VSRARN_B_H : LSX3R_VVV<0x70fa8000>,
+ Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>;
+def VSRARN_H_W : LSX3R_VVV<0x70fb0000>,
+ Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>;
+def VSRARN_W_D : LSX3R_VVV<0x70fb8000>,
+ Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>;
+
+def VSRLRNI_B_H : LSX2RI4_VVVI<0x73444000>,
+ Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>;
+def VSRLRNI_H_W : LSX2RI5_VVVI<0x73448000>,
+ Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>;
+def VSRLRNI_W_D : LSX2RI6_VVVI<0x73450000>,
+ Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>;
+def VSRLRNI_D_Q : LSX2RI7_VVVI<0x73460000>,
+ Sched<[WriteVSHIFTRNIQ128, ReadVSHIFTRNIQ128, ReadVSHIFTRNIQ128]>;
+def VSRARNI_B_H : LSX2RI4_VVVI<0x735c4000>,
+ Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>;
+def VSRARNI_H_W : LSX2RI5_VVVI<0x735c8000>,
+ Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>;
+def VSRARNI_W_D : LSX2RI6_VVVI<0x735d0000>,
+ Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>;
+def VSRARNI_D_Q : LSX2RI7_VVVI<0x735e0000>,
+ Sched<[WriteVSHIFTRNIQ128, ReadVSHIFTRNIQ128, ReadVSHIFTRNIQ128]>;
+
+def VSSRLN_B_H : LSX3R_VVV<0x70fc8000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRLN_H_W : LSX3R_VVV<0x70fd0000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRLN_W_D : LSX3R_VVV<0x70fd8000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRAN_B_H : LSX3R_VVV<0x70fe8000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRAN_H_W : LSX3R_VVV<0x70ff0000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRAN_W_D : LSX3R_VVV<0x70ff8000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRLN_BU_H : LSX3R_VVV<0x71048000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRLN_HU_W : LSX3R_VVV<0x71050000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRLN_WU_D : LSX3R_VVV<0x71058000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRAN_BU_H : LSX3R_VVV<0x71068000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRAN_HU_W : LSX3R_VVV<0x71070000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+def VSSRAN_WU_D : LSX3R_VVV<0x71078000>,
+ Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>;
+
+def VSSRLNI_B_H : LSX2RI4_VVVI<0x73484000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRLNI_H_W : LSX2RI5_VVVI<0x73488000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRLNI_W_D : LSX2RI6_VVVI<0x73490000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRLNI_D_Q : LSX2RI7_VVVI<0x734a0000>,
+ Sched<[WriteVSHIFTNSIQ128, ReadVSHIFTNSIQ128, ReadVSHIFTNSIQ128]>;
+def VSSRANI_B_H : LSX2RI4_VVVI<0x73604000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRANI_H_W : LSX2RI5_VVVI<0x73608000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRANI_W_D : LSX2RI6_VVVI<0x73610000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRANI_D_Q : LSX2RI7_VVVI<0x73620000>,
+ Sched<[WriteVSHIFTNSIQ128, ReadVSHIFTNSIQ128, ReadVSHIFTNSIQ128]>;
+def VSSRLNI_BU_H : LSX2RI4_VVVI<0x734c4000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRLNI_HU_W : LSX2RI5_VVVI<0x734c8000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRLNI_WU_D : LSX2RI6_VVVI<0x734d0000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRLNI_DU_Q : LSX2RI7_VVVI<0x734e0000>,
+ Sched<[WriteVSHIFTNSIQ128, ReadVSHIFTNSIQ128, ReadVSHIFTNSIQ128]>;
+def VSSRANI_BU_H : LSX2RI4_VVVI<0x73644000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRANI_HU_W : LSX2RI5_VVVI<0x73648000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRANI_WU_D : LSX2RI6_VVVI<0x73650000>,
+ Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>;
+def VSSRANI_DU_Q : LSX2RI7_VVVI<0x73660000>,
+ Sched<[WriteVSHIFTNSIQ128, ReadVSHIFTNSIQ128, ReadVSHIFTNSIQ128]>;
+
+def VSSRLRN_B_H : LSX3R_VVV<0x71008000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRLRN_H_W : LSX3R_VVV<0x71010000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRLRN_W_D : LSX3R_VVV<0x71018000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRARN_B_H : LSX3R_VVV<0x71028000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRARN_H_W : LSX3R_VVV<0x71030000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRARN_W_D : LSX3R_VVV<0x71038000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRLRN_BU_H : LSX3R_VVV<0x71088000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRLRN_HU_W : LSX3R_VVV<0x71090000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRLRN_WU_D : LSX3R_VVV<0x71098000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRARN_BU_H : LSX3R_VVV<0x710a8000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRARN_HU_W : LSX3R_VVV<0x710b0000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+def VSSRARN_WU_D : LSX3R_VVV<0x710b8000>,
+ Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>;
+
+def VSSRLRNI_B_H : LSX2RI4_VVVI<0x73504000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRLRNI_H_W : LSX2RI5_VVVI<0x73508000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRLRNI_W_D : LSX2RI6_VVVI<0x73510000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRLRNI_D_Q : LSX2RI7_VVVI<0x73520000>,
+ Sched<[WriteVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128]>;
+def VSSRARNI_B_H : LSX2RI4_VVVI<0x73684000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRARNI_H_W : LSX2RI5_VVVI<0x73688000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRARNI_W_D : LSX2RI6_VVVI<0x73690000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRARNI_D_Q : LSX2RI7_VVVI<0x736a0000>,
+ Sched<[WriteVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128]>;
+def VSSRLRNI_BU_H : LSX2RI4_VVVI<0x73544000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRLRNI_HU_W : LSX2RI5_VVVI<0x73548000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRLRNI_WU_D : LSX2RI6_VVVI<0x73550000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRLRNI_DU_Q : LSX2RI7_VVVI<0x73560000>,
+ Sched<[WriteVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128]>;
+def VSSRARNI_BU_H : LSX2RI4_VVVI<0x736c4000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRARNI_HU_W : LSX2RI5_VVVI<0x736c8000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRARNI_WU_D : LSX2RI6_VVVI<0x736d0000>,
+ Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>;
+def VSSRARNI_DU_Q : LSX2RI7_VVVI<0x736e0000>,
+ Sched<[WriteVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128]>;
+
+def VCLO_B : LSX2R_VV<0x729c0000>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLO_H : LSX2R_VV<0x729c0400>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLO_W : LSX2R_VV<0x729c0800>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLO_D : LSX2R_VV<0x729c0c00>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLZ_B : LSX2R_VV<0x729c1000>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLZ_H : LSX2R_VV<0x729c1400>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLZ_W : LSX2R_VV<0x729c1800>, Sched<[WriteVCL128, ReadVCL128]>;
+def VCLZ_D : LSX2R_VV<0x729c1c00>, Sched<[WriteVCL128, ReadVCL128]>;
+
+def VPCNT_B : LSX2R_VV<0x729c2000>, Sched<[WriteVPCNT128, ReadVPCNT128]>;
+def VPCNT_H : LSX2R_VV<0x729c2400>, Sched<[WriteVPCNT128, ReadVPCNT128]>;
+def VPCNT_W : LSX2R_VV<0x729c2800>, Sched<[WriteVPCNT128, ReadVPCNT128]>;
+def VPCNT_D : LSX2R_VV<0x729c2c00>, Sched<[WriteVPCNT128, ReadVPCNT128]>;
+
+def VBITCLR_B : LSX3R_VVV<0x710c0000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITCLR_H : LSX3R_VVV<0x710c8000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITCLR_W : LSX3R_VVV<0x710d0000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITCLR_D : LSX3R_VVV<0x710d8000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITCLRI_B : LSX2RI3_VVI<0x73102000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITCLRI_H : LSX2RI4_VVI<0x73104000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITCLRI_W : LSX2RI5_VVI<0x73108000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITCLRI_D : LSX2RI6_VVI<0x73110000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+
+def VBITSET_B : LSX3R_VVV<0x710e0000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITSET_H : LSX3R_VVV<0x710e8000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITSET_W : LSX3R_VVV<0x710f0000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITSET_D : LSX3R_VVV<0x710f8000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITSETI_B : LSX2RI3_VVI<0x73142000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITSETI_H : LSX2RI4_VVI<0x73144000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITSETI_W : LSX2RI5_VVI<0x73148000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITSETI_D : LSX2RI6_VVI<0x73150000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+
+def VBITREV_B : LSX3R_VVV<0x71100000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITREV_H : LSX3R_VVV<0x71108000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITREV_W : LSX3R_VVV<0x71110000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITREV_D : LSX3R_VVV<0x71118000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>;
+def VBITREVI_B : LSX2RI3_VVI<0x73182000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITREVI_H : LSX2RI4_VVI<0x73184000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITREVI_W : LSX2RI5_VVI<0x73188000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+def VBITREVI_D : LSX2RI6_VVI<0x73190000>,
+ Sched<[WriteVBITOPS128, ReadVBITOPS128]>;
+
+def VFRSTP_B : LSX3R_VVVV<0x712b0000>,
+ Sched<[WriteVFRSTP128, ReadVFRSTP128, ReadVFRSTP128, ReadVFRSTP128]>;
+def VFRSTP_H : LSX3R_VVVV<0x712b8000>,
+ Sched<[WriteVFRSTP128, ReadVFRSTP128, ReadVFRSTP128, ReadVFRSTP128]>;
+def VFRSTPI_B : LSX2RI5_VVVI<0x729a0000>,
+ Sched<[WriteVFRSTP128, ReadVFRSTP128, ReadVFRSTP128]>;
+def VFRSTPI_H : LSX2RI5_VVVI<0x729a8000>,
+ Sched<[WriteVFRSTP128, ReadVFRSTP128, ReadVFRSTP128]>;
+
+def VFADD_S : LSX3R_VVV<0x71308000>,
+ Sched<[WriteVFADD128, ReadVFADD128, ReadVFADD128]>;
+def VFADD_D : LSX3R_VVV<0x71310000>,
+ Sched<[WriteVFADD128, ReadVFADD128, ReadVFADD128]>;
+def VFSUB_S : LSX3R_VVV<0x71328000>,
+ Sched<[WriteVFADD128, ReadVFADD128, ReadVFADD128]>;
+def VFSUB_D : LSX3R_VVV<0x71330000>,
+ Sched<[WriteVFADD128, ReadVFADD128, ReadVFADD128]>;
+def VFMUL_S : LSX3R_VVV<0x71388000>,
+ Sched<[WriteVFMUL128, ReadVFMUL128, ReadVFMUL128]>;
+def VFMUL_D : LSX3R_VVV<0x71390000>,
+ Sched<[WriteVFMUL128, ReadVFMUL128, ReadVFMUL128]>;
+def VFDIV_S : LSX3R_VVV<0x713a8000>,
+ Sched<[WriteVFDIVS128, ReadVFDIVS128, ReadVFDIVS128]>;
+def VFDIV_D : LSX3R_VVV<0x713b0000>,
+ Sched<[WriteVFDIVD128, ReadVFDIVD128, ReadVFDIVD128]>;
+
+def VFMADD_S : LSX4R_VVVV<0x09100000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFMADD_D : LSX4R_VVVV<0x09200000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFMSUB_S : LSX4R_VVVV<0x09500000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFMSUB_D : LSX4R_VVVV<0x09600000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFNMADD_S : LSX4R_VVVV<0x09900000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFNMADD_D : LSX4R_VVVV<0x09a00000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFNMSUB_S : LSX4R_VVVV<0x09d00000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+def VFNMSUB_D : LSX4R_VVVV<0x09e00000>,
+ Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>;
+
+def VFMAX_S : LSX3R_VVV<0x713c8000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+def VFMAX_D : LSX3R_VVV<0x713d0000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+def VFMIN_S : LSX3R_VVV<0x713e8000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+def VFMIN_D : LSX3R_VVV<0x713f0000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+
+def VFMAXA_S : LSX3R_VVV<0x71408000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+def VFMAXA_D : LSX3R_VVV<0x71410000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+def VFMINA_S : LSX3R_VVV<0x71428000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+def VFMINA_D : LSX3R_VVV<0x71430000>,
+ Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>;
+
+def VFLOGB_S : LSX2R_VV<0x729cc400>, Sched<[WriteVFLOGB128, ReadVFLOGB128]>;
+def VFLOGB_D : LSX2R_VV<0x729cc800>, Sched<[WriteVFLOGB128, ReadVFLOGB128]>;
+
+def VFCLASS_S : LSX2R_VV<0x729cd400>, Sched<[WriteVFCLASS128, ReadVFCLASS128]>;
+def VFCLASS_D : LSX2R_VV<0x729cd800>, Sched<[WriteVFCLASS128, ReadVFCLASS128]>;
+
+def VFSQRT_S : LSX2R_VV<0x729ce400>, Sched<[WriteVFSQRTS128, ReadVFSQRTS128]>;
+def VFSQRT_D : LSX2R_VV<0x729ce800>, Sched<[WriteVFSQRTD128, ReadVFSQRTD128]>;
+def VFRECIP_S : LSX2R_VV<0x729cf400>,
+ Sched<[WriteVFRECIPS128, ReadVFRECIPS128]>;
+def VFRECIP_D : LSX2R_VV<0x729cf800>,
+ Sched<[WriteVFRECIPD128, ReadVFRECIPD128]>;
+def VFRSQRT_S : LSX2R_VV<0x729d0400>,
+ Sched<[WriteVFRSQRTS128, ReadVFRSQRTS128]>;
+def VFRSQRT_D : LSX2R_VV<0x729d0800>,
+ Sched<[WriteVFRSQRTD128, ReadVFRSQRTD128]>;
+def VFRECIPE_S : LSX2R_VV<0x729d1400>,
+ Sched<[WriteVFRECIPE128, ReadVFRECIPE128]>;
+def VFRECIPE_D : LSX2R_VV<0x729d1800>,
+ Sched<[WriteVFRECIPE128, ReadVFRECIPE128]>;
+def VFRSQRTE_S : LSX2R_VV<0x729d2400>,
+ Sched<[WriteVFRSQRTE128, ReadVFRSQRTE128]>;
+def VFRSQRTE_D : LSX2R_VV<0x729d2800>,
+ Sched<[WriteVFRSQRTE128, ReadVFRSQRTE128]>;
+
+def VFCVTL_S_H : LSX2R_VV<0x729de800>, Sched<[WriteVFCVT128, ReadVFCVT128]>;
+def VFCVTH_S_H : LSX2R_VV<0x729dec00>, Sched<[WriteVFCVT128, ReadVFCVT128]>;
+def VFCVTL_D_S : LSX2R_VV<0x729df000>, Sched<[WriteVFCVT128, ReadVFCVT128]>;
+def VFCVTH_D_S : LSX2R_VV<0x729df400>, Sched<[WriteVFCVT128, ReadVFCVT128]>;
+def VFCVT_H_S : LSX3R_VVV<0x71460000>,
+ Sched<[WriteVFCVT128, ReadVFCVT128, ReadVFCVT128]>;
+def VFCVT_S_D : LSX3R_VVV<0x71468000>,
+ Sched<[WriteVFCVT128, ReadVFCVT128, ReadVFCVT128]>;
+
+def VFRINTRNE_S : LSX2R_VV<0x729d7400>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRNE_D : LSX2R_VV<0x729d7800>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRZ_S : LSX2R_VV<0x729d6400>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRZ_D : LSX2R_VV<0x729d6800>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRP_S : LSX2R_VV<0x729d5400>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRP_D : LSX2R_VV<0x729d5800>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRM_S : LSX2R_VV<0x729d4400>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINTRM_D : LSX2R_VV<0x729d4800>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINT_S : LSX2R_VV<0x729d3400>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+def VFRINT_D : LSX2R_VV<0x729d3800>, Sched<[WriteVFRINT128, ReadVFRINT128]>;
+
+def VFTINTRNE_W_S : LSX2R_VV<0x729e5000>,
+ Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRNE_L_D : LSX2R_VV<0x729e5400>,
+ Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRZ_W_S : LSX2R_VV<0x729e4800>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRZ_L_D : LSX2R_VV<0x729e4c00>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRP_W_S : LSX2R_VV<0x729e4000>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRP_L_D : LSX2R_VV<0x729e4400>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRM_W_S : LSX2R_VV<0x729e3800>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRM_L_D : LSX2R_VV<0x729e3c00>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINT_W_S : LSX2R_VV<0x729e3000>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINT_L_D : LSX2R_VV<0x729e3400>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRZ_WU_S : LSX2R_VV<0x729e7000>,
+ Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINTRZ_LU_D : LSX2R_VV<0x729e7400>,
+ Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINT_WU_S : LSX2R_VV<0x729e5800>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+def VFTINT_LU_D : LSX2R_VV<0x729e5c00>, Sched<[WriteVFTINT128, ReadVFTINT128]>;
+
+def VFTINTRNE_W_D : LSX3R_VVV<0x714b8000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRZ_W_D : LSX3R_VVV<0x714b0000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRP_W_D : LSX3R_VVV<0x714a8000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRM_W_D : LSX3R_VVV<0x714a0000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128, ReadVFTINTX128]>;
+def VFTINT_W_D : LSX3R_VVV<0x71498000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128, ReadVFTINTX128]>;
+
+def VFTINTRNEL_L_S : LSX2R_VV<0x729ea000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRNEH_L_S : LSX2R_VV<0x729ea400>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRZL_L_S : LSX2R_VV<0x729e9800>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRZH_L_S : LSX2R_VV<0x729e9c00>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRPL_L_S : LSX2R_VV<0x729e9000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRPH_L_S : LSX2R_VV<0x729e9400>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRML_L_S : LSX2R_VV<0x729e8800>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTRMH_L_S : LSX2R_VV<0x729e8c00>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTL_L_S : LSX2R_VV<0x729e8000>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+def VFTINTH_L_S : LSX2R_VV<0x729e8400>,
+ Sched<[WriteVFTINTX128, ReadVFTINTX128]>;
+
+def VFFINT_S_W : LSX2R_VV<0x729e0000>, Sched<[WriteVFFINT128, ReadVFFINT128]>;
+def VFFINT_D_L : LSX2R_VV<0x729e0800>, Sched<[WriteVFFINT128, ReadVFFINT128]>;
+def VFFINT_S_WU : LSX2R_VV<0x729e0400>, Sched<[WriteVFFINT128, ReadVFFINT128]>;
+def VFFINT_D_LU : LSX2R_VV<0x729e0c00>, Sched<[WriteVFFINT128, ReadVFFINT128]>;
+def VFFINTL_D_W : LSX2R_VV<0x729e1000>,
+ Sched<[WriteVFFINTX128, ReadVFFINTX128]>;
+def VFFINTH_D_W : LSX2R_VV<0x729e1400>,
+ Sched<[WriteVFFINTX128, ReadVFFINTX128]>;
+def VFFINT_S_L : LSX3R_VVV<0x71480000>,
+ Sched<[WriteVFFINTX128, ReadVFFINTX128, ReadVFFINTX128]>;
+
+def VSEQ_B : LSX3R_VVV<0x70000000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSEQ_H : LSX3R_VVV<0x70008000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSEQ_W : LSX3R_VVV<0x70010000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSEQ_D : LSX3R_VVV<0x70018000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSEQI_B : LSX2RI5_VVI<0x72800000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSEQI_H : LSX2RI5_VVI<0x72808000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSEQI_W : LSX2RI5_VVI<0x72810000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSEQI_D : LSX2RI5_VVI<0x72818000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+
+def VSLE_B : LSX3R_VVV<0x70020000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLE_H : LSX3R_VVV<0x70028000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLE_W : LSX3R_VVV<0x70030000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLE_D : LSX3R_VVV<0x70038000>,
+ Sched<[WriteVCMPD128, ReadVCMPD128, ReadVCMPD128]>;
+def VSLEI_B : LSX2RI5_VVI<0x72820000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLEI_H : LSX2RI5_VVI<0x72828000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLEI_W : LSX2RI5_VVI<0x72830000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLEI_D : LSX2RI5_VVI<0x72838000, simm5>,
+ Sched<[WriteVCMPD128, ReadVCMPD128]>;
+
+def VSLE_BU : LSX3R_VVV<0x70040000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLE_HU : LSX3R_VVV<0x70048000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLE_WU : LSX3R_VVV<0x70050000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLE_DU : LSX3R_VVV<0x70058000>,
+ Sched<[WriteVCMPD128, ReadVCMPD128, ReadVCMPD128]>;
+def VSLEI_BU : LSX2RI5_VVI<0x72840000>, Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLEI_HU : LSX2RI5_VVI<0x72848000>, Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLEI_WU : LSX2RI5_VVI<0x72850000>, Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLEI_DU : LSX2RI5_VVI<0x72858000>, Sched<[WriteVCMPD128, ReadVCMPD128]>;
+
+def VSLT_B : LSX3R_VVV<0x70060000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLT_H : LSX3R_VVV<0x70068000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLT_W : LSX3R_VVV<0x70070000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLT_D : LSX3R_VVV<0x70078000>,
+ Sched<[WriteVCMPD128, ReadVCMPD128, ReadVCMPD128]>;
+def VSLTI_B : LSX2RI5_VVI<0x72860000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLTI_H : LSX2RI5_VVI<0x72868000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLTI_W : LSX2RI5_VVI<0x72870000, simm5>,
+ Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLTI_D : LSX2RI5_VVI<0x72878000, simm5>,
+ Sched<[WriteVCMPD128, ReadVCMPD128]>;
+
+def VSLT_BU : LSX3R_VVV<0x70080000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLT_HU : LSX3R_VVV<0x70088000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLT_WU : LSX3R_VVV<0x70090000>,
+ Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>;
+def VSLT_DU : LSX3R_VVV<0x70098000>,
+ Sched<[WriteVCMPD128, ReadVCMPD128, ReadVCMPD128]>;
+def VSLTI_BU : LSX2RI5_VVI<0x72880000>, Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLTI_HU : LSX2RI5_VVI<0x72888000>, Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLTI_WU : LSX2RI5_VVI<0x72890000>, Sched<[WriteVCMP128, ReadVCMP128]>;
+def VSLTI_DU : LSX2RI5_VVI<0x72898000>, Sched<[WriteVCMPD128, ReadVCMPD128]>;
+
+def VFCMP_CAF_S : LSX3R_VVV<0x0c500000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SAF_S : LSX3R_VVV<0x0c508000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CLT_S : LSX3R_VVV<0x0c510000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SLT_S : LSX3R_VVV<0x0c518000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CEQ_S : LSX3R_VVV<0x0c520000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SEQ_S : LSX3R_VVV<0x0c528000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CLE_S : LSX3R_VVV<0x0c530000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SLE_S : LSX3R_VVV<0x0c538000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CUN_S : LSX3R_VVV<0x0c540000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SUN_S : LSX3R_VVV<0x0c548000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CULT_S : LSX3R_VVV<0x0c550000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SULT_S : LSX3R_VVV<0x0c558000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CUEQ_S : LSX3R_VVV<0x0c560000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SUEQ_S : LSX3R_VVV<0x0c568000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CULE_S : LSX3R_VVV<0x0c570000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SULE_S : LSX3R_VVV<0x0c578000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CNE_S : LSX3R_VVV<0x0c580000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SNE_S : LSX3R_VVV<0x0c588000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_COR_S : LSX3R_VVV<0x0c5a0000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SOR_S : LSX3R_VVV<0x0c5a8000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CUNE_S : LSX3R_VVV<0x0c5c0000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SUNE_S : LSX3R_VVV<0x0c5c8000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+
+def VFCMP_CAF_D : LSX3R_VVV<0x0c600000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SAF_D : LSX3R_VVV<0x0c608000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CLT_D : LSX3R_VVV<0x0c610000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SLT_D : LSX3R_VVV<0x0c618000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CEQ_D : LSX3R_VVV<0x0c620000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SEQ_D : LSX3R_VVV<0x0c628000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CLE_D : LSX3R_VVV<0x0c630000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SLE_D : LSX3R_VVV<0x0c638000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CUN_D : LSX3R_VVV<0x0c640000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SUN_D : LSX3R_VVV<0x0c648000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CULT_D : LSX3R_VVV<0x0c650000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SULT_D : LSX3R_VVV<0x0c658000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CUEQ_D : LSX3R_VVV<0x0c660000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SUEQ_D : LSX3R_VVV<0x0c668000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CULE_D : LSX3R_VVV<0x0c670000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SULE_D : LSX3R_VVV<0x0c678000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CNE_D : LSX3R_VVV<0x0c680000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SNE_D : LSX3R_VVV<0x0c688000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_COR_D : LSX3R_VVV<0x0c6a0000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SOR_D : LSX3R_VVV<0x0c6a8000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_CUNE_D : LSX3R_VVV<0x0c6c0000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+def VFCMP_SUNE_D : LSX3R_VVV<0x0c6c8000>,
+ Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>;
+
+def VBITSEL_V : LSX4R_VVVV<0x0d100000>,
+ Sched<[WriteVBITSEL128, ReadVBITSEL128, ReadVBITSEL128, ReadVBITSEL128]>;
+
+def VBITSELI_B : LSX2RI8_VVVI<0x73c40000>,
+ Sched<[WriteVBITSEL128, ReadVBITSEL128, ReadVBITSEL128]>;
+
+def VSETEQZ_V : LSX2R_CV<0x729c9800>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETNEZ_V : LSX2R_CV<0x729c9c00>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETANYEQZ_B : LSX2R_CV<0x729ca000>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETANYEQZ_H : LSX2R_CV<0x729ca400>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETANYEQZ_W : LSX2R_CV<0x729ca800>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETANYEQZ_D : LSX2R_CV<0x729cac00>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETALLNEZ_B : LSX2R_CV<0x729cb000>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETALLNEZ_H : LSX2R_CV<0x729cb400>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETALLNEZ_W : LSX2R_CV<0x729cb800>, Sched<[WriteVSET128, ReadVSET128]>;
+def VSETALLNEZ_D : LSX2R_CV<0x729cbc00>, Sched<[WriteVSET128, ReadVSET128]>;
+
+def VINSGR2VR_B : LSX2RI4_VVRI<0x72eb8000>,
+ Sched<[WriteVINSGR2VR128, ReadVINSGR2VR128, ReadVINSGR2VR128]>;
+def VINSGR2VR_H : LSX2RI3_VVRI<0x72ebc000>,
+ Sched<[WriteVINSGR2VR128, ReadVINSGR2VR128, ReadVINSGR2VR128]>;
+def VINSGR2VR_W : LSX2RI2_VVRI<0x72ebe000>,
+ Sched<[WriteVINSGR2VR128, ReadVINSGR2VR128, ReadVINSGR2VR128]>;
+def VINSGR2VR_D : LSX2RI1_VVRI<0x72ebf000>,
+ Sched<[WriteVINSGR2VR128, ReadVINSGR2VR128, ReadVINSGR2VR128]>;
+def VPICKVE2GR_B : LSX2RI4_RVI<0x72ef8000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_H : LSX2RI3_RVI<0x72efc000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_W : LSX2RI2_RVI<0x72efe000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_D : LSX2RI1_RVI<0x72eff000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_BU : LSX2RI4_RVI<0x72f38000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_HU : LSX2RI3_RVI<0x72f3c000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_WU : LSX2RI2_RVI<0x72f3e000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
+def VPICKVE2GR_DU : LSX2RI1_RVI<0x72f3f000>,
+ Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>;
let isReMaterializable = 1 in {
-def VREPLGR2VR_B : LSX2R_VR<0x729f0000>;
-def VREPLGR2VR_H : LSX2R_VR<0x729f0400>;
-def VREPLGR2VR_W : LSX2R_VR<0x729f0800>;
-def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>;
+def VREPLGR2VR_B : LSX2R_VR<0x729f0000>,
+ Sched<[WriteVREPLGR2VR128, ReadVREPLGR2VR128]>;
+def VREPLGR2VR_H : LSX2R_VR<0x729f0400>,
+ Sched<[WriteVREPLGR2VR128, ReadVREPLGR2VR128]>;
+def VREPLGR2VR_W : LSX2R_VR<0x729f0800>,
+ Sched<[WriteVREPLGR2VRWD128, ReadVREPLGR2VRWD128]>;
+def VREPLGR2VR_D : LSX2R_VR<0x729f0c00>,
+ Sched<[WriteVREPLGR2VRWD128, ReadVREPLGR2VRWD128]>;
}
-def VREPLVE_B : LSX3R_VVR<0x71220000>;
-def VREPLVE_H : LSX3R_VVR<0x71228000>;
-def VREPLVE_W : LSX3R_VVR<0x71230000>;
-def VREPLVE_D : LSX3R_VVR<0x71238000>;
-def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>;
-def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>;
-def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>;
-def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>;
-
-def VBSLL_V : LSX2RI5_VVI<0x728e0000>;
-def VBSRL_V : LSX2RI5_VVI<0x728e8000>;
-
-def VPACKEV_B : LSX3R_VVV<0x71160000>;
-def VPACKEV_H : LSX3R_VVV<0x71168000>;
-def VPACKEV_W : LSX3R_VVV<0x71170000>;
-def VPACKEV_D : LSX3R_VVV<0x71178000>;
-def VPACKOD_B : LSX3R_VVV<0x71180000>;
-def VPACKOD_H : LSX3R_VVV<0x71188000>;
-def VPACKOD_W : LSX3R_VVV<0x71190000>;
-def VPACKOD_D : LSX3R_VVV<0x71198000>;
-
-def VPICKEV_B : LSX3R_VVV<0x711e0000>;
-def VPICKEV_H : LSX3R_VVV<0x711e8000>;
-def VPICKEV_W : LSX3R_VVV<0x711f0000>;
-def VPICKEV_D : LSX3R_VVV<0x711f8000>;
-def VPICKOD_B : LSX3R_VVV<0x71200000>;
-def VPICKOD_H : LSX3R_VVV<0x71208000>;
-def VPICKOD_W : LSX3R_VVV<0x71210000>;
-def VPICKOD_D : LSX3R_VVV<0x71218000>;
-
-def VILVL_B : LSX3R_VVV<0x711a0000>;
-def VILVL_H : LSX3R_VVV<0x711a8000>;
-def VILVL_W : LSX3R_VVV<0x711b0000>;
-def VILVL_D : LSX3R_VVV<0x711b8000>;
-def VILVH_B : LSX3R_VVV<0x711c0000>;
-def VILVH_H : LSX3R_VVV<0x711c8000>;
-def VILVH_W : LSX3R_VVV<0x711d0000>;
-def VILVH_D : LSX3R_VVV<0x711d8000>;
-
-def VSHUF_B : LSX4R_VVVV<0x0d500000>;
-
-def VSHUF_H : LSX3R_VVVV<0x717a8000>;
-def VSHUF_W : LSX3R_VVVV<0x717b0000>;
-def VSHUF_D : LSX3R_VVVV<0x717b8000>;
-
-def VSHUF4I_B : LSX2RI8_VVI<0x73900000>;
-def VSHUF4I_H : LSX2RI8_VVI<0x73940000>;
-def VSHUF4I_W : LSX2RI8_VVI<0x73980000>;
-def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>;
-
-def VPERMI_W : LSX2RI8_VVVI<0x73e40000>;
-
-def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>;
-def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>;
-def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>;
-def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>;
+def VREPLVE_B : LSX3R_VVR<0x71220000>,
+ Sched<[WriteVREPLVE128, ReadVREPLVE128, ReadVREPLVE128]>;
+def VREPLVE_H : LSX3R_VVR<0x71228000>,
+ Sched<[WriteVREPLVE128, ReadVREPLVE128, ReadVREPLVE128]>;
+def VREPLVE_W : LSX3R_VVR<0x71230000>,
+ Sched<[WriteVREPLVE128, ReadVREPLVE128, ReadVREPLVE128]>;
+def VREPLVE_D : LSX3R_VVR<0x71238000>,
+ Sched<[WriteVREPLVE128, ReadVREPLVE128, ReadVREPLVE128]>;
+def VREPLVEI_B : LSX2RI4_VVI<0x72f78000>,
+ Sched<[WriteVREPLVEI128, ReadVREPLVEI128]>;
+def VREPLVEI_H : LSX2RI3_VVI<0x72f7c000>,
+ Sched<[WriteVREPLVEI128, ReadVREPLVEI128]>;
+def VREPLVEI_W : LSX2RI2_VVI<0x72f7e000>,
+ Sched<[WriteVREPLVEI128, ReadVREPLVEI128]>;
+def VREPLVEI_D : LSX2RI1_VVI<0x72f7f000>,
+ Sched<[WriteVREPLVEI128, ReadVREPLVEI128]>;
+
+def VBSLL_V : LSX2RI5_VVI<0x728e0000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+def VBSRL_V : LSX2RI5_VVI<0x728e8000>, Sched<[WriteVSHIFT128, ReadVSHIFT128]>;
+
+def VPACKEV_B : LSX3R_VVV<0x71160000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKEV_H : LSX3R_VVV<0x71168000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKEV_W : LSX3R_VVV<0x71170000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKEV_D : LSX3R_VVV<0x71178000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKOD_B : LSX3R_VVV<0x71180000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKOD_H : LSX3R_VVV<0x71188000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKOD_W : LSX3R_VVV<0x71190000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPACKOD_D : LSX3R_VVV<0x71198000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+
+def VPICKEV_B : LSX3R_VVV<0x711e0000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKEV_H : LSX3R_VVV<0x711e8000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKEV_W : LSX3R_VVV<0x711f0000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKEV_D : LSX3R_VVV<0x711f8000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKOD_B : LSX3R_VVV<0x71200000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKOD_H : LSX3R_VVV<0x71208000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKOD_W : LSX3R_VVV<0x71210000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VPICKOD_D : LSX3R_VVV<0x71218000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+
+def VILVL_B : LSX3R_VVV<0x711a0000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVL_H : LSX3R_VVV<0x711a8000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVL_W : LSX3R_VVV<0x711b0000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVL_D : LSX3R_VVV<0x711b8000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVH_B : LSX3R_VVV<0x711c0000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVH_H : LSX3R_VVV<0x711c8000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVH_W : LSX3R_VVV<0x711d0000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+def VILVH_D : LSX3R_VVV<0x711d8000>,
+ Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>;
+
+def VSHUF_B : LSX4R_VVVV<0x0d500000>,
+ Sched<[WriteVSHUF128, ReadVSHUF128, ReadVSHUF128, ReadVSHUF128]>;
+
+def VSHUF_H : LSX3R_VVVV<0x717a8000>,
+ Sched<[WriteVSHUF128, ReadVSHUF128, ReadVSHUF128, ReadVSHUF128]>;
+def VSHUF_W : LSX3R_VVVV<0x717b0000>,
+ Sched<[WriteVSHUF128, ReadVSHUF128, ReadVSHUF128, ReadVSHUF128]>;
+def VSHUF_D : LSX3R_VVVV<0x717b8000>,
+ Sched<[WriteVSHUF128, ReadVSHUF128, ReadVSHUF128, ReadVSHUF128]>;
+
+def VSHUF4I_B : LSX2RI8_VVI<0x73900000>,
+ Sched<[WriteVSHUF4I128, ReadVSHUF4I128]>;
+def VSHUF4I_H : LSX2RI8_VVI<0x73940000>,
+ Sched<[WriteVSHUF4I128, ReadVSHUF4I128]>;
+def VSHUF4I_W : LSX2RI8_VVI<0x73980000>,
+ Sched<[WriteVSHUF4I128, ReadVSHUF4I128]>;
+def VSHUF4I_D : LSX2RI8_VVVI<0x739c0000>,
+ Sched<[WriteVSHUF4I128, ReadVSHUF4I128, ReadVSHUF4I128]>;
+
+def VPERMI_W : LSX2RI8_VVVI<0x73e40000>,
+ Sched<[WriteVPERMI128, ReadVPERMI128, ReadVPERMI128]>;
+
+def VEXTRINS_D : LSX2RI8_VVVI<0x73800000>,
+ Sched<[WriteVEXTRINS128, ReadVEXTRINS128, ReadVEXTRINS128]>;
+def VEXTRINS_W : LSX2RI8_VVVI<0x73840000>,
+ Sched<[WriteVEXTRINS128, ReadVEXTRINS128, ReadVEXTRINS128]>;
+def VEXTRINS_H : LSX2RI8_VVVI<0x73880000>,
+ Sched<[WriteVEXTRINS128, ReadVEXTRINS128, ReadVEXTRINS128]>;
+def VEXTRINS_B : LSX2RI8_VVVI<0x738c0000>,
+ Sched<[WriteVEXTRINS128, ReadVEXTRINS128, ReadVEXTRINS128]>;
} // mayLoad = 0, mayStore = 0
let mayLoad = 1, mayStore = 0 in {
-def VLD : LSX2RI12_Load<0x2c000000>;
-def VLDX : LSX3R_Load<0x38400000>;
-
-def VLDREPL_B : LSX2RI12_Load<0x30800000>;
-def VLDREPL_H : LSX2RI11_Load<0x30400000>;
-def VLDREPL_W : LSX2RI10_Load<0x30200000>;
-def VLDREPL_D : LSX2RI9_Load<0x30100000>;
+def VLD : LSX2RI12_Load<0x2c000000>, Sched<[WriteVLD128, ReadVMemBase128]>;
+def VLDX : LSX3R_Load<0x38400000>,
+ Sched<[WriteVLDX128, ReadVMemBase128, ReadVMemOffset128]>;
+
+def VLDREPL_B : LSX2RI12_Load<0x30800000>,
+ Sched<[WriteVLDREPL128, ReadVMemBase128]>;
+def VLDREPL_H : LSX2RI11_Load<0x30400000>,
+ Sched<[WriteVLDREPL128, ReadVMemBase128]>;
+def VLDREPL_W : LSX2RI10_Load<0x30200000>,
+ Sched<[WriteVLDREPL128, ReadVMemBase128]>;
+def VLDREPL_D : LSX2RI9_Load<0x30100000>,
+ Sched<[WriteVLDREPL128, ReadVMemBase128]>;
} // mayLoad = 1, mayStore = 0
let mayLoad = 0, mayStore = 1 in {
-def VST : LSX2RI12_Store<0x2c400000>;
-def VSTX : LSX3R_Store<0x38440000>;
-
-def VSTELM_B : LSX2RI8I4_VRII<0x31800000>;
-def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>;
-def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>;
-def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>;
+def VST : LSX2RI12_Store<0x2c400000>,
+ Sched<[WriteVST128, ReadVSTData128, ReadVMemBase128]>;
+def VSTX : LSX3R_Store<0x38440000>,
+ Sched<[WriteVSTX128, ReadVSTData128, ReadVMemBase128, ReadVMemOffset128]>;
+
+def VSTELM_B : LSX2RI8I4_VRII<0x31800000>,
+ Sched<[WriteVSTELM128, ReadVSTData128, ReadVMemBase128]>;
+def VSTELM_H : LSX2RI8I3_VRII<0x31400000, simm8_lsl1>,
+ Sched<[WriteVSTELM128, ReadVSTData128, ReadVMemBase128]>;
+def VSTELM_W : LSX2RI8I2_VRII<0x31200000, simm8_lsl2>,
+ Sched<[WriteVSTELM128, ReadVSTData128, ReadVMemBase128]>;
+def VSTELM_D : LSX2RI8I1_VRII<0x31100000, simm8_lsl3>,
+ Sched<[WriteVSTELM128, ReadVSTData128, ReadVMemBase128]>;
} // mayLoad = 0, mayStore = 1
} // hasSideEffects = 0, Predicates = [HasExtLSX]
diff --git a/llvm/lib/Target/LoongArch/LoongArchSchedLA464.td b/llvm/lib/Target/LoongArch/LoongArchSchedLA464.td
new file mode 100644
index 0000000000000..e27e9d24ca9ea
--- /dev/null
+++ b/llvm/lib/Target/LoongArch/LoongArchSchedLA464.td
@@ -0,0 +1,1080 @@
+//==- LoongArchSchedLA464.td - LA464 Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for LA464 to support instruction
+// scheduling and other instruction cost heuristics.
+// Based on:
+// * Loongson 3A6000: A Star among Chinese CPUs, by Chips and Cheese
+// https://chipsandcheese.com/p/loongson-3a6000-a-star-among-chinese-cpus/
+// * Loongson-3A5000 instruction latency and throughput document, V0.1,
+// 2024/07/24, Loongson Technology. Where the two sources disagree, the
+// measured latency and throughput of the document is used.
+//===----------------------------------------------------------------------===//
+
+def LA464Model : SchedMachineModel {
+ let IssueWidth = 4; // 4-way decode and dispatch
+ let MicroOpBufferSize = 128; // Reorder Buffer size
+ let LoadLatency = 4;
+ let MispredictPenalty = 14; // Estimated value
+ let CompleteModel = 0;
+}
+
+let SchedModel = LA464Model in {
+// Integer Execution Unit
+//
+// Execution Pipes
+// There are four integer execution pipes and two address generation pipes.
+def LA464ALU0 : ProcResource<1>; // ALU, MUL, Branch, ALSL, BSTRINS, BYTEPICK
+def LA464ALU1 : ProcResource<1>; // ALU, MUL, Branch, ALSL, BSTRINS, BYTEPICK
+def LA464ALU2 : ProcResource<1>; // ALU
+def LA464ALU3 : ProcResource<1>; // ALU
+
+def LA464AGU0 : ProcResource<1>; // Load, Store
+def LA464AGU1 : ProcResource<1>; // Load
+
+// Execution Units
+//
+// Integer division runs on a non-pipelined unit behind ALU0. (Estimated)
+def LA464Div : ProcResource<1>;
+
+// Execution pipeline grouping
+//
+// Only ALU0 and ALU1 execute branches, integer multiplies, ALSL, BSTRINS and
+// BYTEPICK according to their throughput (IPC is 2 instead of 4). (Estimated)
+def LA464ALU01 : ProcResGroup<[LA464ALU0, LA464ALU1]>;
+defvar LA464Branch = LA464ALU01;
+
+// Both AGUs generate load addresses, so plain loads reach two per cycle.
+// Stores and the indexed / bounded accesses are measured at one per cycle, so
+// they are modelled on AGU0 alone. (Estimated)
+def LA464AGU : ProcResGroup<[LA464AGU0, LA464AGU1]>;
+
+// Scheduling
+//
+// LA464 has an unified 32 entry integer scheduler.
+def LA464ALU : ProcResGroup<[LA464ALU0, LA464ALU1, LA464ALU2, LA464ALU3]> {
+ let BufferSize = 32;
+}
+
+// Floating-Point / Vector Unit
+//
+// Execution pipes
+// There are two floating point/vector execution pipes.
+def LA464FPU0 : ProcResource<1>; // FALU, FMUL, FMA, FDIV, FMOV, VALU, VNarrow
+def LA464FPU1 : ProcResource<1>; // FALU, FMUL, FMA, VALU
+
+// Execution Units
+//
+// Floating-point division, square root and reciprocal run on a non-pipelined
+// unit behind FPU0. It also executes the vector divide, square root and
+// reciprocal operations. (Estimated)
+def LA464FDiv : ProcResource<1>;
+
+// Only FPU0 moves data between the general purpose or condition flag register
+// file and the floating-point / vector register file, and only FPU0 executes
+// FSEL, so those are limited to one per cycle. (Estimated)
+defvar LA464FMov = LA464FPU0;
+
+// Only FPU0 has the cross-element datapath used by the narrowing vector
+// shifts, VSLLWIL and the resizing floating-point conversions; the document
+// measures one per cycle for all of them. (Estimated)
+defvar LA464VNarrow = LA464FPU0;
+
+// Scheduling
+//
+// LA464 has an unified 32 entry vector/fp scheduler. Both pipes execute the
+// scalar floating-point and the 128-bit / 256-bit vector operations.
+def LA464FPU : ProcResGroup<[LA464FPU0, LA464FPU1]> {
+ let BufferSize = 32;
+}
+
+// Load-Store Unit
+//
+// The LS unit contains two pipelines. Both can issue a load, so the document
+// measures two loads per cycle, while stores are limited to one per cycle.
+def LA464Load : ProcResource<2> {
+ // The LS unit utilizes a 64-entry load queue (LDQ). (Estimated)
+ let BufferSize = 64;
+}
+
+def LA464Store : ProcResource<1> {
+ // The LS unit utilizes a 44-entry store queue (STQ). (Estimated)
+ let BufferSize = 44;
+}
+
+//===----------------------------------------------------------------------===//
+
+// Base Instruction
+// Integer arithmetic and logic, default latency is 1
+def : WriteRes<WriteIALU, [LA464ALU]>;
+def : WriteRes<WriteIALU32, [LA464ALU]>;
+
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+
+// Integer instruction latency ALSL
+def : WriteRes<WriteIALSL, [LA464ALU01]>;
+def : WriteRes<WriteIALSL32, [LA464ALU01]>;
+
+def : ReadAdvance<ReadIALSL, 0>;
+def : ReadAdvance<ReadIALSL32, 0>;
+
+// Integer instruction latency MUL
+let Latency = 4 in {
+ def : WriteRes<WriteIMUL, [LA464ALU01]>;
+ def : WriteRes<WriteIMUL32, [LA464ALU01]>;
+}
+def : ReadAdvance<ReadIMUL, 0>;
+def : ReadAdvance<ReadIMUL32, 0>;
+
+// Integer instruction latency DIV
+// Latency is 5-21 and throughput is 0.08-0.25, pick the worst case.
+let Latency = 21, ReleaseAtCycles = [1, 11] in {
+ def : WriteRes<WriteIDIV32, [LA464ALU0, LA464Div]>;
+}
+// Latency is 5-36 and throughput is 0.048-0.25, pick the worst case.
+let Latency = 36, ReleaseAtCycles = [1, 20] in {
+ def : WriteRes<WriteIDIV, [LA464ALU0, LA464Div]>;
+}
+def : ReadAdvance<ReadIDIV, 0>;
+def : ReadAdvance<ReadIDIV32, 0>;
+
+// Integer instruction latency SHIFT
+def : WriteRes<WriteIShift, [LA464ALU]>;
+def : WriteRes<WriteIShift32, [LA464ALU]>;
+
+def : ReadAdvance<ReadIShift, 0>;
+def : ReadAdvance<ReadIShift32, 0>;
+
+// Integer instruction latency EXT
+def : WriteRes<WriteIEXT, [LA464ALU]>;
+
+def : ReadAdvance<ReadIEXT, 0>;
+
+// Integer instruction latency CLO / CLZ / CTO / CTZ
+def : WriteRes<WriteICL, [LA464ALU]>;
+def : WriteRes<WriteICL32, [LA464ALU]>;
+def : WriteRes<WriteICT, [LA464ALU]>;
+def : WriteRes<WriteICT32, [LA464ALU]>;
+
+def : ReadAdvance<ReadICL, 0>;
+def : ReadAdvance<ReadICL32, 0>;
+def : ReadAdvance<ReadICT, 0>;
+def : ReadAdvance<ReadICT32, 0>;
+
+// Integer instruction latency BytePick
+def : WriteRes<WriteIBytePick, [LA464ALU01]>;
+def : WriteRes<WriteIBytePick32, [LA464ALU01]>;
+
+def : ReadAdvance<ReadIBytePick, 0>;
+def : ReadAdvance<ReadIBytePick32, 0>;
+
+// Integer instruction latency REV
+def : WriteRes<WriteIRev, [LA464ALU]>;
+def : WriteRes<WriteIRev32, [LA464ALU]>;
+
+def : ReadAdvance<ReadIRev, 0>;
+def : ReadAdvance<ReadIRev32, 0>;
+
+// Integer instruction latency BitRev
+def : WriteRes<WriteIBitRev, [LA464ALU]>;
+def : WriteRes<WriteIBitRev32, [LA464ALU]>;
+
+def : ReadAdvance<ReadIBitRev, 0>;
+def : ReadAdvance<ReadIBitRev32, 0>;
+
+// Integer instruction latency BSTRINS
+def : WriteRes<WriteIBstrins, [LA464ALU01]>;
+def : WriteRes<WriteIBstrins32, [LA464ALU01]>;
+
+def : ReadAdvance<ReadIBstrins, 0>;
+def : ReadAdvance<ReadIBstrins32, 0>;
+
+// Integer instruction latency BSTRPICK
+def : WriteRes<WriteIBstrPick, [LA464ALU]>;
+def : WriteRes<WriteIBstrPick32, [LA464ALU]>;
+
+def : ReadAdvance<ReadIBstrPick, 0>;
+def : ReadAdvance<ReadIBstrPick32, 0>;
+
+// Integer instruction latency SELECT
+def : WriteRes<WriteIMASK, [LA464ALU]>;
+
+def : ReadAdvance<ReadIMASK, 0>;
+
+// Integer instruction latency Jump
+def : WriteRes<WriteIJump, [LA464Branch]>;
+
+def : ReadAdvance<ReadIJump, 0>;
+
+// Integer instruction latency LD ST LDX STX
+let Latency = 4 in {
+ def : WriteRes<WriteLD, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteST, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteLDX, [LA464AGU0, LA464Load]>;
+ def : WriteRes<WriteSTX, [LA464AGU0, LA464Store]>;
+}
+def : ReadAdvance<ReadSTData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadMemOffset, 0>;
+
+// Integer instruction latency LDPTR STPTR
+let Latency = 4 in {
+ def : WriteRes<WriteLDPTR, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteSTPTR, [LA464AGU0, LA464Store]>;
+}
+
+// Integer instruction latency LDGT LDLE STGT STLE
+let Latency = 4 in {
+ def : WriteRes<WriteLDGT, [LA464AGU0, LA464Load]>;
+ def : WriteRes<WriteLDLE, [LA464AGU0, LA464Load]>;
+ def : WriteRes<WriteSTGT, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteSTLE, [LA464AGU0, LA464Store]>;
+}
+def : ReadAdvance<ReadMemCmp, 0>;
+
+// Floating-point instruction latency FADD FSUB FMUL FDIV FMADD FMINMAX
+let Latency = 5 in {
+ def : WriteRes<WriteFADD, [LA464FPU]>;
+ def : WriteRes<WriteFMUL, [LA464FPU]>;
+ def : WriteRes<WriteFMADD, [LA464FPU]>;
+}
+let Latency = 2 in {
+ def : WriteRes<WriteFMinMax, [LA464FPU]>;
+}
+def : ReadAdvance<ReadFADD, 0>;
+def : ReadAdvance<ReadFMUL, 0>;
+def : ReadAdvance<ReadFMADD, 0>;
+def : ReadAdvance<ReadFMinMax, 0>;
+// Latency is 6-14, pick the worst case.
+let Latency = 14, ReleaseAtCycles = [1, 7] in {
+ def : WriteRes<WriteFDIV32, [LA464FPU0, LA464FDiv]>;
+}
+// Latency is 6-20, pick the worst case.
+let Latency = 20, ReleaseAtCycles = [1, 11] in {
+ def : WriteRes<WriteFDIV, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadFDIV32, 0>;
+def : ReadAdvance<ReadFDIV, 0>;
+
+// Floating-point instruction latency FABS FNEG FSQRT FRECIP FRSQRT FSCALEB FLOGB FCOPYSIGN FCLASS FCMP
+def : WriteRes<WriteFABS, [LA464FPU]>;
+def : WriteRes<WriteFNEG, [LA464FPU]>;
+def : WriteRes<WriteFCOPYSIGN, [LA464FPU]>;
+let Latency = 2 in {
+ def : WriteRes<WriteFCLASS, [LA464FPU]>;
+}
+def : WriteRes<WriteFCMP, [LA464FPU]>;
+let Latency = 4 in {
+ def : WriteRes<WriteFSCALEB, [LA464FPU]>;
+ def : WriteRes<WriteFLOGB, [LA464FPU]>;
+}
+def : ReadAdvance<ReadFABS, 0>;
+def : ReadAdvance<ReadFNEG, 0>;
+def : ReadAdvance<ReadFSCALEB, 0>;
+def : ReadAdvance<ReadFLOGB, 0>;
+def : ReadAdvance<ReadFCOPYSIGN, 0>;
+def : ReadAdvance<ReadFCLASS, 0>;
+def : ReadAdvance<ReadFCMP, 0>;
+// Latency is 8-16, pick the worst case.
+let Latency = 16, ReleaseAtCycles = [1, 7] in {
+ def : WriteRes<WriteFRECIP32, [LA464FPU0, LA464FDiv]>;
+}
+// Latency is 8-23, pick the worst case.
+let Latency = 23, ReleaseAtCycles = [1, 11] in {
+ def : WriteRes<WriteFRECIP, [LA464FPU0, LA464FDiv]>;
+}
+// Latency is 8-22, pick the worst case.
+let Latency = 22, ReleaseAtCycles = [1, 10] in {
+ def : WriteRes<WriteFSQRT32, [LA464FPU0, LA464FDiv]>;
+}
+// Latency is 8-36, pick the worst case.
+let Latency = 36, ReleaseAtCycles = [1, 18] in {
+ def : WriteRes<WriteFSQRT, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadFSQRT32, 0>;
+def : ReadAdvance<ReadFSQRT, 0>;
+def : ReadAdvance<ReadFRECIP32, 0>;
+def : ReadAdvance<ReadFRECIP, 0>;
+// Latency is 11-33, pick the worst case.
+let Latency = 33, ReleaseAtCycles = [1, 16] in {
+ def : WriteRes<WriteFRSQRT32, [LA464FPU0, LA464FDiv]>;
+}
+// Latency is 11-54, pick the worst case.
+let Latency = 54, ReleaseAtCycles = [1, 27] in {
+ def : WriteRes<WriteFRSQRT, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadFRSQRT32, 0>;
+def : ReadAdvance<ReadFRSQRT, 0>;
+
+// Floating-point instruction latency FCVT FSEL
+let Latency = 2 in {
+ def : WriteRes<WriteFCvtStoD, [LA464FPU]>;
+ def : WriteRes<WriteFCvtDtoS, [LA464FPU]>;
+}
+let Latency = 4 in {
+ def : WriteRes<WriteFCvtStoW, [LA464FPU]>;
+ def : WriteRes<WriteFCvtStoL, [LA464FPU]>;
+ def : WriteRes<WriteFCvtDtoW, [LA464FPU]>;
+ def : WriteRes<WriteFCvtDtoL, [LA464FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS, [LA464FPU]>;
+ def : WriteRes<WriteFCvtWtoD, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoS, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoD, [LA464FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RM, [LA464FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RM, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RM, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RM, [LA464FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RP, [LA464FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RP, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RP, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RP, [LA464FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RZ, [LA464FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RZ, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RZ, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RZ, [LA464FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RNE, [LA464FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RNE, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RNE, [LA464FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RNE, [LA464FPU]>;
+
+ def : WriteRes<WriteFCvtFStoIS, [LA464FPU]>;
+ def : WriteRes<WriteFCvtFDtoID, [LA464FPU]>;
+}
+def : ReadAdvance<ReadFCvtStoD, 0>;
+def : ReadAdvance<ReadFCvtDtoS, 0>;
+
+def : ReadAdvance<ReadFCvtStoW, 0>;
+def : ReadAdvance<ReadFCvtStoL, 0>;
+def : ReadAdvance<ReadFCvtDtoW, 0>;
+def : ReadAdvance<ReadFCvtDtoL, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS, 0>;
+def : ReadAdvance<ReadFCvtWtoD, 0>;
+def : ReadAdvance<ReadFCvtLtoS, 0>;
+def : ReadAdvance<ReadFCvtLtoD, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RM, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RM, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RM, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RM, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RP, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RP, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RP, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RP, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RZ, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RZ, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RZ, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RZ, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RNE, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RNE, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RNE, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RNE, 0>;
+
+def : ReadAdvance<ReadFCvtFStoIS, 0>;
+def : ReadAdvance<ReadFCvtFDtoID, 0>;
+
+def : WriteRes<WriteFSEL, [LA464FMov]>;
+def : ReadAdvance<ReadFSEL, 0>;
+
+// Floating-point instruction latency FMOV
+def : WriteRes<WriteFMovS, [LA464FPU]>;
+def : WriteRes<WriteFMovD, [LA464FPU]>;
+def : WriteRes<WriteFMoveFRtoCF, [LA464FPU]>;
+def : WriteRes<WriteFMoveCFtoFR, [LA464FPU]>;
+
+def : ReadAdvance<ReadFMovS, 0>;
+def : ReadAdvance<ReadFMovD, 0>;
+def : ReadAdvance<ReadFMoveFRtoCF, 0>;
+def : ReadAdvance<ReadFMoveCFtoFR, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteFMovGRtoFRW, [LA464FMov]>;
+ def : WriteRes<WriteFMovGRtoFRD, [LA464FMov]>;
+ def : WriteRes<WriteFMovFRtoGRS, [LA464FMov]>;
+ def : WriteRes<WriteFMovFRHtoGRS, [LA464FMov]>;
+ def : WriteRes<WriteFMovFRtoGRD, [LA464FMov]>;
+}
+let Latency = 3 in {
+ def : WriteRes<WriteFMovGRtoFRHW, [LA464FMov]>;
+}
+def : ReadAdvance<ReadFMovGRtoFRW, 0>;
+def : ReadAdvance<ReadFMovGRtoFRHW, 0>;
+def : ReadAdvance<ReadFMovGRtoFRD, 0>;
+def : ReadAdvance<ReadFMovFRtoGRS, 0>;
+def : ReadAdvance<ReadFMovFRHtoGRS, 0>;
+def : ReadAdvance<ReadFMovFRtoGRD, 0>;
+let Latency = 7, ReleaseAtCycles = [6] in {
+ def : WriteRes<WriteFMoveCFtoGR, [LA464FMov]>;
+}
+let Latency = 15, ReleaseAtCycles = [14] in {
+ def : WriteRes<WriteFMoveGRtoCF, [LA464FMov]>;
+}
+def : ReadAdvance<ReadFMoveCFtoGR, 0>;
+def : ReadAdvance<ReadFMoveGRtoCF, 0>;
+let Latency = 7, ReleaseAtCycles = [6] in {
+ def : WriteRes<WriteFMovFCSRtoGR, [LA464FMov]>;
+}
+def : ReadAdvance<ReadFMovFCSRtoGR, 0>;
+let Latency = 15, ReleaseAtCycles = [14] in {
+ def : WriteRes<WriteFMovGRtoFCSR, [LA464FMov]>;
+}
+def : ReadAdvance<ReadFMovGRtoFCSR, 0>;
+
+// Floating-point instruction latency FJUMP
+def : WriteRes<WriteFJump, [LA464Branch]>;
+
+def : ReadAdvance<ReadFJump, 0>;
+
+// Floating-point instruction latency FLD FST FLDX FSTX
+let Latency = 5 in {
+ def : WriteRes<WriteFLD, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteFST, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteFLDX, [LA464AGU0, LA464Load]>;
+ def : WriteRes<WriteFSTX, [LA464AGU0, LA464Store]>;
+}
+def : ReadAdvance<ReadFSTData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFMemOffset, 0>;
+
+// Floating-point instruction latency FLDGT FLDLE FSTGT FSTLE
+let Latency = 5 in {
+ def : WriteRes<WriteFLDGT, [LA464AGU0, LA464Load, LA464FPU]>;
+ def : WriteRes<WriteFLDLE, [LA464AGU0, LA464Load, LA464FPU]>;
+ def : WriteRes<WriteFSTGT, [LA464AGU0, LA464Store, LA464FPU]>;
+ def : WriteRes<WriteFSTLE, [LA464AGU0, LA464Store, LA464FPU]>;
+}
+def : ReadAdvance<ReadFMemCmp, 0>;
+
+// Integer instruction latency PCADD
+def : WriteRes<WriteIPCAdd, [LA464AGU]>;
+
+def : ReadAdvance<ReadIPCAdd, 0>;
+
+//===----------------------------------------------------------------------===//
+
+// Vector instruction - LSX / LASX
+//
+// Vector integer arithmetic, default latency is 1.
+def : WriteRes<WriteVALU128, [LA464FPU]>;
+def : WriteRes<WriteVALU256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVALU128, 0>;
+def : ReadAdvance<ReadVALU256, 0>;
+
+let Latency = 3 in {
+ def : WriteRes<WriteVALUQ128, [LA464FPU]>;
+ def : WriteRes<WriteVALUQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVALUQ128, 0>;
+def : ReadAdvance<ReadVALUQ256, 0>;
+
+def : WriteRes<WriteVAVG128, [LA464FPU]>;
+def : WriteRes<WriteVAVG256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVAVG128, 0>;
+def : ReadAdvance<ReadVAVG256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVAVGD128, [LA464FPU]>;
+ def : WriteRes<WriteVAVGD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVAVGD128, 0>;
+def : ReadAdvance<ReadVAVGD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVABSD128, [LA464FPU]>;
+ def : WriteRes<WriteVABSD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVABSD128, 0>;
+def : ReadAdvance<ReadVABSD256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVADDA128, [LA464FPU]>;
+ def : WriteRes<WriteVADDA256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVADDA128, 0>;
+def : ReadAdvance<ReadVADDA256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVHADDW128, [LA464FPU]>;
+ def : WriteRes<WriteVHADDW256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVHADDW128, 0>;
+def : ReadAdvance<ReadVHADDW256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVHADDWQ128, [LA464FPU]>;
+ def : WriteRes<WriteVHADDWQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVHADDWQ128, 0>;
+def : ReadAdvance<ReadVHADDWQ256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVWADD128, [LA464FPU]>;
+ def : WriteRes<WriteVWADD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVWADD128, 0>;
+def : ReadAdvance<ReadVWADD256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVWADDQ128, [LA464FPU]>;
+ def : WriteRes<WriteVWADDQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVWADDQ128, 0>;
+def : ReadAdvance<ReadVWADDQ256, 0>;
+
+def : WriteRes<WriteVMINMAX128, [LA464FPU]>;
+def : WriteRes<WriteVMINMAX256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVMINMAX128, 0>;
+def : ReadAdvance<ReadVMINMAX256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVMINMAXD128, [LA464FPU]>;
+ def : WriteRes<WriteVMINMAXD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVMINMAXD128, 0>;
+def : ReadAdvance<ReadVMINMAXD256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVMUL128, [LA464FPU]>;
+ def : WriteRes<WriteVMUL256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVMUL128, 0>;
+def : ReadAdvance<ReadVMUL256, 0>;
+let Latency = 7 in {
+ def : WriteRes<WriteVMULQ128, [LA464FPU]>;
+ def : WriteRes<WriteVMULQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVMULQ128, 0>;
+def : ReadAdvance<ReadVMULQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVMADD128, [LA464FPU]>;
+ def : WriteRes<WriteVMADD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVMADD128, 0>;
+def : ReadAdvance<ReadVMADD256, 0>;
+let Latency = 7 in {
+ def : WriteRes<WriteVMADDQ128, [LA464FPU]>;
+ def : WriteRes<WriteVMADDQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVMADDQ128, 0>;
+def : ReadAdvance<ReadVMADDQ256, 0>;
+// VMOD is slower than VDIV on LA464 and shares the same class.
+// Latency is 26-63 and throughput is 0.029-0.067, pick the worst case.
+let Latency = 63, ReleaseAtCycles = [1, 33] in {
+ def : WriteRes<WriteVDIVB128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVDIVB256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVDIVB128, 0>;
+def : ReadAdvance<ReadVDIVB256, 0>;
+// Latency is 15-41 and throughput is 0.043-0.111, pick the worst case.
+let Latency = 41, ReleaseAtCycles = [1, 22] in {
+ def : WriteRes<WriteVDIVH128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVDIVH256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVDIVH128, 0>;
+def : ReadAdvance<ReadVDIVH256, 0>;
+// Latency is 10-30 and throughput is 0.059-0.167, pick the worst case.
+let Latency = 30, ReleaseAtCycles = [1, 16] in {
+ def : WriteRes<WriteVDIVW128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVDIVW256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVDIVW128, 0>;
+def : ReadAdvance<ReadVDIVW256, 0>;
+// Latency is 7-25 and throughput is 0.071-0.222, pick the worst case.
+let Latency = 25, ReleaseAtCycles = [1, 13] in {
+ def : WriteRes<WriteVDIVD128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVDIVD256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVDIVD128, 0>;
+def : ReadAdvance<ReadVDIVD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSAT128, [LA464FPU]>;
+ def : WriteRes<WriteVSAT256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSAT128, 0>;
+def : ReadAdvance<ReadVSAT256, 0>;
+
+def : WriteRes<WriteVSIGNCOV128, [LA464FPU]>;
+def : WriteRes<WriteVSIGNCOV256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVSIGNCOV128, 0>;
+def : ReadAdvance<ReadVSIGNCOV256, 0>;
+
+def : WriteRes<WriteVEXTH128, [LA464FPU]>;
+def : WriteRes<WriteVEXTH256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVEXTH128, 0>;
+def : ReadAdvance<ReadVEXTH256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVEXT2XV256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVEXT2XV256, 0>;
+
+def : WriteRes<WriteVEXTL128, [LA464FPU]>;
+def : WriteRes<WriteVEXTL256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVEXTL128, 0>;
+def : ReadAdvance<ReadVEXTL256, 0>;
+
+def : WriteRes<WriteVLDI128, [LA464FPU]>;
+def : WriteRes<WriteVLDI256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVLDI128, 0>;
+def : ReadAdvance<ReadVLDI256, 0>;
+
+//
+// Vector compare, mask and condition flag
+def : WriteRes<WriteVCMP128, [LA464FPU]>;
+def : WriteRes<WriteVCMP256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVCMP128, 0>;
+def : ReadAdvance<ReadVCMP256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVCMPD128, [LA464FPU]>;
+ def : WriteRes<WriteVCMPD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVCMPD128, 0>;
+def : ReadAdvance<ReadVCMPD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFCMP128, [LA464FPU]>;
+ def : WriteRes<WriteVFCMP256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFCMP128, 0>;
+def : ReadAdvance<ReadVFCMP256, 0>;
+
+def : WriteRes<WriteVMSK128, [LA464FPU]>;
+def : WriteRes<WriteVMSK256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVMSK128, 0>;
+def : ReadAdvance<ReadVMSK256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSET128, [LA464FPU]>;
+}
+let Latency = 4 in {
+ def : WriteRes<WriteVSET256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSET128, 0>;
+def : ReadAdvance<ReadVSET256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFRSTP128, [LA464FPU]>;
+ def : WriteRes<WriteVFRSTP256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFRSTP128, 0>;
+def : ReadAdvance<ReadVFRSTP256, 0>;
+
+//
+// Vector bit manipulation
+def : WriteRes<WriteVBIT128, [LA464FPU]>;
+def : WriteRes<WriteVBIT256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVBIT128, 0>;
+def : ReadAdvance<ReadVBIT256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVBITOPS128, [LA464FPU]>;
+ def : WriteRes<WriteVBITOPS256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVBITOPS128, 0>;
+def : ReadAdvance<ReadVBITOPS256, 0>;
+
+def : WriteRes<WriteVBITSEL128, [LA464FPU]>;
+def : WriteRes<WriteVBITSEL256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVBITSEL128, 0>;
+def : ReadAdvance<ReadVBITSEL256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVPCNT128, [LA464FPU]>;
+ def : WriteRes<WriteVPCNT256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVPCNT128, 0>;
+def : ReadAdvance<ReadVPCNT256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVCL128, [LA464FPU]>;
+ def : WriteRes<WriteVCL256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVCL128, 0>;
+def : ReadAdvance<ReadVCL256, 0>;
+
+//
+// Vector shift
+def : WriteRes<WriteVSHIFT128, [LA464FPU]>;
+def : WriteRes<WriteVSHIFT256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVSHIFT128, 0>;
+def : ReadAdvance<ReadVSHIFT256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVROTR128, [LA464FPU]>;
+ def : WriteRes<WriteVROTR256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVROTR128, 0>;
+def : ReadAdvance<ReadVROTR256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTR128, [LA464FPU]>;
+ def : WriteRes<WriteVSHIFTR256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSHIFTR128, 0>;
+def : ReadAdvance<ReadVSHIFTR256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSLLWIL128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSLLWIL256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSLLWIL128, 0>;
+def : ReadAdvance<ReadVSLLWIL256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSHIFTN128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTN256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTN128, 0>;
+def : ReadAdvance<ReadVSHIFTN256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTNI128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTNI256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTNI128, 0>;
+def : ReadAdvance<ReadVSHIFTNI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTNIQ128, [LA464FPU]>;
+ def : WriteRes<WriteVSHIFTNIQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSHIFTNIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTNIQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRN128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTRN256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTRN128, 0>;
+def : ReadAdvance<ReadVSHIFTRN256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRNI128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTRNI256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTRNI128, 0>;
+def : ReadAdvance<ReadVSHIFTRNI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTRNIQ128, [LA464FPU]>;
+ def : WriteRes<WriteVSHIFTRNIQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSHIFTRNIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTRNIQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTNS128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTNS256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTNS128, 0>;
+def : ReadAdvance<ReadVSHIFTNS256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTNSI128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTNSI256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTNSI128, 0>;
+def : ReadAdvance<ReadVSHIFTNSI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTNSIQ128, [LA464FPU]>;
+ def : WriteRes<WriteVSHIFTNSIQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSHIFTNSIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTNSIQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRNS128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTRNS256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTRNS128, 0>;
+def : ReadAdvance<ReadVSHIFTRNS256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRNSI128, [LA464VNarrow]>;
+ def : WriteRes<WriteVSHIFTRNSI256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVSHIFTRNSI128, 0>;
+def : ReadAdvance<ReadVSHIFTRNSI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTRNSIQ128, [LA464FPU]>;
+ def : WriteRes<WriteVSHIFTRNSIQ256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVSHIFTRNSIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTRNSIQ256, 0>;
+
+//
+// Vector shuffle, permute and element move
+def : WriteRes<WriteVPACK128, [LA464FPU]>;
+def : WriteRes<WriteVPACK256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVPACK128, 0>;
+def : ReadAdvance<ReadVPACK256, 0>;
+
+def : WriteRes<WriteVSHUF128, [LA464FPU]>;
+def : WriteRes<WriteVSHUF256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVSHUF128, 0>;
+def : ReadAdvance<ReadVSHUF256, 0>;
+
+def : WriteRes<WriteVSHUF4I128, [LA464FPU]>;
+def : WriteRes<WriteVSHUF4I256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVSHUF4I128, 0>;
+def : ReadAdvance<ReadVSHUF4I256, 0>;
+
+def : WriteRes<WriteVHSELI256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVHSELI256, 0>;
+
+def : WriteRes<WriteVPERMI128, [LA464FPU]>;
+def : WriteRes<WriteVPERMI256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVPERMI128, 0>;
+def : ReadAdvance<ReadVPERMI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVPERM256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVPERM256, 0>;
+
+def : WriteRes<WriteVEXTRINS128, [LA464FPU]>;
+def : WriteRes<WriteVEXTRINS256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVEXTRINS128, 0>;
+def : ReadAdvance<ReadVEXTRINS256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVPICKVE256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVPICKVE256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVINSVE0256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVINSVE0256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVREPLVE0256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVREPLVE0256, 0>;
+
+def : WriteRes<WriteVREPLVEI128, [LA464FPU]>;
+def : WriteRes<WriteVREPLVEI256, [LA464FPU]>;
+
+def : ReadAdvance<ReadVREPLVEI128, 0>;
+def : ReadAdvance<ReadVREPLVEI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVREPLVE128, [LA464FMov]>;
+ def : WriteRes<WriteVREPLVE256, [LA464FMov]>;
+}
+def : ReadAdvance<ReadVREPLVE128, 0>;
+def : ReadAdvance<ReadVREPLVE256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVREPLGR2VR128, [LA464FMov]>;
+ def : WriteRes<WriteVREPLGR2VR256, [LA464FMov]>;
+}
+def : ReadAdvance<ReadVREPLGR2VR128, 0>;
+def : ReadAdvance<ReadVREPLGR2VR256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVREPLGR2VRWD128, [LA464FMov]>;
+ def : WriteRes<WriteVREPLGR2VRWD256, [LA464FMov]>;
+}
+def : ReadAdvance<ReadVREPLGR2VRWD128, 0>;
+def : ReadAdvance<ReadVREPLGR2VRWD256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVINSGR2VR128, [LA464FMov]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVINSGR2VR256, [LA464FMov]>;
+}
+def : ReadAdvance<ReadVINSGR2VR128, 0>;
+def : ReadAdvance<ReadVINSGR2VR256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVPICKVE2GR128, [LA464FMov]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVPICKVE2GR256, [LA464FMov]>;
+}
+def : ReadAdvance<ReadVPICKVE2GR128, 0>;
+def : ReadAdvance<ReadVPICKVE2GR256, 0>;
+
+//
+// Vector floating-point arithmetic
+let Latency = 5 in {
+ def : WriteRes<WriteVFADD128, [LA464FPU]>;
+ def : WriteRes<WriteVFADD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFADD128, 0>;
+def : ReadAdvance<ReadVFADD256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFMUL128, [LA464FPU]>;
+ def : WriteRes<WriteVFMUL256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFMUL128, 0>;
+def : ReadAdvance<ReadVFMUL256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFMADD128, [LA464FPU]>;
+ def : WriteRes<WriteVFMADD256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFMADD128, 0>;
+def : ReadAdvance<ReadVFMADD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFMINMAX128, [LA464FPU]>;
+ def : WriteRes<WriteVFMINMAX256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFMINMAX128, 0>;
+def : ReadAdvance<ReadVFMINMAX256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFCLASS128, [LA464FPU]>;
+ def : WriteRes<WriteVFCLASS256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFCLASS128, 0>;
+def : ReadAdvance<ReadVFCLASS256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFLOGB128, [LA464FPU]>;
+ def : WriteRes<WriteVFLOGB256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFLOGB128, 0>;
+def : ReadAdvance<ReadVFLOGB256, 0>;
+// Latency is 9-24 and throughput is 0.0714-0.167, pick the worst case.
+let Latency = 24, ReleaseAtCycles = [1, 13] in {
+ def : WriteRes<WriteVFDIVS128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFDIVS256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFDIVS128, 0>;
+def : ReadAdvance<ReadVFDIVS256, 0>;
+// Latency is 6-20 and throughput is 0.0833-0.222, pick the worst case.
+let Latency = 20, ReleaseAtCycles = [1, 11] in {
+ def : WriteRes<WriteVFDIVD128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFDIVD256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFDIVD128, 0>;
+def : ReadAdvance<ReadVFDIVD256, 0>;
+// Latency is 11-39 and throughput is 0.05-0.167, pick the worst case.
+let Latency = 39, ReleaseAtCycles = [1, 19] in {
+ def : WriteRes<WriteVFSQRTS128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFSQRTS256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFSQRTS128, 0>;
+def : ReadAdvance<ReadVFSQRTS256, 0>;
+// Latency is 8-36 and throughput is 0.054-0.222, pick the worst case.
+let Latency = 36, ReleaseAtCycles = [1, 18] in {
+ def : WriteRes<WriteVFSQRTD128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFSQRTD256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFSQRTD128, 0>;
+def : ReadAdvance<ReadVFSQRTD256, 0>;
+// Latency is 11-27 and throughput is 0.071-0.167, pick the worst case.
+let Latency = 27, ReleaseAtCycles = [1, 13] in {
+ def : WriteRes<WriteVFRECIPS128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFRECIPS256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFRECIPS128, 0>;
+def : ReadAdvance<ReadVFRECIPS256, 0>;
+// Latency is 8-23 and throughput is 0.083-0.222, pick the worst case.
+let Latency = 23, ReleaseAtCycles = [1, 11] in {
+ def : WriteRes<WriteVFRECIPD128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFRECIPD256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFRECIPD128, 0>;
+def : ReadAdvance<ReadVFRECIPD256, 0>;
+// Latency is 17-61 and throughput is 0.032-0.111, pick the worst case.
+let Latency = 61, ReleaseAtCycles = [1, 30] in {
+ def : WriteRes<WriteVFRSQRTS128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFRSQRTS256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFRSQRTS128, 0>;
+def : ReadAdvance<ReadVFRSQRTS256, 0>;
+// Latency is 11-54 and throughput is 0.036-0.167, pick the worst case.
+let Latency = 54, ReleaseAtCycles = [1, 27] in {
+ def : WriteRes<WriteVFRSQRTD128, [LA464FPU0, LA464FDiv]>;
+ def : WriteRes<WriteVFRSQRTD256, [LA464FPU0, LA464FDiv]>;
+}
+def : ReadAdvance<ReadVFRSQRTD128, 0>;
+def : ReadAdvance<ReadVFRSQRTD256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFRINT128, [LA464FPU]>;
+ def : WriteRes<WriteVFRINT256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFRINT128, 0>;
+def : ReadAdvance<ReadVFRINT256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVFCVT128, [LA464VNarrow]>;
+ def : WriteRes<WriteVFCVT256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVFCVT128, 0>;
+def : ReadAdvance<ReadVFCVT256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFTINT128, [LA464FPU]>;
+ def : WriteRes<WriteVFTINT256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFTINT128, 0>;
+def : ReadAdvance<ReadVFTINT256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFTINTX128, [LA464VNarrow]>;
+ def : WriteRes<WriteVFTINTX256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVFTINTX128, 0>;
+def : ReadAdvance<ReadVFTINTX256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFFINT128, [LA464FPU]>;
+ def : WriteRes<WriteVFFINT256, [LA464FPU]>;
+}
+def : ReadAdvance<ReadVFFINT128, 0>;
+def : ReadAdvance<ReadVFFINT256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFFINTX128, [LA464VNarrow]>;
+ def : WriteRes<WriteVFFINTX256, [LA464VNarrow]>;
+}
+def : ReadAdvance<ReadVFFINTX128, 0>;
+def : ReadAdvance<ReadVFFINTX256, 0>;
+
+//
+// Vector memory access
+let Latency = 5 in {
+ def : WriteRes<WriteVLD128, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteVLD256, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteVLDX128, [LA464AGU0, LA464Load]>;
+ def : WriteRes<WriteVLDX256, [LA464AGU0, LA464Load]>;
+ def : WriteRes<WriteVLDREPL128, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteVLDREPL256, [LA464AGU, LA464Load]>;
+ def : WriteRes<WriteVST128, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteVST256, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteVSTX128, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteVSTX256, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteVSTELM128, [LA464AGU0, LA464Store]>;
+ def : WriteRes<WriteVSTELM256, [LA464AGU0, LA464Store]>;
+}
+
+// Vector memory access operands
+def : ReadAdvance<ReadVSTData128, 0>;
+def : ReadAdvance<ReadVMemBase128, 0>;
+def : ReadAdvance<ReadVMemOffset128, 0>;
+def : ReadAdvance<ReadVSTData256, 0>;
+def : ReadAdvance<ReadVMemBase256, 0>;
+def : ReadAdvance<ReadVMemOffset256, 0>;
+
+// FRECIPE / FRSQRTE are only implemented by LA664.
+let Unsupported = true in {
+ def : WriteRes<WriteFRECIPE, []>;
+ def : ReadAdvance<ReadFRECIPE, 0>;
+ def : WriteRes<WriteFRSQRTE, []>;
+ def : ReadAdvance<ReadFRSQRTE, 0>;
+ def : WriteRes<WriteVFRECIPE128, []>;
+ def : ReadAdvance<ReadVFRECIPE128, 0>;
+ def : WriteRes<WriteVFRECIPE256, []>;
+ def : ReadAdvance<ReadVFRECIPE256, 0>;
+ def : WriteRes<WriteVFRSQRTE128, []>;
+ def : ReadAdvance<ReadVFRSQRTE128, 0>;
+ def : WriteRes<WriteVFRSQRTE256, []>;
+ def : ReadAdvance<ReadVFRSQRTE256, 0>;
+}
+
+let Unsupported = true in {
+ def : WriteRes<WriteAtomic, []>;
+ def : ReadAdvance<ReadAtomic, 0>;
+}
+
+let Unsupported = true in {
+ def : WriteRes<WritePseudo, []>;
+ def : ReadAdvance<ReadPseudo, 0>;
+}
+
+let Unsupported = true in {
+ def : WriteRes<WriteOthers, []>;
+ def : ReadAdvance<ReadOthers, 0>;
+}
+
+} // SchedModel
diff --git a/llvm/lib/Target/LoongArch/LoongArchSchedLA664.td b/llvm/lib/Target/LoongArch/LoongArchSchedLA664.td
new file mode 100644
index 0000000000000..80a795888c060
--- /dev/null
+++ b/llvm/lib/Target/LoongArch/LoongArchSchedLA664.td
@@ -0,0 +1,1138 @@
+//==- LoongArchSchedLA664.td - LA664 Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for LA664 to support instruction
+// scheduling and other instruction cost heuristics.
+// Based on:
+// * Loongson 3A6000: A Star among Chinese CPUs, by Chips and Cheese
+// https://chipsandcheese.com/p/loongson-3a6000-a-star-among-chinese-cpus/
+// * Loongson-3A6000 instruction latency and throughput document, V0.1,
+// 2024/07/24, Loongson Technology. Where the two sources disagree, the
+// measured latency and throughput of the document is used, e.g. it reports
+// two FMA operations per cycle instead of one.
+//===----------------------------------------------------------------------===//
+
+def LA664Model : SchedMachineModel {
+ let IssueWidth = 6; // 6-way decode and dispatch
+ let MicroOpBufferSize = 256; // Reorder Buffer size
+ let LoadLatency = 4;
+ let MispredictPenalty = 14; // Estimated value
+ let CompleteModel = 0;
+}
+
+let SchedModel = LA664Model in {
+// Integer Execution Unit
+//
+// Execution Pipes
+def LA664ALU0 : ProcResource<1>; // ALU, MUL, Branch
+def LA664ALU1 : ProcResource<1>; // ALU, MUL, Branch
+def LA664ALU2 : ProcResource<1>; // ALU
+def LA664ALU3 : ProcResource<1>; // ALU
+
+def LA664AGU0 : ProcResource<1>; // Load
+def LA664AGU1 : ProcResource<1>; // Load
+def LA664AGU2 : ProcResource<1>; // Store
+def LA664AGU3 : ProcResource<1>; // Store
+
+// Execution Units
+//
+// Integer division issued on port 0. (Estimiated)
+def LA664Div : ProcResource<1>;
+
+// ALU0 and ALU1 additionally have branch execution capability.
+defvar LA664Branch0 = LA664ALU0;
+defvar LA664Branch1 = LA664ALU1;
+
+// ALU0 and ALU1 have Integer multiplication execution capability.
+defvar LA664Mul0 = LA664ALU0;
+defvar LA664Mul1 = LA664ALU1;
+
+defvar LA664LoadAGU0 = LA664AGU0;
+defvar LA664LoadAGU1 = LA664AGU1;
+defvar LA664StoreAGU0 = LA664AGU2;
+defvar LA664StoreAGU1 = LA664AGU3;
+
+// Execution pipeline grouping
+//
+def LA664Branch : ProcResGroup<[LA664Branch0, LA664Branch1]>;
+def LA664Mul: ProcResGroup<[LA664Mul0, LA664Mul1]>;
+def LA664LoadAGU : ProcResGroup<[LA664LoadAGU0, LA664LoadAGU1]>;
+def LA664StoreAGU : ProcResGroup<[LA664StoreAGU0, LA664StoreAGU1]>;
+
+// Scheduling
+//
+// LA664 has an unified 48 entry Integer scheduler
+def LA664ALU : ProcResGroup<[LA664ALU0, LA664ALU1, LA664ALU2, LA664ALU3]> {
+ let BufferSize=48;
+}
+
+// LA664 has an unified 48 entry AGU scheduler
+def LA664AGU : ProcResGroup<[LA664AGU0, LA664AGU1, LA664AGU2, LA664AGU3]> {
+ let BufferSize=48;
+}
+
+// Floating-Point / Vector Unit
+//
+// Execution pipes
+// There are four floating point/vector execution pipes.
+def LA664FPU0 : ProcResource<1>; // FALU, FMUL, FMA, FDIV, FMOV, VALU, VFPU
+def LA664FPU1 : ProcResource<1>; // FALU, FMUL, FMA, VALU, VFPU
+def LA664FPU2 : ProcResource<1>; // FALU, VALU, VMUL
+def LA664FPU3 : ProcResource<1>; // FALU, VALU, VMUL
+
+// Execution Units
+//
+// FPU0 and FPU1 have float multiplication execution capability. They also
+// execute the vector floating-point operations that are limited to two per
+// cycle, e.g. VFMUL, VFRINT, VFCVT and the resizing VFTINT / VFFINT
+// conversions.
+defvar LA664FMul0 = LA664FPU0;
+defvar LA664FMul1 = LA664FPU1;
+
+// FP division/sqrt on port 0. (Estimated)
+// It also executes the vector divide, square root and reciprocal operations.
+def LA664FDiv : ProcResource<1>;
+
+// Only FPU0 has float move execution capability. (Estimated)
+// It also executes the vector operations that move data between a general
+// purpose register and a vector register, which are limited to one per cycle.
+defvar LA664FMov = LA664FPU0;
+
+// FPU0 and FPU1 have float FMA execution capability. (Estimated)
+// They also execute the vector floating-point FMA operations.
+defvar LA664FMA0 = LA664FPU0;
+defvar LA664FMA1 = LA664FPU1;
+
+// FPU0 and FPU1 have float compare execution capability. (Estimated)
+defvar LA664FCmp0 = LA664FPU0;
+defvar LA664FCmp1 = LA664FPU1;
+
+// FPU2 and FPU3 have vector integer multiplication execution capability. They
+// also execute the other vector integer operations that are limited to two
+// per cycle, e.g. VBITCLR, VPCNT, VSHUF and the narrowing shifts. (Estimated)
+defvar LA664VMul0 = LA664FPU2;
+defvar LA664VMul1 = LA664FPU3;
+
+// Execution pipeline grouping
+//
+// Floating-point multiplies appear to use different pipes than the vector
+// integer ones.
+def LA664FMul : ProcResGroup<[LA664FMul0, LA664FMul1]>;
+def LA664FMA : ProcResGroup<[LA664FMA0, LA664FMA1]>;
+def LA664FCmp : ProcResGroup<[LA664FCmp0, LA664FCmp1]>;
+def LA664VMul : ProcResGroup<[LA664VMul0, LA664VMul1]>;
+
+// Scheduling
+//
+// LA664 has an unified 48 entry vector/fp scheduler.
+// All four pipes execute the operations that reach a throughput of four per
+// cycle, which covers both the scalar floating-point ones and the 128-bit /
+// 256-bit vector ones.
+def LA664FPU : ProcResGroup<[LA664FPU0, LA664FPU1, LA664FPU2, LA664FPU3]> {
+ let BufferSize=48;
+}
+
+// Load-Store Unit
+//
+// The LS unit contains four pipelines, two for load and two for store.
+// LA664 can handle two 256-bit vector accesses per cycle.
+// These can be any combination of loads and stores.
+def LA664Load : ProcResource<2> {
+ // The LS unit utilizes a 80-entry load queue (LDQ).
+ let BufferSize = 80;
+}
+
+def LA664Store : ProcResource<2> {
+ // The LS unit utilizes a 64-entry store queue (STQ).
+ let BufferSize = 64;
+}
+
+//===----------------------------------------------------------------------===//
+
+// Base Instruction
+// Integer arithmetic and logic, default latency is 1
+def : WriteRes<WriteIALU, [LA664ALU]>;
+def : WriteRes<WriteIALU32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+
+// Integer instruction latency ALSL
+def : WriteRes<WriteIALSL, [LA664ALU]>;
+def : WriteRes<WriteIALSL32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIALSL, 0>;
+def : ReadAdvance<ReadIALSL32, 0>;
+
+// Integer instruction latency MUL
+let Latency = 4 in {
+ def : WriteRes<WriteIMUL, [LA664Mul]>;
+ def : WriteRes<WriteIMUL32, [LA664Mul]>;
+}
+def : ReadAdvance<ReadIMUL, 0>;
+def : ReadAdvance<ReadIMUL32, 0>;
+
+// Integer instruction latency DIV
+// Latency 4-19, pick the worst case.
+let Latency = 19, ReleaseAtCycles = [1,12] in {
+ def : WriteRes<WriteIDIV32, [LA664ALU0, LA664Div]>;
+}
+// Latency 4-32, pick the worst case.
+let Latency = 32, ReleaseAtCycles = [1,19] in {
+ def : WriteRes<WriteIDIV, [LA664ALU0, LA664Div]>;
+}
+def : ReadAdvance<ReadIDIV, 0>;
+def : ReadAdvance<ReadIDIV32, 0>;
+
+// Integer instruction latency SHIFT
+def : WriteRes<WriteIShift, [LA664ALU]>;
+def : WriteRes<WriteIShift32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIShift, 0>;
+def : ReadAdvance<ReadIShift32, 0>;
+
+// Integer instruction latency EXT
+def : WriteRes<WriteIEXT, [LA664ALU]>;
+
+def : ReadAdvance<ReadIEXT, 0>;
+
+// Integer instruction latency CLO / CLZ / CTO / CTZ
+def : WriteRes<WriteICL, [LA664ALU]>;
+def : WriteRes<WriteICL32, [LA664ALU]>;
+def : WriteRes<WriteICT, [LA664ALU]>;
+def : WriteRes<WriteICT32, [LA664ALU]>;
+
+def : ReadAdvance<ReadICL, 0>;
+def : ReadAdvance<ReadICL32, 0>;
+def : ReadAdvance<ReadICT, 0>;
+def : ReadAdvance<ReadICT32, 0>;
+
+// Integer instruction latency BytePick
+def : WriteRes<WriteIBytePick, [LA664ALU]>;
+def : WriteRes<WriteIBytePick32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIBytePick, 0>;
+def : ReadAdvance<ReadIBytePick32, 0>;
+
+// Integer instruction latency REV
+def : WriteRes<WriteIRev, [LA664ALU]>;
+def : WriteRes<WriteIRev32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIRev, 0>;
+def : ReadAdvance<ReadIRev32, 0>;
+
+// Integer instruction latency BitRev
+def : WriteRes<WriteIBitRev, [LA664ALU]>;
+def : WriteRes<WriteIBitRev32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIBitRev, 0>;
+def : ReadAdvance<ReadIBitRev32, 0>;
+
+// Integer instruction latency BSTRINS
+def : WriteRes<WriteIBstrins, [LA664ALU]>;
+def : WriteRes<WriteIBstrins32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIBstrins, 0>;
+def : ReadAdvance<ReadIBstrins32, 0>;
+
+// Integer instruction latency BSTRPICK
+def : WriteRes<WriteIBstrPick, [LA664ALU]>;
+def : WriteRes<WriteIBstrPick32, [LA664ALU]>;
+
+def : ReadAdvance<ReadIBstrPick, 0>;
+def : ReadAdvance<ReadIBstrPick32, 0>;
+
+// Integer instruction latency SELECT
+def : WriteRes<WriteIMASK, [LA664ALU]>;
+
+def : ReadAdvance<ReadIMASK, 0>;
+
+// Integer instruction latency Jump
+def : WriteRes<WriteIJump, [LA664Branch]>;
+
+def : ReadAdvance<ReadIJump, 0>;
+
+// Integer instruction latency LD ST LDX STX
+let Latency = 4 in {
+ def : WriteRes<WriteLD, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteST, [LA664StoreAGU, LA664Store]>;
+ def : WriteRes<WriteLDX, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteSTX, [LA664StoreAGU, LA664Store]>;
+}
+def : ReadAdvance<ReadSTData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadMemOffset, 0>;
+
+// Integer instruction latency LDPTR STPTR
+let Latency = 4 in {
+ def : WriteRes<WriteLDPTR, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteSTPTR, [LA664StoreAGU, LA664Store]>;
+}
+
+// Integer instruction latency LDGT LDLE STGT STLE
+let Latency = 4 in {
+ def : WriteRes<WriteLDGT, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteLDLE, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteSTGT, [LA664StoreAGU, LA664Store]>;
+ def : WriteRes<WriteSTLE, [LA664StoreAGU, LA664Store]>;
+}
+def : ReadAdvance<ReadMemCmp, 0>;
+
+// Floating-point instruction latency FADD FSUB FMUL FDIV FMADD FMINMAX
+let Latency = 3 in {
+ def : WriteRes<WriteFADD, [LA664FPU]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteFMUL, [LA664FMul]>;
+ def : WriteRes<WriteFMADD, [LA664FMA]>;
+}
+let Latency = 2 in {
+ def : WriteRes<WriteFMinMax, [LA664FPU]>;
+}
+def : ReadAdvance<ReadFADD, 0>;
+def : ReadAdvance<ReadFMUL, 0>;
+def : ReadAdvance<ReadFMADD, 0>;
+def : ReadAdvance<ReadFMinMax, 0>;
+// Latency is 6-13, pick the worst case.
+let Latency = 13, ReleaseAtCycles = [1, 3] in {
+ def : WriteRes<WriteFDIV32, [LA664FPU0, LA664FDiv]>;
+}
+// Latency is 6-19, pick the worst case.
+let Latency = 19, ReleaseAtCycles = [1, 4] in {
+ def : WriteRes<WriteFDIV, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadFDIV32, 0>;
+def : ReadAdvance<ReadFDIV, 0>;
+
+// Floating-point instruction latency FABS FNEG FSQRT FRECIP FRSQRT FSCALEB FLOGB FCOPYSIGN FCLASS FCMP
+def : WriteRes<WriteFABS, [LA664FPU]>;
+def : WriteRes<WriteFNEG, [LA664FPU]>;
+def : WriteRes<WriteFCOPYSIGN, [LA664FPU]>;
+let Latency = 2 in {
+ def : WriteRes<WriteFCLASS, [LA664FPU]>;
+ def : WriteRes<WriteFCMP, [LA664FCmp]>;
+}
+let Latency = 4 in {
+ def : WriteRes<WriteFSCALEB, [LA664FPU]>;
+ def : WriteRes<WriteFLOGB, [LA664FPU]>;
+}
+def : ReadAdvance<ReadFABS, 0>;
+def : ReadAdvance<ReadFNEG, 0>;
+def : ReadAdvance<ReadFSCALEB, 0>;
+def : ReadAdvance<ReadFLOGB, 0>;
+def : ReadAdvance<ReadFCOPYSIGN, 0>;
+def : ReadAdvance<ReadFCLASS, 0>;
+def : ReadAdvance<ReadFCMP, 0>;
+// Latency is 8-16, pick the worst case.
+let Latency = 16, ReleaseAtCycles = [1, 3] in {
+ def : WriteRes<WriteFRECIP32, [LA664FPU0, LA664FDiv]>;
+}
+// Latency is 8-23, pick the worst case.
+let Latency = 23, ReleaseAtCycles = [1, 4] in {
+ def : WriteRes<WriteFRECIP, [LA664FPU0, LA664FDiv]>;
+}
+// Latency is 8-22, pick the worst case.
+let Latency = 22, ReleaseAtCycles = [1, 4] in {
+ def : WriteRes<WriteFSQRT32, [LA664FPU0, LA664FDiv]>;
+}
+// Latency is 8-36, pick the worst case.
+let Latency = 36, ReleaseAtCycles = [1, 7] in {
+ def : WriteRes<WriteFSQRT, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadFSQRT32, 0>;
+def : ReadAdvance<ReadFSQRT, 0>;
+def : ReadAdvance<ReadFRECIP32, 0>;
+def : ReadAdvance<ReadFRECIP, 0>;
+// Latency is 11-33, pick the worst case.
+let Latency = 33, ReleaseAtCycles = [1, 7] in {
+ def : WriteRes<WriteFRSQRT32, [LA664FPU0, LA664FDiv]>;
+}
+// Latency is 11-54, pick the worst case.
+let Latency = 54, ReleaseAtCycles = [1, 12] in {
+ def : WriteRes<WriteFRSQRT, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadFRSQRT32, 0>;
+def : ReadAdvance<ReadFRSQRT, 0>;
+
+// Floating-point instruction latency FCVT FSEL
+let Latency = 2 in {
+ def : WriteRes<WriteFCvtStoD, [LA664FPU]>;
+ def : WriteRes<WriteFCvtDtoS, [LA664FPU]>;
+}
+let Latency = 4 in {
+ def : WriteRes<WriteFCvtStoW, [LA664FPU]>;
+ def : WriteRes<WriteFCvtStoL, [LA664FPU]>;
+ def : WriteRes<WriteFCvtDtoW, [LA664FPU]>;
+ def : WriteRes<WriteFCvtDtoL, [LA664FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS, [LA664FPU]>;
+ def : WriteRes<WriteFCvtWtoD, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoS, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoD, [LA664FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RM, [LA664FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RM, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RM, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RM, [LA664FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RP, [LA664FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RP, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RP, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RP, [LA664FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RZ, [LA664FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RZ, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RZ, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RZ, [LA664FPU]>;
+
+ def : WriteRes<WriteFCvtWtoS_RNE, [LA664FPU]>;
+ def : WriteRes<WriteFCvtWtoD_RNE, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoS_RNE, [LA664FPU]>;
+ def : WriteRes<WriteFCvtLtoD_RNE, [LA664FPU]>;
+
+ def : WriteRes<WriteFCvtFStoIS, [LA664FPU]>;
+ def : WriteRes<WriteFCvtFDtoID, [LA664FPU]>;
+}
+def : ReadAdvance<ReadFCvtStoD, 0>;
+def : ReadAdvance<ReadFCvtDtoS, 0>;
+
+def : ReadAdvance<ReadFCvtStoW, 0>;
+def : ReadAdvance<ReadFCvtStoL, 0>;
+def : ReadAdvance<ReadFCvtDtoW, 0>;
+def : ReadAdvance<ReadFCvtDtoL, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS, 0>;
+def : ReadAdvance<ReadFCvtWtoD, 0>;
+def : ReadAdvance<ReadFCvtLtoS, 0>;
+def : ReadAdvance<ReadFCvtLtoD, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RM, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RM, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RM, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RM, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RP, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RP, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RP, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RP, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RZ, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RZ, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RZ, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RZ, 0>;
+
+def : ReadAdvance<ReadFCvtWtoS_RNE, 0>;
+def : ReadAdvance<ReadFCvtWtoD_RNE, 0>;
+def : ReadAdvance<ReadFCvtLtoS_RNE, 0>;
+def : ReadAdvance<ReadFCvtLtoD_RNE, 0>;
+
+def : ReadAdvance<ReadFCvtFStoIS, 0>;
+def : ReadAdvance<ReadFCvtFDtoID, 0>;
+
+def : WriteRes<WriteFSEL, [LA664FCmp]>;
+def : ReadAdvance<ReadFSEL, 0>;
+
+// Floating-point instruction latency FMOV
+def : WriteRes<WriteFMovS, [LA664FPU]>;
+def : WriteRes<WriteFMovD, [LA664FPU]>;
+def : WriteRes<WriteFMoveFRtoCF, [LA664FCmp]>;
+def : WriteRes<WriteFMoveCFtoFR, [LA664FCmp]>;
+
+def : ReadAdvance<ReadFMovS, 0>;
+def : ReadAdvance<ReadFMovD, 0>;
+def : ReadAdvance<ReadFMoveFRtoCF, 0>;
+def : ReadAdvance<ReadFMoveCFtoFR, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteFMovGRtoFRW, [LA664FMov]>;
+ def : WriteRes<WriteFMovGRtoFRD, [LA664FMov]>;
+ def : WriteRes<WriteFMovFRtoGRS, [LA664FMov]>;
+ def : WriteRes<WriteFMovFRHtoGRS, [LA664FMov]>;
+ def : WriteRes<WriteFMovFRtoGRD, [LA664FMov]>;
+}
+let Latency = 3 in {
+ def : WriteRes<WriteFMovGRtoFRHW, [LA664FMov]>;
+}
+def : ReadAdvance<ReadFMovGRtoFRW, 0>;
+def : ReadAdvance<ReadFMovGRtoFRHW, 0>;
+def : ReadAdvance<ReadFMovGRtoFRD, 0>;
+def : ReadAdvance<ReadFMovFRtoGRS, 0>;
+def : ReadAdvance<ReadFMovFRHtoGRS, 0>;
+def : ReadAdvance<ReadFMovFRtoGRD, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteFMoveCFtoGR, [LA664FMov]>;
+ def : WriteRes<WriteFMoveGRtoCF, [LA664FMov]>;
+}
+def : ReadAdvance<ReadFMoveCFtoGR, 0>;
+def : ReadAdvance<ReadFMoveGRtoCF, 0>;
+let Latency = 7 in {
+ def : WriteRes<WriteFMovFCSRtoGR, [LA664FMov]>;
+}
+def : ReadAdvance<ReadFMovFCSRtoGR, 0>;
+let Latency = 15 in {
+ def : WriteRes<WriteFMovGRtoFCSR, [LA664FMov]>;
+}
+def : ReadAdvance<ReadFMovGRtoFCSR, 0>;
+
+// Floating-point instruction latency FJUMP
+def : WriteRes<WriteFJump, [LA664Branch]>;
+
+def : ReadAdvance<ReadFJump, 0>;
+
+// Floating-point instruction latency FLD FST FLDX FSTX
+let Latency = 5 in {
+ def : WriteRes<WriteFLD, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteFST, [LA664StoreAGU, LA664Store]>;
+ def : WriteRes<WriteFLDX, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteFSTX, [LA664StoreAGU, LA664Store]>;
+}
+def : ReadAdvance<ReadFSTData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFMemOffset, 0>;
+
+// Floating-point instruction latency FLDGT FLDLE FSTGT FSTLE
+let Latency = 5 in {
+ def : WriteRes<WriteFLDGT, [LA664LoadAGU, LA664Load, LA664FCmp]>;
+ def : WriteRes<WriteFLDLE, [LA664LoadAGU, LA664Load, LA664FCmp]>;
+ def : WriteRes<WriteFSTGT, [LA664StoreAGU, LA664Store, LA664FCmp]>;
+ def : WriteRes<WriteFSTLE, [LA664StoreAGU, LA664Store, LA664FCmp]>;
+}
+def : ReadAdvance<ReadFMemCmp, 0>;
+
+// Floating-point instruction latency FRECIPE/FRSQRTE
+let Latency = 5 in {
+ def : WriteRes<WriteFRECIPE, [LA664FMul]>;
+ def : WriteRes<WriteFRSQRTE, [LA664FMul]>;
+}
+def : ReadAdvance<ReadFRECIPE, 0>;
+def : ReadAdvance<ReadFRSQRTE, 0>;
+
+// Integer instruction latency PCADD
+def : WriteRes<WriteIPCAdd, [LA664LoadAGU]>;
+
+def : ReadAdvance<ReadIPCAdd, 0>;
+
+//===----------------------------------------------------------------------===//
+
+// Vector instruction - LSX / LASX
+//
+// Vector integer arithmetic, default latency is 1.
+def : WriteRes<WriteVALU128, [LA664FPU]>;
+def : WriteRes<WriteVALU256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVALU128, 0>;
+def : ReadAdvance<ReadVALU256, 0>;
+
+let Latency = 3 in {
+ def : WriteRes<WriteVALUQ128, [LA664VMul]>;
+ def : WriteRes<WriteVALUQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVALUQ128, 0>;
+def : ReadAdvance<ReadVALUQ256, 0>;
+
+def : WriteRes<WriteVAVG128, [LA664FPU]>;
+def : WriteRes<WriteVAVG256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVAVG128, 0>;
+def : ReadAdvance<ReadVAVG256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVAVGD128, [LA664FPU]>;
+ def : WriteRes<WriteVAVGD256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVAVGD128, 0>;
+def : ReadAdvance<ReadVAVGD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVABSD128, [LA664VMul]>;
+ def : WriteRes<WriteVABSD256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVABSD128, 0>;
+def : ReadAdvance<ReadVABSD256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVADDA128, [LA664VMul]>;
+ def : WriteRes<WriteVADDA256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVADDA128, 0>;
+def : ReadAdvance<ReadVADDA256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVHADDW128, [LA664VMul]>;
+ def : WriteRes<WriteVHADDW256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVHADDW128, 0>;
+def : ReadAdvance<ReadVHADDW256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVHADDWQ128, [LA664VMul]>;
+ def : WriteRes<WriteVHADDWQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVHADDWQ128, 0>;
+def : ReadAdvance<ReadVHADDWQ256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVWADD128, [LA664VMul]>;
+ def : WriteRes<WriteVWADD256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVWADD128, 0>;
+def : ReadAdvance<ReadVWADD256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVWADDQ128, [LA664VMul]>;
+ def : WriteRes<WriteVWADDQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVWADDQ128, 0>;
+def : ReadAdvance<ReadVWADDQ256, 0>;
+
+def : WriteRes<WriteVMINMAX128, [LA664FPU]>;
+def : WriteRes<WriteVMINMAX256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVMINMAX128, 0>;
+def : ReadAdvance<ReadVMINMAX256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVMINMAXD128, [LA664FPU]>;
+ def : WriteRes<WriteVMINMAXD256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVMINMAXD128, 0>;
+def : ReadAdvance<ReadVMINMAXD256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVMUL128, [LA664VMul]>;
+ def : WriteRes<WriteVMUL256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVMUL128, 0>;
+def : ReadAdvance<ReadVMUL256, 0>;
+let Latency = 7 in {
+ def : WriteRes<WriteVMULQ128, [LA664VMul]>;
+ def : WriteRes<WriteVMULQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVMULQ128, 0>;
+def : ReadAdvance<ReadVMULQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVMADD128, [LA664VMul]>;
+ def : WriteRes<WriteVMADD256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVMADD128, 0>;
+def : ReadAdvance<ReadVMADD256, 0>;
+let Latency = 7 in {
+ def : WriteRes<WriteVMADDQ128, [LA664VMul]>;
+ def : WriteRes<WriteVMADDQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVMADDQ128, 0>;
+def : ReadAdvance<ReadVMADDQ256, 0>;
+// Latency is 24-52 and throughput is 0.03-0.074, pick the worst case.
+let Latency = 52, ReleaseAtCycles = [1, 32] in {
+ def : WriteRes<WriteVDIVB128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVDIVB256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVDIVB128, 0>;
+def : ReadAdvance<ReadVDIVB256, 0>;
+// Latency is 14-35 and throughput is 0.05-0.13, pick the worst case.
+let Latency = 35, ReleaseAtCycles = [1, 19] in {
+ def : WriteRes<WriteVDIVH128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVDIVH256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVDIVH128, 0>;
+def : ReadAdvance<ReadVDIVH256, 0>;
+// Latency is 9-26 and throughput is 0.065-0.22, pick the worst case.
+let Latency = 26, ReleaseAtCycles = [1, 14] in {
+ def : WriteRes<WriteVDIVW128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVDIVW256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVDIVW128, 0>;
+def : ReadAdvance<ReadVDIVW256, 0>;
+// Latency is 6-22 and throughput is 0.08-0.33, pick the worst case.
+let Latency = 22, ReleaseAtCycles = [1, 12] in {
+ def : WriteRes<WriteVDIVD128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVDIVD256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVDIVD128, 0>;
+def : ReadAdvance<ReadVDIVD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSAT128, [LA664VMul]>;
+ def : WriteRes<WriteVSAT256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSAT128, 0>;
+def : ReadAdvance<ReadVSAT256, 0>;
+
+def : WriteRes<WriteVSIGNCOV128, [LA664VMul]>;
+def : WriteRes<WriteVSIGNCOV256, [LA664VMul]>;
+
+def : ReadAdvance<ReadVSIGNCOV128, 0>;
+def : ReadAdvance<ReadVSIGNCOV256, 0>;
+
+def : WriteRes<WriteVEXTH128, [LA664FPU]>;
+def : WriteRes<WriteVEXTH256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVEXTH128, 0>;
+def : ReadAdvance<ReadVEXTH256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVEXT2XV256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVEXT2XV256, 0>;
+
+def : WriteRes<WriteVEXTL128, [LA664FPU]>;
+def : WriteRes<WriteVEXTL256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVEXTL128, 0>;
+def : ReadAdvance<ReadVEXTL256, 0>;
+
+def : WriteRes<WriteVLDI128, [LA664FPU]>;
+def : WriteRes<WriteVLDI256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVLDI128, 0>;
+def : ReadAdvance<ReadVLDI256, 0>;
+
+//
+// Vector compare, mask and condition flag
+def : WriteRes<WriteVCMP128, [LA664FPU]>;
+def : WriteRes<WriteVCMP256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVCMP128, 0>;
+def : ReadAdvance<ReadVCMP256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVCMPD128, [LA664FPU]>;
+ def : WriteRes<WriteVCMPD256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVCMPD128, 0>;
+def : ReadAdvance<ReadVCMPD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFCMP128, [LA664FPU]>;
+ def : WriteRes<WriteVFCMP256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFCMP128, 0>;
+def : ReadAdvance<ReadVFCMP256, 0>;
+
+def : WriteRes<WriteVMSK128, [LA664FPU]>;
+def : WriteRes<WriteVMSK256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVMSK128, 0>;
+def : ReadAdvance<ReadVMSK256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSET128, [LA664VMul]>;
+}
+let Latency = 3 in {
+ def : WriteRes<WriteVSET256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSET128, 0>;
+def : ReadAdvance<ReadVSET256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFRSTP128, [LA664VMul]>;
+ def : WriteRes<WriteVFRSTP256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVFRSTP128, 0>;
+def : ReadAdvance<ReadVFRSTP256, 0>;
+
+//
+// Vector bit manipulation
+def : WriteRes<WriteVBIT128, [LA664FPU]>;
+def : WriteRes<WriteVBIT256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVBIT128, 0>;
+def : ReadAdvance<ReadVBIT256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVBITOPS128, [LA664VMul]>;
+ def : WriteRes<WriteVBITOPS256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVBITOPS128, 0>;
+def : ReadAdvance<ReadVBITOPS256, 0>;
+
+def : WriteRes<WriteVBITSEL128, [LA664VMul]>;
+def : WriteRes<WriteVBITSEL256, [LA664VMul]>;
+
+def : ReadAdvance<ReadVBITSEL128, 0>;
+def : ReadAdvance<ReadVBITSEL256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVPCNT128, [LA664VMul]>;
+ def : WriteRes<WriteVPCNT256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVPCNT128, 0>;
+def : ReadAdvance<ReadVPCNT256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVCL128, [LA664FPU]>;
+ def : WriteRes<WriteVCL256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVCL128, 0>;
+def : ReadAdvance<ReadVCL256, 0>;
+
+//
+// Vector shift
+def : WriteRes<WriteVSHIFT128, [LA664FPU]>;
+def : WriteRes<WriteVSHIFT256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVSHIFT128, 0>;
+def : ReadAdvance<ReadVSHIFT256, 0>;
+
+def : WriteRes<WriteVROTR128, [LA664FPU]>;
+def : WriteRes<WriteVROTR256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVROTR128, 0>;
+def : ReadAdvance<ReadVROTR256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTR128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTR256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTR128, 0>;
+def : ReadAdvance<ReadVSHIFTR256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSLLWIL128, [LA664VMul]>;
+ def : WriteRes<WriteVSLLWIL256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSLLWIL128, 0>;
+def : ReadAdvance<ReadVSLLWIL256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVSHIFTN128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTN256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTN128, 0>;
+def : ReadAdvance<ReadVSHIFTN256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTNI128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTNI256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTNI128, 0>;
+def : ReadAdvance<ReadVSHIFTNI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTNIQ128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTNIQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTNIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTNIQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRN128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTRN256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTRN128, 0>;
+def : ReadAdvance<ReadVSHIFTRN256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRNI128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTRNI256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTRNI128, 0>;
+def : ReadAdvance<ReadVSHIFTRNI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTRNIQ128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTRNIQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTRNIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTRNIQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTNS128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTNS256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTNS128, 0>;
+def : ReadAdvance<ReadVSHIFTNS256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTNSI128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTNSI256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTNSI128, 0>;
+def : ReadAdvance<ReadVSHIFTNSI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTNSIQ128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTNSIQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTNSIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTNSIQ256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRNS128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTRNS256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTRNS128, 0>;
+def : ReadAdvance<ReadVSHIFTRNS256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVSHIFTRNSI128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTRNSI256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTRNSI128, 0>;
+def : ReadAdvance<ReadVSHIFTRNSI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVSHIFTRNSIQ128, [LA664VMul]>;
+ def : WriteRes<WriteVSHIFTRNSIQ256, [LA664VMul]>;
+}
+def : ReadAdvance<ReadVSHIFTRNSIQ128, 0>;
+def : ReadAdvance<ReadVSHIFTRNSIQ256, 0>;
+
+//
+// Vector shuffle, permute and element move
+def : WriteRes<WriteVPACK128, [LA664FPU]>;
+def : WriteRes<WriteVPACK256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVPACK128, 0>;
+def : ReadAdvance<ReadVPACK256, 0>;
+
+def : WriteRes<WriteVSHUF128, [LA664VMul]>;
+def : WriteRes<WriteVSHUF256, [LA664VMul]>;
+
+def : ReadAdvance<ReadVSHUF128, 0>;
+def : ReadAdvance<ReadVSHUF256, 0>;
+
+def : WriteRes<WriteVSHUF4I128, [LA664FPU]>;
+def : WriteRes<WriteVSHUF4I256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVSHUF4I128, 0>;
+def : ReadAdvance<ReadVSHUF4I256, 0>;
+
+def : WriteRes<WriteVHSELI256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVHSELI256, 0>;
+
+def : WriteRes<WriteVPERMI128, [LA664FPU]>;
+def : WriteRes<WriteVPERMI256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVPERMI128, 0>;
+def : ReadAdvance<ReadVPERMI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVPERM256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVPERM256, 0>;
+
+def : WriteRes<WriteVEXTRINS128, [LA664FPU]>;
+def : WriteRes<WriteVEXTRINS256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVEXTRINS128, 0>;
+def : ReadAdvance<ReadVEXTRINS256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVPICKVE256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVPICKVE256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVINSVE0256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVINSVE0256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVREPLVE0256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVREPLVE0256, 0>;
+
+def : WriteRes<WriteVREPLVEI128, [LA664FPU]>;
+def : WriteRes<WriteVREPLVEI256, [LA664FPU]>;
+
+def : ReadAdvance<ReadVREPLVEI128, 0>;
+def : ReadAdvance<ReadVREPLVEI256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVREPLVE128, [LA664FMov]>;
+ def : WriteRes<WriteVREPLVE256, [LA664FMov]>;
+}
+def : ReadAdvance<ReadVREPLVE128, 0>;
+def : ReadAdvance<ReadVREPLVE256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVREPLGR2VR128, [LA664FMov]>;
+ def : WriteRes<WriteVREPLGR2VR256, [LA664FMov]>;
+}
+def : ReadAdvance<ReadVREPLGR2VR128, 0>;
+def : ReadAdvance<ReadVREPLGR2VR256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVREPLGR2VRWD128, [LA664FMov]>;
+ def : WriteRes<WriteVREPLGR2VRWD256, [LA664FMov]>;
+}
+def : ReadAdvance<ReadVREPLGR2VRWD128, 0>;
+def : ReadAdvance<ReadVREPLGR2VRWD256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVINSGR2VR128, [LA664FMov]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVINSGR2VR256, [LA664FMov]>;
+}
+def : ReadAdvance<ReadVINSGR2VR128, 0>;
+def : ReadAdvance<ReadVINSGR2VR256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVPICKVE2GR128, [LA664FMov]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVPICKVE2GR256, [LA664FMov]>;
+}
+def : ReadAdvance<ReadVPICKVE2GR128, 0>;
+def : ReadAdvance<ReadVPICKVE2GR256, 0>;
+
+//
+// Vector floating-point arithmetic
+let Latency = 3 in {
+ def : WriteRes<WriteVFADD128, [LA664FPU]>;
+ def : WriteRes<WriteVFADD256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFADD128, 0>;
+def : ReadAdvance<ReadVFADD256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFMUL128, [LA664FMul]>;
+ def : WriteRes<WriteVFMUL256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFMUL128, 0>;
+def : ReadAdvance<ReadVFMUL256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFMADD128, [LA664FMA]>;
+ def : WriteRes<WriteVFMADD256, [LA664FMA]>;
+}
+def : ReadAdvance<ReadVFMADD128, 0>;
+def : ReadAdvance<ReadVFMADD256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFMINMAX128, [LA664FPU]>;
+ def : WriteRes<WriteVFMINMAX256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFMINMAX128, 0>;
+def : ReadAdvance<ReadVFMINMAX256, 0>;
+let Latency = 2 in {
+ def : WriteRes<WriteVFCLASS128, [LA664FPU]>;
+ def : WriteRes<WriteVFCLASS256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFCLASS128, 0>;
+def : ReadAdvance<ReadVFCLASS256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFLOGB128, [LA664FPU]>;
+ def : WriteRes<WriteVFLOGB256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFLOGB128, 0>;
+def : ReadAdvance<ReadVFLOGB256, 0>;
+// Latency is 9-23 and throughput is 0.08-0.22, pick the worst case.
+let Latency = 23, ReleaseAtCycles = [1, 12] in {
+ def : WriteRes<WriteVFDIVS128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFDIVS256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFDIVS128, 0>;
+def : ReadAdvance<ReadVFDIVS256, 0>;
+// Latency is 6-19 and throughput is 0.095-0.33, pick the worst case.
+let Latency = 19, ReleaseAtCycles = [1, 10] in {
+ def : WriteRes<WriteVFDIVD128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFDIVD256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFDIVD128, 0>;
+def : ReadAdvance<ReadVFDIVD256, 0>;
+// Latency is 11-39 and throughput is 0.054-0.222, pick the worst case.
+let Latency = 39, ReleaseAtCycles = [1, 18] in {
+ def : WriteRes<WriteVFSQRTS128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFSQRTS256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFSQRTS128, 0>;
+def : ReadAdvance<ReadVFSQRTS256, 0>;
+// Latency is 8-36 and throughput is 0.059-0.333, pick the worst case.
+let Latency = 36, ReleaseAtCycles = [1, 16] in {
+ def : WriteRes<WriteVFSQRTD128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFSQRTD256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFSQRTD128, 0>;
+def : ReadAdvance<ReadVFSQRTD256, 0>;
+// Latency is 11-27 and throughput is 0.08-0.222, pick the worst case.
+let Latency = 27, ReleaseAtCycles = [1, 12] in {
+ def : WriteRes<WriteVFRECIPS128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFRECIPS256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFRECIPS128, 0>;
+def : ReadAdvance<ReadVFRECIPS256, 0>;
+// Latency is 8-23 and throughput is 0.095-0.333, pick the worst case.
+let Latency = 23, ReleaseAtCycles = [1, 10] in {
+ def : WriteRes<WriteVFRECIPD128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFRECIPD256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFRECIPD128, 0>;
+def : ReadAdvance<ReadVFRECIPD256, 0>;
+// Latency is 17-61 and throughput is 0.034-0.133, pick the worst case.
+let Latency = 61, ReleaseAtCycles = [1, 28] in {
+ def : WriteRes<WriteVFRSQRTS128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFRSQRTS256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFRSQRTS128, 0>;
+def : ReadAdvance<ReadVFRSQRTS256, 0>;
+// Latency is 11-54 and throughput is 0.038-0.222, pick the worst case.
+let Latency = 54, ReleaseAtCycles = [1, 25] in {
+ def : WriteRes<WriteVFRSQRTD128, [LA664FPU0, LA664FDiv]>;
+ def : WriteRes<WriteVFRSQRTD256, [LA664FPU0, LA664FDiv]>;
+}
+def : ReadAdvance<ReadVFRSQRTD128, 0>;
+def : ReadAdvance<ReadVFRSQRTD256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFRECIPE128, [LA664FMul]>;
+ def : WriteRes<WriteVFRECIPE256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFRECIPE128, 0>;
+def : ReadAdvance<ReadVFRECIPE256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFRSQRTE128, [LA664FMul]>;
+ def : WriteRes<WriteVFRSQRTE256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFRSQRTE128, 0>;
+def : ReadAdvance<ReadVFRSQRTE256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFRINT128, [LA664FMul]>;
+ def : WriteRes<WriteVFRINT256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFRINT128, 0>;
+def : ReadAdvance<ReadVFRINT256, 0>;
+let Latency = 3 in {
+ def : WriteRes<WriteVFCVT128, [LA664FMul]>;
+ def : WriteRes<WriteVFCVT256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFCVT128, 0>;
+def : ReadAdvance<ReadVFCVT256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFTINT128, [LA664FPU]>;
+ def : WriteRes<WriteVFTINT256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFTINT128, 0>;
+def : ReadAdvance<ReadVFTINT256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFTINTX128, [LA664FMul]>;
+ def : WriteRes<WriteVFTINTX256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFTINTX128, 0>;
+def : ReadAdvance<ReadVFTINTX256, 0>;
+let Latency = 4 in {
+ def : WriteRes<WriteVFFINT128, [LA664FPU]>;
+ def : WriteRes<WriteVFFINT256, [LA664FPU]>;
+}
+def : ReadAdvance<ReadVFFINT128, 0>;
+def : ReadAdvance<ReadVFFINT256, 0>;
+let Latency = 5 in {
+ def : WriteRes<WriteVFFINTX128, [LA664FMul]>;
+ def : WriteRes<WriteVFFINTX256, [LA664FMul]>;
+}
+def : ReadAdvance<ReadVFFINTX128, 0>;
+def : ReadAdvance<ReadVFFINTX256, 0>;
+
+//
+// Vector memory access
+let Latency = 5 in {
+ def : WriteRes<WriteVLD128, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteVLD256, [LA664LoadAGU, LA664Load]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVLDX128, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteVLDX256, [LA664LoadAGU, LA664Load]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVLDREPL128, [LA664LoadAGU, LA664Load]>;
+ def : WriteRes<WriteVLDREPL256, [LA664LoadAGU, LA664Load]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVST128, [LA664StoreAGU, LA664Store]>;
+ def : WriteRes<WriteVST256, [LA664StoreAGU, LA664Store]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVSTX128, [LA664StoreAGU, LA664Store]>;
+ def : WriteRes<WriteVSTX256, [LA664StoreAGU, LA664Store]>;
+}
+let Latency = 5 in {
+ def : WriteRes<WriteVSTELM128, [LA664StoreAGU, LA664Store]>;
+ def : WriteRes<WriteVSTELM256, [LA664StoreAGU, LA664Store]>;
+}
+
+// Vector memory access operands
+def : ReadAdvance<ReadVSTData128, 0>;
+def : ReadAdvance<ReadVMemBase128, 0>;
+def : ReadAdvance<ReadVMemOffset128, 0>;
+def : ReadAdvance<ReadVSTData256, 0>;
+def : ReadAdvance<ReadVMemBase256, 0>;
+def : ReadAdvance<ReadVMemOffset256, 0>;
+
+let Unsupported = true in {
+ def : WriteRes<WriteAtomic, []>;
+ def : ReadAdvance<ReadAtomic, 0>;
+}
+
+let Unsupported = true in {
+ def : WriteRes<WritePseudo, []>;
+ def : ReadAdvance<ReadPseudo, 0>;
+}
+
+let Unsupported = true in {
+ def : WriteRes<WriteOthers, []>;
+ def : ReadAdvance<ReadOthers, 0>;
+}
+
+} // SchedModel
\ No newline at end of file
diff --git a/llvm/lib/Target/LoongArch/LoongArchSchedule.td b/llvm/lib/Target/LoongArch/LoongArchSchedule.td
new file mode 100644
index 0000000000000..f9342c5e6ecf2
--- /dev/null
+++ b/llvm/lib/Target/LoongArch/LoongArchSchedule.td
@@ -0,0 +1,520 @@
+//===-- LoongArchSchedule.td - LoongArch Scheduling Definitions ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+/// Define scheduler resources associated with def operands.
+
+/// BASE instruction - integer instruction
+def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
+def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on LA64
+def ReadIALU : SchedRead; // 32 or 64-bit integer ALU operations
+def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on LA64
+//===----------------------------------------------------------------------===//
+// ADD.W SUB.W Sched<[WriteIALU, ReadIALU32, ReadIALU32]>
+// ADD.D SUB.D Sched<[WriteIALU, ReadIALU, ReadIALU]>
+// ADDI.W Sched<[WriteIALU, ReadIALU32]>
+// ADDI.D ADDUI16.D Sched<[WriteIALU, ReadIALU]>
+// AND ANDN OR NOR ORN XOR Sched<[WriteIALU, ReadIALU, ReadIALU]>
+// ANDI XORI ORI Sched<[WriteIALU, ReadIALU]>
+// SLT SLTU Sched<[WriteIALU, ReadIALU, ReadIALU]>
+// SLTI SLTUI Sched<[WriteIALU, ReadIALU]>
+// LU12I.W LU32I.D Sched<[WriteIALU]>
+// LU52I.D Sched<[WriteIALU, ReadIALU]>
+//===----------------------------------------------------------------------===//
+
+def WriteIALSL : SchedWrite; // 32 or 64-bit integer ALSL operations
+def WriteIALSL32 : SchedWrite; // 32-bit integer ALSL operations on LA64
+def ReadIALSL : SchedRead; // 32 or 64-bit integer ALSL operations
+def ReadIALSL32 : SchedRead; // 32-bit integer ALSL operations on LA64
+//===----------------------------------------------------------------------===//
+// ALSL.W ALSL.WU Sched<[WriteIALSL, ReadIALSL32, ReadIALSL32]>
+// ALSL.D Sched<[WriteIALSL, ReadIALSL, ReadIALSL]>
+//===----------------------------------------------------------------------===//
+
+def WriteIPCAdd : SchedWrite; // LoongArch PC ADD instruction operation
+def ReadIPCAdd : SchedRead; // LoongArch PC ADD instruction operation
+//===----------------------------------------------------------------------===//
+// PCADDI PCADDUI12I PCADDU18I PCALAU12I Sched<[WriteIPCAdd]>
+//===----------------------------------------------------------------------===//
+
+def WriteIMUL : SchedWrite; // 32 or 64-bit integer MUL operations
+def WriteIMUL32 : SchedWrite; // 32-bit integer MUL operations on LA64
+def ReadIMUL : SchedRead; // 32 or 64-bit integer MUL operations
+def ReadIMUL32 : SchedRead; // 32-bit integer MUL operations on LA64
+//===----------------------------------------------------------------------===//
+// MUL.W MULH.W MULH.WU Sched<[WriteIMUL, ReadIMUL32, ReadIMUL32]>
+// MUL.D MULH.D MULH.DU Sched<[WriteIMUL, ReadIMUL, ReadIMUL]>
+// MULW.D.W MULW.D.WU Sched<[WriteIMUL, ReadIMUL32, ReadIMUL32]>
+//===----------------------------------------------------------------------===//
+
+def WriteIDIV : SchedWrite; // 32 or 64-bit integer DIV operations
+def WriteIDIV32 : SchedWrite; // 32-bit integer DIV operations on LA64
+def ReadIDIV : SchedRead; // 32 or 64-bit integer DIV operations
+def ReadIDIV32 : SchedRead; // 32-bit integer DIV operations on LA64
+//===----------------------------------------------------------------------===//
+// DIV.W MOD.W DIV.WU MOD.WU Sched<[WriteIDIV, ReadIDIV32, ReadIDIV32]>
+// DIV.D MOD.D DIV.DU MOD.DU Sched<[WriteIDIV, ReadIDIV, ReadIDIV]>
+//===----------------------------------------------------------------------===//
+
+def WriteIShift : SchedWrite; // 32 or 64-bit Shift operations
+def WriteIShift32 : SchedWrite; // 32-bit Shift operations on LA64
+def ReadIShift : SchedRead; // 32 or 64-bit Shift operations
+def ReadIShift32 : SchedRead; // 32-bit Shift operations on LA64
+//===----------------------------------------------------------------------===//
+// SLL.W SRL.W SRA.W ROTR.W Sched<[WriteIShift, ReadIShift32, ReadIShift32]>
+// SLLI.W SRLI.W SRAI.W ROTRI.W Sched<[WriteIShift, ReadIShift32]>
+// SLL.D SRL.D SRA.D ROTR.D Sched<[WriteIShift, ReadIShift, ReadIShift]>
+// SLLI.D SRLI.D SRAI.D ROTRI.D Sched<[WriteIShift, ReadIShift]>
+//===----------------------------------------------------------------------===//
+
+def WriteIEXT : SchedWrite; // 32 or 64-bit EXT operations
+def ReadIEXT : SchedRead; // 32 or 64-bit EXT operations
+//===----------------------------------------------------------------------===//
+// EXT.W.B EXT.W.H Sched<[WriteIEXT, ReadIEXT]>
+//===----------------------------------------------------------------------===//
+
+def WriteICL : SchedWrite; // 32 or 64-bit CLO/CLZ operations
+def WriteICL32 : SchedWrite; // 32-bit CLO/CLZ operations on LA64
+def WriteICT : SchedWrite; // 32 or 64-bit CTO/CTZ operations
+def WriteICT32 : SchedWrite; // 32-bit CTO/CTZ operations on LA64
+def ReadICL : SchedRead; // 32 or 64-bit CLO/CLZ operations
+def ReadICL32 : SchedRead; // 32-bit CLO/CLZ operations on LA64
+def ReadICT : SchedRead; // 32 or 64-bit CTO/CTZ operations
+def ReadICT32 : SchedRead; // 32-bit CTO/CTZ operations on LA64
+//===----------------------------------------------------------------------===//
+// CLO.W CLZ.W Sched<[WriteICL, ReadICL32]>
+// CTO.W CTZ.W Sched<[WriteICT, ReadICT32]>
+// CLO.D CLZ.D Sched<[WriteICL, ReadICL]>
+// CTO.D CTZ.D Sched<[WriteICT, ReadICT]>
+//===----------------------------------------------------------------------===//
+
+def WriteIBytePick : SchedWrite; // 32 or 64-bit BytePick operations
+def WriteIBytePick32 : SchedWrite; // 32-bit BytePick operations on LA64
+def ReadIBytePick : SchedRead; // 32 or 64-bit BytePick operations
+def ReadIBytePick32 : SchedRead; // 32-bit BytePick operations on LA64
+//===----------------------------------------------------------------------===//
+// BYTEPICK.W Sched<[WriteIBytePick, ReadIBytePick32, ReadIBytePick32]>
+// BYTEPICK.D Sched<[WriteIBytePick, ReadIBytePick, ReadIBytePick]>
+//===----------------------------------------------------------------------===//
+
+def WriteIRev : SchedWrite; // 32 or 64-bit RevB operations
+def WriteIRev32 : SchedWrite; // 32-bit RevB operations on LA64
+def ReadIRev : SchedRead; // 32 or 64-bit RevB operations
+def ReadIRev32 : SchedRead; // 32-bit RevB operations on LA64
+//===----------------------------------------------------------------------===//
+// REVB.2H Sched<[WriteIRev, ReadIRev32]>
+// REVB.4H REVB.2W REVB.D Sched<[WriteIRev, ReadIRev]>
+// REVH.2W REVH.D Sched<[WriteIRev, ReadIRev]>
+//===----------------------------------------------------------------------===//
+
+def WriteIBitRev : SchedWrite; // 32 or 64-bit BitRev operations
+def WriteIBitRev32 : SchedWrite; // 32-bit BitRev operations on LA64
+def ReadIBitRev : SchedRead; // 32 or 64-bit BitRev operations
+def ReadIBitRev32 : SchedRead; // 32-bit BitRev operations on LA64
+//===----------------------------------------------------------------------===//
+// BITREV.4B Sched<[WriteIBitRev, ReadIBitRev32]>
+// BITREV.8B BITREV.W BITREV.D Sched<[WriteIBitRev, ReadIBitRev]>
+//===----------------------------------------------------------------------===//
+
+def WriteIBstrins : SchedWrite; // 32 or 64-bit Bstrins operations
+def WriteIBstrins32 : SchedWrite; // 32-bit Bstrins operations on LA64
+def ReadIBstrins : SchedRead; // 32 or 64-bit Bstrins operations
+def ReadIBstrins32 : SchedRead; // 32-bit Bstrins operations on LA64
+//===----------------------------------------------------------------------===//
+// BSTRINS.W Sched<[WriteIBstrins, ReadIBstrins32]>
+// BSTRINS.D Sched<[WriteIBstrins, ReadIBstrins]>
+//===----------------------------------------------------------------------===//
+
+def WriteIBstrPick : SchedWrite; // 32 or 64-bit BstrPick operations
+def WriteIBstrPick32 : SchedWrite; // 32-bit BstrPick operations on LA64
+def ReadIBstrPick : SchedRead; // 32 or 64-bit BstrPick operations
+def ReadIBstrPick32 : SchedRead; // 32-bit BstrPick operations on LA64
+//===----------------------------------------------------------------------===//
+// BSTRPICK.W Sched<[WriteIBstrPick, ReadIBstrPick32]>
+// BSTRPICK.D Sched<[WriteIBstrPick, ReadIBstrPick]>
+//===----------------------------------------------------------------------===//
+
+def WriteIMASK : SchedWrite; // 32 or 64-bit MASK operations
+def ReadIMASK : SchedRead; // 32 or 64-bit MASK operations
+//===----------------------------------------------------------------------===//
+// MASKEQZ MASKNEZ Sched<[WriteIMASK, ReadIMASK]>
+//===----------------------------------------------------------------------===//
+
+def WriteIJump : SchedWrite; // integer Jump
+def ReadIJump : SchedRead; // integer Jump
+//===----------------------------------------------------------------------===//
+// BEQ BNE BLT BGE BLTU BGEU Sched<[WriteIJump, ReadIJump, ReadIJump]>
+// BEQZ BNEZ Sched<[WriteIJump, ReadIJump]>
+// B BL Sched<[WriteIJump]>
+//===----------------------------------------------------------------------===//
+
+def WriteLD : SchedWrite; // Load reg+imm
+def WriteST : SchedWrite; // Store reg+imm
+def WriteLDX : SchedWrite; // Load reg+reg
+def WriteSTX : SchedWrite; // Store reg+reg
+def ReadSTData : SchedRead; // Load / Store STData
+def ReadMemBase : SchedRead; // Load / Store MemBase
+def ReadMemOffset : SchedRead; // Load / Store MemOffset
+//===----------------------------------------------------------------------===//
+// LD.B LD.H LD.W LD.D Sched<[WriteLD, ReadMemBase]>
+// LD.BU LD.HU LD.WU Sched<[WriteLD, ReadMemBase]>
+// ST.B ST.H ST.W ST.D Sched<[WriteST, ReadSTData, ReadMemBase]>
+//
+// def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+//
+// LDX.B LDX.H LDX.W LDX.D Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>
+// LDX.BU LDX.HU LDX.WU Sched<[WriteLDX, ReadMemBase, ReadMemOffset]>
+// STX.B STX.H STX.W STX.D Sched<[WriteSTX, ReadSTData, ReadMemBase, ReadMemOffset]>
+//===----------------------------------------------------------------------===//
+
+def WriteLDPTR : SchedWrite; // Load ptr reg+imm
+def WriteSTPTR : SchedWrite; // Store ptr reg+imm
+//===----------------------------------------------------------------------===//
+// LDPTR.W LDPTR.D Sched<[WriteLDPTR, ReadMemBase]>
+// STPTR.W STPRT.D Sched<[WriteSTPTR, ReadSTData, ReadMemBase]>
+//===----------------------------------------------------------------------===//
+
+def WriteLDGT : SchedWrite; // 64-bit LDGT operations
+def WriteLDLE : SchedWrite; // 64-bit LDLE operations
+def WriteSTGT : SchedWrite; // 64-bit STGT operations
+def WriteSTLE : SchedWrite; // 64-bit STLE operations
+def ReadMemCmp : SchedRead; // LDGT LDLE STGT STLE MemCmp operaitons
+//===----------------------------------------------------------------------===//
+// LDGT.B LDGT.H LDGT.W LDGT.D Sched<[WriteLDGT, ReadMemBase, ReadMemCmp]>
+// LDLE.B LDLE.H LDLE.W LDLE.D Sched<[WriteLDLE, ReadMemBase, ReadMemCmp]>
+// STGT.B STGT.H STGT.W STGT.D Sched<[WriteSTGT, ReadSTData, ReadMemBase, ReadMemCmp]>
+// STLE.B STLE.H STLE.W STLE.D Sched<[WriteSTLE, ReadSTData, ReadMemBase, ReadMemCmp]>
+//===----------------------------------------------------------------------===//
+
+
+/// BASE instruction - floating instruction
+def WriteFADD : SchedWrite; // floating-point addition/subtraction
+def ReadFADD : SchedRead; // floating-point addition/subtraction
+//===----------------------------------------------------------------------===//
+// FADD.S FADD.D FSUB.S FSUB.D Sched<[WriteFADD, ReadFADD, ReadFADD]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMUL : SchedWrite; // floating-point multiply
+def ReadFMUL : SchedRead; // floating-point multiply
+//===----------------------------------------------------------------------===//
+// FMUL.S FMUL.D Sched<[WriteFMUL, ReadFMUL, ReadFMUL]>
+//===----------------------------------------------------------------------===//
+
+def WriteFDIV : SchedWrite; // floating-point divide
+def WriteFDIV32 : SchedWrite; // 32-bit floating-point divide on LA64
+def ReadFDIV : SchedRead; // floating-point divide
+def ReadFDIV32 : SchedRead; // 32-bit floating-point divide on LA64
+//===----------------------------------------------------------------------===//
+// FDIV.S Sched<[WriteFDIV32, ReadFDIV32, ReadFDIV32]>
+// FDIV.D Sched<[WriteFDIV, ReadFDIV, ReadFDIV]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMADD : SchedWrite; // floating-point fused multiply-add
+def ReadFMADD : SchedRead; // floating-point fused multiply-add
+//===----------------------------------------------------------------------===//
+// FMADD.S FMADD.D Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>
+// FMSUB.S FMSUB.D Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>
+// FNMADD.S FNMADD.D Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>
+// FNMSUB.S FNMSUB.D Sched<[WriteFMADD, ReadFMADD, ReadFMADD, ReadFMADD]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMinMax : SchedWrite; // floating-point min or max
+def ReadFMinMax : SchedRead; // floating-point min or max
+//===----------------------------------------------------------------------===//
+// FMAX.S FMAX.D Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>
+// FMIN.S FMIN.D Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>
+// FMAXA.S FMAXA.D Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>
+// FMINA.S FMINA.D Sched<[WriteFMinMax, ReadFMinMax, ReadFMinMax]>
+//===----------------------------------------------------------------------===//
+
+def WriteFABS : SchedWrite; // floating-point abs
+def ReadFABS : SchedRead; // floating-point abs
+//===----------------------------------------------------------------------===//
+// FABS.S FABS.D Sched<[WriteFABS, ReadFABS]>
+//===----------------------------------------------------------------------===//
+
+def WriteFNEG : SchedWrite; // floating-point neg
+def ReadFNEG : SchedRead; // floating-point neg
+//===----------------------------------------------------------------------===//
+// FNEG.S FNEG.D Sched<[WriteFNEG, ReadFNEG]>
+//===----------------------------------------------------------------------===//
+
+def WriteFSQRT : SchedWrite; // floating-point sqrt
+def WriteFSQRT32 : SchedWrite; // 32-bit floating-point sqrt on LA64
+def ReadFSQRT : SchedRead; // floating-point sqrt
+def ReadFSQRT32 : SchedRead; // 32-bit floating-point sqrt on LA64
+//===----------------------------------------------------------------------===//
+// FSQRT.S FSQRT.D Sched<[WriteFSQRT, ReadFSQRT]>
+//===----------------------------------------------------------------------===//
+
+def WriteFRECIP : SchedWrite; // floating-point recip
+def WriteFRECIP32 : SchedWrite; // 32-bit floating-point recip on LA64
+def ReadFRECIP : SchedRead; // floating-point recip
+def ReadFRECIP32 : SchedRead; // 32-bit floating-point recip on LA64
+//===----------------------------------------------------------------------===//
+// FRECIP.S FRECIP.D Sched<[WriteFRECIP, ReadFRECIP]>
+//===----------------------------------------------------------------------===//
+
+def WriteFRSQRT : SchedWrite; // floating-point rsqrt
+def WriteFRSQRT32 : SchedWrite; // 32-bit floating-point rsqrt on LA64
+def ReadFRSQRT : SchedRead; // floating-point rsqrt
+def ReadFRSQRT32 : SchedRead; // 32-bit floating-point rsqrt on LA64
+//===----------------------------------------------------------------------===//
+// FRSQRT.S FRSQRT.D Sched<[WriteFRSQRT, ReadFRSQRT]>
+//===----------------------------------------------------------------------===//
+
+def WriteFRECIPE : SchedWrite; // floating-point recipe
+def ReadFRECIPE : SchedRead; // floating-point recipe
+//===----------------------------------------------------------------------===//
+// FRECIPE.S FRECIPE.D Sched<[WriteFRECIPE, ReadFRECIPE]>
+//===----------------------------------------------------------------------===//
+
+def WriteFRSQRTE : SchedWrite; // floating-point rsqrte
+def ReadFRSQRTE : SchedRead; // floating-point rsqrte
+//===----------------------------------------------------------------------===//
+// FRSQRTE.S FRSQRTE.D Sched<[WriteFRSQRTE, ReadFRSQRTE]>
+//===----------------------------------------------------------------------===//
+
+def WriteFSCALEB : SchedWrite; // floating-point scaleb
+def ReadFSCALEB : SchedRead; // floating-point scaleb
+//===----------------------------------------------------------------------===//
+// FSCALEB.S FSCALEB.D Sched<[WriteFSCALEB, ReadFSCALEB, ReadFSCALEB]>
+//===----------------------------------------------------------------------===//
+
+def WriteFLOGB : SchedWrite; // floating-point logb
+def ReadFLOGB : SchedRead; // floating-point logb
+//===----------------------------------------------------------------------===//
+// FLOGB.S FLOGB.D Sched<[WriteFLOGB, ReadFLOGB]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCOPYSIGN : SchedWrite; // floating-point copysign
+def ReadFCOPYSIGN : SchedRead; // floating-point copysign
+//===----------------------------------------------------------------------===//
+// FCOPYSIGN.S FCOPYSIGN.D Sched<[WriteFCOPYSIGN, ReadFCOPYSIGN, ReadFCOPYSIGN]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCLASS : SchedWrite; // floating-point class
+def ReadFCLASS : SchedRead; // floating-point class
+//===----------------------------------------------------------------------===//
+// FCLASS.S FCLASS.D Sched<[WriteFCLASS, ReadFCLASS]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCMP : SchedWrite; // floating-point condition
+def ReadFCMP : SchedRead; // floating-point condition
+//===----------------------------------------------------------------------===//
+// FCMP.COND.S FCMP.COND.D Sched<[WriteFCMP, ReadFCMP, ReadFCMP]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCvtStoD : SchedWrite; // Conversion single to double
+def WriteFCvtDtoS : SchedWrite; // Conversion double to single
+def ReadFCvtStoD : SchedRead; // Conversion single to double
+def ReadFCvtDtoS : SchedRead; // Conversion double to single
+//===----------------------------------------------------------------------===//
+// FCVT.S.D Sched<[WriteFCvtStoD, ReadFCvtStoD]>
+// FCVT.D.S Sched<[WriteFCvtDtoS, ReadFCvtDtoS]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCvtStoW : SchedWrite; // Conversion single to integer word
+def WriteFCvtStoL : SchedWrite; // Conversion single to integer doubleword
+def WriteFCvtDtoW : SchedWrite; // Conversion double to integer word
+def WriteFCvtDtoL : SchedWrite; // Conversion double to integer doubleword
+def WriteFCvtWtoS : SchedWrite; // Conversion integer word to single
+def WriteFCvtWtoD : SchedWrite; // Conversion integer word to double
+def WriteFCvtLtoS : SchedWrite; // Conversion integer doubleword to single
+def WriteFCvtLtoD : SchedWrite; // Conversion integer doubleword to double
+def ReadFCvtStoW : SchedRead; // Conversion single to integer word
+def ReadFCvtStoL : SchedRead; // Conversion single to integer doubleword
+def ReadFCvtDtoW : SchedRead; // Conversion double to integer word
+def ReadFCvtDtoL : SchedRead; // Conversion double to integer doubleword
+def ReadFCvtWtoS : SchedRead; // Conversion integer word to single
+def ReadFCvtWtoD : SchedRead; // Conversion integer word to double
+def ReadFCvtLtoS : SchedRead; // Conversion integer doubleword to single
+def ReadFCvtLtoD : SchedRead; // Conversion integer doubleword to double
+//===----------------------------------------------------------------------===//
+// FFINT.S.W Sched<[WriteFCvtStoW, ReadFCvtStoW]>
+// FFINT.S.L Sched<[WriteFCvtStoL, ReadFCvtStoL]>
+// FFINT.D.W Sched<[WriteFCvtDtoW, ReadFCvtDtoW]>
+// FFINT.D.L Sched<[WriteFCvtDtoL, ReadFCvtDtoL]>
+// FTINT.W.S Sched<[WriteFCvtWtoS, ReadFCvtWtoS]>
+// FTINT.W.D Sched<[WriteFCvtWtoD, ReadFCvtWtoD]>
+// FTINT.L.S Sched<[WriteFCvtLtoS, ReadFCvtLtoS]>
+// FTINT.L.D Sched<[WriteFCvtLtoD, ReadFCvtLtoD]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCvtWtoS_RM : SchedWrite; // Conversion integer word to single
+def WriteFCvtWtoD_RM : SchedWrite; // Conversion integer word to double
+def WriteFCvtLtoS_RM : SchedWrite; // Conversion integer doubleword to single
+def WriteFCvtLtoD_RM : SchedWrite; // Conversion integer doubleword to double
+def ReadFCvtWtoS_RM : SchedRead; // Conversion integer word to single
+def ReadFCvtWtoD_RM : SchedRead; // Conversion integer word to double
+def ReadFCvtLtoS_RM : SchedRead; // Conversion integer doubleword to single
+def ReadFCvtLtoD_RM : SchedRead; // Conversion integer doubleword to double
+def WriteFCvtWtoS_RP : SchedWrite; // Conversion integer word to single
+def WriteFCvtWtoD_RP : SchedWrite; // Conversion integer word to double
+def WriteFCvtLtoS_RP : SchedWrite; // Conversion integer doubleword to single
+def WriteFCvtLtoD_RP : SchedWrite; // Conversion integer doubleword to double
+def ReadFCvtWtoS_RP : SchedRead; // Conversion integer word to single
+def ReadFCvtWtoD_RP : SchedRead; // Conversion integer word to double
+def ReadFCvtLtoS_RP : SchedRead; // Conversion integer doubleword to single
+def ReadFCvtLtoD_RP : SchedRead; // Conversion integer doubleword to double
+def WriteFCvtWtoS_RZ : SchedWrite; // Conversion integer word to single
+def WriteFCvtWtoD_RZ : SchedWrite; // Conversion integer word to double
+def WriteFCvtLtoS_RZ : SchedWrite; // Conversion integer doubleword to single
+def WriteFCvtLtoD_RZ : SchedWrite; // Conversion integer doubleword to double
+def ReadFCvtWtoS_RZ : SchedRead; // Conversion integer word to single
+def ReadFCvtWtoD_RZ : SchedRead; // Conversion integer word to double
+def ReadFCvtLtoS_RZ : SchedRead; // Conversion integer doubleword to single
+def ReadFCvtLtoD_RZ : SchedRead; // Conversion integer doubleword to double
+def WriteFCvtWtoS_RNE : SchedWrite; // Conversion integer word to single
+def WriteFCvtWtoD_RNE : SchedWrite; // Conversion integer word to double
+def WriteFCvtLtoS_RNE : SchedWrite; // Conversion integer doubleword to single
+def WriteFCvtLtoD_RNE : SchedWrite; // Conversion integer doubleword to double
+def ReadFCvtWtoS_RNE : SchedRead; // Conversion integer word to single
+def ReadFCvtWtoD_RNE : SchedRead; // Conversion integer word to double
+def ReadFCvtLtoS_RNE : SchedRead; // Conversion integer doubleword to single
+def ReadFCvtLtoD_RNE : SchedRead; // Conversion integer doubleword to double
+//===----------------------------------------------------------------------===//
+// FTINTRM.W.S Sched<[WriteFCvtWtoS_RM, ReadFCvtWtoS_RM]>
+// FTINTRM.W.D Sched<[WriteFCvtWtoD_RM, ReadFCvtWtoD_RM]>
+// FTINTRM.L.S Sched<[WriteFCvtLtoS_RM, ReadFCvtLtoS_RM]>
+// FTINTRM.L.D Sched<[WriteFCvtLtoD_RM, ReadFCvtLtoD_RM]>
+// FTINTRP.W.S Sched<[WriteFCvtWtoS_RP, ReadFCvtWtoS_RP]>
+// FTINTRP.W.D Sched<[WriteFCvtWtoD_RP, ReadFCvtWtoD_RP]>
+// FTINTRP.L.S Sched<[WriteFCvtLtoS_RP, ReadFCvtLtoS_RP]>
+// FTINTRP.L.D Sched<[WriteFCvtLtoD_RP, ReadFCvtLtoD_RP]>
+// FTINTRZ.W.S Sched<[WriteFCvtWtoS_RZ, ReadFCvtWtoS_RZ]>
+// FTINTRZ.W.D Sched<[WriteFCvtWtoD_RZ, ReadFCvtWtoD_RZ]>
+// FTINTRZ.L.S Sched<[WriteFCvtLtoS_RZ, ReadFCvtLtoS_RZ]>
+// FTINTRZ.L.D Sched<[WriteFCvtLtoD_RZ, ReadFCvtLtoD_RZ]>
+// FTINTRNE.W.S Sched<[WriteFCvtWtoS_RNE, ReadFCvtWtoS_RNE]>
+// FTINTRNE.W.D Sched<[WriteFCvtWtoD_RNE, ReadFCvtWtoD_RNE]>
+// FTINTRNE.L.S Sched<[WriteFCvtLtoS_RNE, ReadFCvtLtoS_RNE]>
+// FTINTRNE.L.D Sched<[WriteFCvtLtoD_RNE, ReadFCvtLtoD_RNE]>
+//===----------------------------------------------------------------------===//
+
+def WriteFCvtFStoIS : SchedWrite; // Conversion single-floating point to integer single-floating point
+def WriteFCvtFDtoID : SchedWrite; // Conversion double-floating point to integer double-floating point
+def ReadFCvtFStoIS : SchedRead; // Conversion single-floating point to integer single-floating point
+def ReadFCvtFDtoID : SchedRead; // Conversion double-floating point to integer double-floating point
+//===----------------------------------------------------------------------===//
+// FRINT.S Sched<[WriteFCvtFStoIS, ReadFCvtFStoIS]>
+// FRINT.D Sched<[WriteFCvtFDtoID, ReadFCvtFDtoID]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMovS : SchedWrite; // Move single-floating point
+def WriteFMovD : SchedWrite; // Move double-floating point
+def ReadFMovS : SchedRead; // Move single-floating point
+def ReadFMovD : SchedRead; // Move double-floating point
+//===----------------------------------------------------------------------===//
+// FMOV.S Sched<[WriteFMovS, ReadFMovS]>
+// FMOV.D Sched<[WriteFMovD, ReadFMovD]>
+//===----------------------------------------------------------------------===//
+
+def WriteFSEL : SchedWrite; // floating-point select instruction
+def ReadFSEL : SchedRead; // floating-point select instruction
+//===----------------------------------------------------------------------===//
+// FSEL Sched<[WriteFSEL, ReadFSEL, ReadFSEL, ReadFSEL]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMovGRtoFRW : SchedWrite; // Move GR[31: 0] value to FR[31: 0]
+def WriteFMovGRtoFRHW : SchedWrite; // Move GR[63:32] value to FR[63:32]
+def WriteFMovGRtoFRD : SchedWrite; // Move GR[63: 0] value to FR[63: 0]
+def ReadFMovGRtoFRW : SchedRead; // Move GR[31: 0] value to FR[31: 0]
+def ReadFMovGRtoFRHW : SchedRead; // Move GR[63:32] value to FR[63:32]
+def ReadFMovGRtoFRD : SchedRead; // Move GR[63: 0] value to FR[63: 0]
+//===----------------------------------------------------------------------===//
+// MOVGR2FR.W Sched<[WriteFMovGRtoFRW, ReadFMovGRtoFRW]>
+// MOVGR2FRH.W Sched<[WriteFMovGRtoFRHW, ReadFMovGRtoFRHW]>
+// MOVGR2FR.D Sched<[WriteFMovGRtoFRD, ReadFMovGRtoFRD]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMovFRtoGRS : SchedWrite; // Move FR[31: 0] value to GR
+def WriteFMovFRHtoGRS : SchedWrite; // Move FR[63:32] value to GR
+def WriteFMovFRtoGRD : SchedWrite; // Move FR[63: 0] value to GR
+def ReadFMovFRtoGRS : SchedRead; // Move FR[31: 0] value to GR
+def ReadFMovFRHtoGRS : SchedRead; // Move FR[63:32] value to GR
+def ReadFMovFRtoGRD : SchedRead; // Move FR[63: 0] value to GR
+//===----------------------------------------------------------------------===//
+// MOVFR2GR.S Sched<[WriteFMovFRtoGRS, ReadFMovFRtoGRS]>
+// MOVFRH2GR.S Sched<[WriteFMovFRHtoGRS, ReadFMovFRHtoGRS]>
+// MOVFR2GR.D Sched<[WriteFMovFRtoGRD, ReadFMovFRtoGRD]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMovGRtoFCSR : SchedWrite; // Move GR value to FCSR
+def WriteFMovFCSRtoGR : SchedWrite; // Move FCSR value to GR
+def ReadFMovGRtoFCSR : SchedRead; // Move GR value to FCSR
+def ReadFMovFCSRtoGR : SchedRead; // Move FCSR value to GR
+//===----------------------------------------------------------------------===//
+// MOVGR2FCSR Sched<[WriteFMovGRtoFCSR, ReadFMovGRtoFCSR]>
+// MOVFCSR2GR Sched<[WriteFMovFCSRtoGR, ReadFMovFCSRtoGR]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMoveFRtoCF : SchedWrite; // Move FR value to FCC
+def WriteFMoveCFtoFR : SchedWrite; // Move FCC value to FR
+def ReadFMoveFRtoCF : SchedRead; // Move FR value to FCC
+def ReadFMoveCFtoFR : SchedRead; // Move FCC value to FR
+//===----------------------------------------------------------------------===//
+// MOVFR2CF Sched<[WriteFMoveFRtoCF, ReadFMoveFRtoCF]>
+// MOVCF2FR Sched<[WriteFMoveCFtoFR, ReadFMoveCFtoFR]>
+//===----------------------------------------------------------------------===//
+
+def WriteFMoveGRtoCF : SchedWrite; // Move GR value to FCC
+def WriteFMoveCFtoGR : SchedWrite; // Move FCC value to GR
+def ReadFMoveGRtoCF : SchedRead; // Move GR value to FCC
+def ReadFMoveCFtoGR : SchedRead; // Move FCC value to GR
+//===----------------------------------------------------------------------===//
+// MOVGR2CF Sched<[WriteFMoveGRtoCF, ReadFMoveGRtoCF]>
+// MOVCF2GR Sched<[WriteFMoveCFtoGR, ReadFMoveCFtoGR]>
+//===----------------------------------------------------------------------===//
+
+def WriteFJump : SchedWrite; // floating-point JUMP
+def ReadFJump : SchedRead; // floating-point JUMP
+//===----------------------------------------------------------------------===//
+// BCEQZ Sched<[WriteFJump, ReadFJump]>
+// BCNEZ Sched<[WriteFJump, ReadFJump]>
+//===----------------------------------------------------------------------===//
+
+def WriteFLD : SchedWrite; // Load reg+imm
+def WriteFST : SchedWrite; // Store reg+imm
+def WriteFLDX : SchedWrite; // Load reg+reg
+def WriteFSTX : SchedWrite; // Store reg+imm
+def ReadFSTData : SchedRead; // Load / Store FSTData
+def ReadFMemBase : SchedRead; // Load / Store FMemBase
+def ReadFMemOffset : SchedRead; // Load / Store FMemOffset
+//===----------------------------------------------------------------------===//
+// FLD.S FLD.D Sched<[WriteFLD, ReadFMemBase]>
+// FST.S FST.D Sched<[WriteFST, ReadFSTData, ReadFMemBase]>
+// FLDX.S FLDX.D Sched<[WriteFLDX, ReadFMemBase, ReadFMemOffset]>
+// FSTX.S FSTX.D Sched<[WriteFSTX, ReadFSTData, ReadFMemBase, ReadFMemOffset]>
+//===----------------------------------------------------------------------===//
+
+def WriteFLDGT : SchedWrite; // 64-bit FLDGT operations
+def WriteFLDLE : SchedWrite; // 64-bit FLDLE operations
+def WriteFSTGT : SchedWrite; // 64-bit FSTGT operations
+def WriteFSTLE : SchedWrite; // 64-bit FSTLE operations
+def ReadFMemCmp : SchedRead; // FLDGT FLDLE FSTGT FSTLE MemCmp operaitons
+//===----------------------------------------------------------------------===//
+// FLDGT.S FLDGT.D Sched<[WriteFLDGT, ReadFMemBase, ReadFMemCmp]>
+// FLDLE.S FLDLE.D Sched<[WriteFLDLE, ReadFMemBase, ReadFMemCmp]>
+// FSTGT.S FSTGT.D Sched<[WriteFSTGT, ReadFSTData, ReadFMemBase, ReadFMemCmp]>
+// FSTLE.S FSTLE.D Sched<[WriteFSTLE, ReadFSTData, ReadFMemBase, ReadFMemCmp]>
+//===----------------------------------------------------------------------===//
+
+// Atomic Instruction is unsupported scheduling.
+def WriteAtomic : SchedWrite; // Atomic write operations
+def ReadAtomic : SchedRead; // Atomic read operations
+
+// Pseudo Instruction is unsupported scheduling.
+def WritePseudo : SchedWrite; // Pseudo write operations
+def ReadPseudo : SchedRead; // Pseudo read operations
+
+// Others Instruction is unsupported scheduling.
+def WriteOthers : SchedWrite; // Others write operations
+def ReadOthers : SchedRead; // Others read operations
+
+// Include the scheduler resources for other instruction extensions.
+include "LoongArchScheduleV.td"
diff --git a/llvm/lib/Target/LoongArch/LoongArchScheduleV.td b/llvm/lib/Target/LoongArch/LoongArchScheduleV.td
new file mode 100644
index 0000000000000..223af954e9b86
--- /dev/null
+++ b/llvm/lib/Target/LoongArch/LoongArchScheduleV.td
@@ -0,0 +1,1291 @@
+//==- LoongArchScheduleV.td - LoongArch V Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+/// Define scheduler resources associated with def operands.
+///
+/// Vector instruction - LSX (128-bit) / LASX (256-bit)
+///
+/// The 128-bit and the 256-bit form of an operation are kept apart because a
+/// few of them do not share the same timing, e.g. XVINSGR2VR.W is slower than
+/// VINSGR2VR.W and XVSETEQZ.V is slower than VSETEQZ.V.
+
+//===----------------------------------------------------------------------===//
+/// Vector integer arithmetic
+//===----------------------------------------------------------------------===//
+
+def WriteVALU128 : SchedWrite; // 128-bit integer add / sub
+def WriteVALU256 : SchedWrite; // 256-bit integer add / sub
+def ReadVALU128 : SchedRead; // 128-bit integer add / sub
+def ReadVALU256 : SchedRead; // 256-bit integer add / sub
+//===----------------------------------------------------------------------===//
+// VADD.B VADD.H VADD.W VADD.D VSUB.B VSUB.H VSUB.W VSUB.D VSADD.B
+// VSADD.H VSADD.W VSADD.D VSADD.BU VSADD.HU VSADD.WU VSADD.DU
+// VSSUB.B VSSUB.H VSSUB.W VSSUB.D VSSUB.BU VSSUB.HU VSSUB.WU
+// VSSUB.DU
+// Sched<[WriteVALU128, ReadVALU128, ReadVALU128]>
+// VADDI.BU VADDI.HU VADDI.WU VADDI.DU VSUBI.BU VSUBI.HU VSUBI.WU
+// VSUBI.DU VNEG.B VNEG.H VNEG.W VNEG.D
+// Sched<[WriteVALU128, ReadVALU128]>
+// XVADD.B XVADD.H XVADD.W XVADD.D XVSUB.B XVSUB.H XVSUB.W XVSUB.D
+// XVSADD.B XVSADD.H XVSADD.W XVSADD.D XVSADD.BU XVSADD.HU XVSADD.WU
+// XVSADD.DU XVSSUB.B XVSSUB.H XVSSUB.W XVSSUB.D XVSSUB.BU XVSSUB.HU
+// XVSSUB.WU XVSSUB.DU
+// Sched<[WriteVALU256, ReadVALU256, ReadVALU256]>
+// XVADDI.BU XVADDI.HU XVADDI.WU XVADDI.DU XVSUBI.BU XVSUBI.HU
+// XVSUBI.WU XVSUBI.DU XVNEG.B XVNEG.H XVNEG.W XVNEG.D
+// Sched<[WriteVALU256, ReadVALU256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVALUQ128 : SchedWrite; // 128-bit quadword add / sub
+def WriteVALUQ256 : SchedWrite; // 256-bit quadword add / sub
+def ReadVALUQ128 : SchedRead; // 128-bit quadword add / sub
+def ReadVALUQ256 : SchedRead; // 256-bit quadword add / sub
+//===----------------------------------------------------------------------===//
+// VADD.Q VSUB.Q
+// Sched<[WriteVALUQ128, ReadVALUQ128, ReadVALUQ128]>
+// XVADD.Q XVSUB.Q
+// Sched<[WriteVALUQ256, ReadVALUQ256, ReadVALUQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVAVG128 : SchedWrite; // 128-bit integer average
+def WriteVAVG256 : SchedWrite; // 256-bit integer average
+def ReadVAVG128 : SchedRead; // 128-bit integer average
+def ReadVAVG256 : SchedRead; // 256-bit integer average
+//===----------------------------------------------------------------------===//
+// VAVG.B VAVG.H VAVG.W VAVG.BU VAVG.HU VAVG.WU VAVGR.B VAVGR.H
+// VAVGR.W VAVGR.BU VAVGR.HU VAVGR.WU
+// Sched<[WriteVAVG128, ReadVAVG128, ReadVAVG128]>
+// XVAVG.B XVAVG.H XVAVG.W XVAVG.BU XVAVG.HU XVAVG.WU XVAVGR.B
+// XVAVGR.H XVAVGR.W XVAVGR.BU XVAVGR.HU XVAVGR.WU
+// Sched<[WriteVAVG256, ReadVAVG256, ReadVAVG256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVAVGD128 : SchedWrite; // 128-bit doubleword average
+def WriteVAVGD256 : SchedWrite; // 256-bit doubleword average
+def ReadVAVGD128 : SchedRead; // 128-bit doubleword average
+def ReadVAVGD256 : SchedRead; // 256-bit doubleword average
+//===----------------------------------------------------------------------===//
+// VAVG.D VAVG.DU VAVGR.D VAVGR.DU
+// Sched<[WriteVAVGD128, ReadVAVGD128, ReadVAVGD128]>
+// XVAVG.D XVAVG.DU XVAVGR.D XVAVGR.DU
+// Sched<[WriteVAVGD256, ReadVAVGD256, ReadVAVGD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVABSD128 : SchedWrite; // 128-bit integer abs difference
+def WriteVABSD256 : SchedWrite; // 256-bit integer abs difference
+def ReadVABSD128 : SchedRead; // 128-bit integer abs difference
+def ReadVABSD256 : SchedRead; // 256-bit integer abs difference
+//===----------------------------------------------------------------------===//
+// VABSD.B VABSD.H VABSD.W VABSD.D VABSD.BU VABSD.HU VABSD.WU
+// VABSD.DU
+// Sched<[WriteVABSD128, ReadVABSD128, ReadVABSD128]>
+// XVABSD.B XVABSD.H XVABSD.W XVABSD.D XVABSD.BU XVABSD.HU XVABSD.WU
+// XVABSD.DU
+// Sched<[WriteVABSD256, ReadVABSD256, ReadVABSD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVADDA128 : SchedWrite; // 128-bit integer add absolute
+def WriteVADDA256 : SchedWrite; // 256-bit integer add absolute
+def ReadVADDA128 : SchedRead; // 128-bit integer add absolute
+def ReadVADDA256 : SchedRead; // 256-bit integer add absolute
+//===----------------------------------------------------------------------===//
+// VADDA.B VADDA.H VADDA.W VADDA.D
+// Sched<[WriteVADDA128, ReadVADDA128, ReadVADDA128]>
+// XVADDA.B XVADDA.H XVADDA.W XVADDA.D
+// Sched<[WriteVADDA256, ReadVADDA256, ReadVADDA256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVHADDW128 : SchedWrite; // 128-bit horizontal add / sub
+def WriteVHADDW256 : SchedWrite; // 256-bit horizontal add / sub
+def ReadVHADDW128 : SchedRead; // 128-bit horizontal add / sub
+def ReadVHADDW256 : SchedRead; // 256-bit horizontal add / sub
+//===----------------------------------------------------------------------===//
+// VHADDW.H.B VHADDW.W.H VHADDW.D.W VHADDW.HU.BU VHADDW.WU.HU
+// VHADDW.DU.WU VHSUBW.H.B VHSUBW.W.H VHSUBW.D.W VHSUBW.HU.BU
+// VHSUBW.WU.HU VHSUBW.DU.WU
+// Sched<[WriteVHADDW128, ReadVHADDW128, ReadVHADDW128]>
+// XVHADDW.H.B XVHADDW.W.H XVHADDW.D.W XVHADDW.HU.BU XVHADDW.WU.HU
+// XVHADDW.DU.WU XVHSUBW.H.B XVHSUBW.W.H XVHSUBW.D.W XVHSUBW.HU.BU
+// XVHSUBW.WU.HU XVHSUBW.DU.WU
+// Sched<[WriteVHADDW256, ReadVHADDW256, ReadVHADDW256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVHADDWQ128 : SchedWrite; // 128-bit quadword horizontal add
+def WriteVHADDWQ256 : SchedWrite; // 256-bit quadword horizontal add
+def ReadVHADDWQ128 : SchedRead; // 128-bit quadword horizontal add
+def ReadVHADDWQ256 : SchedRead; // 256-bit quadword horizontal add
+//===----------------------------------------------------------------------===//
+// VHADDW.Q.D VHADDW.QU.DU VHSUBW.Q.D VHSUBW.QU.DU
+// Sched<[WriteVHADDWQ128, ReadVHADDWQ128, ReadVHADDWQ128]>
+// XVHADDW.Q.D XVHADDW.QU.DU XVHSUBW.Q.D XVHSUBW.QU.DU
+// Sched<[WriteVHADDWQ256, ReadVHADDWQ256, ReadVHADDWQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVWADD128 : SchedWrite; // 128-bit widening add / sub
+def WriteVWADD256 : SchedWrite; // 256-bit widening add / sub
+def ReadVWADD128 : SchedRead; // 128-bit widening add / sub
+def ReadVWADD256 : SchedRead; // 256-bit widening add / sub
+//===----------------------------------------------------------------------===//
+// VADDWEV.H.B VADDWEV.W.H VADDWEV.D.W VADDWOD.H.B VADDWOD.W.H
+// VADDWOD.D.W VSUBWEV.H.B VSUBWEV.W.H VSUBWEV.D.W VSUBWOD.H.B
+// VSUBWOD.W.H VSUBWOD.D.W VADDWEV.H.BU VADDWEV.W.HU VADDWEV.D.WU
+// VADDWOD.H.BU VADDWOD.W.HU VADDWOD.D.WU VSUBWEV.H.BU VSUBWEV.W.HU
+// VSUBWEV.D.WU VSUBWOD.H.BU VSUBWOD.W.HU VSUBWOD.D.WU VADDWEV.H.BU.B
+// VADDWEV.W.HU.H VADDWEV.D.WU.W VADDWOD.H.BU.B VADDWOD.W.HU.H
+// VADDWOD.D.WU.W
+// Sched<[WriteVWADD128, ReadVWADD128, ReadVWADD128]>
+// XVADDWEV.H.B XVADDWEV.W.H XVADDWEV.D.W XVADDWOD.H.B XVADDWOD.W.H
+// XVADDWOD.D.W XVSUBWEV.H.B XVSUBWEV.W.H XVSUBWEV.D.W XVSUBWOD.H.B
+// XVSUBWOD.W.H XVSUBWOD.D.W XVADDWEV.H.BU XVADDWEV.W.HU XVADDWEV.D.WU
+// XVADDWOD.H.BU XVADDWOD.W.HU XVADDWOD.D.WU XVSUBWEV.H.BU XVSUBWEV.W.HU
+// XVSUBWEV.D.WU XVSUBWOD.H.BU XVSUBWOD.W.HU XVSUBWOD.D.WU
+// XVADDWEV.H.BU.B XVADDWEV.W.HU.H XVADDWEV.D.WU.W XVADDWOD.H.BU.B
+// XVADDWOD.W.HU.H XVADDWOD.D.WU.W
+// Sched<[WriteVWADD256, ReadVWADD256, ReadVWADD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVWADDQ128 : SchedWrite; // 128-bit quadword widening add
+def WriteVWADDQ256 : SchedWrite; // 256-bit quadword widening add
+def ReadVWADDQ128 : SchedRead; // 128-bit quadword widening add
+def ReadVWADDQ256 : SchedRead; // 256-bit quadword widening add
+//===----------------------------------------------------------------------===//
+// VADDWEV.Q.D VADDWOD.Q.D VSUBWEV.Q.D VSUBWOD.Q.D VADDWEV.Q.DU
+// VADDWOD.Q.DU VSUBWEV.Q.DU VSUBWOD.Q.DU VADDWEV.Q.DU.D VADDWOD.Q.DU.D
+// Sched<[WriteVWADDQ128, ReadVWADDQ128, ReadVWADDQ128]>
+// XVADDWEV.Q.D XVADDWOD.Q.D XVSUBWEV.Q.D XVSUBWOD.Q.D XVADDWEV.Q.DU
+// XVADDWOD.Q.DU XVSUBWEV.Q.DU XVSUBWOD.Q.DU XVADDWEV.Q.DU.D
+// XVADDWOD.Q.DU.D
+// Sched<[WriteVWADDQ256, ReadVWADDQ256, ReadVWADDQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMINMAX128 : SchedWrite; // 128-bit integer min / max
+def WriteVMINMAX256 : SchedWrite; // 256-bit integer min / max
+def ReadVMINMAX128 : SchedRead; // 128-bit integer min / max
+def ReadVMINMAX256 : SchedRead; // 256-bit integer min / max
+//===----------------------------------------------------------------------===//
+// VMAX.B VMAX.H VMAX.W VMAX.BU VMAX.HU VMAX.WU VMIN.B VMIN.H VMIN.W
+// VMIN.BU VMIN.HU VMIN.WU
+// Sched<[WriteVMINMAX128, ReadVMINMAX128, ReadVMINMAX128]>
+// VMAXI.B VMAXI.H VMAXI.W VMAXI.BU VMAXI.HU VMAXI.WU VMINI.B VMINI.H
+// VMINI.W VMINI.BU VMINI.HU VMINI.WU
+// Sched<[WriteVMINMAX128, ReadVMINMAX128]>
+// XVMAX.B XVMAX.H XVMAX.W XVMAX.BU XVMAX.HU XVMAX.WU XVMIN.B XVMIN.H
+// XVMIN.W XVMIN.BU XVMIN.HU XVMIN.WU
+// Sched<[WriteVMINMAX256, ReadVMINMAX256, ReadVMINMAX256]>
+// XVMAXI.B XVMAXI.H XVMAXI.W XVMAXI.BU XVMAXI.HU XVMAXI.WU XVMINI.B
+// XVMINI.H XVMINI.W XVMINI.BU XVMINI.HU XVMINI.WU
+// Sched<[WriteVMINMAX256, ReadVMINMAX256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMINMAXD128 : SchedWrite; // 128-bit doubleword min / max
+def WriteVMINMAXD256 : SchedWrite; // 256-bit doubleword min / max
+def ReadVMINMAXD128 : SchedRead; // 128-bit doubleword min / max
+def ReadVMINMAXD256 : SchedRead; // 256-bit doubleword min / max
+//===----------------------------------------------------------------------===//
+// VMAX.D VMAX.DU VMIN.D VMIN.DU
+// Sched<[WriteVMINMAXD128, ReadVMINMAXD128, ReadVMINMAXD128]>
+// VMAXI.D VMAXI.DU VMINI.D VMINI.DU
+// Sched<[WriteVMINMAXD128, ReadVMINMAXD128]>
+// XVMAX.D XVMAX.DU XVMIN.D XVMIN.DU
+// Sched<[WriteVMINMAXD256, ReadVMINMAXD256, ReadVMINMAXD256]>
+// XVMAXI.D XVMAXI.DU XVMINI.D XVMINI.DU
+// Sched<[WriteVMINMAXD256, ReadVMINMAXD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMUL128 : SchedWrite; // 128-bit integer multiply
+def WriteVMUL256 : SchedWrite; // 256-bit integer multiply
+def ReadVMUL128 : SchedRead; // 128-bit integer multiply
+def ReadVMUL256 : SchedRead; // 256-bit integer multiply
+//===----------------------------------------------------------------------===//
+// VMUL.B VMUL.H VMUL.W VMUL.D VMUH.B VMUH.H VMUH.W VMUH.D VMUH.BU
+// VMUH.HU VMUH.WU VMUH.DU VMULWEV.H.B VMULWEV.W.H VMULWEV.D.W
+// VMULWOD.H.B VMULWOD.W.H VMULWOD.D.W VMULWEV.H.BU VMULWEV.W.HU
+// VMULWEV.D.WU VMULWOD.H.BU VMULWOD.W.HU VMULWOD.D.WU VMULWEV.H.BU.B
+// VMULWEV.W.HU.H VMULWEV.D.WU.W VMULWOD.H.BU.B VMULWOD.W.HU.H
+// VMULWOD.D.WU.W
+// Sched<[WriteVMUL128, ReadVMUL128, ReadVMUL128]>
+// XVMUL.B XVMUL.H XVMUL.W XVMUL.D XVMUH.B XVMUH.H XVMUH.W XVMUH.D
+// XVMUH.BU XVMUH.HU XVMUH.WU XVMUH.DU XVMULWEV.H.B XVMULWEV.W.H
+// XVMULWEV.D.W XVMULWOD.H.B XVMULWOD.W.H XVMULWOD.D.W XVMULWEV.H.BU
+// XVMULWEV.W.HU XVMULWEV.D.WU XVMULWOD.H.BU XVMULWOD.W.HU XVMULWOD.D.WU
+// XVMULWEV.H.BU.B XVMULWEV.W.HU.H XVMULWEV.D.WU.W XVMULWOD.H.BU.B
+// XVMULWOD.W.HU.H XVMULWOD.D.WU.W
+// Sched<[WriteVMUL256, ReadVMUL256, ReadVMUL256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMULQ128 : SchedWrite; // 128-bit quadword multiply
+def WriteVMULQ256 : SchedWrite; // 256-bit quadword multiply
+def ReadVMULQ128 : SchedRead; // 128-bit quadword multiply
+def ReadVMULQ256 : SchedRead; // 256-bit quadword multiply
+//===----------------------------------------------------------------------===//
+// VMULWEV.Q.D VMULWOD.Q.D VMULWEV.Q.DU VMULWOD.Q.DU VMULWEV.Q.DU.D
+// VMULWOD.Q.DU.D
+// Sched<[WriteVMULQ128, ReadVMULQ128, ReadVMULQ128]>
+// XVMULWEV.Q.D XVMULWOD.Q.D XVMULWEV.Q.DU XVMULWOD.Q.DU XVMULWEV.Q.DU.D
+// XVMULWOD.Q.DU.D
+// Sched<[WriteVMULQ256, ReadVMULQ256, ReadVMULQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMADD128 : SchedWrite; // 128-bit integer multiply-add
+def WriteVMADD256 : SchedWrite; // 256-bit integer multiply-add
+def ReadVMADD128 : SchedRead; // 128-bit integer multiply-add
+def ReadVMADD256 : SchedRead; // 256-bit integer multiply-add
+//===----------------------------------------------------------------------===//
+// VMADD.B VMADD.H VMADD.W VMADD.D VMSUB.B VMSUB.H VMSUB.W VMSUB.D
+// VMADDWEV.H.B VMADDWEV.W.H VMADDWEV.D.W VMADDWOD.H.B VMADDWOD.W.H
+// VMADDWOD.D.W VMADDWEV.H.BU VMADDWEV.W.HU VMADDWEV.D.WU VMADDWOD.H.BU
+// VMADDWOD.W.HU VMADDWOD.D.WU VMADDWEV.H.BU.B VMADDWEV.W.HU.H
+// VMADDWEV.D.WU.W VMADDWOD.H.BU.B VMADDWOD.W.HU.H VMADDWOD.D.WU.W
+// Sched<[WriteVMADD128, ReadVMADD128, ReadVMADD128, ReadVMADD128]>
+// XVMADD.B XVMADD.H XVMADD.W XVMADD.D XVMSUB.B XVMSUB.H XVMSUB.W
+// XVMSUB.D XVMADDWEV.H.B XVMADDWEV.W.H XVMADDWEV.D.W XVMADDWOD.H.B
+// XVMADDWOD.W.H XVMADDWOD.D.W XVMADDWEV.H.BU XVMADDWEV.W.HU
+// XVMADDWEV.D.WU XVMADDWOD.H.BU XVMADDWOD.W.HU XVMADDWOD.D.WU
+// XVMADDWEV.H.BU.B XVMADDWEV.W.HU.H XVMADDWEV.D.WU.W XVMADDWOD.H.BU.B
+// XVMADDWOD.W.HU.H XVMADDWOD.D.WU.W
+// Sched<[WriteVMADD256, ReadVMADD256, ReadVMADD256, ReadVMADD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMADDQ128 : SchedWrite; // 128-bit quadword multiply-add
+def WriteVMADDQ256 : SchedWrite; // 256-bit quadword multiply-add
+def ReadVMADDQ128 : SchedRead; // 128-bit quadword multiply-add
+def ReadVMADDQ256 : SchedRead; // 256-bit quadword multiply-add
+//===----------------------------------------------------------------------===//
+// VMADDWEV.Q.D VMADDWOD.Q.D VMADDWEV.Q.DU VMADDWOD.Q.DU VMADDWEV.Q.DU.D
+// VMADDWOD.Q.DU.D
+// Sched<[WriteVMADDQ128, ReadVMADDQ128, ReadVMADDQ128, ReadVMADDQ128]>
+// XVMADDWEV.Q.D XVMADDWOD.Q.D XVMADDWEV.Q.DU XVMADDWOD.Q.DU
+// XVMADDWEV.Q.DU.D XVMADDWOD.Q.DU.D
+// Sched<[WriteVMADDQ256, ReadVMADDQ256, ReadVMADDQ256, ReadVMADDQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVDIVB128 : SchedWrite; // 128-bit byte integer divide
+def WriteVDIVB256 : SchedWrite; // 256-bit byte integer divide
+def ReadVDIVB128 : SchedRead; // 128-bit byte integer divide
+def ReadVDIVB256 : SchedRead; // 256-bit byte integer divide
+//===----------------------------------------------------------------------===//
+// VDIV.B VDIV.BU VMOD.B VMOD.BU
+// Sched<[WriteVDIVB128, ReadVDIVB128, ReadVDIVB128]>
+// XVDIV.B XVDIV.BU XVMOD.B XVMOD.BU
+// Sched<[WriteVDIVB256, ReadVDIVB256, ReadVDIVB256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVDIVH128 : SchedWrite; // 128-bit halfword divide
+def WriteVDIVH256 : SchedWrite; // 256-bit halfword divide
+def ReadVDIVH128 : SchedRead; // 128-bit halfword divide
+def ReadVDIVH256 : SchedRead; // 256-bit halfword divide
+//===----------------------------------------------------------------------===//
+// VDIV.H VDIV.HU VMOD.H VMOD.HU
+// Sched<[WriteVDIVH128, ReadVDIVH128, ReadVDIVH128]>
+// XVDIV.H XVDIV.HU XVMOD.H XVMOD.HU
+// Sched<[WriteVDIVH256, ReadVDIVH256, ReadVDIVH256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVDIVW128 : SchedWrite; // 128-bit word integer divide
+def WriteVDIVW256 : SchedWrite; // 256-bit word integer divide
+def ReadVDIVW128 : SchedRead; // 128-bit word integer divide
+def ReadVDIVW256 : SchedRead; // 256-bit word integer divide
+//===----------------------------------------------------------------------===//
+// VDIV.W VDIV.WU VMOD.W VMOD.WU
+// Sched<[WriteVDIVW128, ReadVDIVW128, ReadVDIVW128]>
+// XVDIV.W XVDIV.WU XVMOD.W XVMOD.WU
+// Sched<[WriteVDIVW256, ReadVDIVW256, ReadVDIVW256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVDIVD128 : SchedWrite; // 128-bit doubleword divide
+def WriteVDIVD256 : SchedWrite; // 256-bit doubleword divide
+def ReadVDIVD128 : SchedRead; // 128-bit doubleword divide
+def ReadVDIVD256 : SchedRead; // 256-bit doubleword divide
+//===----------------------------------------------------------------------===//
+// VDIV.D VDIV.DU VMOD.D VMOD.DU
+// Sched<[WriteVDIVD128, ReadVDIVD128, ReadVDIVD128]>
+// XVDIV.D XVDIV.DU XVMOD.D XVMOD.DU
+// Sched<[WriteVDIVD256, ReadVDIVD256, ReadVDIVD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSAT128 : SchedWrite; // 128-bit integer saturate
+def WriteVSAT256 : SchedWrite; // 256-bit integer saturate
+def ReadVSAT128 : SchedRead; // 128-bit integer saturate
+def ReadVSAT256 : SchedRead; // 256-bit integer saturate
+//===----------------------------------------------------------------------===//
+// VSAT.B VSAT.H VSAT.W VSAT.D VSAT.BU VSAT.HU VSAT.WU VSAT.DU
+// Sched<[WriteVSAT128, ReadVSAT128]>
+// XVSAT.B XVSAT.H XVSAT.W XVSAT.D XVSAT.BU XVSAT.HU XVSAT.WU
+// XVSAT.DU
+// Sched<[WriteVSAT256, ReadVSAT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSIGNCOV128 : SchedWrite; // 128-bit integer sign transfer
+def WriteVSIGNCOV256 : SchedWrite; // 256-bit integer sign transfer
+def ReadVSIGNCOV128 : SchedRead; // 128-bit integer sign transfer
+def ReadVSIGNCOV256 : SchedRead; // 256-bit integer sign transfer
+//===----------------------------------------------------------------------===//
+// VSIGNCOV.B VSIGNCOV.H VSIGNCOV.W VSIGNCOV.D
+// Sched<[WriteVSIGNCOV128, ReadVSIGNCOV128, ReadVSIGNCOV128]>
+// XVSIGNCOV.B XVSIGNCOV.H XVSIGNCOV.W XVSIGNCOV.D
+// Sched<[WriteVSIGNCOV256, ReadVSIGNCOV256, ReadVSIGNCOV256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVEXTH128 : SchedWrite; // 128-bit high-half extend
+def WriteVEXTH256 : SchedWrite; // 256-bit high-half extend
+def ReadVEXTH128 : SchedRead; // 128-bit high-half extend
+def ReadVEXTH256 : SchedRead; // 256-bit high-half extend
+//===----------------------------------------------------------------------===//
+// VEXTH.H.B VEXTH.W.H VEXTH.D.W VEXTH.Q.D VEXTH.HU.BU VEXTH.WU.HU
+// VEXTH.DU.WU VEXTH.QU.DU
+// Sched<[WriteVEXTH128, ReadVEXTH128]>
+// XVEXTH.H.B XVEXTH.W.H XVEXTH.D.W XVEXTH.Q.D XVEXTH.HU.BU
+// XVEXTH.WU.HU XVEXTH.DU.WU XVEXTH.QU.DU
+// Sched<[WriteVEXTH256, ReadVEXTH256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVEXT2XV256 : SchedWrite; // 256-bit low-half extend
+def ReadVEXT2XV256 : SchedRead; // 256-bit low-half extend
+//===----------------------------------------------------------------------===//
+// VEXT2XV.H.B VEXT2XV.W.B VEXT2XV.D.B VEXT2XV.W.H VEXT2XV.D.H
+// VEXT2XV.D.W VEXT2XV.HU.BU VEXT2XV.WU.BU VEXT2XV.DU.BU VEXT2XV.WU.HU
+// VEXT2XV.DU.HU VEXT2XV.DU.WU
+// Sched<[WriteVEXT2XV256, ReadVEXT2XV256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVEXTL128 : SchedWrite; // 128-bit extend to quadword
+def WriteVEXTL256 : SchedWrite; // 256-bit extend to quadword
+def ReadVEXTL128 : SchedRead; // 128-bit extend to quadword
+def ReadVEXTL256 : SchedRead; // 256-bit extend to quadword
+//===----------------------------------------------------------------------===//
+// VEXTL.Q.D VEXTL.QU.DU
+// Sched<[WriteVEXTL128, ReadVEXTL128]>
+// XVEXTL.Q.D XVEXTL.QU.DU
+// Sched<[WriteVEXTL256, ReadVEXTL256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVLDI128 : SchedWrite; // 128-bit immediate load
+def WriteVLDI256 : SchedWrite; // 256-bit immediate load
+def ReadVLDI128 : SchedRead; // 128-bit immediate load
+def ReadVLDI256 : SchedRead; // 256-bit immediate load
+//===----------------------------------------------------------------------===//
+// VLDI
+// Sched<[WriteVLDI128]>
+// XVLDI
+// Sched<[WriteVLDI256]>
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+/// Vector compare, mask and condition flag
+//===----------------------------------------------------------------------===//
+
+def WriteVCMP128 : SchedWrite; // 128-bit integer compare
+def WriteVCMP256 : SchedWrite; // 256-bit integer compare
+def ReadVCMP128 : SchedRead; // 128-bit integer compare
+def ReadVCMP256 : SchedRead; // 256-bit integer compare
+//===----------------------------------------------------------------------===//
+// VSEQ.B VSEQ.H VSEQ.W VSEQ.D VSLE.B VSLE.H VSLE.W VSLE.BU VSLE.HU
+// VSLE.WU VSLT.B VSLT.H VSLT.W VSLT.BU VSLT.HU VSLT.WU
+// Sched<[WriteVCMP128, ReadVCMP128, ReadVCMP128]>
+// VSEQI.B VSEQI.H VSEQI.W VSEQI.D VSLEI.B VSLEI.H VSLEI.W VSLEI.BU
+// VSLEI.HU VSLEI.WU VSLTI.B VSLTI.H VSLTI.W VSLTI.BU VSLTI.HU
+// VSLTI.WU
+// Sched<[WriteVCMP128, ReadVCMP128]>
+// XVSEQ.B XVSEQ.H XVSEQ.W XVSEQ.D XVSLE.B XVSLE.H XVSLE.W XVSLE.BU
+// XVSLE.HU XVSLE.WU XVSLT.B XVSLT.H XVSLT.W XVSLT.BU XVSLT.HU
+// XVSLT.WU
+// Sched<[WriteVCMP256, ReadVCMP256, ReadVCMP256]>
+// XVSEQI.B XVSEQI.H XVSEQI.W XVSEQI.D XVSLEI.B XVSLEI.H XVSLEI.W
+// XVSLEI.BU XVSLEI.HU XVSLEI.WU XVSLTI.B XVSLTI.H XVSLTI.W XVSLTI.BU
+// XVSLTI.HU XVSLTI.WU
+// Sched<[WriteVCMP256, ReadVCMP256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVCMPD128 : SchedWrite; // 128-bit doubleword compare
+def WriteVCMPD256 : SchedWrite; // 256-bit doubleword compare
+def ReadVCMPD128 : SchedRead; // 128-bit doubleword compare
+def ReadVCMPD256 : SchedRead; // 256-bit doubleword compare
+//===----------------------------------------------------------------------===//
+// VSLE.D VSLE.DU VSLT.D VSLT.DU
+// Sched<[WriteVCMPD128, ReadVCMPD128, ReadVCMPD128]>
+// VSLEI.D VSLEI.DU VSLTI.D VSLTI.DU
+// Sched<[WriteVCMPD128, ReadVCMPD128]>
+// XVSLE.D XVSLE.DU XVSLT.D XVSLT.DU
+// Sched<[WriteVCMPD256, ReadVCMPD256, ReadVCMPD256]>
+// XVSLEI.D XVSLEI.DU XVSLTI.D XVSLTI.DU
+// Sched<[WriteVCMPD256, ReadVCMPD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFCMP128 : SchedWrite; // 128-bit FP compare
+def WriteVFCMP256 : SchedWrite; // 256-bit FP compare
+def ReadVFCMP128 : SchedRead; // 128-bit FP compare
+def ReadVFCMP256 : SchedRead; // 256-bit FP compare
+//===----------------------------------------------------------------------===//
+// VFCMP.CAF.S VFCMP.SAF.S VFCMP.CLT.S VFCMP.SLT.S VFCMP.CEQ.S
+// VFCMP.SEQ.S VFCMP.CLE.S VFCMP.SLE.S VFCMP.CUN.S VFCMP.SUN.S
+// VFCMP.CULT.S VFCMP.SULT.S VFCMP.CUEQ.S VFCMP.SUEQ.S VFCMP.CULE.S
+// VFCMP.SULE.S VFCMP.CNE.S VFCMP.SNE.S VFCMP.COR.S VFCMP.SOR.S
+// VFCMP.CUNE.S VFCMP.SUNE.S VFCMP.CAF.D VFCMP.SAF.D VFCMP.CLT.D
+// VFCMP.SLT.D VFCMP.CEQ.D VFCMP.SEQ.D VFCMP.CLE.D VFCMP.SLE.D
+// VFCMP.CUN.D VFCMP.SUN.D VFCMP.CULT.D VFCMP.SULT.D VFCMP.CUEQ.D
+// VFCMP.SUEQ.D VFCMP.CULE.D VFCMP.SULE.D VFCMP.CNE.D VFCMP.SNE.D
+// VFCMP.COR.D VFCMP.SOR.D VFCMP.CUNE.D VFCMP.SUNE.D
+// Sched<[WriteVFCMP128, ReadVFCMP128, ReadVFCMP128]>
+// XVFCMP.CAF.S XVFCMP.SAF.S XVFCMP.CLT.S XVFCMP.SLT.S XVFCMP.CEQ.S
+// XVFCMP.SEQ.S XVFCMP.CLE.S XVFCMP.SLE.S XVFCMP.CUN.S XVFCMP.SUN.S
+// XVFCMP.CULT.S XVFCMP.SULT.S XVFCMP.CUEQ.S XVFCMP.SUEQ.S XVFCMP.CULE.S
+// XVFCMP.SULE.S XVFCMP.CNE.S XVFCMP.SNE.S XVFCMP.COR.S XVFCMP.SOR.S
+// XVFCMP.CUNE.S XVFCMP.SUNE.S XVFCMP.CAF.D XVFCMP.SAF.D XVFCMP.CLT.D
+// XVFCMP.SLT.D XVFCMP.CEQ.D XVFCMP.SEQ.D XVFCMP.CLE.D XVFCMP.SLE.D
+// XVFCMP.CUN.D XVFCMP.SUN.D XVFCMP.CULT.D XVFCMP.SULT.D XVFCMP.CUEQ.D
+// XVFCMP.SUEQ.D XVFCMP.CULE.D XVFCMP.SULE.D XVFCMP.CNE.D XVFCMP.SNE.D
+// XVFCMP.COR.D XVFCMP.SOR.D XVFCMP.CUNE.D XVFCMP.SUNE.D
+// Sched<[WriteVFCMP256, ReadVFCMP256, ReadVFCMP256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVMSK128 : SchedWrite; // 128-bit mask generation
+def WriteVMSK256 : SchedWrite; // 256-bit mask generation
+def ReadVMSK128 : SchedRead; // 128-bit mask generation
+def ReadVMSK256 : SchedRead; // 256-bit mask generation
+//===----------------------------------------------------------------------===//
+// VMSKLTZ.B VMSKLTZ.H VMSKLTZ.W VMSKLTZ.D VMSKGEZ.B VMSKNZ.B
+// Sched<[WriteVMSK128, ReadVMSK128]>
+// XVMSKLTZ.B XVMSKLTZ.H XVMSKLTZ.W XVMSKLTZ.D XVMSKGEZ.B XVMSKNZ.B
+// Sched<[WriteVMSK256, ReadVMSK256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSET128 : SchedWrite; // 128-bit condition flag set
+def WriteVSET256 : SchedWrite; // 256-bit condition flag set
+def ReadVSET128 : SchedRead; // 128-bit condition flag set
+def ReadVSET256 : SchedRead; // 256-bit condition flag set
+//===----------------------------------------------------------------------===//
+// VSETEQZ.V VSETNEZ.V VSETANYEQZ.B VSETANYEQZ.H VSETANYEQZ.W
+// VSETANYEQZ.D VSETALLNEZ.B VSETALLNEZ.H VSETALLNEZ.W VSETALLNEZ.D
+// Sched<[WriteVSET128, ReadVSET128]>
+// XVSETEQZ.V XVSETNEZ.V XVSETANYEQZ.B XVSETANYEQZ.H XVSETANYEQZ.W
+// XVSETANYEQZ.D XVSETALLNEZ.B XVSETALLNEZ.H XVSETALLNEZ.W XVSETALLNEZ.D
+// Sched<[WriteVSET256, ReadVSET256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRSTP128 : SchedWrite; // 128-bit find first negative elem
+def WriteVFRSTP256 : SchedWrite; // 256-bit find first negative elem
+def ReadVFRSTP128 : SchedRead; // 128-bit find first negative elem
+def ReadVFRSTP256 : SchedRead; // 256-bit find first negative elem
+//===----------------------------------------------------------------------===//
+// VFRSTP.B VFRSTP.H
+// Sched<[WriteVFRSTP128, ReadVFRSTP128, ReadVFRSTP128, ReadVFRSTP128]>
+// VFRSTPI.B VFRSTPI.H
+// Sched<[WriteVFRSTP128, ReadVFRSTP128, ReadVFRSTP128]>
+// XVFRSTP.B XVFRSTP.H
+// Sched<[WriteVFRSTP256, ReadVFRSTP256, ReadVFRSTP256, ReadVFRSTP256]>
+// XVFRSTPI.B XVFRSTPI.H
+// Sched<[WriteVFRSTP256, ReadVFRSTP256, ReadVFRSTP256]>
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+/// Vector bit manipulation
+//===----------------------------------------------------------------------===//
+
+def WriteVBIT128 : SchedWrite; // 128-bit bitwise logic
+def WriteVBIT256 : SchedWrite; // 256-bit bitwise logic
+def ReadVBIT128 : SchedRead; // 128-bit bitwise logic
+def ReadVBIT256 : SchedRead; // 256-bit bitwise logic
+//===----------------------------------------------------------------------===//
+// VAND.V VOR.V VXOR.V VNOR.V VANDN.V VORN.V
+// Sched<[WriteVBIT128, ReadVBIT128, ReadVBIT128]>
+// VANDI.B VORI.B VXORI.B VNORI.B
+// Sched<[WriteVBIT128, ReadVBIT128]>
+// XVAND.V XVOR.V XVXOR.V XVNOR.V XVANDN.V XVORN.V
+// Sched<[WriteVBIT256, ReadVBIT256, ReadVBIT256]>
+// XVANDI.B XVORI.B XVXORI.B XVNORI.B
+// Sched<[WriteVBIT256, ReadVBIT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVBITOPS128 : SchedWrite; // 128-bit single-bit operation
+def WriteVBITOPS256 : SchedWrite; // 256-bit single-bit operation
+def ReadVBITOPS128 : SchedRead; // 128-bit single-bit operation
+def ReadVBITOPS256 : SchedRead; // 256-bit single-bit operation
+//===----------------------------------------------------------------------===//
+// VBITCLR.B VBITCLR.H VBITCLR.W VBITCLR.D VBITSET.B VBITSET.H
+// VBITSET.W VBITSET.D VBITREV.B VBITREV.H VBITREV.W VBITREV.D
+// Sched<[WriteVBITOPS128, ReadVBITOPS128, ReadVBITOPS128]>
+// VBITCLRI.B VBITCLRI.H VBITCLRI.W VBITCLRI.D VBITSETI.B VBITSETI.H
+// VBITSETI.W VBITSETI.D VBITREVI.B VBITREVI.H VBITREVI.W VBITREVI.D
+// Sched<[WriteVBITOPS128, ReadVBITOPS128]>
+// XVBITCLR.B XVBITCLR.H XVBITCLR.W XVBITCLR.D XVBITSET.B XVBITSET.H
+// XVBITSET.W XVBITSET.D XVBITREV.B XVBITREV.H XVBITREV.W XVBITREV.D
+// Sched<[WriteVBITOPS256, ReadVBITOPS256, ReadVBITOPS256]>
+// XVBITCLRI.B XVBITCLRI.H XVBITCLRI.W XVBITCLRI.D XVBITSETI.B
+// XVBITSETI.H XVBITSETI.W XVBITSETI.D XVBITREVI.B XVBITREVI.H
+// XVBITREVI.W XVBITREVI.D
+// Sched<[WriteVBITOPS256, ReadVBITOPS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVBITSEL128 : SchedWrite; // 128-bit bitwise select
+def WriteVBITSEL256 : SchedWrite; // 256-bit bitwise select
+def ReadVBITSEL128 : SchedRead; // 128-bit bitwise select
+def ReadVBITSEL256 : SchedRead; // 256-bit bitwise select
+//===----------------------------------------------------------------------===//
+// VBITSEL.V
+// Sched<[WriteVBITSEL128, ReadVBITSEL128, ReadVBITSEL128, ReadVBITSEL128]>
+// VBITSELI.B
+// Sched<[WriteVBITSEL128, ReadVBITSEL128, ReadVBITSEL128]>
+// XVBITSEL.V
+// Sched<[WriteVBITSEL256, ReadVBITSEL256, ReadVBITSEL256, ReadVBITSEL256]>
+// XVBITSELI.B
+// Sched<[WriteVBITSEL256, ReadVBITSEL256, ReadVBITSEL256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVPCNT128 : SchedWrite; // 128-bit population count
+def WriteVPCNT256 : SchedWrite; // 256-bit population count
+def ReadVPCNT128 : SchedRead; // 128-bit population count
+def ReadVPCNT256 : SchedRead; // 256-bit population count
+//===----------------------------------------------------------------------===//
+// VPCNT.B VPCNT.H VPCNT.W VPCNT.D
+// Sched<[WriteVPCNT128, ReadVPCNT128]>
+// XVPCNT.B XVPCNT.H XVPCNT.W XVPCNT.D
+// Sched<[WriteVPCNT256, ReadVPCNT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVCL128 : SchedWrite; // 128-bit count leading one / zero
+def WriteVCL256 : SchedWrite; // 256-bit count leading one / zero
+def ReadVCL128 : SchedRead; // 128-bit count leading one / zero
+def ReadVCL256 : SchedRead; // 256-bit count leading one / zero
+//===----------------------------------------------------------------------===//
+// VCLO.B VCLO.H VCLO.W VCLO.D VCLZ.B VCLZ.H VCLZ.W VCLZ.D
+// Sched<[WriteVCL128, ReadVCL128]>
+// XVCLO.B XVCLO.H XVCLO.W XVCLO.D XVCLZ.B XVCLZ.H XVCLZ.W XVCLZ.D
+// Sched<[WriteVCL256, ReadVCL256]>
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+/// Vector shift
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFT128 : SchedWrite; // 128-bit integer shift
+def WriteVSHIFT256 : SchedWrite; // 256-bit integer shift
+def ReadVSHIFT128 : SchedRead; // 128-bit integer shift
+def ReadVSHIFT256 : SchedRead; // 256-bit integer shift
+//===----------------------------------------------------------------------===//
+// VSLL.B VSLL.H VSLL.W VSLL.D VSRL.B VSRL.H VSRL.W VSRL.D VSRA.B
+// VSRA.H VSRA.W VSRA.D
+// Sched<[WriteVSHIFT128, ReadVSHIFT128, ReadVSHIFT128]>
+// VSLLI.B VSLLI.H VSLLI.W VSLLI.D VSRLI.B VSRLI.H VSRLI.W VSRLI.D
+// VSRAI.B VSRAI.H VSRAI.W VSRAI.D VBSLL.V VBSRL.V
+// Sched<[WriteVSHIFT128, ReadVSHIFT128]>
+// XVSLL.B XVSLL.H XVSLL.W XVSLL.D XVSRL.B XVSRL.H XVSRL.W XVSRL.D
+// XVSRA.B XVSRA.H XVSRA.W XVSRA.D
+// Sched<[WriteVSHIFT256, ReadVSHIFT256, ReadVSHIFT256]>
+// XVSLLI.B XVSLLI.H XVSLLI.W XVSLLI.D XVSRLI.B XVSRLI.H XVSRLI.W
+// XVSRLI.D XVSRAI.B XVSRAI.H XVSRAI.W XVSRAI.D XVBSLL.V XVBSRL.V
+// Sched<[WriteVSHIFT256, ReadVSHIFT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVROTR128 : SchedWrite; // 128-bit integer rotate
+def WriteVROTR256 : SchedWrite; // 256-bit integer rotate
+def ReadVROTR128 : SchedRead; // 128-bit integer rotate
+def ReadVROTR256 : SchedRead; // 256-bit integer rotate
+//===----------------------------------------------------------------------===//
+// VROTR.B VROTR.H VROTR.W VROTR.D
+// Sched<[WriteVROTR128, ReadVROTR128, ReadVROTR128]>
+// VROTRI.B VROTRI.H VROTRI.W VROTRI.D
+// Sched<[WriteVROTR128, ReadVROTR128]>
+// XVROTR.B XVROTR.H XVROTR.W XVROTR.D
+// Sched<[WriteVROTR256, ReadVROTR256, ReadVROTR256]>
+// XVROTRI.B XVROTRI.H XVROTRI.W XVROTRI.D
+// Sched<[WriteVROTR256, ReadVROTR256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTR128 : SchedWrite; // 128-bit shift with rounding
+def WriteVSHIFTR256 : SchedWrite; // 256-bit shift with rounding
+def ReadVSHIFTR128 : SchedRead; // 128-bit shift with rounding
+def ReadVSHIFTR256 : SchedRead; // 256-bit shift with rounding
+//===----------------------------------------------------------------------===//
+// VSRLR.B VSRLR.H VSRLR.W VSRLR.D VSRAR.B VSRAR.H VSRAR.W VSRAR.D
+// Sched<[WriteVSHIFTR128, ReadVSHIFTR128, ReadVSHIFTR128]>
+// VSRLRI.B VSRLRI.H VSRLRI.W VSRLRI.D VSRARI.B VSRARI.H VSRARI.W
+// VSRARI.D
+// Sched<[WriteVSHIFTR128, ReadVSHIFTR128]>
+// XVSRLR.B XVSRLR.H XVSRLR.W XVSRLR.D XVSRAR.B XVSRAR.H XVSRAR.W
+// XVSRAR.D
+// Sched<[WriteVSHIFTR256, ReadVSHIFTR256, ReadVSHIFTR256]>
+// XVSRLRI.B XVSRLRI.H XVSRLRI.W XVSRLRI.D XVSRARI.B XVSRARI.H
+// XVSRARI.W XVSRARI.D
+// Sched<[WriteVSHIFTR256, ReadVSHIFTR256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSLLWIL128 : SchedWrite; // 128-bit widening shift left
+def WriteVSLLWIL256 : SchedWrite; // 256-bit widening shift left
+def ReadVSLLWIL128 : SchedRead; // 128-bit widening shift left
+def ReadVSLLWIL256 : SchedRead; // 256-bit widening shift left
+//===----------------------------------------------------------------------===//
+// VSLLWIL.H.B VSLLWIL.W.H VSLLWIL.D.W VSLLWIL.HU.BU VSLLWIL.WU.HU
+// VSLLWIL.DU.WU
+// Sched<[WriteVSLLWIL128, ReadVSLLWIL128]>
+// XVSLLWIL.H.B XVSLLWIL.W.H XVSLLWIL.D.W XVSLLWIL.HU.BU XVSLLWIL.WU.HU
+// XVSLLWIL.DU.WU
+// Sched<[WriteVSLLWIL256, ReadVSLLWIL256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTN128 : SchedWrite; // 128-bit narrowing shift
+def WriteVSHIFTN256 : SchedWrite; // 256-bit narrowing shift
+def ReadVSHIFTN128 : SchedRead; // 128-bit narrowing shift
+def ReadVSHIFTN256 : SchedRead; // 256-bit narrowing shift
+//===----------------------------------------------------------------------===//
+// VSRLN.B.H VSRLN.H.W VSRLN.W.D VSRAN.B.H VSRAN.H.W VSRAN.W.D
+// Sched<[WriteVSHIFTN128, ReadVSHIFTN128, ReadVSHIFTN128]>
+// XVSRLN.B.H XVSRLN.H.W XVSRLN.W.D XVSRAN.B.H XVSRAN.H.W XVSRAN.W.D
+// Sched<[WriteVSHIFTN256, ReadVSHIFTN256, ReadVSHIFTN256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTNI128 : SchedWrite; // 128-bit narrowing shift by imm
+def WriteVSHIFTNI256 : SchedWrite; // 256-bit narrowing shift by imm
+def ReadVSHIFTNI128 : SchedRead; // 128-bit narrowing shift by imm
+def ReadVSHIFTNI256 : SchedRead; // 256-bit narrowing shift by imm
+//===----------------------------------------------------------------------===//
+// VSRLNI.B.H VSRLNI.H.W VSRLNI.W.D VSRANI.B.H VSRANI.H.W VSRANI.W.D
+// Sched<[WriteVSHIFTNI128, ReadVSHIFTNI128, ReadVSHIFTNI128]>
+// XVSRLNI.B.H XVSRLNI.H.W XVSRLNI.W.D XVSRANI.B.H XVSRANI.H.W
+// XVSRANI.W.D
+// Sched<[WriteVSHIFTNI256, ReadVSHIFTNI256, ReadVSHIFTNI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTNIQ128 : SchedWrite; // 128-bit quadword narrow shf imm
+def WriteVSHIFTNIQ256 : SchedWrite; // 256-bit quadword narrow shf imm
+def ReadVSHIFTNIQ128 : SchedRead; // 128-bit quadword narrow shf imm
+def ReadVSHIFTNIQ256 : SchedRead; // 256-bit quadword narrow shf imm
+//===----------------------------------------------------------------------===//
+// VSRLNI.D.Q VSRANI.D.Q
+// Sched<[WriteVSHIFTNIQ128, ReadVSHIFTNIQ128, ReadVSHIFTNIQ128]>
+// XVSRLNI.D.Q XVSRANI.D.Q
+// Sched<[WriteVSHIFTNIQ256, ReadVSHIFTNIQ256, ReadVSHIFTNIQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTRN128 : SchedWrite; // 128-bit rounding narrow shift
+def WriteVSHIFTRN256 : SchedWrite; // 256-bit rounding narrow shift
+def ReadVSHIFTRN128 : SchedRead; // 128-bit rounding narrow shift
+def ReadVSHIFTRN256 : SchedRead; // 256-bit rounding narrow shift
+//===----------------------------------------------------------------------===//
+// VSRLRN.B.H VSRLRN.H.W VSRLRN.W.D VSRARN.B.H VSRARN.H.W VSRARN.W.D
+// Sched<[WriteVSHIFTRN128, ReadVSHIFTRN128, ReadVSHIFTRN128]>
+// XVSRLRN.B.H XVSRLRN.H.W XVSRLRN.W.D XVSRARN.B.H XVSRARN.H.W
+// XVSRARN.W.D
+// Sched<[WriteVSHIFTRN256, ReadVSHIFTRN256, ReadVSHIFTRN256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTRNI128 : SchedWrite; // 128-bit round narrow shf by imm
+def WriteVSHIFTRNI256 : SchedWrite; // 256-bit round narrow shf by imm
+def ReadVSHIFTRNI128 : SchedRead; // 128-bit round narrow shf by imm
+def ReadVSHIFTRNI256 : SchedRead; // 256-bit round narrow shf by imm
+//===----------------------------------------------------------------------===//
+// VSRLRNI.B.H VSRLRNI.H.W VSRLRNI.W.D VSRARNI.B.H VSRARNI.H.W
+// VSRARNI.W.D
+// Sched<[WriteVSHIFTRNI128, ReadVSHIFTRNI128, ReadVSHIFTRNI128]>
+// XVSRLRNI.B.H XVSRLRNI.H.W XVSRLRNI.W.D XVSRARNI.B.H XVSRARNI.H.W
+// XVSRARNI.W.D
+// Sched<[WriteVSHIFTRNI256, ReadVSHIFTRNI256, ReadVSHIFTRNI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTRNIQ128 : SchedWrite; // 128-bit quadword rnd narrow imm
+def WriteVSHIFTRNIQ256 : SchedWrite; // 256-bit quadword rnd narrow imm
+def ReadVSHIFTRNIQ128 : SchedRead; // 128-bit quadword rnd narrow imm
+def ReadVSHIFTRNIQ256 : SchedRead; // 256-bit quadword rnd narrow imm
+//===----------------------------------------------------------------------===//
+// VSRLRNI.D.Q VSRARNI.D.Q
+// Sched<[WriteVSHIFTRNIQ128, ReadVSHIFTRNIQ128, ReadVSHIFTRNIQ128]>
+// XVSRLRNI.D.Q XVSRARNI.D.Q
+// Sched<[WriteVSHIFTRNIQ256, ReadVSHIFTRNIQ256, ReadVSHIFTRNIQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTNS128 : SchedWrite; // 128-bit sat narrowing shift
+def WriteVSHIFTNS256 : SchedWrite; // 256-bit sat narrowing shift
+def ReadVSHIFTNS128 : SchedRead; // 128-bit sat narrowing shift
+def ReadVSHIFTNS256 : SchedRead; // 256-bit sat narrowing shift
+//===----------------------------------------------------------------------===//
+// VSSRLN.B.H VSSRLN.H.W VSSRLN.W.D VSSRAN.B.H VSSRAN.H.W VSSRAN.W.D
+// VSSRLN.BU.H VSSRLN.HU.W VSSRLN.WU.D VSSRAN.BU.H VSSRAN.HU.W
+// VSSRAN.WU.D
+// Sched<[WriteVSHIFTNS128, ReadVSHIFTNS128, ReadVSHIFTNS128]>
+// XVSSRLN.B.H XVSSRLN.H.W XVSSRLN.W.D XVSSRAN.B.H XVSSRAN.H.W
+// XVSSRAN.W.D XVSSRLN.BU.H XVSSRLN.HU.W XVSSRLN.WU.D XVSSRAN.BU.H
+// XVSSRAN.HU.W XVSSRAN.WU.D
+// Sched<[WriteVSHIFTNS256, ReadVSHIFTNS256, ReadVSHIFTNS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTNSI128 : SchedWrite; // 128-bit sat narrow shf by imm
+def WriteVSHIFTNSI256 : SchedWrite; // 256-bit sat narrow shf by imm
+def ReadVSHIFTNSI128 : SchedRead; // 128-bit sat narrow shf by imm
+def ReadVSHIFTNSI256 : SchedRead; // 256-bit sat narrow shf by imm
+//===----------------------------------------------------------------------===//
+// VSSRLNI.B.H VSSRLNI.H.W VSSRLNI.W.D VSSRANI.B.H VSSRANI.H.W
+// VSSRANI.W.D VSSRLNI.BU.H VSSRLNI.HU.W VSSRLNI.WU.D VSSRANI.BU.H
+// VSSRANI.HU.W VSSRANI.WU.D
+// Sched<[WriteVSHIFTNSI128, ReadVSHIFTNSI128, ReadVSHIFTNSI128]>
+// XVSSRLNI.B.H XVSSRLNI.H.W XVSSRLNI.W.D XVSSRANI.B.H XVSSRANI.H.W
+// XVSSRANI.W.D XVSSRLNI.BU.H XVSSRLNI.HU.W XVSSRLNI.WU.D XVSSRANI.BU.H
+// XVSSRANI.HU.W XVSSRANI.WU.D
+// Sched<[WriteVSHIFTNSI256, ReadVSHIFTNSI256, ReadVSHIFTNSI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTNSIQ128 : SchedWrite; // 128-bit quadword sat narrow imm
+def WriteVSHIFTNSIQ256 : SchedWrite; // 256-bit quadword sat narrow imm
+def ReadVSHIFTNSIQ128 : SchedRead; // 128-bit quadword sat narrow imm
+def ReadVSHIFTNSIQ256 : SchedRead; // 256-bit quadword sat narrow imm
+//===----------------------------------------------------------------------===//
+// VSSRLNI.D.Q VSSRANI.D.Q VSSRLNI.DU.Q VSSRANI.DU.Q
+// Sched<[WriteVSHIFTNSIQ128, ReadVSHIFTNSIQ128, ReadVSHIFTNSIQ128]>
+// XVSSRLNI.D.Q XVSSRANI.D.Q XVSSRLNI.DU.Q XVSSRANI.DU.Q
+// Sched<[WriteVSHIFTNSIQ256, ReadVSHIFTNSIQ256, ReadVSHIFTNSIQ256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTRNS128 : SchedWrite; // 128-bit round sat narrow shift
+def WriteVSHIFTRNS256 : SchedWrite; // 256-bit round sat narrow shift
+def ReadVSHIFTRNS128 : SchedRead; // 128-bit round sat narrow shift
+def ReadVSHIFTRNS256 : SchedRead; // 256-bit round sat narrow shift
+//===----------------------------------------------------------------------===//
+// VSSRLRN.B.H VSSRLRN.H.W VSSRLRN.W.D VSSRARN.B.H VSSRARN.H.W
+// VSSRARN.W.D VSSRLRN.BU.H VSSRLRN.HU.W VSSRLRN.WU.D VSSRARN.BU.H
+// VSSRARN.HU.W VSSRARN.WU.D
+// Sched<[WriteVSHIFTRNS128, ReadVSHIFTRNS128, ReadVSHIFTRNS128]>
+// XVSSRLRN.B.H XVSSRLRN.H.W XVSSRLRN.W.D XVSSRARN.B.H XVSSRARN.H.W
+// XVSSRARN.W.D XVSSRLRN.BU.H XVSSRLRN.HU.W XVSSRLRN.WU.D XVSSRARN.BU.H
+// XVSSRARN.HU.W XVSSRARN.WU.D
+// Sched<[WriteVSHIFTRNS256, ReadVSHIFTRNS256, ReadVSHIFTRNS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTRNSI128 : SchedWrite; // 128-bit rnd sat narrow shf imm
+def WriteVSHIFTRNSI256 : SchedWrite; // 256-bit rnd sat narrow shf imm
+def ReadVSHIFTRNSI128 : SchedRead; // 128-bit rnd sat narrow shf imm
+def ReadVSHIFTRNSI256 : SchedRead; // 256-bit rnd sat narrow shf imm
+//===----------------------------------------------------------------------===//
+// VSSRLRNI.B.H VSSRLRNI.H.W VSSRLRNI.W.D VSSRARNI.B.H VSSRARNI.H.W
+// VSSRARNI.W.D VSSRLRNI.BU.H VSSRLRNI.HU.W VSSRLRNI.WU.D VSSRARNI.BU.H
+// VSSRARNI.HU.W VSSRARNI.WU.D
+// Sched<[WriteVSHIFTRNSI128, ReadVSHIFTRNSI128, ReadVSHIFTRNSI128]>
+// XVSSRLRNI.B.H XVSSRLRNI.H.W XVSSRLRNI.W.D XVSSRARNI.B.H XVSSRARNI.H.W
+// XVSSRARNI.W.D XVSSRLRNI.BU.H XVSSRLRNI.HU.W XVSSRLRNI.WU.D
+// XVSSRARNI.BU.H XVSSRARNI.HU.W XVSSRARNI.WU.D
+// Sched<[WriteVSHIFTRNSI256, ReadVSHIFTRNSI256, ReadVSHIFTRNSI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHIFTRNSIQ128 : SchedWrite; // 128-bit quadword rnd sat narrow
+def WriteVSHIFTRNSIQ256 : SchedWrite; // 256-bit quadword rnd sat narrow
+def ReadVSHIFTRNSIQ128 : SchedRead; // 128-bit quadword rnd sat narrow
+def ReadVSHIFTRNSIQ256 : SchedRead; // 256-bit quadword rnd sat narrow
+//===----------------------------------------------------------------------===//
+// VSSRLRNI.D.Q VSSRARNI.D.Q VSSRLRNI.DU.Q VSSRARNI.DU.Q
+// Sched<[WriteVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128, ReadVSHIFTRNSIQ128]>
+// XVSSRLRNI.D.Q XVSSRARNI.D.Q XVSSRLRNI.DU.Q XVSSRARNI.DU.Q
+// Sched<[WriteVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256, ReadVSHIFTRNSIQ256]>
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+/// Vector shuffle, permute and element move
+//===----------------------------------------------------------------------===//
+
+def WriteVPACK128 : SchedWrite; // 128-bit interleave / pack
+def WriteVPACK256 : SchedWrite; // 256-bit interleave / pack
+def ReadVPACK128 : SchedRead; // 128-bit interleave / pack
+def ReadVPACK256 : SchedRead; // 256-bit interleave / pack
+//===----------------------------------------------------------------------===//
+// VPACKEV.B VPACKEV.H VPACKEV.W VPACKEV.D VPACKOD.B VPACKOD.H
+// VPACKOD.W VPACKOD.D VPICKEV.B VPICKEV.H VPICKEV.W VPICKEV.D
+// VPICKOD.B VPICKOD.H VPICKOD.W VPICKOD.D VILVL.B VILVL.H VILVL.W
+// VILVL.D VILVH.B VILVH.H VILVH.W VILVH.D
+// Sched<[WriteVPACK128, ReadVPACK128, ReadVPACK128]>
+// XVPACKEV.B XVPACKEV.H XVPACKEV.W XVPACKEV.D XVPACKOD.B XVPACKOD.H
+// XVPACKOD.W XVPACKOD.D XVPICKEV.B XVPICKEV.H XVPICKEV.W XVPICKEV.D
+// XVPICKOD.B XVPICKOD.H XVPICKOD.W XVPICKOD.D XVILVL.B XVILVL.H
+// XVILVL.W XVILVL.D XVILVH.B XVILVH.H XVILVH.W XVILVH.D
+// Sched<[WriteVPACK256, ReadVPACK256, ReadVPACK256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHUF128 : SchedWrite; // 128-bit shuffle by register
+def WriteVSHUF256 : SchedWrite; // 256-bit shuffle by register
+def ReadVSHUF128 : SchedRead; // 128-bit shuffle by register
+def ReadVSHUF256 : SchedRead; // 256-bit shuffle by register
+//===----------------------------------------------------------------------===//
+// VSHUF.B VSHUF.H VSHUF.W VSHUF.D
+// Sched<[WriteVSHUF128, ReadVSHUF128, ReadVSHUF128, ReadVSHUF128]>
+// XVSHUF.B XVSHUF.H XVSHUF.W XVSHUF.D
+// Sched<[WriteVSHUF256, ReadVSHUF256, ReadVSHUF256, ReadVSHUF256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSHUF4I128 : SchedWrite; // 128-bit shuffle by immediate
+def WriteVSHUF4I256 : SchedWrite; // 256-bit shuffle by immediate
+def ReadVSHUF4I128 : SchedRead; // 128-bit shuffle by immediate
+def ReadVSHUF4I256 : SchedRead; // 256-bit shuffle by immediate
+//===----------------------------------------------------------------------===//
+// VSHUF4I.B VSHUF4I.H VSHUF4I.W
+// Sched<[WriteVSHUF4I128, ReadVSHUF4I128]>
+// VSHUF4I.D
+// Sched<[WriteVSHUF4I128, ReadVSHUF4I128, ReadVSHUF4I128]>
+// XVSHUF4I.B XVSHUF4I.H XVSHUF4I.W
+// Sched<[WriteVSHUF4I256, ReadVSHUF4I256]>
+// XVSHUF4I.D
+// Sched<[WriteVSHUF4I256, ReadVSHUF4I256, ReadVSHUF4I256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVHSELI256 : SchedWrite; // 256-bit half select by imm
+def ReadVHSELI256 : SchedRead; // 256-bit half select by imm
+//===----------------------------------------------------------------------===//
+// XVHSELI.D
+// Sched<[WriteVHSELI256, ReadVHSELI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVPERMI128 : SchedWrite; // 128-bit lane permute by imm
+def WriteVPERMI256 : SchedWrite; // 256-bit lane permute by imm
+def ReadVPERMI128 : SchedRead; // 128-bit lane permute by imm
+def ReadVPERMI256 : SchedRead; // 256-bit lane permute by imm
+//===----------------------------------------------------------------------===//
+// VPERMI.W
+// Sched<[WriteVPERMI128, ReadVPERMI128, ReadVPERMI128]>
+// XVPERMI.W
+// Sched<[WriteVPERMI256, ReadVPERMI256, ReadVPERMI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVPERM256 : SchedWrite; // 256-bit cross-lane permute
+def ReadVPERM256 : SchedRead; // 256-bit cross-lane permute
+//===----------------------------------------------------------------------===//
+// XVPERM.W XVPERMI.Q
+// Sched<[WriteVPERM256, ReadVPERM256, ReadVPERM256]>
+// XVPERMI.D
+// Sched<[WriteVPERM256, ReadVPERM256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVEXTRINS128 : SchedWrite; // 128-bit element extract + insert
+def WriteVEXTRINS256 : SchedWrite; // 256-bit element extract + insert
+def ReadVEXTRINS128 : SchedRead; // 128-bit element extract + insert
+def ReadVEXTRINS256 : SchedRead; // 256-bit element extract + insert
+//===----------------------------------------------------------------------===//
+// VEXTRINS.D VEXTRINS.W VEXTRINS.H VEXTRINS.B
+// Sched<[WriteVEXTRINS128, ReadVEXTRINS128, ReadVEXTRINS128]>
+// XVEXTRINS.D XVEXTRINS.W XVEXTRINS.H XVEXTRINS.B
+// Sched<[WriteVEXTRINS256, ReadVEXTRINS256, ReadVEXTRINS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVPICKVE256 : SchedWrite; // 256-bit cross-lane elem pick
+def ReadVPICKVE256 : SchedRead; // 256-bit cross-lane elem pick
+//===----------------------------------------------------------------------===//
+// XVPICKVE.W XVPICKVE.D
+// Sched<[WriteVPICKVE256, ReadVPICKVE256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVINSVE0256 : SchedWrite; // 256-bit cross-lane elem insert
+def ReadVINSVE0256 : SchedRead; // 256-bit cross-lane elem insert
+//===----------------------------------------------------------------------===//
+// XVINSVE0.W XVINSVE0.D
+// Sched<[WriteVINSVE0256, ReadVINSVE0256, ReadVINSVE0256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVREPLVE0256 : SchedWrite; // 256-bit cross-lane broadcast
+def ReadVREPLVE0256 : SchedRead; // 256-bit cross-lane broadcast
+//===----------------------------------------------------------------------===//
+// XVREPLVE0.B XVREPLVE0.H XVREPLVE0.W XVREPLVE0.D XVREPLVE0.Q
+// Sched<[WriteVREPLVE0256, ReadVREPLVE0256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVREPLVEI128 : SchedWrite; // 128-bit elem broadcast by imm
+def WriteVREPLVEI256 : SchedWrite; // 256-bit elem broadcast by imm
+def ReadVREPLVEI128 : SchedRead; // 128-bit elem broadcast by imm
+def ReadVREPLVEI256 : SchedRead; // 256-bit elem broadcast by imm
+//===----------------------------------------------------------------------===//
+// VREPLVEI.B VREPLVEI.H VREPLVEI.W VREPLVEI.D
+// Sched<[WriteVREPLVEI128, ReadVREPLVEI128]>
+// XVREPL128VEI.B XVREPL128VEI.H XVREPL128VEI.W XVREPL128VEI.D
+// Sched<[WriteVREPLVEI256, ReadVREPLVEI256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVREPLVE128 : SchedWrite; // 128-bit elem broadcast by reg
+def WriteVREPLVE256 : SchedWrite; // 256-bit elem broadcast by reg
+def ReadVREPLVE128 : SchedRead; // 128-bit elem broadcast by reg
+def ReadVREPLVE256 : SchedRead; // 256-bit elem broadcast by reg
+//===----------------------------------------------------------------------===//
+// VREPLVE.B VREPLVE.H VREPLVE.W VREPLVE.D
+// Sched<[WriteVREPLVE128, ReadVREPLVE128, ReadVREPLVE128]>
+// XVREPLVE.B XVREPLVE.H XVREPLVE.W XVREPLVE.D
+// Sched<[WriteVREPLVE256, ReadVREPLVE256, ReadVREPLVE256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVREPLGR2VR128 : SchedWrite; // 128-bit B/H broadcast from GPR
+def WriteVREPLGR2VR256 : SchedWrite; // 256-bit B/H broadcast from GPR
+def ReadVREPLGR2VR128 : SchedRead; // 128-bit B/H broadcast from GPR
+def ReadVREPLGR2VR256 : SchedRead; // 256-bit B/H broadcast from GPR
+//===----------------------------------------------------------------------===//
+// VREPLGR2VR.B VREPLGR2VR.H
+// Sched<[WriteVREPLGR2VR128, ReadVREPLGR2VR128]>
+// XVREPLGR2VR.B XVREPLGR2VR.H
+// Sched<[WriteVREPLGR2VR256, ReadVREPLGR2VR256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVREPLGR2VRWD128 : SchedWrite; // 128-bit W/D broadcast from GPR
+def WriteVREPLGR2VRWD256 : SchedWrite; // 256-bit W/D broadcast from GPR
+def ReadVREPLGR2VRWD128 : SchedRead; // 128-bit W/D broadcast from GPR
+def ReadVREPLGR2VRWD256 : SchedRead; // 256-bit W/D broadcast from GPR
+//===----------------------------------------------------------------------===//
+// VREPLGR2VR.W VREPLGR2VR.D
+// Sched<[WriteVREPLGR2VRWD128, ReadVREPLGR2VRWD128]>
+// XVREPLGR2VR.W XVREPLGR2VR.D
+// Sched<[WriteVREPLGR2VRWD256, ReadVREPLGR2VRWD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVINSGR2VR128 : SchedWrite; // 128-bit elem insert from GPR
+def WriteVINSGR2VR256 : SchedWrite; // 256-bit elem insert from GPR
+def ReadVINSGR2VR128 : SchedRead; // 128-bit elem insert from GPR
+def ReadVINSGR2VR256 : SchedRead; // 256-bit elem insert from GPR
+//===----------------------------------------------------------------------===//
+// VINSGR2VR.B VINSGR2VR.H VINSGR2VR.W VINSGR2VR.D
+// Sched<[WriteVINSGR2VR128, ReadVINSGR2VR128, ReadVINSGR2VR128]>
+// XVINSGR2VR.W XVINSGR2VR.D
+// Sched<[WriteVINSGR2VR256, ReadVINSGR2VR256, ReadVINSGR2VR256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVPICKVE2GR128 : SchedWrite; // 128-bit elem extract to GPR
+def WriteVPICKVE2GR256 : SchedWrite; // 256-bit elem extract to GPR
+def ReadVPICKVE2GR128 : SchedRead; // 128-bit elem extract to GPR
+def ReadVPICKVE2GR256 : SchedRead; // 256-bit elem extract to GPR
+//===----------------------------------------------------------------------===//
+// VPICKVE2GR.B VPICKVE2GR.H VPICKVE2GR.W VPICKVE2GR.D VPICKVE2GR.BU
+// VPICKVE2GR.HU VPICKVE2GR.WU VPICKVE2GR.DU
+// Sched<[WriteVPICKVE2GR128, ReadVPICKVE2GR128]>
+// XVPICKVE2GR.W XVPICKVE2GR.D XVPICKVE2GR.WU XVPICKVE2GR.DU
+// Sched<[WriteVPICKVE2GR256, ReadVPICKVE2GR256]>
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+/// Vector floating-point arithmetic
+//===----------------------------------------------------------------------===//
+
+def WriteVFADD128 : SchedWrite; // 128-bit FP add / sub
+def WriteVFADD256 : SchedWrite; // 256-bit FP add / sub
+def ReadVFADD128 : SchedRead; // 128-bit FP add / sub
+def ReadVFADD256 : SchedRead; // 256-bit FP add / sub
+//===----------------------------------------------------------------------===//
+// VFADD.S VFADD.D VFSUB.S VFSUB.D
+// Sched<[WriteVFADD128, ReadVFADD128, ReadVFADD128]>
+// XVFADD.S XVFADD.D XVFSUB.S XVFSUB.D
+// Sched<[WriteVFADD256, ReadVFADD256, ReadVFADD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFMUL128 : SchedWrite; // 128-bit FP multiply
+def WriteVFMUL256 : SchedWrite; // 256-bit FP multiply
+def ReadVFMUL128 : SchedRead; // 128-bit FP multiply
+def ReadVFMUL256 : SchedRead; // 256-bit FP multiply
+//===----------------------------------------------------------------------===//
+// VFMUL.S VFMUL.D
+// Sched<[WriteVFMUL128, ReadVFMUL128, ReadVFMUL128]>
+// XVFMUL.S XVFMUL.D
+// Sched<[WriteVFMUL256, ReadVFMUL256, ReadVFMUL256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFMADD128 : SchedWrite; // 128-bit FP fused multiply-add
+def WriteVFMADD256 : SchedWrite; // 256-bit FP fused multiply-add
+def ReadVFMADD128 : SchedRead; // 128-bit FP fused multiply-add
+def ReadVFMADD256 : SchedRead; // 256-bit FP fused multiply-add
+//===----------------------------------------------------------------------===//
+// VFMADD.S VFMADD.D VFMSUB.S VFMSUB.D VFNMADD.S VFNMADD.D VFNMSUB.S
+// VFNMSUB.D
+// Sched<[WriteVFMADD128, ReadVFMADD128, ReadVFMADD128, ReadVFMADD128]>
+// XVFMADD.S XVFMADD.D XVFMSUB.S XVFMSUB.D XVFNMADD.S XVFNMADD.D
+// XVFNMSUB.S XVFNMSUB.D
+// Sched<[WriteVFMADD256, ReadVFMADD256, ReadVFMADD256, ReadVFMADD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFMINMAX128 : SchedWrite; // 128-bit FP min / max
+def WriteVFMINMAX256 : SchedWrite; // 256-bit FP min / max
+def ReadVFMINMAX128 : SchedRead; // 128-bit FP min / max
+def ReadVFMINMAX256 : SchedRead; // 256-bit FP min / max
+//===----------------------------------------------------------------------===//
+// VFMAX.S VFMAX.D VFMIN.S VFMIN.D VFMAXA.S VFMAXA.D VFMINA.S
+// VFMINA.D
+// Sched<[WriteVFMINMAX128, ReadVFMINMAX128, ReadVFMINMAX128]>
+// XVFMAX.S XVFMAX.D XVFMIN.S XVFMIN.D XVFMAXA.S XVFMAXA.D XVFMINA.S
+// XVFMINA.D
+// Sched<[WriteVFMINMAX256, ReadVFMINMAX256, ReadVFMINMAX256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFCLASS128 : SchedWrite; // 128-bit FP class
+def WriteVFCLASS256 : SchedWrite; // 256-bit FP class
+def ReadVFCLASS128 : SchedRead; // 128-bit FP class
+def ReadVFCLASS256 : SchedRead; // 256-bit FP class
+//===----------------------------------------------------------------------===//
+// VFCLASS.S VFCLASS.D
+// Sched<[WriteVFCLASS128, ReadVFCLASS128]>
+// XVFCLASS.S XVFCLASS.D
+// Sched<[WriteVFCLASS256, ReadVFCLASS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFLOGB128 : SchedWrite; // 128-bit FP exponent extract
+def WriteVFLOGB256 : SchedWrite; // 256-bit FP exponent extract
+def ReadVFLOGB128 : SchedRead; // 128-bit FP exponent extract
+def ReadVFLOGB256 : SchedRead; // 256-bit FP exponent extract
+//===----------------------------------------------------------------------===//
+// VFLOGB.S VFLOGB.D
+// Sched<[WriteVFLOGB128, ReadVFLOGB128]>
+// XVFLOGB.S XVFLOGB.D
+// Sched<[WriteVFLOGB256, ReadVFLOGB256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFDIVS128 : SchedWrite; // 128-bit FP single divide
+def WriteVFDIVS256 : SchedWrite; // 256-bit FP single divide
+def ReadVFDIVS128 : SchedRead; // 128-bit FP single divide
+def ReadVFDIVS256 : SchedRead; // 256-bit FP single divide
+//===----------------------------------------------------------------------===//
+// VFDIV.S
+// Sched<[WriteVFDIVS128, ReadVFDIVS128, ReadVFDIVS128]>
+// XVFDIV.S
+// Sched<[WriteVFDIVS256, ReadVFDIVS256, ReadVFDIVS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFDIVD128 : SchedWrite; // 128-bit FP double divide
+def WriteVFDIVD256 : SchedWrite; // 256-bit FP double divide
+def ReadVFDIVD128 : SchedRead; // 128-bit FP double divide
+def ReadVFDIVD256 : SchedRead; // 256-bit FP double divide
+//===----------------------------------------------------------------------===//
+// VFDIV.D
+// Sched<[WriteVFDIVD128, ReadVFDIVD128, ReadVFDIVD128]>
+// XVFDIV.D
+// Sched<[WriteVFDIVD256, ReadVFDIVD256, ReadVFDIVD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFSQRTS128 : SchedWrite; // 128-bit FP single sqrt
+def WriteVFSQRTS256 : SchedWrite; // 256-bit FP single sqrt
+def ReadVFSQRTS128 : SchedRead; // 128-bit FP single sqrt
+def ReadVFSQRTS256 : SchedRead; // 256-bit FP single sqrt
+//===----------------------------------------------------------------------===//
+// VFSQRT.S
+// Sched<[WriteVFSQRTS128, ReadVFSQRTS128]>
+// XVFSQRT.S
+// Sched<[WriteVFSQRTS256, ReadVFSQRTS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFSQRTD128 : SchedWrite; // 128-bit FP double sqrt
+def WriteVFSQRTD256 : SchedWrite; // 256-bit FP double sqrt
+def ReadVFSQRTD128 : SchedRead; // 128-bit FP double sqrt
+def ReadVFSQRTD256 : SchedRead; // 256-bit FP double sqrt
+//===----------------------------------------------------------------------===//
+// VFSQRT.D
+// Sched<[WriteVFSQRTD128, ReadVFSQRTD128]>
+// XVFSQRT.D
+// Sched<[WriteVFSQRTD256, ReadVFSQRTD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRECIPS128 : SchedWrite; // 128-bit FP single recip
+def WriteVFRECIPS256 : SchedWrite; // 256-bit FP single recip
+def ReadVFRECIPS128 : SchedRead; // 128-bit FP single recip
+def ReadVFRECIPS256 : SchedRead; // 256-bit FP single recip
+//===----------------------------------------------------------------------===//
+// VFRECIP.S
+// Sched<[WriteVFRECIPS128, ReadVFRECIPS128]>
+// XVFRECIP.S
+// Sched<[WriteVFRECIPS256, ReadVFRECIPS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRECIPD128 : SchedWrite; // 128-bit FP double recip
+def WriteVFRECIPD256 : SchedWrite; // 256-bit FP double recip
+def ReadVFRECIPD128 : SchedRead; // 128-bit FP double recip
+def ReadVFRECIPD256 : SchedRead; // 256-bit FP double recip
+//===----------------------------------------------------------------------===//
+// VFRECIP.D
+// Sched<[WriteVFRECIPD128, ReadVFRECIPD128]>
+// XVFRECIP.D
+// Sched<[WriteVFRECIPD256, ReadVFRECIPD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRSQRTS128 : SchedWrite; // 128-bit FP single rsqrt
+def WriteVFRSQRTS256 : SchedWrite; // 256-bit FP single rsqrt
+def ReadVFRSQRTS128 : SchedRead; // 128-bit FP single rsqrt
+def ReadVFRSQRTS256 : SchedRead; // 256-bit FP single rsqrt
+//===----------------------------------------------------------------------===//
+// VFRSQRT.S
+// Sched<[WriteVFRSQRTS128, ReadVFRSQRTS128]>
+// XVFRSQRT.S
+// Sched<[WriteVFRSQRTS256, ReadVFRSQRTS256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRSQRTD128 : SchedWrite; // 128-bit FP double rsqrt
+def WriteVFRSQRTD256 : SchedWrite; // 256-bit FP double rsqrt
+def ReadVFRSQRTD128 : SchedRead; // 128-bit FP double rsqrt
+def ReadVFRSQRTD256 : SchedRead; // 256-bit FP double rsqrt
+//===----------------------------------------------------------------------===//
+// VFRSQRT.D
+// Sched<[WriteVFRSQRTD128, ReadVFRSQRTD128]>
+// XVFRSQRT.D
+// Sched<[WriteVFRSQRTD256, ReadVFRSQRTD256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRECIPE128 : SchedWrite; // 128-bit FP approximate recip
+def WriteVFRECIPE256 : SchedWrite; // 256-bit FP approximate recip
+def ReadVFRECIPE128 : SchedRead; // 128-bit FP approximate recip
+def ReadVFRECIPE256 : SchedRead; // 256-bit FP approximate recip
+//===----------------------------------------------------------------------===//
+// VFRECIPE.S VFRECIPE.D
+// Sched<[WriteVFRECIPE128, ReadVFRECIPE128]>
+// XVFRECIPE.S XVFRECIPE.D
+// Sched<[WriteVFRECIPE256, ReadVFRECIPE256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRSQRTE128 : SchedWrite; // 128-bit FP approximate rsqrt
+def WriteVFRSQRTE256 : SchedWrite; // 256-bit FP approximate rsqrt
+def ReadVFRSQRTE128 : SchedRead; // 128-bit FP approximate rsqrt
+def ReadVFRSQRTE256 : SchedRead; // 256-bit FP approximate rsqrt
+//===----------------------------------------------------------------------===//
+// VFRSQRTE.S VFRSQRTE.D
+// Sched<[WriteVFRSQRTE128, ReadVFRSQRTE128]>
+// XVFRSQRTE.S XVFRSQRTE.D
+// Sched<[WriteVFRSQRTE256, ReadVFRSQRTE256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFRINT128 : SchedWrite; // 128-bit FP round to integer
+def WriteVFRINT256 : SchedWrite; // 256-bit FP round to integer
+def ReadVFRINT128 : SchedRead; // 128-bit FP round to integer
+def ReadVFRINT256 : SchedRead; // 256-bit FP round to integer
+//===----------------------------------------------------------------------===//
+// VFRINTRNE.S VFRINTRNE.D VFRINTRZ.S VFRINTRZ.D VFRINTRP.S VFRINTRP.D
+// VFRINTRM.S VFRINTRM.D VFRINT.S VFRINT.D
+// Sched<[WriteVFRINT128, ReadVFRINT128]>
+// XVFRINTRNE.S XVFRINTRNE.D XVFRINTRZ.S XVFRINTRZ.D XVFRINTRP.S
+// XVFRINTRP.D XVFRINTRM.S XVFRINTRM.D XVFRINT.S XVFRINT.D
+// Sched<[WriteVFRINT256, ReadVFRINT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFCVT128 : SchedWrite; // 128-bit FP precision convert
+def WriteVFCVT256 : SchedWrite; // 256-bit FP precision convert
+def ReadVFCVT128 : SchedRead; // 128-bit FP precision convert
+def ReadVFCVT256 : SchedRead; // 256-bit FP precision convert
+//===----------------------------------------------------------------------===//
+// VFCVTL.S.H VFCVTH.S.H VFCVTL.D.S VFCVTH.D.S
+// Sched<[WriteVFCVT128, ReadVFCVT128]>
+// VFCVT.H.S VFCVT.S.D
+// Sched<[WriteVFCVT128, ReadVFCVT128, ReadVFCVT128]>
+// XVFCVTL.S.H XVFCVTH.S.H XVFCVTL.D.S XVFCVTH.D.S
+// Sched<[WriteVFCVT256, ReadVFCVT256]>
+// XVFCVT.H.S XVFCVT.S.D
+// Sched<[WriteVFCVT256, ReadVFCVT256, ReadVFCVT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFTINT128 : SchedWrite; // 128-bit FP to integer convert
+def WriteVFTINT256 : SchedWrite; // 256-bit FP to integer convert
+def ReadVFTINT128 : SchedRead; // 128-bit FP to integer convert
+def ReadVFTINT256 : SchedRead; // 256-bit FP to integer convert
+//===----------------------------------------------------------------------===//
+// VFTINTRNE.W.S VFTINTRNE.L.D VFTINTRZ.W.S VFTINTRZ.L.D VFTINTRP.W.S
+// VFTINTRP.L.D VFTINTRM.W.S VFTINTRM.L.D VFTINT.W.S VFTINT.L.D
+// VFTINTRZ.WU.S VFTINTRZ.LU.D VFTINT.WU.S VFTINT.LU.D
+// Sched<[WriteVFTINT128, ReadVFTINT128]>
+// XVFTINTRNE.W.S XVFTINTRNE.L.D XVFTINTRZ.W.S XVFTINTRZ.L.D
+// XVFTINTRP.W.S XVFTINTRP.L.D XVFTINTRM.W.S XVFTINTRM.L.D XVFTINT.W.S
+// XVFTINT.L.D XVFTINTRZ.WU.S XVFTINTRZ.LU.D XVFTINT.WU.S XVFTINT.LU.D
+// Sched<[WriteVFTINT256, ReadVFTINT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFTINTX128 : SchedWrite; // 128-bit FP to integer, resized
+def WriteVFTINTX256 : SchedWrite; // 256-bit FP to integer, resized
+def ReadVFTINTX128 : SchedRead; // 128-bit FP to integer, resized
+def ReadVFTINTX256 : SchedRead; // 256-bit FP to integer, resized
+//===----------------------------------------------------------------------===//
+// VFTINTRNE.W.D VFTINTRZ.W.D VFTINTRP.W.D VFTINTRM.W.D VFTINT.W.D
+// Sched<[WriteVFTINTX128, ReadVFTINTX128, ReadVFTINTX128]>
+// VFTINTRNEL.L.S VFTINTRNEH.L.S VFTINTRZL.L.S VFTINTRZH.L.S
+// VFTINTRPL.L.S VFTINTRPH.L.S VFTINTRML.L.S VFTINTRMH.L.S VFTINTL.L.S
+// VFTINTH.L.S
+// Sched<[WriteVFTINTX128, ReadVFTINTX128]>
+// XVFTINTRNE.W.D XVFTINTRZ.W.D XVFTINTRP.W.D XVFTINTRM.W.D XVFTINT.W.D
+// Sched<[WriteVFTINTX256, ReadVFTINTX256, ReadVFTINTX256]>
+// XVFTINTRNEL.L.S XVFTINTRNEH.L.S XVFTINTRZL.L.S XVFTINTRZH.L.S
+// XVFTINTRPL.L.S XVFTINTRPH.L.S XVFTINTRML.L.S XVFTINTRMH.L.S
+// XVFTINTL.L.S XVFTINTH.L.S
+// Sched<[WriteVFTINTX256, ReadVFTINTX256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFFINT128 : SchedWrite; // 128-bit integer to FP convert
+def WriteVFFINT256 : SchedWrite; // 256-bit integer to FP convert
+def ReadVFFINT128 : SchedRead; // 128-bit integer to FP convert
+def ReadVFFINT256 : SchedRead; // 256-bit integer to FP convert
+//===----------------------------------------------------------------------===//
+// VFFINT.S.W VFFINT.D.L VFFINT.S.WU VFFINT.D.LU
+// Sched<[WriteVFFINT128, ReadVFFINT128]>
+// XVFFINT.S.W XVFFINT.D.L XVFFINT.S.WU XVFFINT.D.LU
+// Sched<[WriteVFFINT256, ReadVFFINT256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVFFINTX128 : SchedWrite; // 128-bit integer to FP, resized
+def WriteVFFINTX256 : SchedWrite; // 256-bit integer to FP, resized
+def ReadVFFINTX128 : SchedRead; // 128-bit integer to FP, resized
+def ReadVFFINTX256 : SchedRead; // 256-bit integer to FP, resized
+//===----------------------------------------------------------------------===//
+// VFFINTL.D.W VFFINTH.D.W
+// Sched<[WriteVFFINTX128, ReadVFFINTX128]>
+// VFFINT.S.L
+// Sched<[WriteVFFINTX128, ReadVFFINTX128, ReadVFFINTX128]>
+// XVFFINTL.D.W XVFFINTH.D.W
+// Sched<[WriteVFFINTX256, ReadVFFINTX256]>
+// XVFFINT.S.L
+// Sched<[WriteVFFINTX256, ReadVFFINTX256, ReadVFFINTX256]>
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+/// Vector memory access
+//===----------------------------------------------------------------------===//
+
+def WriteVLD128 : SchedWrite; // 128-bit load, reg+imm
+def WriteVLD256 : SchedWrite; // 256-bit load, reg+imm
+//===----------------------------------------------------------------------===//
+// VLD
+// Sched<[WriteVLD128, ReadVMemBase128]>
+// XVLD
+// Sched<[WriteVLD256, ReadVMemBase256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVLDX128 : SchedWrite; // 128-bit load, reg+reg
+def WriteVLDX256 : SchedWrite; // 256-bit load, reg+reg
+//===----------------------------------------------------------------------===//
+// VLDX
+// Sched<[WriteVLDX128, ReadVMemBase128, ReadVMemOffset128]>
+// XVLDX
+// Sched<[WriteVLDX256, ReadVMemBase256, ReadVMemOffset256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVLDREPL128 : SchedWrite; // 128-bit load and broadcast
+def WriteVLDREPL256 : SchedWrite; // 256-bit load and broadcast
+//===----------------------------------------------------------------------===//
+// VLDREPL.B VLDREPL.H VLDREPL.W VLDREPL.D
+// Sched<[WriteVLDREPL128, ReadVMemBase128]>
+// XVLDREPL.B XVLDREPL.H XVLDREPL.W XVLDREPL.D
+// Sched<[WriteVLDREPL256, ReadVMemBase256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVST128 : SchedWrite; // 128-bit store, reg+imm
+def WriteVST256 : SchedWrite; // 256-bit store, reg+imm
+//===----------------------------------------------------------------------===//
+// VST
+// Sched<[WriteVST128, ReadVSTData128, ReadVMemBase128]>
+// XVST
+// Sched<[WriteVST256, ReadVSTData256, ReadVMemBase256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSTX128 : SchedWrite; // 128-bit store, reg+reg
+def WriteVSTX256 : SchedWrite; // 256-bit store, reg+reg
+//===----------------------------------------------------------------------===//
+// VSTX
+// Sched<[WriteVSTX128, ReadVSTData128, ReadVMemBase128, ReadVMemOffset128]>
+// XVSTX
+// Sched<[WriteVSTX256, ReadVSTData256, ReadVMemBase256, ReadVMemOffset256]>
+//===----------------------------------------------------------------------===//
+
+def WriteVSTELM128 : SchedWrite; // 128-bit element store
+def WriteVSTELM256 : SchedWrite; // 256-bit element store
+//===----------------------------------------------------------------------===//
+// VSTELM.B VSTELM.H VSTELM.W VSTELM.D
+// Sched<[WriteVSTELM128, ReadVSTData128, ReadVMemBase128]>
+// XVSTELM.B XVSTELM.H XVSTELM.W XVSTELM.D
+// Sched<[WriteVSTELM256, ReadVSTData256, ReadVMemBase256]>
+//===----------------------------------------------------------------------===//
+
+def ReadVSTData128 : SchedRead; // 128-bit store data
+def ReadVMemBase128 : SchedRead; // 128-bit address base
+def ReadVMemOffset128 : SchedRead; // 128-bit address offset
+def ReadVSTData256 : SchedRead; // 256-bit store data
+def ReadVMemBase256 : SchedRead; // 256-bit address base
+def ReadVMemOffset256 : SchedRead; // 256-bit address offset
+
diff --git a/llvm/test/tools/llvm-mca/LoongArch/Inputs/floating-point.s b/llvm/test/tools/llvm-mca/LoongArch/Inputs/floating-point.s
new file mode 100644
index 0000000000000..28865a2576122
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/Inputs/floating-point.s
@@ -0,0 +1,27 @@
+fadd.d $fa0, $fa1, $fa2
+fmul.d $fa0, $fa1, $fa2
+fmadd.d $fa0, $fa1, $fa2, $fa3
+fmax.d $fa0, $fa1, $fa2
+fabs.d $fa0, $fa1
+fcopysign.d $fa0, $fa1, $fa2
+fclass.d $fa0, $fa1
+fscaleb.d $fa0, $fa1, $fa2
+flogb.d $fa0, $fa1
+fdiv.s $fa0, $fa1, $fa2
+fdiv.d $fa0, $fa1, $fa2
+fsqrt.s $fa0, $fa1
+fsqrt.d $fa0, $fa1
+frecip.d $fa0, $fa1
+frsqrt.d $fa0, $fa1
+fcmp.ceq.d $fcc0, $fa1, $fa2
+fsel $fa0, $fa1, $fa2, $fcc0
+fcvt.s.d $fa0, $fa1
+ftint.w.d $fa0, $fa1
+ffint.d.l $fa0, $fa1
+frint.d $fa0, $fa1
+fmov.d $fa0, $fa1
+movgr2fr.d $fa0, $a1
+movfr2gr.d $a0, $fa1
+movgr2cf $fcc0, $a0
+movcf2gr $a0, $fcc0
+bcnez $fcc0, 8
diff --git a/llvm/test/tools/llvm-mca/LoongArch/Inputs/integer.s b/llvm/test/tools/llvm-mca/LoongArch/Inputs/integer.s
new file mode 100644
index 0000000000000..5d51599ac289e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/Inputs/integer.s
@@ -0,0 +1,22 @@
+add.d $a0, $a1, $a2
+addi.d $a0, $a1, 1
+and $a0, $a1, $a2
+nor $a0, $a1, $a2
+slt $a0, $a1, $a2
+maskeqz $a0, $a1, $a2
+lu12i.w $a0, 1
+sll.d $a0, $a1, $a2
+slli.d $a0, $a1, 1
+rotr.d $a0, $a1, $a2
+alsl.d $a0, $a1, $a2, 1
+bytepick.d $a0, $a1, $a2, 1
+bstrins.d $a0, $a1, 15, 8
+bstrpick.d $a0, $a1, 15, 8
+ext.w.b $a0, $a1
+clo.d $a0, $a1
+ctz.d $a0, $a1
+revb.d $a0, $a1
+bitrev.d $a0, $a1
+pcaddi $a0, 1
+b 4
+beq $a0, $a1, 8
diff --git a/llvm/test/tools/llvm-mca/LoongArch/Inputs/lasx.s b/llvm/test/tools/llvm-mca/LoongArch/Inputs/lasx.s
new file mode 100644
index 0000000000000..f9e3a2c01e292
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/Inputs/lasx.s
@@ -0,0 +1,27 @@
+xvadd.w $xr0, $xr1, $xr2
+xvmax.d $xr0, $xr1, $xr2
+xvhaddw.d.w $xr0, $xr1, $xr2
+xvmul.w $xr0, $xr1, $xr2
+xvmulwev.q.d $xr0, $xr1, $xr2
+xvdiv.w $xr0, $xr1, $xr2
+xvsll.w $xr0, $xr1, $xr2
+xvrotr.w $xr0, $xr1, $xr2
+xvsrln.b.h $xr0, $xr1, $xr2
+xvbitsel.v $xr0, $xr1, $xr2, $xr3
+xvpcnt.w $xr0, $xr1
+xvsetallnez.w $fcc0, $xr1
+xvshuf.w $xr0, $xr1, $xr2
+xvperm.w $xr0, $xr1, $xr2
+xvpermi.d $xr0, $xr1, 1
+xvpickve.w $xr0, $xr1, 0
+xvinsve0.w $xr0, $xr1, 0
+xvreplve0.b $xr0, $xr1
+vext2xv.d.b $xr0, $xr1
+xvreplgr2vr.w $xr0, $a1
+xvinsgr2vr.w $xr0, $a1, 0
+xvpickve2gr.w $a0, $xr1, 0
+xvfadd.d $xr0, $xr1, $xr2
+xvfmadd.d $xr0, $xr1, $xr2, $xr3
+xvfdiv.s $xr0, $xr1, $xr2
+xvfcvt.h.s $xr0, $xr1, $xr2
+xvftint.w.d $xr0, $xr1, $xr2
diff --git a/llvm/test/tools/llvm-mca/LoongArch/Inputs/lsx.s b/llvm/test/tools/llvm-mca/LoongArch/Inputs/lsx.s
new file mode 100644
index 0000000000000..23dbf7093d0de
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/Inputs/lsx.s
@@ -0,0 +1,41 @@
+vadd.w $vr0, $vr1, $vr2
+vadd.q $vr0, $vr1, $vr2
+vmax.w $vr0, $vr1, $vr2
+vmax.d $vr0, $vr1, $vr2
+vavg.w $vr0, $vr1, $vr2
+vabsd.w $vr0, $vr1, $vr2
+vadda.w $vr0, $vr1, $vr2
+vhaddw.d.w $vr0, $vr1, $vr2
+vaddwev.d.w $vr0, $vr1, $vr2
+vmul.w $vr0, $vr1, $vr2
+vmulwev.q.d $vr0, $vr1, $vr2
+vmadd.w $vr0, $vr1, $vr2
+vdiv.w $vr0, $vr1, $vr2
+vdiv.d $vr0, $vr1, $vr2
+vsll.w $vr0, $vr1, $vr2
+vrotr.w $vr0, $vr1, $vr2
+vsrlr.w $vr0, $vr1, $vr2
+vsrln.b.h $vr0, $vr1, $vr2
+vsllwil.d.w $vr0, $vr1, 0
+vand.v $vr0, $vr1, $vr2
+vbitclr.w $vr0, $vr1, $vr2
+vbitsel.v $vr0, $vr1, $vr2, $vr3
+vpcnt.w $vr0, $vr1
+vclz.w $vr0, $vr1
+vseq.w $vr0, $vr1, $vr2
+vslt.d $vr0, $vr1, $vr2
+vsetallnez.w $fcc0, $vr1
+vshuf.w $vr0, $vr1, $vr2
+vpickev.w $vr0, $vr1, $vr2
+vreplgr2vr.w $vr0, $a1
+vinsgr2vr.w $vr0, $a1, 0
+vpickve2gr.w $a0, $vr1, 0
+vfadd.d $vr0, $vr1, $vr2
+vfmul.d $vr0, $vr1, $vr2
+vfmadd.d $vr0, $vr1, $vr2, $vr3
+vfdiv.s $vr0, $vr1, $vr2
+vfsqrt.d $vr0, $vr1
+vfcmp.ceq.d $vr0, $vr1, $vr2
+vfcvt.h.s $vr0, $vr1, $vr2
+vftint.w.d $vr0, $vr1, $vr2
+vffint.s.w $vr0, $vr1
diff --git a/llvm/test/tools/llvm-mca/LoongArch/Inputs/memory.s b/llvm/test/tools/llvm-mca/LoongArch/Inputs/memory.s
new file mode 100644
index 0000000000000..23ffbd5e94885
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/Inputs/memory.s
@@ -0,0 +1,22 @@
+ld.b $a0, $a1, 0
+ld.d $a0, $a1, 0
+ldx.d $a0, $a1, $a2
+ldptr.d $a0, $a1, 0
+st.d $a0, $a1, 0
+stx.d $a0, $a1, $a2
+stptr.d $a0, $a1, 0
+fld.s $fa0, $a1, 0
+fld.d $fa0, $a1, 0
+fldx.d $fa0, $a1, $a2
+fst.d $fa0, $a1, 0
+fstx.d $fa0, $a1, $a2
+vld $vr0, $a1, 0
+vldx $vr0, $a1, $a2
+vldrepl.d $vr0, $a1, 0
+vst $vr0, $a1, 0
+vstx $vr0, $a1, $a2
+vstelm.d $vr0, $a1, 0, 0
+xvld $xr0, $a1, 0
+xvldx $xr0, $a1, $a2
+xvst $xr0, $a1, 0
+xvstelm.d $xr0, $a1, 0, 0
diff --git a/llvm/test/tools/llvm-mca/LoongArch/Inputs/mul-div.s b/llvm/test/tools/llvm-mca/LoongArch/Inputs/mul-div.s
new file mode 100644
index 0000000000000..d59f1de9dcaf6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/Inputs/mul-div.s
@@ -0,0 +1,9 @@
+mul.w $a0, $a1, $a2
+mulh.w $a0, $a1, $a2
+mulw.d.w $a0, $a1, $a2
+mul.d $a0, $a1, $a2
+mulh.du $a0, $a1, $a2
+div.w $a0, $a1, $a2
+mod.wu $a0, $a1, $a2
+div.d $a0, $a1, $a2
+mod.du $a0, $a1, $a2
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA464/floating-point.test b/llvm/test/tools/llvm-mca/LoongArch/LA464/floating-point.test
new file mode 100644
index 0000000000000..e08245190963a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA464/floating-point.test
@@ -0,0 +1,88 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la464 -iterations=1 -instruction-tables %p/../Inputs/floating-point.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 fadd.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 5 0.50 fmul.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 5 0.50 fmadd.d $fa0, $fa1, $fa2, $fa3
+# CHECK-NEXT: 1 2 0.50 fmax.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 1 0.50 fabs.d $fa0, $fa1
+# CHECK-NEXT: 1 1 0.50 fcopysign.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 2 0.50 fclass.d $fa0, $fa1
+# CHECK-NEXT: 1 4 0.50 fscaleb.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 4 0.50 flogb.d $fa0, $fa1
+# CHECK-NEXT: 1 14 7.00 fdiv.s $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 20 11.00 fdiv.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 22 10.00 fsqrt.s $fa0, $fa1
+# CHECK-NEXT: 1 36 18.00 fsqrt.d $fa0, $fa1
+# CHECK-NEXT: 1 23 11.00 frecip.d $fa0, $fa1
+# CHECK-NEXT: 1 54 27.00 frsqrt.d $fa0, $fa1
+# CHECK-NEXT: 1 1 0.50 fcmp.ceq.d $fcc0, $fa1, $fa2
+# CHECK-NEXT: 1 1 1.00 fsel $fa0, $fa1, $fa2, $fcc0
+# CHECK-NEXT: 1 2 0.50 fcvt.s.d $fa0, $fa1
+# CHECK-NEXT: 1 4 0.50 ftint.w.d $fa0, $fa1
+# CHECK-NEXT: 1 4 0.50 ffint.d.l $fa0, $fa1
+# CHECK-NEXT: 1 4 0.50 frint.d $fa0, $fa1
+# CHECK-NEXT: 1 1 0.50 fmov.d $fa0, $fa1
+# CHECK-NEXT: 1 2 1.00 movgr2fr.d $fa0, $a1
+# CHECK-NEXT: 1 2 1.00 movfr2gr.d $a0, $fa1
+# CHECK-NEXT: 1 15 14.00 movgr2cf $fcc0, $a0
+# CHECK-NEXT: 1 7 6.00 movcf2gr $a0, $fcc0
+# CHECK-NEXT: 1 1 0.50 bcnez $fcc0, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA464AGU0
+# CHECK-NEXT: [1] - LA464AGU1
+# CHECK-NEXT: [2] - LA464ALU0
+# CHECK-NEXT: [3] - LA464ALU1
+# CHECK-NEXT: [4] - LA464ALU2
+# CHECK-NEXT: [5] - LA464ALU3
+# CHECK-NEXT: [6] - LA464Div
+# CHECK-NEXT: [7] - LA464FDiv
+# CHECK-NEXT: [8] - LA464FPU0
+# CHECK-NEXT: [9] - LA464FPU1
+# CHECK-NEXT: [10.0] - LA464Load
+# CHECK-NEXT: [10.1] - LA464Load
+# CHECK-NEXT: [11] - LA464Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
+# CHECK-NEXT: - - 0.50 0.50 - - - 84.00 36.50 7.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fadd.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fmul.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fmadd.d $fa0, $fa1, $fa2, $fa3
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fmax.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fabs.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fcopysign.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fclass.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fscaleb.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - flogb.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - 7.00 1.00 - - - - fdiv.s $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - 11.00 1.00 - - - - fdiv.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - 10.00 1.00 - - - - fsqrt.s $fa0, $fa1
+# CHECK-NEXT: - - - - - - - 18.00 1.00 - - - - fsqrt.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - 11.00 1.00 - - - - frecip.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - 27.00 1.00 - - - - frsqrt.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fcmp.ceq.d $fcc0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - fsel $fa0, $fa1, $fa2, $fcc0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fcvt.s.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - ftint.w.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - ffint.d.l $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - frint.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - fmov.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - movgr2fr.d $fa0, $a1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - movfr2gr.d $a0, $fa1
+# CHECK-NEXT: - - - - - - - - 14.00 - - - - movgr2cf $fcc0, $a0
+# CHECK-NEXT: - - - - - - - - 6.00 - - - - movcf2gr $a0, $fcc0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - bcnez $fcc0, 8
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA464/integer.test b/llvm/test/tools/llvm-mca/LoongArch/LA464/integer.test
new file mode 100644
index 0000000000000..af4080bcd6a88
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA464/integer.test
@@ -0,0 +1,78 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la464 -iterations=1 -instruction-tables %p/../Inputs/integer.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 add.d $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 addi.d $a0, $a1, 1
+# CHECK-NEXT: 1 1 0.25 and $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 nor $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 slt $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 maskeqz $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 lu12i.w $a0, 1
+# CHECK-NEXT: 1 1 0.25 sll.d $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 slli.d $a0, $a1, 1
+# CHECK-NEXT: 1 1 0.25 rotr.d $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.50 alsl.d $a0, $a1, $a2, 1
+# CHECK-NEXT: 1 1 0.50 bytepick.d $a0, $a1, $a2, 1
+# CHECK-NEXT: 1 1 0.50 bstrins.d $a0, $a1, 15, 8
+# CHECK-NEXT: 1 1 0.25 bstrpick.d $a0, $a1, 15, 8
+# CHECK-NEXT: 1 1 0.25 ext.w.b $a0, $a1
+# CHECK-NEXT: 1 1 0.25 clo.d $a0, $a1
+# CHECK-NEXT: 1 1 0.25 ctz.d $a0, $a1
+# CHECK-NEXT: 1 1 0.25 revb.d $a0, $a1
+# CHECK-NEXT: 1 1 0.25 bitrev.d $a0, $a1
+# CHECK-NEXT: 1 1 0.50 pcaddi $a0, 1
+# CHECK-NEXT: 1 1 0.50 b 4
+# CHECK-NEXT: 1 1 0.50 beq $a0, $a1, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA464AGU0
+# CHECK-NEXT: [1] - LA464AGU1
+# CHECK-NEXT: [2] - LA464ALU0
+# CHECK-NEXT: [3] - LA464ALU1
+# CHECK-NEXT: [4] - LA464ALU2
+# CHECK-NEXT: [5] - LA464ALU3
+# CHECK-NEXT: [6] - LA464Div
+# CHECK-NEXT: [7] - LA464FDiv
+# CHECK-NEXT: [8] - LA464FPU0
+# CHECK-NEXT: [9] - LA464FPU1
+# CHECK-NEXT: [10.0] - LA464Load
+# CHECK-NEXT: [10.1] - LA464Load
+# CHECK-NEXT: [11] - LA464Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
+# CHECK-NEXT: 0.50 0.50 6.50 6.50 4.00 4.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - add.d $a0, $a1, $a2
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - addi.d $a0, $a1, 1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - and $a0, $a1, $a2
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - nor $a0, $a1, $a2
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - slt $a0, $a1, $a2
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - maskeqz $a0, $a1, $a2
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - lu12i.w $a0, 1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - sll.d $a0, $a1, $a2
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - slli.d $a0, $a1, 1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - rotr.d $a0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - alsl.d $a0, $a1, $a2, 1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - bytepick.d $a0, $a1, $a2, 1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - bstrins.d $a0, $a1, 15, 8
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - bstrpick.d $a0, $a1, 15, 8
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - ext.w.b $a0, $a1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - clo.d $a0, $a1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - ctz.d $a0, $a1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - revb.d $a0, $a1
+# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - bitrev.d $a0, $a1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - pcaddi $a0, 1
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - b 4
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - beq $a0, $a1, 8
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA464/lasx.test b/llvm/test/tools/llvm-mca/LoongArch/LA464/lasx.test
new file mode 100644
index 0000000000000..6ad9cefb4589b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA464/lasx.test
@@ -0,0 +1,88 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la464 -iterations=1 -instruction-tables %p/../Inputs/lasx.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 xvadd.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 0.50 xvmax.d $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 0.50 xvhaddw.d.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 4 0.50 xvmul.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 7 0.50 xvmulwev.q.d $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 30 16.00 xvdiv.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 1 0.50 xvsll.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 0.50 xvrotr.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 1.00 xvsrln.b.h $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 1 0.50 xvbitsel.v $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: 1 2 0.50 xvpcnt.w $xr0, $xr1
+# CHECK-NEXT: 1 4 0.50 xvsetallnez.w $fcc0, $xr1
+# CHECK-NEXT: 1 1 0.50 xvshuf.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 3 0.50 xvperm.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 3 0.50 xvpermi.d $xr0, $xr1, 1
+# CHECK-NEXT: 1 3 0.50 xvpickve.w $xr0, $xr1, 0
+# CHECK-NEXT: 1 3 0.50 xvinsve0.w $xr0, $xr1, 0
+# CHECK-NEXT: 1 3 0.50 xvreplve0.b $xr0, $xr1
+# CHECK-NEXT: 1 3 0.50 vext2xv.d.b $xr0, $xr1
+# CHECK-NEXT: 1 2 1.00 xvreplgr2vr.w $xr0, $a1
+# CHECK-NEXT: 1 5 1.00 xvinsgr2vr.w $xr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 xvpickve2gr.w $a0, $xr1, 0
+# CHECK-NEXT: 1 5 0.50 xvfadd.d $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 5 0.50 xvfmadd.d $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: 1 24 13.00 xvfdiv.s $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 3 1.00 xvfcvt.h.s $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 5 1.00 xvftint.w.d $xr0, $xr1, $xr2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA464AGU0
+# CHECK-NEXT: [1] - LA464AGU1
+# CHECK-NEXT: [2] - LA464ALU0
+# CHECK-NEXT: [3] - LA464ALU1
+# CHECK-NEXT: [4] - LA464ALU2
+# CHECK-NEXT: [5] - LA464ALU3
+# CHECK-NEXT: [6] - LA464Div
+# CHECK-NEXT: [7] - LA464FDiv
+# CHECK-NEXT: [8] - LA464FPU0
+# CHECK-NEXT: [9] - LA464FPU1
+# CHECK-NEXT: [10.0] - LA464Load
+# CHECK-NEXT: [10.1] - LA464Load
+# CHECK-NEXT: [11] - LA464Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
+# CHECK-NEXT: - - - - - - - 29.00 17.50 9.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvadd.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvmax.d $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvhaddw.d.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvmul.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvmulwev.q.d $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - 16.00 1.00 - - - - xvdiv.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvsll.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvrotr.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - xvsrln.b.h $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvbitsel.v $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvpcnt.w $xr0, $xr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvsetallnez.w $fcc0, $xr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvshuf.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvperm.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvpermi.d $xr0, $xr1, 1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvpickve.w $xr0, $xr1, 0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvinsve0.w $xr0, $xr1, 0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvreplve0.b $xr0, $xr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vext2xv.d.b $xr0, $xr1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - xvreplgr2vr.w $xr0, $a1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - xvinsgr2vr.w $xr0, $a1, 0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - xvpickve2gr.w $a0, $xr1, 0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvfadd.d $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - xvfmadd.d $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: - - - - - - - 13.00 1.00 - - - - xvfdiv.s $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - xvfcvt.h.s $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - xvftint.w.d $xr0, $xr1, $xr2
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA464/lsx.test b/llvm/test/tools/llvm-mca/LoongArch/LA464/lsx.test
new file mode 100644
index 0000000000000..5b142681d51e5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA464/lsx.test
@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la464 -iterations=1 -instruction-tables %p/../Inputs/lsx.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 vadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vadd.q $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.50 vmax.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vmax.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.50 vavg.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vabsd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vadda.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vhaddw.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vaddwev.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 4 0.50 vmul.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 7 0.50 vmulwev.q.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 4 0.50 vmadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 30 16.00 vdiv.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 25 13.00 vdiv.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.50 vsll.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vrotr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vsrlr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 1.00 vsrln.b.h $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 1.00 vsllwil.d.w $vr0, $vr1, 0
+# CHECK-NEXT: 1 1 0.50 vand.v $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vbitclr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.50 vbitsel.v $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: 1 2 0.50 vpcnt.w $vr0, $vr1
+# CHECK-NEXT: 1 2 0.50 vclz.w $vr0, $vr1
+# CHECK-NEXT: 1 1 0.50 vseq.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vslt.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vsetallnez.w $fcc0, $vr1
+# CHECK-NEXT: 1 1 0.50 vshuf.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.50 vpickev.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 1.00 vreplgr2vr.w $vr0, $a1
+# CHECK-NEXT: 1 3 1.00 vinsgr2vr.w $vr0, $a1, 0
+# CHECK-NEXT: 1 3 1.00 vpickve2gr.w $a0, $vr1, 0
+# CHECK-NEXT: 1 5 0.50 vfadd.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 5 0.50 vfmul.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 5 0.50 vfmadd.d $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: 1 24 13.00 vfdiv.s $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 36 18.00 vfsqrt.d $vr0, $vr1
+# CHECK-NEXT: 1 2 0.50 vfcmp.ceq.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 1.00 vfcvt.h.s $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 5 1.00 vftint.w.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 4 0.50 vffint.s.w $vr0, $vr1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA464AGU0
+# CHECK-NEXT: [1] - LA464AGU1
+# CHECK-NEXT: [2] - LA464ALU0
+# CHECK-NEXT: [3] - LA464ALU1
+# CHECK-NEXT: [4] - LA464ALU2
+# CHECK-NEXT: [5] - LA464ALU3
+# CHECK-NEXT: [6] - LA464Div
+# CHECK-NEXT: [7] - LA464FDiv
+# CHECK-NEXT: [8] - LA464FPU0
+# CHECK-NEXT: [9] - LA464FPU1
+# CHECK-NEXT: [10.0] - LA464Load
+# CHECK-NEXT: [10.1] - LA464Load
+# CHECK-NEXT: [11] - LA464Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
+# CHECK-NEXT: - - - - - - - 60.00 26.00 15.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vadd.q $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vmax.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vmax.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vavg.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vabsd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vadda.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vhaddw.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vaddwev.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vmul.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vmulwev.q.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vmadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - 16.00 1.00 - - - - vdiv.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - 13.00 1.00 - - - - vdiv.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vsll.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vrotr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vsrlr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsrln.b.h $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsllwil.d.w $vr0, $vr1, 0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vand.v $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vbitclr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vbitsel.v $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vpcnt.w $vr0, $vr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vclz.w $vr0, $vr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vseq.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vslt.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vsetallnez.w $fcc0, $vr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vshuf.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vpickev.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vreplgr2vr.w $vr0, $a1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vinsgr2vr.w $vr0, $a1, 0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vpickve2gr.w $a0, $vr1, 0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vfadd.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vfmul.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vfmadd.d $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: - - - - - - - 13.00 1.00 - - - - vfdiv.s $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - 18.00 1.00 - - - - vfsqrt.d $vr0, $vr1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vfcmp.ceq.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vfcvt.h.s $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vftint.w.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - vffint.s.w $vr0, $vr1
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA464/memory.test b/llvm/test/tools/llvm-mca/LoongArch/LA464/memory.test
new file mode 100644
index 0000000000000..06ba6d194ec7c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA464/memory.test
@@ -0,0 +1,78 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la464 -iterations=1 -instruction-tables %p/../Inputs/memory.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 * ld.b $a0, $a1, 0
+# CHECK-NEXT: 1 4 0.50 * ld.d $a0, $a1, 0
+# CHECK-NEXT: 1 4 1.00 * ldx.d $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 * ldptr.d $a0, $a1, 0
+# CHECK-NEXT: 1 4 1.00 * st.d $a0, $a1, 0
+# CHECK-NEXT: 1 4 1.00 * stx.d $a0, $a1, $a2
+# CHECK-NEXT: 1 4 1.00 * stptr.d $a0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * fld.s $fa0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * fld.d $fa0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * fldx.d $fa0, $a1, $a2
+# CHECK-NEXT: 1 5 1.00 * fst.d $fa0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * fstx.d $fa0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * vld $vr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * vldx $vr0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * vldrepl.d $vr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * vst $vr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * vstx $vr0, $a1, $a2
+# CHECK-NEXT: 1 5 1.00 * vstelm.d $vr0, $a1, 0, 0
+# CHECK-NEXT: 1 5 0.50 * xvld $xr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * xvldx $xr0, $a1, $a2
+# CHECK-NEXT: 1 5 1.00 * xvst $xr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 * xvstelm.d $xr0, $a1, 0, 0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA464AGU0
+# CHECK-NEXT: [1] - LA464AGU1
+# CHECK-NEXT: [2] - LA464ALU0
+# CHECK-NEXT: [3] - LA464ALU1
+# CHECK-NEXT: [4] - LA464ALU2
+# CHECK-NEXT: [5] - LA464ALU3
+# CHECK-NEXT: [6] - LA464Div
+# CHECK-NEXT: [7] - LA464FDiv
+# CHECK-NEXT: [8] - LA464FPU0
+# CHECK-NEXT: [9] - LA464FPU1
+# CHECK-NEXT: [10.0] - LA464Load
+# CHECK-NEXT: [10.1] - LA464Load
+# CHECK-NEXT: [11] - LA464Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
+# CHECK-NEXT: 18.00 4.00 - - - - - - - - 6.00 6.00 10.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - ld.b $a0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - ld.d $a0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - 0.50 0.50 - ldx.d $a0, $a1, $a2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - ldptr.d $a0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 st.d $a0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 stx.d $a0, $a1, $a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 stptr.d $a0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - fld.s $fa0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - fld.d $fa0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - 0.50 0.50 - fldx.d $fa0, $a1, $a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 fst.d $fa0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 fstx.d $fa0, $a1, $a2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - vld $vr0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - 0.50 0.50 - vldx $vr0, $a1, $a2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - vldrepl.d $vr0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 vst $vr0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 vstx $vr0, $a1, $a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 vstelm.d $vr0, $a1, 0, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - 0.50 0.50 - xvld $xr0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - 0.50 0.50 - xvldx $xr0, $a1, $a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 xvst $xr0, $a1, 0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 1.00 xvstelm.d $xr0, $a1, 0, 0
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA464/mul-div.test b/llvm/test/tools/llvm-mca/LoongArch/LA464/mul-div.test
new file mode 100644
index 0000000000000..4cfb948c330d7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA464/mul-div.test
@@ -0,0 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la464 -iterations=1 -instruction-tables %p/../Inputs/mul-div.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 mul.w $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mulh.w $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mulw.d.w $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mul.d $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mulh.du $a0, $a1, $a2
+# CHECK-NEXT: 1 21 11.00 div.w $a0, $a1, $a2
+# CHECK-NEXT: 1 21 11.00 mod.wu $a0, $a1, $a2
+# CHECK-NEXT: 1 36 20.00 div.d $a0, $a1, $a2
+# CHECK-NEXT: 1 36 20.00 mod.du $a0, $a1, $a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA464AGU0
+# CHECK-NEXT: [1] - LA464AGU1
+# CHECK-NEXT: [2] - LA464ALU0
+# CHECK-NEXT: [3] - LA464ALU1
+# CHECK-NEXT: [4] - LA464ALU2
+# CHECK-NEXT: [5] - LA464ALU3
+# CHECK-NEXT: [6] - LA464Div
+# CHECK-NEXT: [7] - LA464FDiv
+# CHECK-NEXT: [8] - LA464FPU0
+# CHECK-NEXT: [9] - LA464FPU1
+# CHECK-NEXT: [10.0] - LA464Load
+# CHECK-NEXT: [10.1] - LA464Load
+# CHECK-NEXT: [11] - LA464Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11]
+# CHECK-NEXT: - - 6.50 2.50 - - 62.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10.0] [10.1] [11] Instructions:
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - mul.w $a0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - mulh.w $a0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - mulw.d.w $a0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - mul.d $a0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - mulh.du $a0, $a1, $a2
+# CHECK-NEXT: - - 1.00 - - - 11.00 - - - - - - div.w $a0, $a1, $a2
+# CHECK-NEXT: - - 1.00 - - - 11.00 - - - - - - mod.wu $a0, $a1, $a2
+# CHECK-NEXT: - - 1.00 - - - 20.00 - - - - - - div.d $a0, $a1, $a2
+# CHECK-NEXT: - - 1.00 - - - 20.00 - - - - - - mod.du $a0, $a1, $a2
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA664/floating-point.test b/llvm/test/tools/llvm-mca/LoongArch/LA664/floating-point.test
new file mode 100644
index 0000000000000..22aa8a07a3ef5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA664/floating-point.test
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la664 -iterations=1 -instruction-tables %p/../Inputs/floating-point.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.25 fadd.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 5 0.50 fmul.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 5 0.50 fmadd.d $fa0, $fa1, $fa2, $fa3
+# CHECK-NEXT: 1 2 0.25 fmax.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 1 0.25 fabs.d $fa0, $fa1
+# CHECK-NEXT: 1 1 0.25 fcopysign.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 2 0.25 fclass.d $fa0, $fa1
+# CHECK-NEXT: 1 4 0.25 fscaleb.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 4 0.25 flogb.d $fa0, $fa1
+# CHECK-NEXT: 1 13 3.00 fdiv.s $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 19 4.00 fdiv.d $fa0, $fa1, $fa2
+# CHECK-NEXT: 1 22 4.00 fsqrt.s $fa0, $fa1
+# CHECK-NEXT: 1 36 7.00 fsqrt.d $fa0, $fa1
+# CHECK-NEXT: 1 23 4.00 frecip.d $fa0, $fa1
+# CHECK-NEXT: 1 54 12.00 frsqrt.d $fa0, $fa1
+# CHECK-NEXT: 1 2 0.50 fcmp.ceq.d $fcc0, $fa1, $fa2
+# CHECK-NEXT: 1 1 0.50 fsel $fa0, $fa1, $fa2, $fcc0
+# CHECK-NEXT: 1 2 0.25 fcvt.s.d $fa0, $fa1
+# CHECK-NEXT: 1 4 0.25 ftint.w.d $fa0, $fa1
+# CHECK-NEXT: 1 4 0.25 ffint.d.l $fa0, $fa1
+# CHECK-NEXT: 1 4 0.25 frint.d $fa0, $fa1
+# CHECK-NEXT: 1 1 0.25 fmov.d $fa0, $fa1
+# CHECK-NEXT: 1 2 1.00 movgr2fr.d $fa0, $a1
+# CHECK-NEXT: 1 2 1.00 movfr2gr.d $a0, $fa1
+# CHECK-NEXT: 1 2 1.00 movgr2cf $fcc0, $a0
+# CHECK-NEXT: 1 2 1.00 movcf2gr $a0, $fcc0
+# CHECK-NEXT: 1 1 0.50 bcnez $fcc0, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA664AGU0
+# CHECK-NEXT: [1] - LA664AGU1
+# CHECK-NEXT: [2] - LA664AGU2
+# CHECK-NEXT: [3] - LA664AGU3
+# CHECK-NEXT: [4] - LA664ALU0
+# CHECK-NEXT: [5] - LA664ALU1
+# CHECK-NEXT: [6] - LA664ALU2
+# CHECK-NEXT: [7] - LA664ALU3
+# CHECK-NEXT: [8] - LA664Div
+# CHECK-NEXT: [9] - LA664FDiv
+# CHECK-NEXT: [10] - LA664FPU0
+# CHECK-NEXT: [11] - LA664FPU1
+# CHECK-NEXT: [12] - LA664FPU2
+# CHECK-NEXT: [13] - LA664FPU3
+# CHECK-NEXT: [14.0] - LA664Load
+# CHECK-NEXT: [14.1] - LA664Load
+# CHECK-NEXT: [15.0] - LA664Store
+# CHECK-NEXT: [15.1] - LA664Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - 0.50 0.50 - - - 34.00 15.00 5.00 3.00 3.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fadd.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - fmul.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - fmadd.d $fa0, $fa1, $fa2, $fa3
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fmax.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fabs.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fcopysign.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fclass.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fscaleb.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - flogb.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - 3.00 1.00 - - - - - - - fdiv.s $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - 4.00 1.00 - - - - - - - fdiv.d $fa0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - 4.00 1.00 - - - - - - - fsqrt.s $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - 7.00 1.00 - - - - - - - fsqrt.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - 4.00 1.00 - - - - - - - frecip.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - 12.00 1.00 - - - - - - - frsqrt.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - fcmp.ceq.d $fcc0, $fa1, $fa2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - fsel $fa0, $fa1, $fa2, $fcc0
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fcvt.s.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - ftint.w.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - ffint.d.l $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - frint.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fmov.d $fa0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - movgr2fr.d $fa0, $a1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - movfr2gr.d $a0, $fa1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - movgr2cf $fcc0, $a0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - movcf2gr $a0, $fcc0
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - bcnez $fcc0, 8
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA664/integer.test b/llvm/test/tools/llvm-mca/LoongArch/LA664/integer.test
new file mode 100644
index 0000000000000..f50d2616c3124
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA664/integer.test
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la664 -iterations=1 -instruction-tables %p/../Inputs/integer.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 add.d $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 addi.d $a0, $a1, 1
+# CHECK-NEXT: 1 1 0.25 and $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 nor $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 slt $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 maskeqz $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 lu12i.w $a0, 1
+# CHECK-NEXT: 1 1 0.25 sll.d $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 slli.d $a0, $a1, 1
+# CHECK-NEXT: 1 1 0.25 rotr.d $a0, $a1, $a2
+# CHECK-NEXT: 1 1 0.25 alsl.d $a0, $a1, $a2, 1
+# CHECK-NEXT: 1 1 0.25 bytepick.d $a0, $a1, $a2, 1
+# CHECK-NEXT: 1 1 0.25 bstrins.d $a0, $a1, 15, 8
+# CHECK-NEXT: 1 1 0.25 bstrpick.d $a0, $a1, 15, 8
+# CHECK-NEXT: 1 1 0.25 ext.w.b $a0, $a1
+# CHECK-NEXT: 1 1 0.25 clo.d $a0, $a1
+# CHECK-NEXT: 1 1 0.25 ctz.d $a0, $a1
+# CHECK-NEXT: 1 1 0.25 revb.d $a0, $a1
+# CHECK-NEXT: 1 1 0.25 bitrev.d $a0, $a1
+# CHECK-NEXT: 1 1 0.50 pcaddi $a0, 1
+# CHECK-NEXT: 1 1 0.50 b 4
+# CHECK-NEXT: 1 1 0.50 beq $a0, $a1, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA664AGU0
+# CHECK-NEXT: [1] - LA664AGU1
+# CHECK-NEXT: [2] - LA664AGU2
+# CHECK-NEXT: [3] - LA664AGU3
+# CHECK-NEXT: [4] - LA664ALU0
+# CHECK-NEXT: [5] - LA664ALU1
+# CHECK-NEXT: [6] - LA664ALU2
+# CHECK-NEXT: [7] - LA664ALU3
+# CHECK-NEXT: [8] - LA664Div
+# CHECK-NEXT: [9] - LA664FDiv
+# CHECK-NEXT: [10] - LA664FPU0
+# CHECK-NEXT: [11] - LA664FPU1
+# CHECK-NEXT: [12] - LA664FPU2
+# CHECK-NEXT: [13] - LA664FPU3
+# CHECK-NEXT: [14.0] - LA664Load
+# CHECK-NEXT: [14.1] - LA664Load
+# CHECK-NEXT: [15.0] - LA664Store
+# CHECK-NEXT: [15.1] - LA664Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 0.50 0.50 - - 5.75 5.75 4.75 4.75 - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - add.d $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - addi.d $a0, $a1, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - and $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - nor $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - slt $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - maskeqz $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - lu12i.w $a0, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - sll.d $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - slli.d $a0, $a1, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - rotr.d $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - alsl.d $a0, $a1, $a2, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - bytepick.d $a0, $a1, $a2, 1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - bstrins.d $a0, $a1, 15, 8
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - bstrpick.d $a0, $a1, 15, 8
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - ext.w.b $a0, $a1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - clo.d $a0, $a1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - ctz.d $a0, $a1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - revb.d $a0, $a1
+# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - bitrev.d $a0, $a1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - pcaddi $a0, 1
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - b 4
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - beq $a0, $a1, 8
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA664/lasx.test b/llvm/test/tools/llvm-mca/LoongArch/LA664/lasx.test
new file mode 100644
index 0000000000000..9047bcc93385c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA664/lasx.test
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la664 -iterations=1 -instruction-tables %p/../Inputs/lasx.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 xvadd.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 0.25 xvmax.d $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 0.50 xvhaddw.d.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 4 0.50 xvmul.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 7 0.50 xvmulwev.q.d $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 26 14.00 xvdiv.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 1 0.25 xvsll.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 1 0.25 xvrotr.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 2 0.50 xvsrln.b.h $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 1 0.50 xvbitsel.v $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: 1 2 0.50 xvpcnt.w $xr0, $xr1
+# CHECK-NEXT: 1 3 0.50 xvsetallnez.w $fcc0, $xr1
+# CHECK-NEXT: 1 1 0.50 xvshuf.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 3 0.25 xvperm.w $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 3 0.25 xvpermi.d $xr0, $xr1, 1
+# CHECK-NEXT: 1 3 0.25 xvpickve.w $xr0, $xr1, 0
+# CHECK-NEXT: 1 3 0.25 xvinsve0.w $xr0, $xr1, 0
+# CHECK-NEXT: 1 3 0.25 xvreplve0.b $xr0, $xr1
+# CHECK-NEXT: 1 3 0.25 vext2xv.d.b $xr0, $xr1
+# CHECK-NEXT: 1 2 1.00 xvreplgr2vr.w $xr0, $a1
+# CHECK-NEXT: 1 5 1.00 xvinsgr2vr.w $xr0, $a1, 0
+# CHECK-NEXT: 1 5 1.00 xvpickve2gr.w $a0, $xr1, 0
+# CHECK-NEXT: 1 3 0.25 xvfadd.d $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 5 0.50 xvfmadd.d $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: 1 23 12.00 xvfdiv.s $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 3 0.50 xvfcvt.h.s $xr0, $xr1, $xr2
+# CHECK-NEXT: 1 5 0.50 xvftint.w.d $xr0, $xr1, $xr2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA664AGU0
+# CHECK-NEXT: [1] - LA664AGU1
+# CHECK-NEXT: [2] - LA664AGU2
+# CHECK-NEXT: [3] - LA664AGU3
+# CHECK-NEXT: [4] - LA664ALU0
+# CHECK-NEXT: [5] - LA664ALU1
+# CHECK-NEXT: [6] - LA664ALU2
+# CHECK-NEXT: [7] - LA664ALU3
+# CHECK-NEXT: [8] - LA664Div
+# CHECK-NEXT: [9] - LA664FDiv
+# CHECK-NEXT: [10] - LA664FPU0
+# CHECK-NEXT: [11] - LA664FPU1
+# CHECK-NEXT: [12] - LA664FPU2
+# CHECK-NEXT: [13] - LA664FPU3
+# CHECK-NEXT: [14.0] - LA664Load
+# CHECK-NEXT: [14.1] - LA664Load
+# CHECK-NEXT: [15.0] - LA664Store
+# CHECK-NEXT: [15.1] - LA664Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - 26.00 9.25 4.25 6.75 6.75 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvadd.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvmax.d $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvhaddw.d.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvmul.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvmulwev.q.d $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - 14.00 1.00 - - - - - - - xvdiv.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvsll.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvrotr.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvsrln.b.h $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvbitsel.v $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvpcnt.w $xr0, $xr1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvsetallnez.w $fcc0, $xr1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - xvshuf.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvperm.w $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvpermi.d $xr0, $xr1, 1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvpickve.w $xr0, $xr1, 0
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvinsve0.w $xr0, $xr1, 0
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvreplve0.b $xr0, $xr1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vext2xv.d.b $xr0, $xr1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - xvreplgr2vr.w $xr0, $a1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - xvinsgr2vr.w $xr0, $a1, 0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - xvpickve2gr.w $a0, $xr1, 0
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - xvfadd.d $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - xvfmadd.d $xr0, $xr1, $xr2, $xr3
+# CHECK-NEXT: - - - - - - - - - 12.00 1.00 - - - - - - - xvfdiv.s $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - xvfcvt.h.s $xr0, $xr1, $xr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - xvftint.w.d $xr0, $xr1, $xr2
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA664/lsx.test b/llvm/test/tools/llvm-mca/LoongArch/LA664/lsx.test
new file mode 100644
index 0000000000000..bd46440c04c68
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA664/lsx.test
@@ -0,0 +1,121 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la664 -iterations=1 -instruction-tables %p/../Inputs/lsx.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 vadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vadd.q $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.25 vmax.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.25 vmax.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.25 vavg.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vabsd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vadda.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vhaddw.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vaddwev.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 4 0.50 vmul.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 7 0.50 vmulwev.q.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 4 0.50 vmadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 26 14.00 vdiv.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 22 12.00 vdiv.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.25 vsll.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.25 vrotr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vsrlr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vsrln.b.h $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vsllwil.d.w $vr0, $vr1, 0
+# CHECK-NEXT: 1 1 0.25 vand.v $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vbitclr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.50 vbitsel.v $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: 1 2 0.50 vpcnt.w $vr0, $vr1
+# CHECK-NEXT: 1 2 0.25 vclz.w $vr0, $vr1
+# CHECK-NEXT: 1 1 0.25 vseq.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.25 vslt.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 0.50 vsetallnez.w $fcc0, $vr1
+# CHECK-NEXT: 1 1 0.50 vshuf.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 1 0.25 vpickev.w $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 2 1.00 vreplgr2vr.w $vr0, $a1
+# CHECK-NEXT: 1 3 1.00 vinsgr2vr.w $vr0, $a1, 0
+# CHECK-NEXT: 1 3 1.00 vpickve2gr.w $a0, $vr1, 0
+# CHECK-NEXT: 1 3 0.25 vfadd.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 5 0.50 vfmul.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 5 0.50 vfmadd.d $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: 1 23 12.00 vfdiv.s $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 36 16.00 vfsqrt.d $vr0, $vr1
+# CHECK-NEXT: 1 2 0.25 vfcmp.ceq.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 3 0.50 vfcvt.h.s $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 5 0.50 vftint.w.d $vr0, $vr1, $vr2
+# CHECK-NEXT: 1 4 0.25 vffint.s.w $vr0, $vr1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA664AGU0
+# CHECK-NEXT: [1] - LA664AGU1
+# CHECK-NEXT: [2] - LA664AGU2
+# CHECK-NEXT: [3] - LA664AGU3
+# CHECK-NEXT: [4] - LA664ALU0
+# CHECK-NEXT: [5] - LA664ALU1
+# CHECK-NEXT: [6] - LA664ALU2
+# CHECK-NEXT: [7] - LA664ALU3
+# CHECK-NEXT: [8] - LA664Div
+# CHECK-NEXT: [9] - LA664FDiv
+# CHECK-NEXT: [10] - LA664FPU0
+# CHECK-NEXT: [11] - LA664FPU1
+# CHECK-NEXT: [12] - LA664FPU2
+# CHECK-NEXT: [13] - LA664FPU3
+# CHECK-NEXT: [14.0] - LA664Load
+# CHECK-NEXT: [14.1] - LA664Load
+# CHECK-NEXT: [15.0] - LA664Store
+# CHECK-NEXT: [15.1] - LA664Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - 54.00 12.50 5.50 11.50 11.50 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vadd.q $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vmax.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vmax.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vavg.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vabsd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vadda.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vhaddw.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vaddwev.d.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vmul.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vmulwev.q.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vmadd.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - 14.00 1.00 - - - - - - - vdiv.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - 12.00 1.00 - - - - - - - vdiv.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vsll.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vrotr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vsrlr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vsrln.b.h $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vsllwil.d.w $vr0, $vr1, 0
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vand.v $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vbitclr.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vbitsel.v $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vpcnt.w $vr0, $vr1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vclz.w $vr0, $vr1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vseq.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vslt.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vsetallnez.w $fcc0, $vr1
+# CHECK-NEXT: - - - - - - - - - - - - 0.50 0.50 - - - - vshuf.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vpickev.w $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - vreplgr2vr.w $vr0, $a1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - vinsgr2vr.w $vr0, $a1, 0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - vpickve2gr.w $a0, $vr1, 0
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vfadd.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - vfmul.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - vfmadd.d $vr0, $vr1, $vr2, $vr3
+# CHECK-NEXT: - - - - - - - - - 12.00 1.00 - - - - - - - vfdiv.s $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - 16.00 1.00 - - - - - - - vfsqrt.d $vr0, $vr1
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vfcmp.ceq.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - vfcvt.h.s $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.50 0.50 - - - - - - vftint.w.d $vr0, $vr1, $vr2
+# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - vffint.s.w $vr0, $vr1
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA664/memory.test b/llvm/test/tools/llvm-mca/LoongArch/LA664/memory.test
new file mode 100644
index 0000000000000..1be059df2cdb9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA664/memory.test
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la664 -iterations=1 -instruction-tables %p/../Inputs/memory.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 * ld.b $a0, $a1, 0
+# CHECK-NEXT: 1 4 0.50 * ld.d $a0, $a1, 0
+# CHECK-NEXT: 1 4 0.50 * ldx.d $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 * ldptr.d $a0, $a1, 0
+# CHECK-NEXT: 1 4 0.50 * st.d $a0, $a1, 0
+# CHECK-NEXT: 1 4 0.50 * stx.d $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 * stptr.d $a0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * fld.s $fa0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * fld.d $fa0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * fldx.d $fa0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * fst.d $fa0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * fstx.d $fa0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * vld $vr0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * vldx $vr0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * vldrepl.d $vr0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * vst $vr0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * vstx $vr0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * vstelm.d $vr0, $a1, 0, 0
+# CHECK-NEXT: 1 5 0.50 * xvld $xr0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * xvldx $xr0, $a1, $a2
+# CHECK-NEXT: 1 5 0.50 * xvst $xr0, $a1, 0
+# CHECK-NEXT: 1 5 0.50 * xvstelm.d $xr0, $a1, 0, 0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA664AGU0
+# CHECK-NEXT: [1] - LA664AGU1
+# CHECK-NEXT: [2] - LA664AGU2
+# CHECK-NEXT: [3] - LA664AGU3
+# CHECK-NEXT: [4] - LA664ALU0
+# CHECK-NEXT: [5] - LA664ALU1
+# CHECK-NEXT: [6] - LA664ALU2
+# CHECK-NEXT: [7] - LA664ALU3
+# CHECK-NEXT: [8] - LA664Div
+# CHECK-NEXT: [9] - LA664FDiv
+# CHECK-NEXT: [10] - LA664FPU0
+# CHECK-NEXT: [11] - LA664FPU1
+# CHECK-NEXT: [12] - LA664FPU2
+# CHECK-NEXT: [13] - LA664FPU3
+# CHECK-NEXT: [14.0] - LA664Load
+# CHECK-NEXT: [14.1] - LA664Load
+# CHECK-NEXT: [15.0] - LA664Store
+# CHECK-NEXT: [15.1] - LA664Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 6.00 6.00 5.00 5.00 - - - - - - - - - - 6.00 6.00 5.00 5.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - ld.b $a0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - ld.d $a0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - ldx.d $a0, $a1, $a2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - ldptr.d $a0, $a1, 0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 st.d $a0, $a1, 0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 stx.d $a0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 stptr.d $a0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - fld.s $fa0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - fld.d $fa0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - fldx.d $fa0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 fst.d $fa0, $a1, 0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 fstx.d $fa0, $a1, $a2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - vld $vr0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - vldx $vr0, $a1, $a2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - vldrepl.d $vr0, $a1, 0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 vst $vr0, $a1, 0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 vstx $vr0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 vstelm.d $vr0, $a1, 0, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - xvld $xr0, $a1, 0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 - - xvldx $xr0, $a1, $a2
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 xvst $xr0, $a1, 0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - - - - - 0.50 0.50 xvstelm.d $xr0, $a1, 0, 0
diff --git a/llvm/test/tools/llvm-mca/LoongArch/LA664/mul-div.test b/llvm/test/tools/llvm-mca/LoongArch/LA664/mul-div.test
new file mode 100644
index 0000000000000..681435aa5f693
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/LA664/mul-div.test
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=loongarch64 -mcpu=la664 -iterations=1 -instruction-tables %p/../Inputs/mul-div.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 mul.w $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mulh.w $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mulw.d.w $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mul.d $a0, $a1, $a2
+# CHECK-NEXT: 1 4 0.50 mulh.du $a0, $a1, $a2
+# CHECK-NEXT: 1 19 12.00 div.w $a0, $a1, $a2
+# CHECK-NEXT: 1 19 12.00 mod.wu $a0, $a1, $a2
+# CHECK-NEXT: 1 32 19.00 div.d $a0, $a1, $a2
+# CHECK-NEXT: 1 32 19.00 mod.du $a0, $a1, $a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - LA664AGU0
+# CHECK-NEXT: [1] - LA664AGU1
+# CHECK-NEXT: [2] - LA664AGU2
+# CHECK-NEXT: [3] - LA664AGU3
+# CHECK-NEXT: [4] - LA664ALU0
+# CHECK-NEXT: [5] - LA664ALU1
+# CHECK-NEXT: [6] - LA664ALU2
+# CHECK-NEXT: [7] - LA664ALU3
+# CHECK-NEXT: [8] - LA664Div
+# CHECK-NEXT: [9] - LA664FDiv
+# CHECK-NEXT: [10] - LA664FPU0
+# CHECK-NEXT: [11] - LA664FPU1
+# CHECK-NEXT: [12] - LA664FPU2
+# CHECK-NEXT: [13] - LA664FPU3
+# CHECK-NEXT: [14.0] - LA664Load
+# CHECK-NEXT: [14.1] - LA664Load
+# CHECK-NEXT: [15.0] - LA664Store
+# CHECK-NEXT: [15.1] - LA664Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - 6.50 2.50 - - 62.00 - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - mul.w $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - mulh.w $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - mulw.d.w $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - mul.d $a0, $a1, $a2
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - mulh.du $a0, $a1, $a2
+# CHECK-NEXT: - - - - 1.00 - - - 12.00 - - - - - - - - - div.w $a0, $a1, $a2
+# CHECK-NEXT: - - - - 1.00 - - - 12.00 - - - - - - - - - mod.wu $a0, $a1, $a2
+# CHECK-NEXT: - - - - 1.00 - - - 19.00 - - - - - - - - - div.d $a0, $a1, $a2
+# CHECK-NEXT: - - - - 1.00 - - - 19.00 - - - - - - - - - mod.du $a0, $a1, $a2
diff --git a/llvm/test/tools/llvm-mca/LoongArch/lit.local.cfg b/llvm/test/tools/llvm-mca/LoongArch/lit.local.cfg
new file mode 100644
index 0000000000000..2b5a4893e686f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/LoongArch/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'LoongArch' in config.root.targets:
+ config.unsupported = True
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