[llvm] [llvm] Update tests to use struct path TBAA (PR #226051)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 24 00:50:42 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Nikita Popov (nikic)
<details>
<summary>Changes</summary>
The new format was introduced more than a decade ago, so make sure it's used in tests. The tests currently get away with it due to a TBAA upgrade applied in the IR parser.
Disclosure: AI-generated change.
---
Patch is 32.64 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226051.diff
46 Files Affected:
- (modified) llvm/test/CodeGen/AArch64/arm64-abi_align.ll (+4-2)
- (modified) llvm/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll (+6-3)
- (modified) llvm/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/arm64-prefetch-new.ll (+2-1)
- (modified) llvm/test/CodeGen/AArch64/arm64-prefetch.ll (+4-2)
- (modified) llvm/test/CodeGen/AArch64/instr-ref-ldv.ll (+2-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir (+6-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir (+12-4)
- (modified) llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll (+2-1)
- (modified) llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/circ_ld.ll (+6-3)
- (modified) llvm/test/CodeGen/Hexagon/cmpb-eq.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/early-if-spare.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/hwloop-preh.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/insert4.ll (+4-2)
- (modified) llvm/test/CodeGen/Hexagon/mux-basic.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/pic-simple.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/pic-static.ll (+4-2)
- (modified) llvm/test/CodeGen/Hexagon/predicate-logical.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/rdf-copy.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/sdata-basic.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/store-widen.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/swp-stages4.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/swp-stages5.ll (+2-1)
- (modified) llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll (+2-1)
- (modified) llvm/test/CodeGen/PowerPC/aa-tbaa.ll (+4-2)
- (modified) llvm/test/CodeGen/SystemZ/alias-01.ll (+4-2)
- (modified) llvm/test/CodeGen/X86/merge_store_duplicated_loads.ll (+8-6)
- (modified) llvm/test/Transforms/GVN/opt-remarks.ll (+2-1)
- (modified) llvm/test/Transforms/GVN/tbaa.ll (+2-1)
- (modified) llvm/test/Transforms/GVNSink/sink-common-code.ll (+4-2)
- (modified) llvm/test/Transforms/InstCombine/store.ll (+2-1)
- (modified) llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll (+4-2)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-metadata.ll (+4-2)
- (modified) llvm/test/Transforms/LoopVectorize/metadata.ll (+2-1)
- (modified) llvm/test/Transforms/MergedLoadStoreMotion/preserve-store-metadata.ll (+3-2)
- (modified) llvm/test/Transforms/NewGVN/tbaa.ll (+2-1)
- (modified) llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll (+2-1)
- (modified) llvm/test/Transforms/SLPVectorizer/X86/metadata.ll (+2-1)
- (modified) llvm/test/Transforms/SROA/tbaa-struct2.ll (+6-2)
- (modified) llvm/test/Transforms/Scalarizer/basic-inseltpoison.ll (+4-2)
- (modified) llvm/test/Transforms/Scalarizer/basic.ll (+4-2)
- (modified) llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll (+4-2)
- (modified) llvm/test/Transforms/SimplifyCFG/basictest.ll (+2-1)
- (modified) llvm/test/Transforms/VectorCombine/alias.ll (+2-1)
``````````diff
diff --git a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
index 4a36721a91e25..fc3f9c267e81f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
@@ -514,8 +514,10 @@ attributes #3 = { nounwind }
attributes #4 = { nounwind }
attributes #5 = { nobuiltin }
-!0 = !{!"int", !1}
+!0 = !{!5, !5, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
-!3 = !{!"short", !1}
+!3 = !{!6, !6, i64 0}
!4 = !{i64 0, i64 4, !0, i64 4, i64 2, !3, i64 8, i64 4, !0, i64 12, i64 2, !3, i64 16, i64 4, !0, i64 20, i64 2, !3}
+!5 = !{!"int", !1}
+!6 = !{!"short", !1}
diff --git a/llvm/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll b/llvm/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
index 358a2c3404815..a65a08b6e8b27 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
@@ -184,7 +184,10 @@ declare hidden fastcc i32 @Maze1Mech(i64, i64, i64, i64, i64, i32, i32) nounwind
; Materializable
declare hidden fastcc void @CleanNet(i64) nounwind ssp
-!0 = !{!"long", !1}
-!1 = !{!"omnipotent char", !2}
+!0 = !{!4, !4, i64 0}
+!1 = !{!5, !5, i64 0}
!2 = !{!"Simple C/C++ TBAA"}
-!3 = !{!"any pointer", !1}
+!3 = !{!6, !6, i64 0}
+!4 = !{!"long", !5}
+!5 = !{!"omnipotent char", !2}
+!6 = !{!"any pointer", !5}
diff --git a/llvm/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll b/llvm/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll
index 8ef31720806f1..bf6c7d1909dae 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll
@@ -19,6 +19,7 @@ define internal fastcc void @callee(ptr nocapture %p, i32 %a) nounwind optsize n
ret void
}
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/AArch64/arm64-prefetch-new.ll b/llvm/test/CodeGen/AArch64/arm64-prefetch-new.ll
index da7d74afe56be..06df6ad50f465 100644
--- a/llvm/test/CodeGen/AArch64/arm64-prefetch-new.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-prefetch-new.ll
@@ -61,7 +61,8 @@ declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 im
attributes #0 = { inaccessiblemem_or_argmemonly nounwind willreturn }
-!0 = !{!"int", !1}
+!0 = !{!4, !4, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{!"any pointer", !1}
+!4 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/AArch64/arm64-prefetch.ll b/llvm/test/CodeGen/AArch64/arm64-prefetch.ll
index 55652e3de5a17..1407e699ef6b5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-prefetch.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-prefetch.ll
@@ -105,7 +105,9 @@ entry:
declare void @llvm.prefetch(ptr nocapture, i32, i32, i32) nounwind
-!0 = !{!"int", !1}
+!0 = !{!4, !4, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
-!3 = !{!"any pointer", !1}
+!3 = !{!5, !5, i64 0}
+!4 = !{!"int", !1}
+!5 = !{!"any pointer", !1}
diff --git a/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll b/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll
index 7d9b495c89dc8..3bdbe4103748f 100644
--- a/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll
+++ b/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll
@@ -68,5 +68,6 @@ cleanup: ; preds = %_ZNK4llvm3opt7ArgLi
!9478 = distinct !DILocation(scope: !9391)
!9480 = !DILocation(scope: !9441, inlinedAt: !9478)
!9527 = !DILocation(scope: !9440, inlinedAt: !9478)
-!9528 = !{!"any pointer", !9530, i64 0}
+!9528 = !{!9533, !9533, i64 0, i64 0}
!9530 = !{}
+!9533 = !{!"any pointer", !9530}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
index 4b52e96f5a5ef..53684171867e8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
@@ -28,9 +28,10 @@
}
!0 = !{i24 0, i24 1048575}
- !1 = !{!"omnipotent char", !2}
+ !1 = !{!4, !4, i64 0}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{i24 0, i24 1048575}
+ !4 = !{!"omnipotent char", !2}
...
# Make sure range metadata is not preserved when widening loads, but
@@ -44,7 +45,7 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
+ ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !0, addrspace 1)
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
@@ -65,7 +66,7 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
+ ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !0, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !range !3, !tbaa !1)
@@ -81,7 +82,7 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
+ ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !0, addrspace 1)
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
@@ -102,7 +103,7 @@ body: |
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
- ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
+ ; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !0, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !tbaa !1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
index 0bbafccef1fd8..7d4d5cddbb417 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
@@ -16,9 +16,10 @@
}
!0 = !{i96 0, i96 9223372036854775808}
- !1 = !{!"omnipotent char", !2}
+ !1 = !{!4, !4, i64 0}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{i32 0, i32 2147483646}
+ !4 = !{!"omnipotent char", !2}
...
# Make sure range metadata is not preserved when widening loads, but
@@ -42,6 +43,13 @@ body: |
; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; GFX7-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
+ ;
+ ; GFX12-LABEL: name: split_smrd_load_range
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[LOAD:%[0-9]+]]:sgpr(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>) from constant-pool, align 8, !range !4, addrspace 4)
+ ; GFX12-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(<3 x s32>) = G_LOAD %0 :: (load (<3 x s32>) from constant-pool, align 8, addrspace 4, !range !3)
$sgpr0_sgpr1_sgpr2 = COPY %1
@@ -59,10 +67,10 @@ body: |
; GFX7: liveins: $sgpr0_sgpr1
; GFX7-NEXT: {{ $}}
; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
- ; GFX7-NEXT: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>) from constant-pool, !tbaa !2, addrspace 4)
+ ; GFX7-NEXT: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>) from constant-pool, !tbaa !1, addrspace 4)
; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(i64) = G_CONSTANT i64 8
; GFX7-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](i64)
- ; GFX7-NEXT: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s32) from constant-pool + 8, align 8, !tbaa !2, addrspace 4)
+ ; GFX7-NEXT: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s32) from constant-pool + 8, align 8, !tbaa !1, addrspace 4)
; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)
; GFX7-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -71,7 +79,7 @@ body: |
; GFX12: liveins: $sgpr0_sgpr1
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
- ; GFX12-NEXT: [[LOAD:%[0-9]+]]:sgpr(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>) from constant-pool, align 8, !tbaa !2, addrspace 4)
+ ; GFX12-NEXT: [[LOAD:%[0-9]+]]:sgpr(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>) from constant-pool, align 8, !tbaa !1, addrspace 4)
; GFX12-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(<3 x s32>) = G_LOAD %0 :: (load (<3 x s32>) from constant-pool, align 8, addrspace 4, !tbaa !1)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll b/llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
index e14ee60611236..7daee933f96c1 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-lds-with-alias-scope.ll
@@ -44,7 +44,7 @@ bb:
ret void
}
- !0 = !{!"omnipotent char", !1, i64 0}
+ !0 = !{!8, !8, i64 0, i64 0}
!1 = !{!1}
!2 = !{!3}
!3 = distinct !{!3, !4}
@@ -52,3 +52,4 @@ bb:
!5 = !{!3}
!6 = !{!7}
!7 = !{!7, !4}
+ !8 = !{!"omnipotent char", !1}
diff --git a/llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll b/llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
index fb17cdb1e4204..b2c13ec965fbe 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-lds-with-noalias.ll
@@ -61,12 +61,13 @@ bb:
ret void
}
- !0 = !{!"omnipotent char", !1, i64 0}
+ !0 = !{!6, !6, i64 0, i64 0}
!1 = !{!1}
!2 = !{!3}
!3 = distinct !{!3, !4}
!4 = distinct !{!4}
!5 = !{!3}
+ !6 = !{!"omnipotent char", !1}
;.
; CHECK: [[TBAA1]] = !{[[META2:![0-9]+]], [[META2]], i64 0, i64 0}
; CHECK: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]]}
diff --git a/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll b/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
index 2b9fd396ec879..9c00ca3bf7962 100644
--- a/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
+++ b/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll
@@ -63,8 +63,9 @@ declare i64 @llvm.hexagon.A4.combineir(i32, i32) nounwind readnone
declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) nounwind readnone
-!0 = !{!"long", !1}
+!0 = !{!5, !5, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{i32 18362}
!4 = !{i32 18893}
+!5 = !{!"long", !1}
diff --git a/llvm/test/CodeGen/Hexagon/circ_ld.ll b/llvm/test/CodeGen/Hexagon/circ_ld.ll
index a44de2d8f6f3f..71a3046e70119 100644
--- a/llvm/test/CodeGen/Hexagon/circ_ld.ll
+++ b/llvm/test/CodeGen/Hexagon/circ_ld.ll
@@ -115,7 +115,10 @@ entry:
declare ptr @llvm.hexagon.circ.ldw(ptr, ptr, i32, i32) nounwind
-!0 = !{!"omnipotent char", !1}
+!0 = !{!4, !4, i64 0}
!1 = !{!"Simple C/C++ TBAA"}
-!2 = !{!"short", !0}
-!3 = !{!"int", !0}
+!2 = !{!5, !5, i64 0}
+!3 = !{!6, !6, i64 0}
+!4 = !{!"omnipotent char", !1}
+!5 = !{!"short", !4}
+!6 = !{!"int", !4}
diff --git a/llvm/test/CodeGen/Hexagon/cmpb-eq.ll b/llvm/test/CodeGen/Hexagon/cmpb-eq.ll
index d88e11d12ec42..f394eba7bea32 100644
--- a/llvm/test/CodeGen/Hexagon/cmpb-eq.ll
+++ b/llvm/test/CodeGen/Hexagon/cmpb-eq.ll
@@ -49,5 +49,6 @@ if.end21: ; preds = %for.body
br i1 %tobool, label %if.then12.loopexit, label %for.body
}
-!0 = !{!"omnipotent char", !1}
+!0 = !{!2, !2, i64 0}
!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"omnipotent char", !1}
diff --git a/llvm/test/CodeGen/Hexagon/early-if-spare.ll b/llvm/test/CodeGen/Hexagon/early-if-spare.ll
index 07497e93dbe5c..9b32600868b5a 100644
--- a/llvm/test/CodeGen/Hexagon/early-if-spare.ll
+++ b/llvm/test/CodeGen/Hexagon/early-if-spare.ll
@@ -53,6 +53,7 @@ declare i32 @bar(ptr) nounwind
attributes #0 = { nounwind "target-cpu"="hexagonv5" }
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll
index c1a97220fc612..11487b6fa72a2 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll
@@ -37,8 +37,9 @@ return: ; preds = %return.loopexit, %f
ret i32 %retval.0
}
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" }
diff --git a/llvm/test/CodeGen/Hexagon/insert4.ll b/llvm/test/CodeGen/Hexagon/insert4.ll
index 1122b39870366..e11a84d0929d9 100644
--- a/llvm/test/CodeGen/Hexagon/insert4.ll
+++ b/llvm/test/CodeGen/Hexagon/insert4.ll
@@ -106,6 +106,8 @@ declare i64 @llvm.hexagon.A2.vaddhs(i64, i64) #1
attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" }
attributes #1 = { nounwind readnone }
-!0 = !{!"short", !1}
-!1 = !{!"omnipotent char", !2}
+!0 = !{!3, !3, i64 0}
+!1 = !{!4, !4, i64 0}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"short", !4}
+!4 = !{!"omnipotent char", !2}
diff --git a/llvm/test/CodeGen/Hexagon/mux-basic.ll b/llvm/test/CodeGen/Hexagon/mux-basic.ll
index 0707b744696a7..0cb23d4140d4d 100644
--- a/llvm/test/CodeGen/Hexagon/mux-basic.ll
+++ b/llvm/test/CodeGen/Hexagon/mux-basic.ll
@@ -22,6 +22,7 @@ entry:
ret void
}
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/Hexagon/pic-simple.ll b/llvm/test/CodeGen/Hexagon/pic-simple.ll
index b17dd599effa1..3d9d07cecebe7 100644
--- a/llvm/test/CodeGen/Hexagon/pic-simple.ll
+++ b/llvm/test/CodeGen/Hexagon/pic-simple.ll
@@ -17,6 +17,7 @@ entry:
declare i32 @baz(i32)
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/Hexagon/pic-static.ll b/llvm/test/CodeGen/Hexagon/pic-static.ll
index 8ef75a5f95d94..4d1974975e177 100644
--- a/llvm/test/CodeGen/Hexagon/pic-static.ll
+++ b/llvm/test/CodeGen/Hexagon/pic-static.ll
@@ -15,7 +15,9 @@ entry:
ret i32 %add
}
-!0 = !{!"any pointer", !1}
+!0 = !{!4, !4, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
-!3 = !{!"int", !1}
+!3 = !{!5, !5, i64 0}
+!4 = !{!"any pointer", !1}
+!5 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/Hexagon/predicate-logical.ll b/llvm/test/CodeGen/Hexagon/predicate-logical.ll
index f5217729fe8ec..3d3020cfc8b11 100644
--- a/llvm/test/CodeGen/Hexagon/predicate-logical.ll
+++ b/llvm/test/CodeGen/Hexagon/predicate-logical.ll
@@ -25,6 +25,7 @@ entry:
declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64) nounwind readnone
-!0 = !{!"long long", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"long long", !1}
diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy.ll b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
index 36cc0d4facf7c..084cc7e507922 100644
--- a/llvm/test/CodeGen/Hexagon/rdf-copy.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
@@ -52,6 +52,7 @@ if.end: ; preds = %if.end.loopexit, %e
attributes #0 = { nounwind "target-features"="-packets" }
-!0 = !{!"any pointer", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"any pointer", !1}
diff --git a/llvm/test/CodeGen/Hexagon/sdata-basic.ll b/llvm/test/CodeGen/Hexagon/sdata-basic.ll
index 3234c225e7a49..f626e891d5cf9 100644
--- a/llvm/test/CodeGen/Hexagon/sdata-basic.ll
+++ b/llvm/test/CodeGen/Hexagon/sdata-basic.ll
@@ -11,6 +11,7 @@ entry:
ret i32 %0
}
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/Hexagon/store-widen.ll b/llvm/test/CodeGen/Hexagon/store-widen.ll
index 931adbea00637..abbdeb6266b23 100644
--- a/llvm/test/CodeGen/Hexagon/store-widen.ll
+++ b/llvm/test/CodeGen/Hexagon/store-widen.ll
@@ -13,6 +13,7 @@ entry:
ret void
}
-!0 = !{!"short", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"short", !1}
diff --git a/llvm/test/CodeGen/Hexagon/swp-stages4.ll b/llvm/test/CodeGen/Hexagon/swp-stages4.ll
index fff6fb0177ce2..bab71473d03d5 100644
--- a/llvm/test/CodeGen/Hexagon/swp-stages4.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-stages4.ll
@@ -90,5 +90,6 @@ for.end104:
attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" }
-!0 = !{!"omnipotent char", !1}
+!0 = !{!2, !2, i64 0}
!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"omnipotent char", !1}
diff --git a/llvm/test/CodeGen/Hexagon/swp-stages5.ll b/llvm/test/CodeGen/Hexagon/swp-stages5.ll
index f3bc8891b4202..fef902334e12d 100644
--- a/llvm/test/CodeGen/Hexagon/swp-stages5.ll
+++ b/llvm/test/CodeGen/Hexagon/swp-stages5.ll
@@ -73,5 +73,6 @@ for.end:
attributes #0 = { nounwind }
-!0 = !{!"omnipotent char", !1}
+!0 = !{!2, !2, i64 0}
!1 = !{!"Simple C/C++ TBAA"}
+!2 = !{!"omnipotent char", !1}
diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll
index de9661e161a9c..19d06993bd096 100644
--- a/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll
@@ -465,6 +465,7 @@ declare i64 @llvm.hexagon.S2.asl.r.vw(i64, i32) #1
attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
-!0 = !{!"int", !1}
+!0 = !{!3, !3, i64 0}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/llvm/test/CodeGen/PowerPC/aa-tbaa.ll b/llvm/test/CodeGen/PowerPC/aa-tbaa.ll
index 02f5c39a769a3..1c47953933d63 100644
--- a/llvm/test/CodeGen/PowerPC/aa-tbaa.ll
+++ b/llvm/test/CodeGen/PowerPC/aa-tbaa.ll
@@ -36,6 +36,8 @@ next:
}
!0 = !{ !"root" }
-!1 = !{ !"set1", !0 }
-!2 = !{ !"set2", !0 }
+!1 = !{!3, !3, i64 0}
+!2 = !{!4, !4, i64 0}
+!3 = !{!"set1", !0}
+!4 = !{!"set2", !0}
diff --git a/llvm/test/CodeGen/SystemZ/alias-01.ll b/llvm/test/CodeGen/SystemZ/alias-01.ll
index 79792de99a6b4..92c5826ef1709 100644
--- a/llvm/test/CodeGen/SystemZ/alias-01.ll
+++ b/llvm/test/CodeGen/SystemZ/alias-01.ll
@@ -18,5 +18,7 @@ define void @f1(ptr %src1, ptr %dest) {
}
!0 = !{ !"root" }
-!1 = !{ !"set1", !0 }
-!2 = !{ !"set2", !0 }
+!1 = !{!3, !3, i64 0}
+!2 = !{!4, !4, i64 0}
+!3 = !{!"set1", !0}
+!4 = !{!"set2", !0}
diff --git a/llvm/test/CodeGen/X86/merge_store_duplicated_loads.ll b/llvm/test/CodeGen/X86/merge_store_duplicated_loads.ll
index 70c3e804f1216..d017c063a49dc 100644
--- a/llvm/test/CodeGen/X86/merge_store_duplicated_loads.ll
+++ b/llvm/test/CodeGen/X86/merge_store_duplicated_loads.ll
@@ -15,17 +15,17 @@ define void @merge_double(ptr noalias nocapture %st, ptr noalias nocapture reado
; CHECK-NEXT: movsd %xmm1, 24(%rdi)
; CHECK-NEXT: retq
%ld_idx1 = getelementptr inbounds double, ptr %ld, i64 1
- %ld0 = load double, ptr %ld, align 8, !tbaa !2
- %ld1 = load double, ptr %ld_idx1, align 8, !tbaa !2
+ %ld0 = load double, ptr %ld, align 8, !tbaa !5
+ %ld1 = load double, ptr %ld_idx1, align 8, !tbaa !5
%st_idx1 = getelementptr inbounds do...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226051
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