[llvm] RegisterCoalescer: Don't mark a remat def dead when the copy destination covers it (PR #226037)
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llvm-commits at lists.llvm.org
Wed Sep 23 23:46:13 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-regalloc
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
When rematerializing into a physical register that is not exactly the copy's
destination, reMaterializeDef marks the rematerialized def dead and adds an
implicit-def of the copy destination. That is only correct when the rematerialized
instruction defines more than the copy asked for, so the extra part really is unused.
It is wrong when the def is covered by the copy destination, since then it is
part of that live value:
undef %0.sub_32bit:gr64 = MOV32ri -11
$rax = COPY %0
; coalesces to
dead $eax = MOV32ri -11, implicit-def $rax
$eax is the live low half of $rax, so it must not be dead. Only set the dead
flag when the def has register units the copy destination does not cover.
This makes the dead flags consistent with what LiveVariables would produce
in these scenarios.
Co-Authored-By: Claude Opus 5 <noreply@<!-- -->anthropic.com>
---
Patch is 64.82 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226037.diff
15 Files Affected:
- (modified) llvm/lib/CodeGen/RegisterCoalescer.cpp (+9-5)
- (modified) llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/masked-udiv.ll (+208-225)
- (modified) llvm/test/CodeGen/X86/min-legal-vector-width.ll (+32-32)
- (added) llvm/test/CodeGen/X86/rematerialize-sub-super-reg-dead-flags.mir (+84)
- (modified) llvm/test/CodeGen/X86/rematerialize-sub-super-reg.mir (+60-5)
- (modified) llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/statepoint-invoke-ra.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/statepoint-ra.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/statepoint-vreg-details.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/udiv_fix.ll (+16-18)
- (modified) llvm/test/CodeGen/X86/udiv_fix_sat.ll (+40-42)
- (modified) llvm/test/CodeGen/X86/vector-idiv-strictfp.ll (+87-104)
- (modified) llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll (+60-72)
``````````diff
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 23b151ed7b981..85831d46a5dcb 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1639,11 +1639,15 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
assert(DstReg.isPhysical() &&
"Only expect virtual or physical registers in remat");
- // When we're rematerializing into a not-quite-right register we already add
- // the real definition as an implicit-def, but we should also be marking the
- // "official" register as dead, since nothing else is going to use it as a
- // result of this remat. Not doing this can affect pressure tracking.
- NewMI.getOperand(0).setIsDead(true);
+ // CopyDstReg is added as an implicit-def below. The remat may also define
+ // units CopyDstReg does not cover; nothing uses those, so the def is dead.
+ // If CopyDstReg covers every defined unit, the def is part of that live
+ // value and must stay live.
+ Register DefReg = NewMI.getOperand(0).getReg();
+ if (any_of(TRI->regunits(DefReg.asMCReg()), [&](MCRegUnit Unit) {
+ return !TRI->hasRegUnit(CopyDstReg, Unit);
+ }))
+ NewMI.getOperand(0).setIsDead(true);
bool HasDefMatchingCopy = false;
for (auto [OpIndex, Reg] : NewMIImplDefs) {
diff --git a/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir b/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
index ca087b17eab3f..87fdc47a526ba 100644
--- a/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
+++ b/llvm/test/CodeGen/X86/coalesce-commute-partial-def-implicit-read.mir
@@ -34,7 +34,7 @@ body: |
; CHECK-NEXT: successors: %bb.6(0x3efbefbf), %bb.3(0x41041041)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- ; CHECK-NEXT: dead $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
+ ; CHECK-NEXT: $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
; CHECK-NEXT: $rsi = COPY [[MOV32r0_1]]
; CHECK-NEXT: CALL64r [[MOV32r0_]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
diff --git a/llvm/test/CodeGen/X86/masked-udiv.ll b/llvm/test/CodeGen/X86/masked-udiv.ll
index 51114074232cb..7fbddc22cc38a 100644
--- a/llvm/test/CodeGen/X86/masked-udiv.ll
+++ b/llvm/test/CodeGen/X86/masked-udiv.ll
@@ -204,40 +204,39 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; SSE2-LABEL: udiv_v4i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,1,1]
+; SSE2-NEXT: movdqa %xmm0, %xmm5
+; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
; SSE2-NEXT: pslld $31, %xmm6
; SSE2-NEXT: psrad $31, %xmm6
-; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1,1]
-; SSE2-NEXT: pand %xmm6, %xmm2
-; SSE2-NEXT: pandn %xmm5, %xmm6
-; SSE2-NEXT: por %xmm2, %xmm6
-; SSE2-NEXT: movq %xmm6, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,1,1]
+; SSE2-NEXT: pslld $31, %xmm4
+; SSE2-NEXT: psrad $31, %xmm4
+; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [1,1]
+; SSE2-NEXT: pand %xmm4, %xmm2
+; SSE2-NEXT: pandn %xmm7, %xmm4
+; SSE2-NEXT: por %xmm2, %xmm4
+; SSE2-NEXT: movq %xmm4, %rcx
; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm6[2,3,2,3]
-; SSE2-NEXT: movq %xmm2, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: movq %rax, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[2,3,2,3]
+; SSE2-NEXT: movq %xmm2, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3]
+; SSE2-NEXT: movq %xmm2, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rsi
-; SSE2-NEXT: movq %rax, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,2,3,3]
-; SSE2-NEXT: pslld $31, %xmm4
-; SSE2-NEXT: psrad $31, %xmm4
-; SSE2-NEXT: pand %xmm4, %xmm3
-; SSE2-NEXT: pandn %xmm5, %xmm4
-; SSE2-NEXT: por %xmm3, %xmm4
-; SSE2-NEXT: movq %xmm4, %rdi
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm2
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-NEXT: pand %xmm6, %xmm3
+; SSE2-NEXT: pandn %xmm7, %xmm6
+; SSE2-NEXT: por %xmm3, %xmm6
+; SSE2-NEXT: movq %xmm6, %rcx
; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rdi
-; SSE2-NEXT: movq %rcx, %xmm0
-; SSE2-NEXT: movq %rsi, %xmm2
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-NEXT: divq %rcx
; SSE2-NEXT: movq %rax, %xmm2
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[2,3,2,3]
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[2,3,2,3]
; SSE2-NEXT: movq %xmm3, %rcx
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE2-NEXT: movq %xmm1, %rax
@@ -251,39 +250,38 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; SSE42-LABEL: udiv_v4i64:
; SSE42: # %bb.0:
; SSE42-NEXT: movdqa %xmm0, %xmm5
+; SSE42-NEXT: pshufd {{.*#+}} xmm6 = xmm4[2,2,3,3]
; SSE42-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm4[0],zero,xmm4[1],zero
; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd {{.*#+}} xmm6 = [1,1]
-; SSE42-NEXT: movapd %xmm6, %xmm7
+; SSE42-NEXT: movapd {{.*#+}} xmm4 = [1,1]
+; SSE42-NEXT: movapd %xmm4, %xmm7
; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm7
; SSE42-NEXT: pextrq $1, %xmm7, %rcx
; SSE42-NEXT: pextrq $1, %xmm5, %rax
+; SSE42-NEXT: psllq $63, %xmm6
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %rcx
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm4[2,2,3,3]
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movq %xmm7, %rdi
-; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm6
-; SSE42-NEXT: pextrq $1, %xmm6, %r8
-; SSE42-NEXT: pextrq $1, %xmm1, %rsi
+; SSE42-NEXT: movq %rax, %xmm8
+; SSE42-NEXT: movq %xmm7, %rcx
; SSE42-NEXT: movq %xmm5, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rdi
-; SSE42-NEXT: movq %rax, %rdi
-; SSE42-NEXT: movq %rsi, %rax
-; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r8
-; SSE42-NEXT: movq %rcx, %xmm2
-; SSE42-NEXT: movq %rdi, %xmm0
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE42-NEXT: divq %rcx
; SSE42-NEXT: movq %rax, %xmm2
-; SSE42-NEXT: movq %xmm6, %rcx
+; SSE42-NEXT: movdqa %xmm6, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm4
+; SSE42-NEXT: pextrq $1, %xmm4, %rcx
+; SSE42-NEXT: pextrq $1, %xmm1, %rax
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm8[0]
+; SSE42-NEXT: xorl %edx, %edx
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm0
+; SSE42-NEXT: movq %xmm4, %rcx
; SSE42-NEXT: movq %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
; SSE42-NEXT: movq %rax, %xmm1
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE42-NEXT: movdqa %xmm2, %xmm0
; SSE42-NEXT: retq
;
; AVX2-LABEL: udiv_v4i64:
@@ -303,20 +301,19 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; AVX2-NEXT: vmovq %xmm3, %rax
; AVX2-NEXT: xorl %edx, %edx
; AVX2-NEXT: divq %rsi
-; AVX2-NEXT: movq %rax, %rsi
-; AVX2-NEXT: vpextrq $1, %xmm1, %rdi
+; AVX2-NEXT: vmovq %rcx, %xmm2
+; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX2-NEXT: vmovq %rax, %xmm3
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rdi
-; AVX2-NEXT: movq %rax, %rdi
-; AVX2-NEXT: vmovq %rcx, %xmm2
-; AVX2-NEXT: vmovq %rsi, %xmm3
+; AVX2-NEXT: divq %rcx
+; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: vmovq %xmm1, %rsi
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: xorl %edx, %edx
-; AVX2-NEXT: divq %rcx
-; AVX2-NEXT: vmovq %rdi, %xmm0
+; AVX2-NEXT: divq %rsi
+; AVX2-NEXT: vmovq %rcx, %xmm0
; AVX2-NEXT: vmovq %rax, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -819,181 +816,169 @@ define <3 x i10> @udiv_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
define <8 x i64> @udiv_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i1> %m) {
; SSE2-LABEL: udiv_v8i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
-; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,0,0]
+; SSE2-NEXT: movdqa %xmm0, %xmm8
+; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm0[3,3,3,3]
; SSE2-NEXT: pshufhw {{.*#+}} xmm9 = xmm9[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
+; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm9
+; SSE2-NEXT: psrad $31, %xmm9
+; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm0[2,2,2,2]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm10 = xmm10[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm10[0,0,2,2]
; SSE2-NEXT: pslld $31, %xmm10
; SSE2-NEXT: psrad $31, %xmm10
-; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [1,1]
-; SSE2-NEXT: pand %xmm10, %xmm4
-; SSE2-NEXT: pandn %xmm9, %xmm10
-; SSE2-NEXT: por %xmm4, %xmm10
-; SSE2-NEXT: movq %xmm10, %rcx
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm0[1,1,1,1]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm11 = xmm11[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm11[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm12
+; SSE2-NEXT: psrad $31, %xmm12
+; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
+; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
+; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm0[0,0,2,2]
+; SSE2-NEXT: pslld $31, %xmm13
+; SSE2-NEXT: psrad $31, %xmm13
+; SSE2-NEXT: movdqa {{.*#+}} xmm11 = [1,1]
+; SSE2-NEXT: pand %xmm13, %xmm4
+; SSE2-NEXT: pandn %xmm11, %xmm13
+; SSE2-NEXT: por %xmm4, %xmm13
+; SSE2-NEXT: movq %xmm13, %rcx
+; SSE2-NEXT: movq %xmm8, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm10[2,3,2,3]
-; SSE2-NEXT: movq %xmm4, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: movq %rax, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm13[2,3,2,3]
+; SSE2-NEXT: movq %xmm4, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[2,3,2,3]
+; SSE2-NEXT: movq %xmm4, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rsi
-; SSE2-NEXT: movq %rax, %rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[1,1,1,1]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm0
-; SSE2-NEXT: psrad $31, %xmm0
-; SSE2-NEXT: pand %xmm0, %xmm5
-; SSE2-NEXT: pandn %xmm9, %xmm0
-; SSE2-NEXT: por %xmm5, %xmm0
-; SSE2-NEXT: movq %xmm0, %rdi
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm4
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
+; SSE2-NEXT: pand %xmm12, %xmm5
+; SSE2-NEXT: pandn %xmm11, %xmm12
+; SSE2-NEXT: por %xmm5, %xmm12
+; SSE2-NEXT: movq %xmm12, %rcx
; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %rdi
-; SSE2-NEXT: movq %rax, %rdi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %r8
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm4
+; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm12[2,3,2,3]
+; SSE2-NEXT: movq %xmm5, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r8
-; SSE2-NEXT: movq %rax, %r8
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[2,2,2,2]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm0
-; SSE2-NEXT: psrad $31, %xmm0
-; SSE2-NEXT: pand %xmm0, %xmm6
-; SSE2-NEXT: pandn %xmm9, %xmm0
-; SSE2-NEXT: por %xmm6, %xmm0
-; SSE2-NEXT: movq %xmm0, %r9
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0]
+; SSE2-NEXT: pand %xmm10, %xmm6
+; SSE2-NEXT: pandn %xmm11, %xmm10
+; SSE2-NEXT: por %xmm6, %xmm10
+; SSE2-NEXT: movq %xmm10, %rcx
; SSE2-NEXT: movq %xmm2, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r9
-; SSE2-NEXT: movq %rax, %r9
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %r10
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm5
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm10[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r10
-; SSE2-NEXT: movq %rax, %r10
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm8[3,3,3,3]
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE2-NEXT: pslld $31, %xmm5
-; SSE2-NEXT: psrad $31, %xmm5
-; SSE2-NEXT: pand %xmm5, %xmm7
-; SSE2-NEXT: pandn %xmm9, %xmm5
-; SSE2-NEXT: por %xmm7, %xmm5
-; SSE2-NEXT: movq %xmm5, %r11
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm1[0]
+; SSE2-NEXT: pand %xmm9, %xmm7
+; SSE2-NEXT: pandn %xmm11, %xmm9
+; SSE2-NEXT: por %xmm7, %xmm9
+; SSE2-NEXT: movq %xmm9, %rcx
; SSE2-NEXT: movq %xmm3, %rax
; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divq %r11
-; SSE2-NEXT: movq %rcx, %xmm0
-; SSE2-NEXT: movq %rsi, %xmm4
-; SSE2-NEXT: movq %rdi, %xmm1
-; SSE2-NEXT: movq %r8, %xmm6
-; SSE2-NEXT: movq %r9, %xmm2
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm6[0]
-; SSE2-NEXT: movq %r10, %xmm4
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
-; SSE2-NEXT: movq %rax, %xmm4
-; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3]
-; SSE2-NEXT: movq %xmm5, %rcx
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
-; SSE2-NEXT: movq %xmm3, %rax
+; SSE2-NEXT: divq %rcx
+; SSE2-NEXT: movq %rax, %xmm6
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm9[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rcx
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[2,3,2,3]
+; SSE2-NEXT: movq %xmm1, %rax
; SSE2-NEXT: xorl %edx, %edx
; SSE2-NEXT: divq %rcx
-; SSE2-NEXT: movq %rax, %xmm3
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
-; SSE2-NEXT: movdqa %xmm4, %xmm3
+; SSE2-NEXT: movq %rax, %xmm1
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm1[0]
+; SSE2-NEXT: movdqa %xmm4, %xmm1
+; SSE2-NEXT: movdqa %xmm5, %xmm2
+; SSE2-NEXT: movdqa %xmm6, %xmm3
; SSE2-NEXT: retq
;
; SSE42-LABEL: udiv_v8i64:
; SSE42: # %bb.0:
-; SSE42-NEXT: pushq %rbx
-; SSE42-NEXT: .cfi_def_cfa_offset 16
-; SSE42-NEXT: .cfi_offset %rbx, -16
-; SSE42-NEXT: movdqa %xmm0, %xmm8
-; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm10[0],zero,zero,zero,xmm10[1],zero,zero,zero
+; SSE42-NEXT: movdqa %xmm0, %xmm11
+; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
+; SSE42-NEXT: pshufd {{.*#+}} xmm8 = xmm0[3,3,3,3]
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm8 = xmm8[0],zero,zero,zero,xmm8[1],zero,zero,zero
+; SSE42-NEXT: psllq $63, %xmm8
+; SSE42-NEXT: pshufd {{.*#+}} xmm9 = xmm0[2,3,2,3]
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm9 = xmm9[0],zero,zero,zero,xmm9[1],zero,zero,zero
+; SSE42-NEXT: psllq $63, %xmm9
+; SSE42-NEXT: pshufd {{.*#+}} xmm10 = xmm0[1,1,1,1]
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm10 = xmm10[0],zero,zero,zero,xmm10[1],zero,zero,zero
+; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd {{.*#+}} xmm9 = [1,1]
-; SSE42-NEXT: movapd %xmm9, %xmm11
-; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm11
-; SSE42-NEXT: pextrq $1, %xmm11, %rcx
-; SSE42-NEXT: pextrq $1, %xmm8, %rax
+; SSE42-NEXT: movapd {{.*#+}} xmm12 = [1,1]
+; SSE42-NEXT: movapd %xmm12, %xmm13
+; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm13
+; SSE42-NEXT: pextrq $1, %xmm13, %rcx
+; SSE42-NEXT: pextrq $1, %xmm11, %rax
+; SSE42-NEXT: psllq $63, %xmm10
; SSE42-NEXT: xorl %edx, %edx
; SSE42-NEXT: divq %rcx
-; SSE42-NEXT: movq %rax, %rcx
-; SSE42-NEXT: movq %xmm11, %rsi
-; SSE42-NEXT: movq %xmm8, %rax
+; SSE42-NEXT: movq %rax, %xmm0
+; SSE42-NEXT: movq %xmm13, %rcx
+; SSE42-NEXT: movq %xmm11, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rsi
-; SSE42-NEXT: movq %rax, %rsi
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,1,1]
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movapd %xmm9, %xmm4
-; SSE42-NEXT: blendvpd %xmm0, %xmm5, %xmm4
-; SSE42-NEXT: pextrq $1, %xmm4, %rdi
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm4
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
+; SSE42-NEXT: movapd %xmm12, %xmm11
+; SSE42-NEXT: movdqa %xmm10, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm5, %xmm11
+; SSE42-NEXT: pextrq $1, %xmm11, %rcx
; SSE42-NEXT: pextrq $1, %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rdi
-; SSE42-NEXT: movq %rax, %rdi
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm10[2,3,2,3]
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movq %xmm4, %r8
-; SSE42-NEXT: movapd %xmm9, %xmm4
-; SSE42-NEXT: blendvpd %xmm0, %xmm6, %xmm4
-; SSE42-NEXT: pextrq $1, %xmm4, %r10
-; SSE42-NEXT: pextrq $1, %xmm2, %r9
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm5
+; SSE42-NEXT: movq %xmm11, %rcx
; SSE42-NEXT: movq %xmm1, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r8
-; SSE42-NEXT: movq %rax, %r8
-; SSE42-NEXT: movq %r9, %rax
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm1
+; SSE42-NEXT: movapd %xmm12, %xmm10
+; SSE42-NEXT: movdqa %xmm9, %xmm0
+; SSE42-NEXT: blendvpd %xmm0, %xmm6, %xmm10
+; SSE42-NEXT: pextrq $1, %xmm10, %rcx
+; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm5[0]
+; SSE42-NEXT: pextrq $1, %xmm2, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r10
-; SSE42-NEXT: movq %rax, %r9
-; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm10[3,3,3,3]
-; SSE42-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
-; SSE42-NEXT: psllq $63, %xmm0
-; SSE42-NEXT: movq %xmm4, %r11
-; SSE42-NEXT: blendvpd %xmm0, %xmm7, %xmm9
-; SSE42-NEXT: pextrq $1, %xmm9, %rbx
-; SSE42-NEXT: pextrq $1, %xmm3, %r10
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm5
+; SSE42-NEXT: movq %xmm10, %rcx
; SSE42-NEXT: movq %xmm2, %rax
; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %r11
-; SSE42-NEXT: movq %rax, %r11
-; SSE42-NEXT: movq %r10, %rax
-; SSE42-NEXT: xorl %edx, %edx
-; SSE42-NEXT: divq %rbx
-; SSE42-NEXT: movq %rcx, %xmm2
-; SSE42-NEXT: movq %rsi, %xmm0
-; SSE42-NEXT: movq %rdi, %xmm4
-; SSE42-NEXT: movq %r8, %xmm1
-; SSE42-NEXT: movq %r9, %xmm5
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
-; SSE42-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm4[0]
-; SSE42-NEXT: movq %r11, %xmm2
+; SSE42-NEXT: divq %rcx
+; SSE42-NEXT: movq %rax, %xmm2
+; SSE42-NEXT: movdqa %xmm8, %xmm0
+; SSE42...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226037
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