[llvm] [RISCV][TableGen] Return instruction size from isCompressibleInst (PR #225660)
Sudharsan Veeravalli via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 22:48:02 PDT 2026
https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/225660
>From f1cb65fd72100d4fcd7525e3a28b13b5e4f07392 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: Wed, 23 Sep 2026 14:34:16 +0530
Subject: [PATCH 1/4] [RISCV][TableGen] Return compressed instruction size from
isCompressibleInst
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 6 ++++--
llvm/test/TableGen/CompressInstEmitter/suboperands.td | 3 +++
llvm/test/TableGen/RegClassByHwModeCompressPat.td | 10 +++++++++-
llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp | 5 +----
llvm/utils/TableGen/CompressInstEmitter.cpp | 8 +++++++-
5 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index b057c6066516f..496a5ef31703a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2014,8 +2014,10 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
return getInstBundleSize(MI);
if (MI.getParent() && MI.getParent()->getParent()) {
- if (isCompressibleInst(MI, STI))
- return 2;
+ unsigned Size = 0;
+ if (isCompressibleInst(MI, STI, &Size)) {
+ return Size;
+ }
}
switch (Opcode) {
diff --git a/llvm/test/TableGen/CompressInstEmitter/suboperands.td b/llvm/test/TableGen/CompressInstEmitter/suboperands.td
index af0c861720162..b64d9e5f501e7 100644
--- a/llvm/test/TableGen/CompressInstEmitter/suboperands.td
+++ b/llvm/test/TableGen/CompressInstEmitter/suboperands.td
@@ -233,6 +233,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
// CHECK-NEXT: // small $dst, $addr
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: addr
+// CHECK-NEXT: if (Size) *Size = 2;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK: case Arch::BigInst2: {
@@ -246,6 +247,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
// CHECK-NEXT: // Operand: imm
+// CHECK-NEXT: if (Size) *Size = 2;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK: case Arch::BigInst3: {
@@ -258,5 +260,6 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
// CHECK-NEXT: // small $dst, $addr
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: addr
+// CHECK-NEXT: if (Size) *Size = 2;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
diff --git a/llvm/test/TableGen/RegClassByHwModeCompressPat.td b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
index 1e22ca8a4a2b8..e64b08918dbe4 100644
--- a/llvm/test/TableGen/RegClassByHwModeCompressPat.td
+++ b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
@@ -274,7 +274,9 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: }
// CHECK: static bool isCompressibleInst(const MachineInstr &MI,
-// CHECK-NEXT: const MyTargetSubtarget &STI) {
+// CHECK-NEXT: const MyTargetSubtarget &STI,
+// CHECK-NEXT: unsigned *Size = nullptr) {
+// CHECK-NEXT: if (Size) *Size = 0;
// CHECK-NEXT: {{\[\[}}maybe_unused]] unsigned HwModeId = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
// CHECK-NEXT: switch (MI.getOpcode()) {
// CHECK-NEXT: default: return false;
@@ -286,6 +288,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // ptr_mov.small $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
+// CHECK-NEXT: if (Size) *Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
@@ -295,6 +298,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // ptr_mov.tied $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
+// CHECK-NEXT: if (Size) *Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
@@ -303,6 +307,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: getMyTargetMCRegisterClass(MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]).contains(MI.getOperand(0).getReg())) {
// CHECK-NEXT: // ptr_mov.zero $dst
// CHECK-NEXT: // Operand: dst
+// CHECK-NEXT: if (Size) *Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: break;
@@ -315,6 +320,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // x_mov.small $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
+// CHECK-NEXT: if (Size) *Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
@@ -324,6 +330,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // x_mov.tied $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
+// CHECK-NEXT: if (Size) *Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
@@ -332,6 +339,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: getMyTargetMCRegisterClass(MyTarget::XRegsRegClassID).contains(MI.getOperand(0).getReg())) {
// CHECK-NEXT: // x_mov.zero $dst
// CHECK-NEXT: // Operand: dst
+// CHECK-NEXT: if (Size) *Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: break;
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index cb18413c7ddc2..f96b1047b6350 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -436,11 +436,8 @@ TEST_P(RISCVXQCIInstrInfoTest, XQCIEInstSize) {
return BuildMI(MBB, DebugLoc(), TII->get(Opcode)).addImm(4096).getInstr();
};
- // FIXME: The instructions being checked in this test all compress to 4 byte
- // instructions but getInstSizeInBytes() currently returns 2 for all
- // instructions that are compressible.
auto CheckSize = [&](MachineInstr *MI) {
- EXPECT_EQ(2u, TII->getInstSizeInBytes(*MI));
+ EXPECT_EQ(4u, TII->getInstSizeInBytes(*MI));
};
CheckSize(MakeLoad(RISCV::QC_E_LW));
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 8f8245ea9ed27..d0df24b15ec9f 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -633,7 +633,9 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
} else if (EType == EmitterType::CheckCompress) {
FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
- FuncH.indent(31) << "const " << TargetName << "Subtarget &STI) {\n";
+ FuncH.indent(31) << "const " << TargetName << "Subtarget &STI,\n";
+ FuncH.indent(31) << "unsigned *Size = nullptr) {\n";
+ FuncH.indent(2) << "if (Size) *Size = 0;\n";
}
// HwModeId is used if we have any RegClassByHwMode patterns
if (!Target.getAllRegClassByHwMode().empty())
@@ -901,6 +903,10 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
++OpNo;
}
}
+ if (EType == EmitterType::CheckCompress) {
+ CodeStream.indent(6) << "if (Size) *Size = " << Dest.TheDef->getValueAsInt("Size")
+ << ";\n";
+ }
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
mergeCondAndCode(CaseStream, CondString, CodeString);
>From 0d021a19b069700645c178de46e961b63d3871bb Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: Wed, 23 Sep 2026 15:21:36 +0530
Subject: [PATCH 2/4] Clang-format
---
llvm/utils/TableGen/CompressInstEmitter.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index d0df24b15ec9f..c2873c3ab6da8 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -904,8 +904,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
}
}
if (EType == EmitterType::CheckCompress) {
- CodeStream.indent(6) << "if (Size) *Size = " << Dest.TheDef->getValueAsInt("Size")
- << ";\n";
+ CodeStream.indent(6) << "if (Size) *Size = "
+ << Dest.TheDef->getValueAsInt("Size") << ";\n";
}
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
>From 9ec78ec45530c3863392b43106f09981d2d5864d Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: Thu, 24 Sep 2026 11:09:08 +0530
Subject: [PATCH 3/4] Make Size non-optional and remove braces
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 ++++----
.../TableGen/CompressInstEmitter/suboperands.td | 6 +++---
.../test/TableGen/RegClassByHwModeCompressPat.td | 16 ++++++++--------
llvm/utils/TableGen/CompressInstEmitter.cpp | 8 ++++----
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 496a5ef31703a..27270ee44f6e1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2003,8 +2003,9 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
if (requiresNTLHint(MI)) {
if (STI.hasStdExtZca()) {
- if (isCompressibleInst(MI, STI))
- return 4; // c.ntl.all + c.load/c.store
+ unsigned Size = 0;
+ if (isCompressibleInst(MI, STI, Size))
+ return 2 + Size; // c.ntl.all + c.load/c.store
return 6; // c.ntl.all + load/store
}
return 8; // ntl.all + load/store
@@ -2015,9 +2016,8 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
if (MI.getParent() && MI.getParent()->getParent()) {
unsigned Size = 0;
- if (isCompressibleInst(MI, STI, &Size)) {
+ if (isCompressibleInst(MI, STI, Size))
return Size;
- }
}
switch (Opcode) {
diff --git a/llvm/test/TableGen/CompressInstEmitter/suboperands.td b/llvm/test/TableGen/CompressInstEmitter/suboperands.td
index b64d9e5f501e7..76e53d899e0c3 100644
--- a/llvm/test/TableGen/CompressInstEmitter/suboperands.td
+++ b/llvm/test/TableGen/CompressInstEmitter/suboperands.td
@@ -233,7 +233,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
// CHECK-NEXT: // small $dst, $addr
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: addr
-// CHECK-NEXT: if (Size) *Size = 2;
+// CHECK-NEXT: Size = 2;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK: case Arch::BigInst2: {
@@ -247,7 +247,7 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
// CHECK-NEXT: // Operand: imm
-// CHECK-NEXT: if (Size) *Size = 2;
+// CHECK-NEXT: Size = 2;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK: case Arch::BigInst3: {
@@ -260,6 +260,6 @@ def : CompressPat<(BigInst3 RegsC:$dst, RegsC:$src, simm6:$imm),
// CHECK-NEXT: // small $dst, $addr
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: addr
-// CHECK-NEXT: if (Size) *Size = 2;
+// CHECK-NEXT: Size = 2;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
diff --git a/llvm/test/TableGen/RegClassByHwModeCompressPat.td b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
index e64b08918dbe4..9a9a8cc55cfa2 100644
--- a/llvm/test/TableGen/RegClassByHwModeCompressPat.td
+++ b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
@@ -275,8 +275,8 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK: static bool isCompressibleInst(const MachineInstr &MI,
// CHECK-NEXT: const MyTargetSubtarget &STI,
-// CHECK-NEXT: unsigned *Size = nullptr) {
-// CHECK-NEXT: if (Size) *Size = 0;
+// CHECK-NEXT: unsigned &Size) {
+// CHECK-NEXT: Size = 0;
// CHECK-NEXT: {{\[\[}}maybe_unused]] unsigned HwModeId = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
// CHECK-NEXT: switch (MI.getOpcode()) {
// CHECK-NEXT: default: return false;
@@ -288,7 +288,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // ptr_mov.small $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
-// CHECK-NEXT: if (Size) *Size = 1;
+// CHECK-NEXT: Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
@@ -298,7 +298,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // ptr_mov.tied $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
-// CHECK-NEXT: if (Size) *Size = 1;
+// CHECK-NEXT: Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
@@ -307,7 +307,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: getMyTargetMCRegisterClass(MyTargetRegClassByHwModeTables[HwModeId][MyTarget::PtrRC]).contains(MI.getOperand(0).getReg())) {
// CHECK-NEXT: // ptr_mov.zero $dst
// CHECK-NEXT: // Operand: dst
-// CHECK-NEXT: if (Size) *Size = 1;
+// CHECK-NEXT: Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: break;
@@ -320,7 +320,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // x_mov.small $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
-// CHECK-NEXT: if (Size) *Size = 1;
+// CHECK-NEXT: Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() && MI.getOperand(0).isReg() &&
@@ -330,7 +330,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: // x_mov.tied $dst, $src
// CHECK-NEXT: // Operand: dst
// CHECK-NEXT: // Operand: src
-// CHECK-NEXT: if (Size) *Size = 1;
+// CHECK-NEXT: Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: if (MI.getOperand(1).isReg() &&
@@ -339,7 +339,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK-NEXT: getMyTargetMCRegisterClass(MyTarget::XRegsRegClassID).contains(MI.getOperand(0).getReg())) {
// CHECK-NEXT: // x_mov.zero $dst
// CHECK-NEXT: // Operand: dst
-// CHECK-NEXT: if (Size) *Size = 1;
+// CHECK-NEXT: Size = 1;
// CHECK-NEXT: return true;
// CHECK-NEXT: } // if
// CHECK-NEXT: break;
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index c2873c3ab6da8..018391366108e 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -634,8 +634,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
} else if (EType == EmitterType::CheckCompress) {
FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
FuncH.indent(31) << "const " << TargetName << "Subtarget &STI,\n";
- FuncH.indent(31) << "unsigned *Size = nullptr) {\n";
- FuncH.indent(2) << "if (Size) *Size = 0;\n";
+ FuncH.indent(31) << "unsigned &Size) {\n";
+ FuncH.indent(2) << "Size = 0;\n";
}
// HwModeId is used if we have any RegClassByHwMode patterns
if (!Target.getAllRegClassByHwMode().empty())
@@ -904,8 +904,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
}
}
if (EType == EmitterType::CheckCompress) {
- CodeStream.indent(6) << "if (Size) *Size = "
- << Dest.TheDef->getValueAsInt("Size") << ";\n";
+ CodeStream.indent(6) << "Size = " << Dest.TheDef->getValueAsInt("Size")
+ << ";\n";
}
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
>From f78f964cc99e7db2443ba104fd7b93bf103b0a90 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: Thu, 24 Sep 2026 11:17:15 +0530
Subject: [PATCH 4/4] Add Comments
---
llvm/test/TableGen/RegClassByHwModeCompressPat.td | 1 +
llvm/utils/TableGen/CompressInstEmitter.cpp | 15 +++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/llvm/test/TableGen/RegClassByHwModeCompressPat.td b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
index 9a9a8cc55cfa2..da7eee03f8605 100644
--- a/llvm/test/TableGen/RegClassByHwModeCompressPat.td
+++ b/llvm/test/TableGen/RegClassByHwModeCompressPat.td
@@ -276,6 +276,7 @@ def : CompressPat<(PTR_MOV PtrRC:$dst, PtrRC:$src),
// CHECK: static bool isCompressibleInst(const MachineInstr &MI,
// CHECK-NEXT: const MyTargetSubtarget &STI,
// CHECK-NEXT: unsigned &Size) {
+// CHECK-NEXT: // Size is non-zero only when a compression pattern matches.
// CHECK-NEXT: Size = 0;
// CHECK-NEXT: {{\[\[}}maybe_unused]] unsigned HwModeId = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
// CHECK-NEXT: switch (MI.getOpcode()) {
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index 018391366108e..00d511626861a 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -50,11 +50,16 @@
// bool uncompressInst(MCInst &OutInst, const MCInst &MI,
// const MCSubtargetInfo &STI);
//
-// In addition, it exports a function for checking whether
-// an instruction is compressable:
+// In addition, it exports a function for checking whether an instruction is
+// compressible and, when it is, reporting the compressed instruction size:
//
-// bool isCompressibleInst(const MachineInstr& MI,
-// const <TargetName>Subtarget &STI);
+// bool isCompressibleInst(const MachineInstr &MI,
+// const <TargetName>Subtarget &STI,
+// unsigned &Size);
+//
+// Size is initialized to zero. A successful match sets Size to the non-zero
+// compressed instruction size and returns true. If the instruction is not
+// compressible, the function returns false and Size remains zero.
//
// The clients that include this auto-generated header file and
// invoke these functions can compress an instruction before emitting
@@ -635,6 +640,8 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
FuncH.indent(31) << "const " << TargetName << "Subtarget &STI,\n";
FuncH.indent(31) << "unsigned &Size) {\n";
+ FuncH.indent(2)
+ << "// Size is non-zero only when a compression pattern matches.\n";
FuncH.indent(2) << "Size = 0;\n";
}
// HwModeId is used if we have any RegClassByHwMode patterns
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