[llvm] Add v79 scalar non-temporal forms. (PR #226017)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 21:47:52 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Abinaya Saravanan (quic-asaravan)
<details>
<summary>Changes</summary>
Also add support for the non-temporal forms of dcfetch and dczeroa.
Fixes https://github.com/llvm/llvm-project/issues/221485
---
Full diff: https://github.com/llvm/llvm-project/pull/226017.diff
2 Files Affected:
- (modified) llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (+214)
- (added) llvm/test/MC/Hexagon/v79-nontemporal.s (+140)
``````````diff
diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
index b188134d60d39..a354abf9211e6 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -20987,6 +20987,199 @@ let BaseOpcode = "S2_storerb_pci";
let isNVStorable = 1;
let Constraints = "$Rx32 = $Rx32in";
}
+def S2_pstorerbf_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
+"if (!$Pv4) memb($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>,
+Enc_cc449f, Requires<[HasV79]> {
+let Inst{2-2} = 0b1;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010000;
+let isPredicated = 1;
+let isPredicatedFalse = 1;
+let addrMode = PostInc;
+let accessSize = ByteAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerbt_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
+"if ($Pv4) memb($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>,
+Enc_cc449f, Requires<[HasV79]> {
+let Inst{2-2} = 0b0;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010000;
+let isPredicated = 1;
+let addrMode = PostInc;
+let accessSize = ByteAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerdf_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
+"if (!$Pv4) memd($Rx32++#$Ii):nt = $Rtt32",
+tc_9edefe01, TypeST>,
+Enc_9a33d5, Requires<[HasV79]> {
+let Inst{2-2} = 0b1;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010110;
+let isPredicated = 1;
+let isPredicatedFalse = 1;
+let addrMode = PostInc;
+let accessSize = DoubleWordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerdt_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
+"if ($Pv4) memd($Rx32++#$Ii):nt = $Rtt32",
+tc_9edefe01, TypeST>,
+Enc_9a33d5, Requires<[HasV79]> {
+let Inst{2-2} = 0b0;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010110;
+let isPredicated = 1;
+let addrMode = PostInc;
+let accessSize = DoubleWordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerhf_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
+"if (!$Pv4) memh($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>,
+Enc_b886fd, Requires<[HasV79]> {
+let Inst{2-2} = 0b1;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010010;
+let isPredicated = 1;
+let isPredicatedFalse = 1;
+let addrMode = PostInc;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerht_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
+"if ($Pv4) memh($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>,
+Enc_b886fd, Requires<[HasV79]> {
+let Inst{2-2} = 0b0;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010010;
+let isPredicated = 1;
+let addrMode = PostInc;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerif_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
+"if (!$Pv4) memw($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>,
+Enc_7eaeb6, Requires<[HasV79]> {
+let Inst{2-2} = 0b1;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010100;
+let isPredicated = 1;
+let isPredicatedFalse = 1;
+let addrMode = PostInc;
+let accessSize = WordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_pstorerit_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
+"if ($Pv4) memw($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>,
+Enc_7eaeb6, Requires<[HasV79]> {
+let Inst{2-2} = 0b0;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b1;
+let Inst{31-21} = 0b10101010100;
+let isPredicated = 1;
+let addrMode = PostInc;
+let accessSize = WordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_storerb_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
+"memb($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>, Enc_10bc21,
+Requires<[HasV79]> {
+let Inst{2-0} = 0b000;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b10101010000;
+let addrMode = PostInc;
+let accessSize = ByteAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_storerd_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
+"memd($Rx32++#$Ii):nt = $Rtt32",
+tc_9edefe01, TypeST>, Enc_85bf58,
+Requires<[HasV79]> {
+let Inst{2-0} = 0b000;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b10101010110;
+let addrMode = PostInc;
+let accessSize = DoubleWordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_storerh_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
+"memh($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>, Enc_052c7d,
+Requires<[HasV79]> {
+let Inst{2-0} = 0b000;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b10101010010;
+let addrMode = PostInc;
+let accessSize = HalfWordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+def S2_storeri_pi_nt : HInst<
+(outs IntRegs:$Rx32),
+(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
+"memw($Rx32++#$Ii):nt = $Rt32",
+tc_9edefe01, TypeST>, Enc_db40cd,
+Requires<[HasV79]> {
+let Inst{2-0} = 0b000;
+let Inst{7-7} = 0b0;
+let Inst{13-13} = 0b0;
+let Inst{31-21} = 0b10101010100;
+let addrMode = PostInc;
+let accessSize = WordAccess;
+let mayStore = 1;
+let Constraints = "$Rx32 = $Rx32in";
+}
+
def S2_storerb_pcr : HInst<
(outs IntRegs:$Rx32),
(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
@@ -41208,6 +41401,17 @@ let addrMode = BaseImmOffset;
let isRestrictNoSlot1Store = 1;
let hasSideEffects = 1;
}
+def Y2_dcfetchbo_nt : HInst<
+(outs),
+(ins IntRegs:$Rs32, u11_3Imm:$Ii),
+"dcfetch($Rs32+#$Ii):nt",
+tc_2237d952, TypeLD>, Enc_2d829e,
+Requires<[HasV79]> {
+let Inst{13-11} = 0b100;
+let Inst{31-21} = 0b10010100000;
+let addrMode = BaseImmOffset;
+let isRestrictNoSlot1Store = 1;
+}
def Y2_dcinva : HInst<
(outs),
(ins IntRegs:$Rs32),
@@ -41268,6 +41472,16 @@ let isRestrictSlot1AOK = 1;
let mayStore = 1;
let hasSideEffects = 1;
}
+def Y2_dczeroa_nt : HInst<
+(outs),
+(ins IntRegs:$Rs32),
+"dczeroa($Rs32):nt",
+tc_b1ae5f67, TypeST>, Enc_ecbcc8, Requires<[HasV79]> {
+let Inst{13-0} = 0b10000000000000;
+let Inst{31-21} = 0b10100000110;
+let isRestrictSlot1AOK = 1;
+let mayStore = 1;
+}
def Y2_getimask : HInst<
(outs IntRegs:$Rd32),
(ins IntRegs:$Rs32),
diff --git a/llvm/test/MC/Hexagon/v79-nontemporal.s b/llvm/test/MC/Hexagon/v79-nontemporal.s
new file mode 100644
index 0000000000000..68910c255e2c3
--- /dev/null
+++ b/llvm/test/MC/Hexagon/v79-nontemporal.s
@@ -0,0 +1,140 @@
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv79 -show-encoding < %s \
+# RUN: | FileCheck %s --check-prefix=ENC
+#
+# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv79 \
+# RUN: -filetype=obj < %s \
+# RUN: | llvm-objdump --mcpu=hexagonv79 -d - \
+# RUN: | FileCheck %s --check-prefix=DIS
+#
+# Verify raw-byte disassembly independently from assembly.
+# RUN: echo "0x00 0xc3 0x02 0xaa" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-B
+#
+# RUN: echo "0x08 0xc3 0x82 0xaa" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-W
+#
+# RUN: echo "0x08 0xc2 0xc2 0xaa" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-D
+#
+# RUN: echo "0x08 0xe3 0x82 0xaa" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-P
+#
+# RUN: echo "0x0c 0xe3 0x82 0xaa" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-NP
+#
+# RUN: echo "0x00 0xe0 0xc2 0xa0" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-ZERO
+#
+# RUN: echo "0x00 0xe0 0x02 0x94" \
+# RUN: | llvm-mc -triple=hexagon -mcpu=hexagonv79 -disassemble \
+# RUN: | FileCheck %s --check-prefix=RAW-FETCH
+# RUN: echo 'memw(r2++#4):nt = r3' \
+# RUN: | not llvm-mc -triple=hexagon -mcpu=hexagonv75 2>&1 \
+# RUN: | FileCheck %s --check-prefix=V75-ERR
+
+{
+ memb(r2++#0):nt = r3
+}
+# ENC: memb(r2++#0):nt = r3
+# ENC-NEXT: } // encoding: [0x00,0xc3,0x02,0xaa]
+# DIS: memb(r2++#0x0):nt = r3
+
+{
+ memh(r2++#2):nt = r3
+}
+# ENC: memh(r2++#2):nt = r3
+# ENC-NEXT: } // encoding: [0x08,0xc3,0x42,0xaa]
+# DIS: memh(r2++#0x2):nt = r3
+
+{
+ memw(r2++#4):nt = r3
+}
+# ENC: memw(r2++#4):nt = r3
+# ENC-NEXT: } // encoding: [0x08,0xc3,0x82,0xaa]
+# DIS: memw(r2++#0x4):nt = r3
+
+{
+ memd(r2++#8):nt = r3:2
+}
+# ENC: memd(r2++#8):nt = r3:2
+# ENC-NEXT: } // encoding: [0x08,0xc2,0xc2,0xaa]
+# DIS: memd(r2++#0x8):nt = r3:2
+
+{
+ if (p0) memw(r2++#4):nt = r3
+}
+# ENC: if (p0) memw(r2++#4):nt = r3
+# ENC-NEXT: } // encoding: [0x08,0xe3,0x82,0xaa]
+# DIS: if (p0) memw(r2++#0x4):nt = r3
+
+{
+ if (!p0) memw(r2++#4):nt = r3
+}
+# ENC: if (!p0) memw(r2++#4):nt = r3
+# ENC-NEXT: } // encoding: [0x0c,0xe3,0x82,0xaa]
+# DIS: if (!p0) memw(r2++#0x4):nt = r3
+
+{
+ if (p0) memb(r2++#0):nt = r3
+}
+# ENC: if (p0) memb(r2++#0):nt = r3
+# ENC-NEXT: } // encoding: [0x00,0xe3,0x02,0xaa]
+
+{
+ if (!p0) memb(r2++#0):nt = r3
+}
+# ENC: if (!p0) memb(r2++#0):nt = r3
+# ENC-NEXT: } // encoding: [0x04,0xe3,0x02,0xaa]
+
+{
+ if (p0) memh(r2++#2):nt = r3
+}
+# ENC: if (p0) memh(r2++#2):nt = r3
+# ENC-NEXT: } // encoding: [0x08,0xe3,0x42,0xaa]
+
+{
+ if (!p0) memh(r2++#2):nt = r3
+}
+# ENC: if (!p0) memh(r2++#2):nt = r3
+# ENC-NEXT: } // encoding: [0x0c,0xe3,0x42,0xaa]
+
+{
+ if (p0) memd(r2++#8):nt = r3:2
+}
+# ENC: if (p0) memd(r2++#8):nt = r3:2
+# ENC-NEXT: } // encoding: [0x08,0xe2,0xc2,0xaa]
+
+{
+ if (!p0) memd(r2++#8):nt = r3:2
+}
+# ENC: if (!p0) memd(r2++#8):nt = r3:2
+# ENC-NEXT: } // encoding: [0x0c,0xe2,0xc2,0xaa]
+
+{
+ dczeroa(r2):nt
+}
+# ENC: dczeroa(r2):nt
+# ENC-NEXT: } // encoding: [0x00,0xe0,0xc2,0xa0]
+# DIS: dczeroa(r2):nt
+
+{
+ dcfetch(r2+#0):nt
+}
+# ENC: dcfetch(r2+#0):nt
+# ENC-NEXT: } // encoding: [0x00,0xe0,0x02,0x94]
+# DIS: dcfetch(r2+#0x0):nt
+
+# RAW-B: memb(r2++#0):nt = r3
+# RAW-W: memw(r2++#4):nt = r3
+# RAW-D: memd(r2++#8):nt = r3:2
+# RAW-P: if (p0) memw(r2++#4):nt = r3
+# RAW-NP: if (!p0) memw(r2++#4):nt = r3
+# RAW-ZERO: dczeroa(r2):nt
+# RAW-FETCH: dcfetch(r2+#0):nt
+# V75-ERR: error: instruction requires: -mv79 or higher
``````````
</details>
https://github.com/llvm/llvm-project/pull/226017
More information about the llvm-commits
mailing list