[llvm] a0e841b - [RISCV] Bump Zvfofp8min to 0.9 and add link to the spec. (#225848)
via llvm-commits
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Wed Sep 23 21:15:29 PDT 2026
Author: Craig Topper
Date: 2026-09-23T21:15:22-07:00
New Revision: a0e841b2d7034f3756d1c1a0c8fb5577e63fc114
URL: https://github.com/llvm/llvm-project/commit/a0e841b2d7034f3756d1c1a0c8fb5577e63fc114
DIFF: https://github.com/llvm/llvm-project/commit/a0e841b2d7034f3756d1c1a0c8fb5577e63fc114.diff
LOG: [RISCV] Bump Zvfofp8min to 0.9 and add link to the spec. (#225848)
The version was bumped to 0.9 when it was moved to an ISA manual PR.
Added:
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.md
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index df77bd2b2ac1f..d459b07c960c1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -257,7 +257,7 @@
// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)
// CHECK-NEXT: zvfbdota32f 0.2 'Zvfbdota32f' (FP32 batched dot-product extension)
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
-// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
+// CHECK-NEXT: zvfofp8min 0.9 'Zvfofp8min' (Vector OFP8 Converts)
// CHECK-NEXT: zvfqwbdota8f 0.2 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)
// CHECK-NEXT: zvfqwdota8f 0.2 'Zvfqwdota8f' (OCP FP8 Dot-Product)
// CHECK-NEXT: zvfwbdota16bf 0.2 'Zvfwbdota16bf' (BF16 batched dot-product extension)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index a387cef5d729d..3d667a6f46df5 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1799,12 +1799,12 @@
// CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32ifzvfofp8min0p2 -E -dM %s \
+// RUN: -march=rv32ifzvfofp8min0p9 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64ifzvfofp8min0p2 -E -dM %s \
+// RUN: -march=rv64ifzvfofp8min0p9 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s
-// CHECK-ZVFOFP8MIN-EXT: __riscv_zvfofp8min 2000{{$}}
+// CHECK-ZVFOFP8MIN-EXT: __riscv_zvfofp8min 9000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md
index c8fe7efcb10f0..9a8fc1ff5693d 100644
--- a/llvm/docs/RISCVUsage.md
+++ b/llvm/docs/RISCVUsage.md
@@ -407,6 +407,10 @@ The primary goal of experimental support is to assist in the process of ratifica
: LLVM implements the [0.1 draft specification](https://github.com/riscv/riscv-zilx).
+`experimental-zvfofp8min`
+
+: LLVM implements the [0.9 draft specification](https://github.com/riscv/riscv-isa-manual/pull/2979).
+
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
## Vendor Extensions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 78829df334114..d83a50bb68293 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -771,7 +771,7 @@ def HasStdExtZfhOrZvfh
"'Zvfh' (Vector Half-Precision Floating-Point)">;
def FeatureStdExtZvfofp8min
- : RISCVExperimentalExtension<0, 2,
+ : RISCVExperimentalExtension<0, 9,
"Vector OFP8 Converts", [FeatureStdExtZve32f]>;
def HasStdExtZvfofp8min
: Predicate<"Subtarget->hasStdExtZvfofp8min()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 75fa2e1e6a9e8..4e50291c4edde 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -518,7 +518,7 @@
; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0"
+; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0"
; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0"
; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr1p0"
; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
@@ -693,7 +693,7 @@
; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0"
+; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0"
; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0"
; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr1p0"
; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr1p0_zalrsc1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index fbc1d434eb03b..5f1c3e0a0d377 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -480,8 +480,8 @@
.attribute arch, "rv32i_zvfbfwma1p0"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-.attribute arch, "rv32i_zvfofp8min0p2"
-# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0"
+.attribute arch, "rv32i_zvfofp8min0p9"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0"
.attribute arch, "rv32ia_zacas1p0"
# CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index a85048987cb1b..774d49b444e3c 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1683,7 +1683,7 @@ Experimental extensions
zvdot4a8i 0.1
zvfbdota32f 0.2
zvfbfa 0.1
- zvfofp8min 0.2
+ zvfofp8min 0.9
zvfqwbdota8f 0.2
zvfqwdota8f 0.2
zvfwbdota16bf 0.2
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