[llvm] [RISCV] Require Zve32f for XAndesVSIntH FP conversions (PR #226001)

[Zeyi Xu via llvm-commits]

zeyi2 wrote:

A possible follow-up: The [Andes specification (PDF p. 125)](https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf#page=125) says: "For RV64, this extension is present if `misa.V == 1 & mmsc_cfg.VSIH == 1`, for RV32, it is present if `misa.V == 1 & mmsc_cfg2.VSIH == 1`".

The [RISC-V vector specification](https://github.com/riscvarchive/riscv-v-spec/blob/2f68ef7256d6ec53e4d2bd7cb12862f406d64e34/v-spec.adoc#L5121-L5127) associates `misa.v` with the single-letter V extension. And LLVM currently makes XAndesVSIntH imply only [Zve32x](https://github.com/llvm/llvm-project/blob/d34f738562d824c237ec35cfff3ec34f57ba41b0/llvm/lib/Target/RISCV/RISCVFeatures.td#L1651-L1653).

It is unclear to me whether this difference is intentional, so I have left the existing dependency unchanged in this PR.

https://github.com/llvm/llvm-project/pull/226001