[llvm] [RISCV] Require Zve32f for XAndesVSIntH FP conversions (PR #226001)

[Zeyi Xu via llvm-commits]

https://github.com/zeyi2 created https://github.com/llvm/llvm-project/pull/226001

None

>From 0703a553a6d511944f6ff506650c25acc58d9df1 Mon Sep 17 00:00:00 2001
From: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: Thu, 24 Sep 2026 10:57:29 +0800
Subject: [PATCH] [RISCV] Require Zve32f for XAndesVSIntH FP conversions

---
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td |  4 ++++
 llvm/test/MC/RISCV/xandesvsinth-invalid.s     | 15 +++++++++++++++
 llvm/test/MC/RISCV/xandesvsinth-valid.s       | 18 +++++++++---------
 3 files changed, 28 insertions(+), 9 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xandesvsinth-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
index e1d2920612907..b556b91adbd03 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
@@ -736,10 +736,14 @@ let Predicates = [HasVendorXAndesVBFHCvt],
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVendorXAndesVSIntH] in {
+
+  let append Predicates = [HasVInstructionsAnyF] in {
   def NDS_VFWCVT_F_N  : NDSRVInstVSINTCvt<0b00100, "nds.vfwcvt.f.n.v">;
   def NDS_VFWCVT_F_NU : NDSRVInstVSINTCvt<0b00101, "nds.vfwcvt.f.nu.v">;
   def NDS_VFWCVT_F_B  : NDSRVInstVSINTCvt<0b00110, "nds.vfwcvt.f.b.v">;
   def NDS_VFWCVT_F_BU : NDSRVInstVSINTCvt<0b00111, "nds.vfwcvt.f.bu.v">;
+  } // append Predicates = [HasVInstructionsAnyF]
+
   def NDS_VLE4_V : NDSRVInstVSINTLN<0b00000, "nds.vle4.v">;
 } // Predicates = [HasVendorXAndesVSIntH]
 
diff --git a/llvm/test/MC/RISCV/xandesvsinth-invalid.s b/llvm/test/MC/RISCV/xandesvsinth-invalid.s
new file mode 100644
index 0000000000000..818ac98d9e30e
--- /dev/null
+++ b/llvm/test/MC/RISCV/xandesvsinth-invalid.s
@@ -0,0 +1,15 @@
+# XAndesVSIntH - Andes Vector Small INT Handling Extension
+# RUN: not llvm-mc -triple=riscv32 -mattr=+xandesvsinth < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xandesvsinth < %s 2>&1 | FileCheck %s
+
+# CHECK: :[[@LINE+1]]:1: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors){{$}}
+nds.vfwcvt.f.n.v v8, v10
+
+# CHECK: :[[@LINE+1]]:1: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors){{$}}
+nds.vfwcvt.f.nu.v v8, v10
+
+# CHECK: :[[@LINE+1]]:1: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors){{$}}
+nds.vfwcvt.f.b.v v8, v10
+
+# CHECK: :[[@LINE+1]]:1: error: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32f' (Vector Extensions for Embedded Processors){{$}}
+nds.vfwcvt.f.bu.v v8, v10
diff --git a/llvm/test/MC/RISCV/xandesvsinth-valid.s b/llvm/test/MC/RISCV/xandesvsinth-valid.s
index 387bb116fe86f..ab5868676905b 100644
--- a/llvm/test/MC/RISCV/xandesvsinth-valid.s
+++ b/llvm/test/MC/RISCV/xandesvsinth-valid.s
@@ -1,17 +1,17 @@
-# XAndesVSIntLoad - Andes Vector INT4 Load Extension
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvsinth -show-encoding \
+# XAndesVSIntH - Andes Vector Small INT Handling Extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvsinth,+zve32f -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvsinth < %s \
-# RUN:     | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvsinth,+zve32f < %s \
+# RUN:     | llvm-objdump --mattr=+xandesvsinth,+zve32f -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ %s
-# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zve32f -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvsinth -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvsinth,+zve32f -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvsinth < %s \
-# RUN:     | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvsinth,+zve32f < %s \
+# RUN:     | llvm-objdump --mattr=+xandesvsinth,+zve32f -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ %s
-# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv64 -mattr=+zve32f -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # CHECK-OBJ: nds.vfwcvt.f.n.v  v8, v10
 # CHECK-ASM: nds.vfwcvt.f.n.v  v8, v10