[llvm] 620a9e9 - [RISCV] Combine two consecutive VSLIDEDOWN_VL nodes into one (#225232)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 16:47:22 PDT 2026
Author: Min-Yih Hsu
Date: 2026-09-23T16:47:13-07:00
New Revision: 620a9e9afaae2d51f186fd0f41988e3b326a127c
URL: https://github.com/llvm/llvm-project/commit/620a9e9afaae2d51f186fd0f41988e3b326a127c
DIFF: https://github.com/llvm/llvm-project/commit/620a9e9afaae2d51f186fd0f41988e3b326a127c.diff
LOG: [RISCV] Combine two consecutive VSLIDEDOWN_VL nodes into one (#225232)
Given this pattern
```
%down0 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset0, %mask, %vl0
%down1 = RISCVISD::VSLIDEDOWN_VL undef, %down0, %offset1, %mask, %vl1
```
we can turn it into
```
%down1 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset2, %mask, %vl1
```
where %offset2 is `%offset0 + %offset1`, if `%vl0 >= %offset1 + %vl1`.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5534eac885d9e..fd4c5024f044a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22468,6 +22468,12 @@ static SDValue performVECTOR_INTERLEAVECombine(SDNode *N, SelectionDAG &DAG) {
return DAG.getMergeValues(Operands, DL);
}
+static bool isVLMax(SDValue VL) {
+ return (isa<RegisterSDNode>(VL) &&
+ cast<RegisterSDNode>(VL)->getReg() == RISCV::X0) ||
+ isAllOnesConstant(VL);
+}
+
static SDValue performVSlideUpDownCombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
unsigned Opcode = N->getOpcode();
@@ -22477,64 +22483,110 @@ static SDValue performVSlideUpDownCombine(SDNode *N, SelectionDAG &DAG,
if (N->getOperand(1)->isUndef())
return N->getOperand(0);
- SDValue SlideDown = N->getOperand(1);
- SDValue SlideUpOffset = N->getOperand(2);
- SDValue SlideUpMask = N->getOperand(3);
- SDValue SlideUpVL = N->getOperand(4);
-
// Given this pattern
// ```
// %down = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset, %mask, %vl0
// %up = RISCVISD::VSLIDEUP_VL %val, %down, %offset, %mask, %vl1
// ```
// We can simplify it with `%val`, as it's doing redundant shifting.
- if (Opcode != RISCVISD::VSLIDEUP_VL ||
- SlideDown.getOpcode() != RISCVISD::VSLIDEDOWN_VL)
- return SDValue();
+ if (Opcode == RISCVISD::VSLIDEUP_VL) {
+ SDValue SlideDown = N->getOperand(1);
+ SDValue SlideUpOffset = N->getOperand(2);
+ SDValue SlideUpMask = N->getOperand(3);
+ SDValue SlideUpVL = N->getOperand(4);
- SDValue SlideDownPassthru = SlideDown->getOperand(0);
- SDValue SlideDownVal = SlideDown->getOperand(1);
- SDValue SlideDownOffset = SlideDown->getOperand(2);
- SDValue SlideDownMask = SlideDown->getOperand(3);
- SDValue SlideDownVL = SlideDown->getOperand(4);
- if (!SlideDownPassthru.isUndef() || SlideDownVal != N->getOperand(0) ||
- SlideDownOffset != SlideUpOffset)
- return SDValue();
+ if (SlideDown.getOpcode() != RISCVISD::VSLIDEDOWN_VL)
+ return SDValue();
- auto isVLMax = [](SDValue VL) {
- return (isa<RegisterSDNode>(VL) &&
- cast<RegisterSDNode>(VL)->getReg() == RISCV::X0) ||
- isAllOnesConstant(VL);
- };
+ SDValue SlideDownPassthru = SlideDown->getOperand(0);
+ SDValue SlideDownVal = SlideDown->getOperand(1);
+ SDValue SlideDownOffset = SlideDown->getOperand(2);
+ SDValue SlideDownMask = SlideDown->getOperand(3);
+ SDValue SlideDownVL = SlideDown->getOperand(4);
+ if (!SlideDownPassthru.isUndef() || SlideDownVal != N->getOperand(0) ||
+ SlideDownOffset != SlideUpOffset)
+ return SDValue();
+
+ // Check VLs.
+ // First, we need to worry about the zeros shifted into VSLIDEDOWN_VL. In
+ // this scenario, the worst case would be %vl0 = VLMAX, as %down is
+ // guaranteed to have those zeros. Our goal here is to ensure elements from
+ // %down that are actually inserted into %up are not those zeros. The number
+ // of %down that are actually inserted would be `%vl1 - %offset`, and the
+ // number of non-zero elements from %down would be `VLMAX - %offset`.
+ // Therefore, the invariant would be
+ // `%vl1 - %offset <= VLMAX - %offset` ---> `%vl1 <= VLMAX`
+ // Thus, we will never read those zeros that are shifted in by
+ // VSLIDEDOWN_VL. Second, we don't want slideup to read past the result
+ // produced by slidedown. So the condition for this case would be `%vl0 +
+ // %offset >= %vl1`.
+ if (!isVLMax(SlideDownVL)) {
+ KnownBits DownVLKB = DAG.computeKnownBits(SlideDownVL);
+ KnownBits UpVLKB = DAG.computeKnownBits(SlideUpVL);
+ KnownBits OffsetKB = DAG.computeKnownBits(SlideDownOffset);
+ if (!KnownBits::uge(KnownBits::add(DownVLKB, OffsetKB), UpVLKB)
+ .value_or(false))
+ return SDValue();
+ }
+
+ // Check if they are both all-ones masks.
+ if (SlideDownMask.getOpcode() != RISCVISD::VMSET_VL ||
+ SlideUpMask.getOpcode() != RISCVISD::VMSET_VL)
+ return SDValue();
+
+ return SlideDownVal;
+ }
+
+ // Given this pattern
+ // ```
+ // %down0 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset0, %mask, %vl0
+ // %down1 = RISCVISD::VSLIDEDOWN_VL undef, %down0, %offset1, %mask, %vl1
+ // ```
+ // we can turn it into
+ // ```
+ // %down1 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset2, %mask, %vl1
+ // ```
+ // where %offset2 is `%offset0 + %offset1`, if `%vl0 >= %offset1 + %vl1`.
+ // Note that we don't limit %down0 to be one-use as this transformation
+ // could improve IPC even if %down has more than one use.
+ SDValue Down0 = N->getOperand(1);
+ if (Down0.getOpcode() != RISCVISD::VSLIDEDOWN_VL ||
+ !N->getOperand(0).isUndef() || !Down0.getOperand(0).isUndef())
+ return SDValue();
+
+ SDValue Val = Down0.getOperand(1);
+ SDValue Offset0 = Down0.getOperand(2);
+ SDValue Mask0 = Down0.getOperand(3);
+ SDValue VL0 = Down0.getOperand(4);
+ SDValue Offset1 = N->getOperand(2);
+ SDValue Mask1 = N->getOperand(3);
+ SDValue VL1 = N->getOperand(4);
// Check VLs.
- // First, we need to worry about the zeros shifted into VSLIDEDOWN_VL. In this
- // scenario, the worst case would be %vl0 = VLMAX, as %down is guaranteed to
- // have those zeros. Our goal here is to ensure elements from %down that are
- // actually inserted into %up are not those zeros. The number of %down that
- // are actually inserted would be `%vl1 - %offset`, and the number of non-zero
- // elements from %down would be `VLMAX - %offset`. Therefore, the invariant
- // would be
- // `%vl1 - %offset <= VLMAX - %offset` ---> `%vl1 <= VLMAX`
- // Thus, we will never read those zeros that are shifted in by VSLIDEDOWN_VL.
- // Second, we don't want slideup to read past the result produced by
- // slidedown. So the condition for this case would be `%vl0 + %offset >=
- // %vl1`.
- if (!isVLMax(SlideDownVL)) {
- KnownBits DownVLKB = DAG.computeKnownBits(SlideDownVL);
- KnownBits UpVLKB = DAG.computeKnownBits(SlideUpVL);
- KnownBits OffsetKB = DAG.computeKnownBits(SlideDownOffset);
- if (!KnownBits::uge(KnownBits::add(DownVLKB, OffsetKB), UpVLKB)
+ if (!isVLMax(VL0)) {
+ KnownBits VL0KB = DAG.computeKnownBits(VL0);
+ KnownBits VL1KB = DAG.computeKnownBits(VL1);
+ KnownBits Offset1KB = DAG.computeKnownBits(Offset1);
+ if (!KnownBits::uge(VL0KB, KnownBits::add(VL1KB, Offset1KB))
.value_or(false))
return SDValue();
}
// Check if they are both all-ones masks.
- if (SlideDownMask.getOpcode() != RISCVISD::VMSET_VL ||
- SlideUpMask.getOpcode() != RISCVISD::VMSET_VL)
+ if (Mask0.getOpcode() != RISCVISD::VMSET_VL ||
+ Mask1.getOpcode() != RISCVISD::VMSET_VL)
return SDValue();
- return SlideDownVal;
+ SDLoc DL(N);
+ // Even if %offset0 and %offset1 are both constants, and `%offset0 + %offset1`
+ // exceeds uimm5, using an extra register to materialize the new offset + .vx
+ // is probably still more beneficial.
+ SDValue NewOffset =
+ DAG.getNode(ISD::ADD, DL, Subtarget.getXLenVT(), Offset0, Offset1);
+ EVT VecVT = N->getValueType(0);
+ return DAG.getNode(
+ RISCVISD::VSLIDEDOWN_VL, DL, VecVT,
+ {DAG.getPOISON(VecVT), Val, NewOffset, Mask1, VL1, N->getOperand(5)});
}
// Convert from one FMA opcode to another based on whether we are negating the
@@ -23985,10 +24037,7 @@ static SDValue combineTruncOfSraSext(SDNode *N, SelectionDAG &DAG) {
SDValue Mask = N->getOperand(1);
SDValue VL = N->getOperand(2);
- bool IsVLMAX = isAllOnesConstant(VL) ||
- (isa<RegisterSDNode>(VL) &&
- cast<RegisterSDNode>(VL)->getReg() == RISCV::X0);
- if (!IsVLMAX || Mask.getOpcode() != RISCVISD::VMSET_VL ||
+ if (!isVLMax(VL) || Mask.getOpcode() != RISCVISD::VMSET_VL ||
Mask.getOperand(0) != VL)
return SDValue();
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index 5f99971612eb5..1baa2a14cf57c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -701,17 +701,61 @@ define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_12
+; RV64ZVE32F-NEXT: .LBB12_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_13
+; RV64ZVE32F-NEXT: .LBB12_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB12_5
+; RV64ZVE32F-NEXT: .LBB12_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB12_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_15
+; RV64ZVE32F-NEXT: .LBB12_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_16
+; RV64ZVE32F-NEXT: .LBB12_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB12_10
+; RV64ZVE32F-NEXT: .LBB12_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lbu a0, 0(a0)
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB12_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB12_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB12_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB12_2
+; RV64ZVE32F-NEXT: .LBB12_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -720,46 +764,30 @@ define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB12_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB12_3
+; RV64ZVE32F-NEXT: .LBB12_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, mf2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB12_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB12_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB12_4
+; RV64ZVE32F-NEXT: j .LBB12_5
+; RV64ZVE32F-NEXT: .LBB12_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, mf2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB12_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB12_7
+; RV64ZVE32F-NEXT: .LBB12_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -768,34 +796,20 @@ define <8 x i8> @mgather_baseidx_v8i8(ptr %base, <8 x i8> %idxs, <8 x i1> %m, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB12_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB12_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB12_8
+; RV64ZVE32F-NEXT: .LBB12_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, mf2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB12_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB12_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB12_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB12_9
+; RV64ZVE32F-NEXT: j .LBB12_10
%ptrs = getelementptr inbounds i8, ptr %base, <8 x i8> %idxs
%v = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> %m, <8 x i8> %passthru)
ret <8 x i8> %v
@@ -1383,18 +1397,66 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_12
+; RV64ZVE32F-NEXT: .LBB23_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_13
+; RV64ZVE32F-NEXT: .LBB23_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB23_5
+; RV64ZVE32F-NEXT: .LBB23_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB23_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_15
+; RV64ZVE32F-NEXT: .LBB23_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_16
+; RV64ZVE32F-NEXT: .LBB23_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB23_10
+; RV64ZVE32F-NEXT: .LBB23_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB23_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB23_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB23_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB23_2
+; RV64ZVE32F-NEXT: .LBB23_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1405,40 +1467,23 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB23_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB23_3
+; RV64ZVE32F-NEXT: .LBB23_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB23_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB23_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB23_4
+; RV64ZVE32F-NEXT: j .LBB23_5
+; RV64ZVE32F-NEXT: .LBB23_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -1447,10 +1492,9 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB23_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB23_7
+; RV64ZVE32F-NEXT: .LBB23_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1461,13 +1505,12 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB23_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB23_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB23_8
+; RV64ZVE32F-NEXT: .LBB23_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
@@ -1475,24 +1518,9 @@ define <8 x i16> @mgather_baseidx_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB23_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB23_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB23_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB23_9
+; RV64ZVE32F-NEXT: j .LBB23_10
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i8> %idxs
%v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
ret <8 x i16> %v
@@ -1524,18 +1552,66 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_12
+; RV64ZVE32F-NEXT: .LBB24_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_13
+; RV64ZVE32F-NEXT: .LBB24_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB24_5
+; RV64ZVE32F-NEXT: .LBB24_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB24_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_15
+; RV64ZVE32F-NEXT: .LBB24_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_16
+; RV64ZVE32F-NEXT: .LBB24_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB24_10
+; RV64ZVE32F-NEXT: .LBB24_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB24_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB24_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB24_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB24_2
+; RV64ZVE32F-NEXT: .LBB24_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1546,40 +1622,23 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB24_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB24_3
+; RV64ZVE32F-NEXT: .LBB24_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB24_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB24_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB24_4
+; RV64ZVE32F-NEXT: j .LBB24_5
+; RV64ZVE32F-NEXT: .LBB24_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -1588,10 +1647,9 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB24_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB24_7
+; RV64ZVE32F-NEXT: .LBB24_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1602,13 +1660,12 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB24_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB24_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB24_8
+; RV64ZVE32F-NEXT: .LBB24_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
@@ -1616,24 +1673,9 @@ define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB24_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB24_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB24_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB24_9
+; RV64ZVE32F-NEXT: j .LBB24_10
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs
%v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
@@ -1664,8 +1706,59 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_12
+; RV64ZVE32F-NEXT: .LBB25_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_13
+; RV64ZVE32F-NEXT: .LBB25_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB25_5
+; RV64ZVE32F-NEXT: .LBB25_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB25_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_15
+; RV64ZVE32F-NEXT: .LBB25_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_16
+; RV64ZVE32F-NEXT: .LBB25_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB25_10
+; RV64ZVE32F-NEXT: .LBB25_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: zext.b a1, a1
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB25_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB25_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -1673,10 +1766,9 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB25_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB25_2
+; RV64ZVE32F-NEXT: .LBB25_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1688,55 +1780,36 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB25_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB25_3
+; RV64ZVE32F-NEXT: .LBB25_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB25_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: bnez a2, .LBB25_4
+; RV64ZVE32F-NEXT: j .LBB25_5
+; RV64ZVE32F-NEXT: .LBB25_14: # %cond.load10
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB25_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB25_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB25_7
+; RV64ZVE32F-NEXT: .LBB25_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1748,13 +1821,12 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB25_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB25_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB25_8
+; RV64ZVE32F-NEXT: .LBB25_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -1763,25 +1835,9 @@ define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB25_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB25_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: zext.b a1, a1
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB25_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB25_9
+; RV64ZVE32F-NEXT: j .LBB25_10
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs
%v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
@@ -1812,18 +1868,64 @@ define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_12
+; RV64ZVE32F-NEXT: .LBB26_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_13
+; RV64ZVE32F-NEXT: .LBB26_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB26_5
+; RV64ZVE32F-NEXT: .LBB26_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB26_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_15
+; RV64ZVE32F-NEXT: .LBB26_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_16
+; RV64ZVE32F-NEXT: .LBB26_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB26_10
+; RV64ZVE32F-NEXT: .LBB26_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB26_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB26_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB26_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB26_2
+; RV64ZVE32F-NEXT: .LBB26_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1833,38 +1935,22 @@ define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB26_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB26_3
+; RV64ZVE32F-NEXT: .LBB26_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB26_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB26_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB26_4
+; RV64ZVE32F-NEXT: j .LBB26_5
+; RV64ZVE32F-NEXT: .LBB26_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -1872,10 +1958,9 @@ define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB26_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB26_7
+; RV64ZVE32F-NEXT: .LBB26_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1885,36 +1970,21 @@ define <8 x i16> @mgather_baseidx_v8i16(ptr %base, <8 x i16> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB26_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB26_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB26_8
+; RV64ZVE32F-NEXT: .LBB26_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB26_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB26_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB26_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB26_9
+; RV64ZVE32F-NEXT: j .LBB26_10
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %idxs
%v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
ret <8 x i16> %v
@@ -2389,18 +2459,66 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_12
+; RV64ZVE32F-NEXT: .LBB35_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_13
+; RV64ZVE32F-NEXT: .LBB35_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_5
+; RV64ZVE32F-NEXT: .LBB35_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB35_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_15
+; RV64ZVE32F-NEXT: .LBB35_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_16
+; RV64ZVE32F-NEXT: .LBB35_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB35_10
+; RV64ZVE32F-NEXT: .LBB35_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lw a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB35_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB35_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB35_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_2
+; RV64ZVE32F-NEXT: .LBB35_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2411,40 +2529,23 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB35_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_3
+; RV64ZVE32F-NEXT: .LBB35_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB35_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB35_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_4
+; RV64ZVE32F-NEXT: j .LBB35_5
+; RV64ZVE32F-NEXT: .LBB35_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2453,10 +2554,9 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB35_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_7
+; RV64ZVE32F-NEXT: .LBB35_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2467,13 +2567,12 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB35_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_8
+; RV64ZVE32F-NEXT: .LBB35_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
@@ -2481,24 +2580,9 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB35_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB35_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB35_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB35_9
+; RV64ZVE32F-NEXT: j .LBB35_10
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i8> %idxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
ret <8 x i32> %v
@@ -2529,18 +2613,66 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_12
+; RV64ZVE32F-NEXT: .LBB36_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_13
+; RV64ZVE32F-NEXT: .LBB36_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB36_5
+; RV64ZVE32F-NEXT: .LBB36_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB36_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_15
+; RV64ZVE32F-NEXT: .LBB36_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_16
+; RV64ZVE32F-NEXT: .LBB36_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB36_10
+; RV64ZVE32F-NEXT: .LBB36_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lw a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB36_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB36_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB36_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB36_2
+; RV64ZVE32F-NEXT: .LBB36_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2551,40 +2683,23 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB36_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB36_3
+; RV64ZVE32F-NEXT: .LBB36_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB36_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB36_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB36_4
+; RV64ZVE32F-NEXT: j .LBB36_5
+; RV64ZVE32F-NEXT: .LBB36_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2593,10 +2708,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB36_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB36_7
+; RV64ZVE32F-NEXT: .LBB36_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2607,13 +2721,12 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB36_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB36_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB36_8
+; RV64ZVE32F-NEXT: .LBB36_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
@@ -2621,24 +2734,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB36_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB36_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB36_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB36_9
+; RV64ZVE32F-NEXT: j .LBB36_10
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
@@ -2671,19 +2769,69 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_12
+; RV64ZVE32F-NEXT: .LBB37_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_13
+; RV64ZVE32F-NEXT: .LBB37_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB37_5
+; RV64ZVE32F-NEXT: .LBB37_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB37_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_15
+; RV64ZVE32F-NEXT: .LBB37_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_16
+; RV64ZVE32F-NEXT: .LBB37_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB37_10
+; RV64ZVE32F-NEXT: .LBB37_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: zext.b a1, a1
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lw a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB37_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB37_11: # %cond.load
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB37_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB37_2
+; RV64ZVE32F-NEXT: .LBB37_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2695,42 +2843,24 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB37_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB37_3
+; RV64ZVE32F-NEXT: .LBB37_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB37_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB37_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB37_4
+; RV64ZVE32F-NEXT: j .LBB37_5
+; RV64ZVE32F-NEXT: .LBB37_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -2740,10 +2870,9 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB37_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB37_7
+; RV64ZVE32F-NEXT: .LBB37_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2755,13 +2884,12 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB37_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB37_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB37_8
+; RV64ZVE32F-NEXT: .LBB37_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2770,25 +2898,9 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB37_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB37_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: zext.b a1, a1
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB37_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB37_9
+; RV64ZVE32F-NEXT: j .LBB37_10
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
@@ -2821,8 +2933,57 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_12
+; RV64ZVE32F-NEXT: .LBB38_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_13
+; RV64ZVE32F-NEXT: .LBB38_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB38_5
+; RV64ZVE32F-NEXT: .LBB38_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB38_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_15
+; RV64ZVE32F-NEXT: .LBB38_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_16
+; RV64ZVE32F-NEXT: .LBB38_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB38_10
+; RV64ZVE32F-NEXT: .LBB38_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lw a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB38_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB38_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -2830,10 +2991,9 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB38_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB38_2
+; RV64ZVE32F-NEXT: .LBB38_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2844,40 +3004,23 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB38_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB38_3
+; RV64ZVE32F-NEXT: .LBB38_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB38_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB38_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB38_4
+; RV64ZVE32F-NEXT: j .LBB38_5
+; RV64ZVE32F-NEXT: .LBB38_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -2886,10 +3029,9 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB38_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB38_7
+; RV64ZVE32F-NEXT: .LBB38_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2900,13 +3042,12 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB38_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB38_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB38_8
+; RV64ZVE32F-NEXT: .LBB38_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
@@ -2914,24 +3055,9 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB38_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB38_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB38_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB38_9
+; RV64ZVE32F-NEXT: j .LBB38_10
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i16> %idxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
ret <8 x i32> %v
@@ -2963,8 +3089,57 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_12
+; RV64ZVE32F-NEXT: .LBB39_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_13
+; RV64ZVE32F-NEXT: .LBB39_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB39_5
+; RV64ZVE32F-NEXT: .LBB39_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB39_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_15
+; RV64ZVE32F-NEXT: .LBB39_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_16
+; RV64ZVE32F-NEXT: .LBB39_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB39_10
+; RV64ZVE32F-NEXT: .LBB39_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lw a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB39_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB39_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -2972,10 +3147,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB39_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB39_2
+; RV64ZVE32F-NEXT: .LBB39_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -2986,40 +3160,23 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB39_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB39_3
+; RV64ZVE32F-NEXT: .LBB39_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB39_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB39_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB39_4
+; RV64ZVE32F-NEXT: j .LBB39_5
+; RV64ZVE32F-NEXT: .LBB39_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -3028,10 +3185,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB39_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB39_7
+; RV64ZVE32F-NEXT: .LBB39_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -3042,13 +3198,12 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB39_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB39_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB39_8
+; RV64ZVE32F-NEXT: .LBB39_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
@@ -3056,24 +3211,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB39_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB39_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB39_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB39_9
+; RV64ZVE32F-NEXT: j .LBB39_10
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
@@ -3106,22 +3246,19 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 46
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB40_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_12
+; RV64ZVE32F-NEXT: .LBB40_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_13
+; RV64ZVE32F-NEXT: .LBB40_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB40_5
+; RV64ZVE32F-NEXT: .LBB40_4: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
@@ -3129,29 +3266,52 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB40_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 46
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB40_6: # %else5
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB40_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_15
+; RV64ZVE32F-NEXT: .LBB40_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_16
+; RV64ZVE32F-NEXT: .LBB40_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB40_10
+; RV64ZVE32F-NEXT: .LBB40_9: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 48
+; RV64ZVE32F-NEXT: srli a1, a1, 46
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lw a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB40_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB40_11: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 46
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB40_2
+; RV64ZVE32F-NEXT: .LBB40_12: # %cond.load1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
@@ -3159,14 +3319,26 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: lw a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB40_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB40_3
+; RV64ZVE32F-NEXT: .LBB40_13: # %cond.load4
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 46
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB40_4
+; RV64ZVE32F-NEXT: j .LBB40_5
+; RV64ZVE32F-NEXT: .LBB40_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
@@ -3176,10 +3348,9 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB40_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB40_7
+; RV64ZVE32F-NEXT: .LBB40_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -3191,13 +3362,12 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB40_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB40_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB40_8
+; RV64ZVE32F-NEXT: .LBB40_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -3206,25 +3376,9 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB40_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB40_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 48
-; RV64ZVE32F-NEXT: srli a1, a1, 46
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lw a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB40_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB40_9
+; RV64ZVE32F-NEXT: j .LBB40_10
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %eidxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
@@ -3254,79 +3408,43 @@ define <8 x i32> @mgather_baseidx_v8i32(ptr %base, <8 x i32> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB41_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB41_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_12
+; RV64ZVE32F-NEXT: .LBB41_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB41_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1
-; RV64ZVE32F-NEXT: .LBB41_4: # %else2
+; RV64ZVE32F-NEXT: .LBB41_3: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB41_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v13, a2
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 2
-; RV64ZVE32F-NEXT: .LBB41_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
+; RV64ZVE32F-NEXT: .LBB41_4: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB41_15
-; RV64ZVE32F-NEXT: # %bb.7: # %else8
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_13
+; RV64ZVE32F-NEXT: # %bb.5: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB41_16
-; RV64ZVE32F-NEXT: .LBB41_8: # %else11
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_14
+; RV64ZVE32F-NEXT: .LBB41_6: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB41_10
-; RV64ZVE32F-NEXT: .LBB41_9: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB41_10: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_15
+; RV64ZVE32F-NEXT: .LBB41_7: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB41_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB41_12: # %else17
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_16
+; RV64ZVE32F-NEXT: .LBB41_8: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB41_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
+; RV64ZVE32F-NEXT: beqz a1, .LBB41_10
+; RV64ZVE32F-NEXT: .LBB41_9: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v12, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -3334,31 +3452,76 @@ define <8 x i32> @mgather_baseidx_v8i32(ptr %base, <8 x i32> %idxs, <8 x i1> %m,
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB41_14: # %else20
+; RV64ZVE32F-NEXT: .LBB41_10: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv2r.v v8, v10
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB41_15: # %cond.load7
+; RV64ZVE32F-NEXT: .LBB41_11: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB41_2
+; RV64ZVE32F-NEXT: .LBB41_12: # %cond.load1
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB41_3
+; RV64ZVE32F-NEXT: j .LBB41_4
+; RV64ZVE32F-NEXT: .LBB41_13: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.s.x v8, a2
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 3
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB41_8
-; RV64ZVE32F-NEXT: .LBB41_16: # %cond.load10
+; RV64ZVE32F-NEXT: beqz a2, .LBB41_6
+; RV64ZVE32F-NEXT: .LBB41_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lw a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
+; RV64ZVE32F-NEXT: vmv.s.x v8, a2
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB41_9
+; RV64ZVE32F-NEXT: beqz a2, .LBB41_7
+; RV64ZVE32F-NEXT: .LBB41_15: # %cond.load13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v12, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v8, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: beqz a2, .LBB41_8
+; RV64ZVE32F-NEXT: .LBB41_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v12, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lw a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v8, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 6
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB41_9
; RV64ZVE32F-NEXT: j .LBB41_10
%ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %idxs
%v = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x i32> %passthru)
@@ -4120,110 +4283,112 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-LABEL: mgather_baseidx_v8i8_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB48_3
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
+; RV64ZVE32F-NEXT: beqz a3, .LBB48_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB48_4
+; RV64ZVE32F-NEXT: andi a4, a6, 2
+; RV64ZVE32F-NEXT: bnez a4, .LBB48_6
; RV64ZVE32F-NEXT: .LBB48_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB48_5
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB48_7
; RV64ZVE32F-NEXT: .LBB48_3:
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
+; RV64ZVE32F-NEXT: bnez a7, .LBB48_8
+; RV64ZVE32F-NEXT: .LBB48_4:
+; RV64ZVE32F-NEXT: ld a7, 24(a2)
+; RV64ZVE32F-NEXT: j .LBB48_9
+; RV64ZVE32F-NEXT: .LBB48_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB48_2
-; RV64ZVE32F-NEXT: .LBB48_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB48_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB48_5: # %else2
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB48_3
+; RV64ZVE32F-NEXT: .LBB48_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB48_8
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a6, v9
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: bnez a7, .LBB48_9
-; RV64ZVE32F-NEXT: .LBB48_7:
-; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: j .LBB48_10
-; RV64ZVE32F-NEXT: .LBB48_8:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB48_7
-; RV64ZVE32F-NEXT: .LBB48_9: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vmv.x.s a5, v9
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
+; RV64ZVE32F-NEXT: beqz a7, .LBB48_4
+; RV64ZVE32F-NEXT: .LBB48_8: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a7, v9
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: .LBB48_10: # %else8
+; RV64ZVE32F-NEXT: .LBB48_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB48_13
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load10
+; RV64ZVE32F-NEXT: andi t0, a6, 16
+; RV64ZVE32F-NEXT: beqz t0, .LBB48_14
+; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB48_14
-; RV64ZVE32F-NEXT: .LBB48_12:
+; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: bnez t1, .LBB48_15
+; RV64ZVE32F-NEXT: .LBB48_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB48_15
+; RV64ZVE32F-NEXT: andi t2, a6, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB48_16
+; RV64ZVE32F-NEXT: .LBB48_12:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB48_17
; RV64ZVE32F-NEXT: .LBB48_13:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB48_18
+; RV64ZVE32F-NEXT: .LBB48_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB48_12
-; RV64ZVE32F-NEXT: .LBB48_14: # %cond.load13
+; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: beqz t1, .LBB48_11
+; RV64ZVE32F-NEXT: .LBB48_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v9
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB48_15: # %else14
+; RV64ZVE32F-NEXT: andi t2, a6, 64
+; RV64ZVE32F-NEXT: beqz t2, .LBB48_12
+; RV64ZVE32F-NEXT: .LBB48_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
-; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB48_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s t2, v9
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB48_19
-; RV64ZVE32F-NEXT: .LBB48_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB48_20
-; RV64ZVE32F-NEXT: .LBB48_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB48_17
-; RV64ZVE32F-NEXT: .LBB48_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB48_13
+; RV64ZVE32F-NEXT: .LBB48_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB48_20: # %else20
+; RV64ZVE32F-NEXT: .LBB48_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -4398,110 +4563,112 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i8_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a5, v0
-; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB49_3
+; RV64ZVE32F-NEXT: vmv.x.s a6, v0
+; RV64ZVE32F-NEXT: andi a3, a6, 1
+; RV64ZVE32F-NEXT: beqz a3, .LBB49_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB49_4
+; RV64ZVE32F-NEXT: andi a4, a6, 2
+; RV64ZVE32F-NEXT: bnez a4, .LBB49_6
; RV64ZVE32F-NEXT: .LBB49_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB49_5
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: bnez a5, .LBB49_7
; RV64ZVE32F-NEXT: .LBB49_3:
+; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
+; RV64ZVE32F-NEXT: bnez a7, .LBB49_8
+; RV64ZVE32F-NEXT: .LBB49_4:
+; RV64ZVE32F-NEXT: ld a7, 24(a2)
+; RV64ZVE32F-NEXT: j .LBB49_9
+; RV64ZVE32F-NEXT: .LBB49_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a5, 2
+; RV64ZVE32F-NEXT: andi a4, a6, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB49_2
-; RV64ZVE32F-NEXT: .LBB49_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB49_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB49_5: # %else2
+; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: beqz a5, .LBB49_3
+; RV64ZVE32F-NEXT: .LBB49_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB49_8
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a6, v9
-; RV64ZVE32F-NEXT: slli a6, a6, 3
-; RV64ZVE32F-NEXT: add a6, a1, a6
-; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: bnez a7, .LBB49_9
-; RV64ZVE32F-NEXT: .LBB49_7:
-; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: j .LBB49_10
-; RV64ZVE32F-NEXT: .LBB49_8:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB49_7
-; RV64ZVE32F-NEXT: .LBB49_9: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vmv.x.s a5, v9
+; RV64ZVE32F-NEXT: slli a5, a5, 3
+; RV64ZVE32F-NEXT: add a5, a1, a5
+; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: andi a7, a6, 8
+; RV64ZVE32F-NEXT: beqz a7, .LBB49_4
+; RV64ZVE32F-NEXT: .LBB49_8: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a7, v9
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: .LBB49_10: # %else8
+; RV64ZVE32F-NEXT: .LBB49_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB49_13
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load10
+; RV64ZVE32F-NEXT: andi t0, a6, 16
+; RV64ZVE32F-NEXT: beqz t0, .LBB49_14
+; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB49_14
-; RV64ZVE32F-NEXT: .LBB49_12:
+; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: bnez t1, .LBB49_15
+; RV64ZVE32F-NEXT: .LBB49_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB49_15
+; RV64ZVE32F-NEXT: andi t2, a6, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB49_16
+; RV64ZVE32F-NEXT: .LBB49_12:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: bnez a6, .LBB49_17
; RV64ZVE32F-NEXT: .LBB49_13:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB49_18
+; RV64ZVE32F-NEXT: .LBB49_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB49_12
-; RV64ZVE32F-NEXT: .LBB49_14: # %cond.load13
+; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: beqz t1, .LBB49_11
+; RV64ZVE32F-NEXT: .LBB49_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v9
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB49_15: # %else14
+; RV64ZVE32F-NEXT: andi t2, a6, 64
+; RV64ZVE32F-NEXT: beqz t2, .LBB49_12
+; RV64ZVE32F-NEXT: .LBB49_16: # %cond.load16
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
-; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB49_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s t2, v9
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB49_19
-; RV64ZVE32F-NEXT: .LBB49_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB49_20
-; RV64ZVE32F-NEXT: .LBB49_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB49_17
-; RV64ZVE32F-NEXT: .LBB49_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: andi a6, a6, -128
+; RV64ZVE32F-NEXT: beqz a6, .LBB49_13
+; RV64ZVE32F-NEXT: .LBB49_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB49_20: # %else20
+; RV64ZVE32F-NEXT: .LBB49_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a6, 16(a0)
+; RV64ZVE32F-NEXT: sd a5, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -4680,7 +4847,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB50_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB50_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: zext.b a3, a3
@@ -4688,15 +4855,23 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB50_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB50_6
; RV64ZVE32F-NEXT: .LBB50_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB50_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB50_7
; RV64ZVE32F-NEXT: .LBB50_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: bnez a7, .LBB50_8
+; RV64ZVE32F-NEXT: .LBB50_4:
+; RV64ZVE32F-NEXT: ld a7, 24(a2)
+; RV64ZVE32F-NEXT: j .LBB50_9
+; RV64ZVE32F-NEXT: .LBB50_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB50_2
-; RV64ZVE32F-NEXT: .LBB50_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB50_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
@@ -4704,54 +4879,55 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB50_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB50_3
+; RV64ZVE32F-NEXT: .LBB50_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB50_8
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v9
; RV64ZVE32F-NEXT: zext.b a6, a6
; RV64ZVE32F-NEXT: slli a6, a6, 3
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: bnez a7, .LBB50_9
-; RV64ZVE32F-NEXT: .LBB50_7:
-; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: j .LBB50_10
-; RV64ZVE32F-NEXT: .LBB50_8:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB50_7
-; RV64ZVE32F-NEXT: .LBB50_9: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: beqz a7, .LBB50_4
+; RV64ZVE32F-NEXT: .LBB50_8: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a7, v9
; RV64ZVE32F-NEXT: zext.b a7, a7
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: .LBB50_10: # %else8
+; RV64ZVE32F-NEXT: .LBB50_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB50_13
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB50_14
+; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: zext.b t0, t0
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB50_14
-; RV64ZVE32F-NEXT: .LBB50_12:
+; RV64ZVE32F-NEXT: bnez t1, .LBB50_15
+; RV64ZVE32F-NEXT: .LBB50_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB50_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB50_16
+; RV64ZVE32F-NEXT: .LBB50_12:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB50_17
; RV64ZVE32F-NEXT: .LBB50_13:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB50_18
+; RV64ZVE32F-NEXT: .LBB50_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB50_12
-; RV64ZVE32F-NEXT: .LBB50_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB50_11
+; RV64ZVE32F-NEXT: .LBB50_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v9
@@ -4759,34 +4935,27 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB50_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB50_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: beqz t2, .LBB50_12
+; RV64ZVE32F-NEXT: .LBB50_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s t2, v9
; RV64ZVE32F-NEXT: zext.b t2, t2
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB50_19
-; RV64ZVE32F-NEXT: .LBB50_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB50_20
-; RV64ZVE32F-NEXT: .LBB50_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB50_17
-; RV64ZVE32F-NEXT: .LBB50_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB50_13
+; RV64ZVE32F-NEXT: .LBB50_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB50_20: # %else20
+; RV64ZVE32F-NEXT: .LBB50_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -4969,7 +5138,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB51_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB51_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -4977,98 +5146,100 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB51_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB51_6
; RV64ZVE32F-NEXT: .LBB51_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB51_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB51_7
; RV64ZVE32F-NEXT: .LBB51_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: bnez a7, .LBB51_8
+; RV64ZVE32F-NEXT: .LBB51_4:
+; RV64ZVE32F-NEXT: ld a7, 24(a2)
+; RV64ZVE32F-NEXT: j .LBB51_9
+; RV64ZVE32F-NEXT: .LBB51_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB51_2
-; RV64ZVE32F-NEXT: .LBB51_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB51_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB51_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB51_3
+; RV64ZVE32F-NEXT: .LBB51_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB51_8
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v9
; RV64ZVE32F-NEXT: slli a6, a6, 3
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: bnez a7, .LBB51_9
-; RV64ZVE32F-NEXT: .LBB51_7:
-; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: j .LBB51_10
-; RV64ZVE32F-NEXT: .LBB51_8:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB51_7
-; RV64ZVE32F-NEXT: .LBB51_9: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: beqz a7, .LBB51_4
+; RV64ZVE32F-NEXT: .LBB51_8: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a7, v9
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: .LBB51_10: # %else8
+; RV64ZVE32F-NEXT: .LBB51_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB51_13
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB51_14
+; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB51_14
-; RV64ZVE32F-NEXT: .LBB51_12:
+; RV64ZVE32F-NEXT: bnez t1, .LBB51_15
+; RV64ZVE32F-NEXT: .LBB51_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB51_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB51_16
+; RV64ZVE32F-NEXT: .LBB51_12:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB51_17
; RV64ZVE32F-NEXT: .LBB51_13:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB51_18
+; RV64ZVE32F-NEXT: .LBB51_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB51_12
-; RV64ZVE32F-NEXT: .LBB51_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB51_11
+; RV64ZVE32F-NEXT: .LBB51_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v9
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB51_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB51_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: beqz t2, .LBB51_12
+; RV64ZVE32F-NEXT: .LBB51_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s t2, v9
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB51_19
-; RV64ZVE32F-NEXT: .LBB51_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB51_20
-; RV64ZVE32F-NEXT: .LBB51_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB51_17
-; RV64ZVE32F-NEXT: .LBB51_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB51_13
+; RV64ZVE32F-NEXT: .LBB51_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB51_20: # %else20
+; RV64ZVE32F-NEXT: .LBB51_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -5250,7 +5421,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB52_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB52_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -5258,98 +5429,100 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB52_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB52_6
; RV64ZVE32F-NEXT: .LBB52_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB52_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB52_7
; RV64ZVE32F-NEXT: .LBB52_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: bnez a7, .LBB52_8
+; RV64ZVE32F-NEXT: .LBB52_4:
+; RV64ZVE32F-NEXT: ld a7, 24(a2)
+; RV64ZVE32F-NEXT: j .LBB52_9
+; RV64ZVE32F-NEXT: .LBB52_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB52_2
-; RV64ZVE32F-NEXT: .LBB52_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB52_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB52_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB52_3
+; RV64ZVE32F-NEXT: .LBB52_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB52_8
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v9
; RV64ZVE32F-NEXT: slli a6, a6, 3
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: bnez a7, .LBB52_9
-; RV64ZVE32F-NEXT: .LBB52_7:
-; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: j .LBB52_10
-; RV64ZVE32F-NEXT: .LBB52_8:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB52_7
-; RV64ZVE32F-NEXT: .LBB52_9: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: beqz a7, .LBB52_4
+; RV64ZVE32F-NEXT: .LBB52_8: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a7, v9
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: .LBB52_10: # %else8
+; RV64ZVE32F-NEXT: .LBB52_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB52_13
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB52_14
+; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB52_14
-; RV64ZVE32F-NEXT: .LBB52_12:
+; RV64ZVE32F-NEXT: bnez t1, .LBB52_15
+; RV64ZVE32F-NEXT: .LBB52_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB52_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB52_16
+; RV64ZVE32F-NEXT: .LBB52_12:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB52_17
; RV64ZVE32F-NEXT: .LBB52_13:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB52_18
+; RV64ZVE32F-NEXT: .LBB52_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB52_12
-; RV64ZVE32F-NEXT: .LBB52_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB52_11
+; RV64ZVE32F-NEXT: .LBB52_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v9
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB52_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB52_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: beqz t2, .LBB52_12
+; RV64ZVE32F-NEXT: .LBB52_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s t2, v9
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB52_19
-; RV64ZVE32F-NEXT: .LBB52_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB52_20
-; RV64ZVE32F-NEXT: .LBB52_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB52_17
-; RV64ZVE32F-NEXT: .LBB52_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB52_13
+; RV64ZVE32F-NEXT: .LBB52_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB52_20: # %else20
+; RV64ZVE32F-NEXT: .LBB52_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -5533,7 +5706,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB53_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB53_5
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -5542,15 +5715,23 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB53_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB53_6
; RV64ZVE32F-NEXT: .LBB53_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB53_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB53_7
; RV64ZVE32F-NEXT: .LBB53_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: andi a7, a5, 8
+; RV64ZVE32F-NEXT: bnez a7, .LBB53_8
+; RV64ZVE32F-NEXT: .LBB53_4:
+; RV64ZVE32F-NEXT: ld a7, 24(a2)
+; RV64ZVE32F-NEXT: j .LBB53_9
+; RV64ZVE32F-NEXT: .LBB53_5:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB53_2
-; RV64ZVE32F-NEXT: .LBB53_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB53_6: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
@@ -5558,54 +5739,55 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli a4, a4, 45
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB53_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB53_3
+; RV64ZVE32F-NEXT: .LBB53_7: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB53_8
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v9
; RV64ZVE32F-NEXT: slli a6, a6, 48
; RV64ZVE32F-NEXT: srli a6, a6, 45
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: bnez a7, .LBB53_9
-; RV64ZVE32F-NEXT: .LBB53_7:
-; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: j .LBB53_10
-; RV64ZVE32F-NEXT: .LBB53_8:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB53_7
-; RV64ZVE32F-NEXT: .LBB53_9: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: beqz a7, .LBB53_4
+; RV64ZVE32F-NEXT: .LBB53_8: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a7, v9
; RV64ZVE32F-NEXT: slli a7, a7, 48
; RV64ZVE32F-NEXT: srli a7, a7, 45
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: .LBB53_10: # %else8
+; RV64ZVE32F-NEXT: .LBB53_9: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB53_13
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB53_14
+; RV64ZVE32F-NEXT: # %bb.10: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s t0, v8
; RV64ZVE32F-NEXT: slli t0, t0, 48
; RV64ZVE32F-NEXT: srli t0, t0, 45
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB53_14
-; RV64ZVE32F-NEXT: .LBB53_12:
+; RV64ZVE32F-NEXT: bnez t1, .LBB53_15
+; RV64ZVE32F-NEXT: .LBB53_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB53_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB53_16
+; RV64ZVE32F-NEXT: .LBB53_12:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB53_17
; RV64ZVE32F-NEXT: .LBB53_13:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB53_18
+; RV64ZVE32F-NEXT: .LBB53_14:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB53_12
-; RV64ZVE32F-NEXT: .LBB53_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB53_11
+; RV64ZVE32F-NEXT: .LBB53_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v9
@@ -5613,34 +5795,27 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: srli t1, t1, 45
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB53_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB53_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: beqz t2, .LBB53_12
+; RV64ZVE32F-NEXT: .LBB53_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s t2, v9
; RV64ZVE32F-NEXT: slli t2, t2, 48
; RV64ZVE32F-NEXT: srli t2, t2, 45
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB53_19
-; RV64ZVE32F-NEXT: .LBB53_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB53_20
-; RV64ZVE32F-NEXT: .LBB53_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB53_17
-; RV64ZVE32F-NEXT: .LBB53_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB53_13
+; RV64ZVE32F-NEXT: .LBB53_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB53_20: # %else20
+; RV64ZVE32F-NEXT: .LBB53_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -5820,7 +5995,7 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB54_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB54_4
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -5828,100 +6003,101 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB54_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB54_5
; RV64ZVE32F-NEXT: .LBB54_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB54_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB54_6
; RV64ZVE32F-NEXT: .LBB54_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: j .LBB54_7
+; RV64ZVE32F-NEXT: .LBB54_4:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB54_2
-; RV64ZVE32F-NEXT: .LBB54_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB54_5: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v10
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB54_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB54_3
+; RV64ZVE32F-NEXT: .LBB54_6: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB54_7
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v10
; RV64ZVE32F-NEXT: slli a6, a6, 3
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: j .LBB54_8
-; RV64ZVE32F-NEXT: .LBB54_7:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: .LBB54_8: # %else5
+; RV64ZVE32F-NEXT: .LBB54_7: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB54_12
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7
+; RV64ZVE32F-NEXT: beqz a7, .LBB54_13
+; RV64ZVE32F-NEXT: # %bb.8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a7, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a7, v8
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: bnez t0, .LBB54_13
-; RV64ZVE32F-NEXT: .LBB54_10:
+; RV64ZVE32F-NEXT: bnez t0, .LBB54_14
+; RV64ZVE32F-NEXT: .LBB54_9:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB54_14
-; RV64ZVE32F-NEXT: .LBB54_11:
+; RV64ZVE32F-NEXT: bnez t1, .LBB54_15
+; RV64ZVE32F-NEXT: .LBB54_10:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB54_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB54_16
+; RV64ZVE32F-NEXT: .LBB54_11:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB54_17
; RV64ZVE32F-NEXT: .LBB54_12:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB54_18
+; RV64ZVE32F-NEXT: .LBB54_13:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB54_10
-; RV64ZVE32F-NEXT: .LBB54_13: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB54_9
+; RV64ZVE32F-NEXT: .LBB54_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s t0, v8
+; RV64ZVE32F-NEXT: vmv.x.s t0, v10
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB54_11
-; RV64ZVE32F-NEXT: .LBB54_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB54_10
+; RV64ZVE32F-NEXT: .LBB54_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s t1, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB54_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB54_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
+; RV64ZVE32F-NEXT: beqz t2, .LBB54_11
+; RV64ZVE32F-NEXT: .LBB54_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB54_19
-; RV64ZVE32F-NEXT: .LBB54_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB54_20
-; RV64ZVE32F-NEXT: .LBB54_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB54_17
-; RV64ZVE32F-NEXT: .LBB54_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB54_12
+; RV64ZVE32F-NEXT: .LBB54_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB54_20: # %else20
+; RV64ZVE32F-NEXT: .LBB54_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -6100,7 +6276,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB55_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB55_4
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -6108,100 +6284,101 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB55_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB55_5
; RV64ZVE32F-NEXT: .LBB55_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB55_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB55_6
; RV64ZVE32F-NEXT: .LBB55_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: j .LBB55_7
+; RV64ZVE32F-NEXT: .LBB55_4:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB55_2
-; RV64ZVE32F-NEXT: .LBB55_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB55_5: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v10
; RV64ZVE32F-NEXT: slli a4, a4, 3
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB55_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB55_3
+; RV64ZVE32F-NEXT: .LBB55_6: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB55_7
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v10
; RV64ZVE32F-NEXT: slli a6, a6, 3
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: j .LBB55_8
-; RV64ZVE32F-NEXT: .LBB55_7:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: .LBB55_8: # %else5
+; RV64ZVE32F-NEXT: .LBB55_7: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB55_12
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7
+; RV64ZVE32F-NEXT: beqz a7, .LBB55_13
+; RV64ZVE32F-NEXT: # %bb.8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a7, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a7, v8
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: bnez t0, .LBB55_13
-; RV64ZVE32F-NEXT: .LBB55_10:
+; RV64ZVE32F-NEXT: bnez t0, .LBB55_14
+; RV64ZVE32F-NEXT: .LBB55_9:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB55_14
-; RV64ZVE32F-NEXT: .LBB55_11:
+; RV64ZVE32F-NEXT: bnez t1, .LBB55_15
+; RV64ZVE32F-NEXT: .LBB55_10:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB55_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB55_16
+; RV64ZVE32F-NEXT: .LBB55_11:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB55_17
; RV64ZVE32F-NEXT: .LBB55_12:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB55_18
+; RV64ZVE32F-NEXT: .LBB55_13:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB55_10
-; RV64ZVE32F-NEXT: .LBB55_13: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB55_9
+; RV64ZVE32F-NEXT: .LBB55_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s t0, v8
+; RV64ZVE32F-NEXT: vmv.x.s t0, v10
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB55_11
-; RV64ZVE32F-NEXT: .LBB55_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB55_10
+; RV64ZVE32F-NEXT: .LBB55_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s t1, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB55_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB55_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
+; RV64ZVE32F-NEXT: beqz t2, .LBB55_11
+; RV64ZVE32F-NEXT: .LBB55_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB55_19
-; RV64ZVE32F-NEXT: .LBB55_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB55_20
-; RV64ZVE32F-NEXT: .LBB55_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB55_17
-; RV64ZVE32F-NEXT: .LBB55_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB55_12
+; RV64ZVE32F-NEXT: .LBB55_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB55_20: # %else20
+; RV64ZVE32F-NEXT: .LBB55_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -6381,7 +6558,7 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a5, v0
; RV64ZVE32F-NEXT: andi a3, a5, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB56_3
+; RV64ZVE32F-NEXT: beqz a3, .LBB56_4
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
@@ -6390,15 +6567,19 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
; RV64ZVE32F-NEXT: andi a4, a5, 2
-; RV64ZVE32F-NEXT: bnez a4, .LBB56_4
+; RV64ZVE32F-NEXT: bnez a4, .LBB56_5
; RV64ZVE32F-NEXT: .LBB56_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
-; RV64ZVE32F-NEXT: j .LBB56_5
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: bnez a6, .LBB56_6
; RV64ZVE32F-NEXT: .LBB56_3:
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
+; RV64ZVE32F-NEXT: j .LBB56_7
+; RV64ZVE32F-NEXT: .LBB56_4:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB56_2
-; RV64ZVE32F-NEXT: .LBB56_4: # %cond.load1
+; RV64ZVE32F-NEXT: .LBB56_5: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a4, v10
@@ -6406,91 +6587,88 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: srli a4, a4, 29
; RV64ZVE32F-NEXT: add a4, a1, a4
; RV64ZVE32F-NEXT: ld a4, 0(a4)
-; RV64ZVE32F-NEXT: .LBB56_5: # %else2
+; RV64ZVE32F-NEXT: andi a6, a5, 4
+; RV64ZVE32F-NEXT: beqz a6, .LBB56_3
+; RV64ZVE32F-NEXT: .LBB56_6: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a6, a5, 4
-; RV64ZVE32F-NEXT: beqz a6, .LBB56_7
-; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a6, v10
; RV64ZVE32F-NEXT: slli a6, a6, 32
; RV64ZVE32F-NEXT: srli a6, a6, 29
; RV64ZVE32F-NEXT: add a6, a1, a6
; RV64ZVE32F-NEXT: ld a6, 0(a6)
-; RV64ZVE32F-NEXT: j .LBB56_8
-; RV64ZVE32F-NEXT: .LBB56_7:
-; RV64ZVE32F-NEXT: ld a6, 16(a2)
-; RV64ZVE32F-NEXT: .LBB56_8: # %else5
+; RV64ZVE32F-NEXT: .LBB56_7: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a7, a5, 8
-; RV64ZVE32F-NEXT: beqz a7, .LBB56_12
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7
+; RV64ZVE32F-NEXT: beqz a7, .LBB56_13
+; RV64ZVE32F-NEXT: # %bb.8: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a7, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a7, v8
; RV64ZVE32F-NEXT: slli a7, a7, 32
; RV64ZVE32F-NEXT: srli a7, a7, 29
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: bnez t0, .LBB56_13
-; RV64ZVE32F-NEXT: .LBB56_10:
+; RV64ZVE32F-NEXT: bnez t0, .LBB56_14
+; RV64ZVE32F-NEXT: .LBB56_9:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: bnez t1, .LBB56_14
-; RV64ZVE32F-NEXT: .LBB56_11:
+; RV64ZVE32F-NEXT: bnez t1, .LBB56_15
+; RV64ZVE32F-NEXT: .LBB56_10:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
-; RV64ZVE32F-NEXT: j .LBB56_15
+; RV64ZVE32F-NEXT: andi t2, a5, 64
+; RV64ZVE32F-NEXT: bnez t2, .LBB56_16
+; RV64ZVE32F-NEXT: .LBB56_11:
+; RV64ZVE32F-NEXT: ld t2, 48(a2)
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB56_17
; RV64ZVE32F-NEXT: .LBB56_12:
+; RV64ZVE32F-NEXT: ld a1, 56(a2)
+; RV64ZVE32F-NEXT: j .LBB56_18
+; RV64ZVE32F-NEXT: .LBB56_13:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
; RV64ZVE32F-NEXT: andi t0, a5, 16
-; RV64ZVE32F-NEXT: beqz t0, .LBB56_10
-; RV64ZVE32F-NEXT: .LBB56_13: # %cond.load10
+; RV64ZVE32F-NEXT: beqz t0, .LBB56_9
+; RV64ZVE32F-NEXT: .LBB56_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s t0, v8
+; RV64ZVE32F-NEXT: vmv.x.s t0, v10
; RV64ZVE32F-NEXT: slli t0, t0, 32
; RV64ZVE32F-NEXT: srli t0, t0, 29
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
; RV64ZVE32F-NEXT: andi t1, a5, 32
-; RV64ZVE32F-NEXT: beqz t1, .LBB56_11
-; RV64ZVE32F-NEXT: .LBB56_14: # %cond.load13
+; RV64ZVE32F-NEXT: beqz t1, .LBB56_10
+; RV64ZVE32F-NEXT: .LBB56_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s t1, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: slli t1, t1, 32
; RV64ZVE32F-NEXT: srli t1, t1, 29
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
-; RV64ZVE32F-NEXT: .LBB56_15: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi t2, a5, 64
-; RV64ZVE32F-NEXT: beqz t2, .LBB56_18
-; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
+; RV64ZVE32F-NEXT: beqz t2, .LBB56_11
+; RV64ZVE32F-NEXT: .LBB56_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: slli t2, t2, 32
; RV64ZVE32F-NEXT: srli t2, t2, 29
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: bnez a5, .LBB56_19
-; RV64ZVE32F-NEXT: .LBB56_17:
-; RV64ZVE32F-NEXT: ld a1, 56(a2)
-; RV64ZVE32F-NEXT: j .LBB56_20
-; RV64ZVE32F-NEXT: .LBB56_18:
-; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a5, a5, -128
-; RV64ZVE32F-NEXT: beqz a5, .LBB56_17
-; RV64ZVE32F-NEXT: .LBB56_19: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a5, .LBB56_12
+; RV64ZVE32F-NEXT: .LBB56_17: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: ld a1, 0(a1)
-; RV64ZVE32F-NEXT: .LBB56_20: # %else20
+; RV64ZVE32F-NEXT: .LBB56_18: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
; RV64ZVE32F-NEXT: sd a6, 16(a0)
@@ -7130,18 +7308,66 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_12
+; RV64ZVE32F-NEXT: .LBB64_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_13
+; RV64ZVE32F-NEXT: .LBB64_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB64_5
+; RV64ZVE32F-NEXT: .LBB64_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB64_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_15
+; RV64ZVE32F-NEXT: .LBB64_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_16
+; RV64ZVE32F-NEXT: .LBB64_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB64_10
+; RV64ZVE32F-NEXT: .LBB64_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB64_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB64_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB64_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB64_2
+; RV64ZVE32F-NEXT: .LBB64_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7152,40 +7378,23 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB64_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB64_3
+; RV64ZVE32F-NEXT: .LBB64_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB64_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB64_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB64_4
+; RV64ZVE32F-NEXT: j .LBB64_5
+; RV64ZVE32F-NEXT: .LBB64_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -7194,10 +7403,9 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB64_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB64_7
+; RV64ZVE32F-NEXT: .LBB64_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7208,13 +7416,12 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB64_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB64_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB64_8
+; RV64ZVE32F-NEXT: .LBB64_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
@@ -7222,24 +7429,9 @@ define <8 x bfloat> @mgather_baseidx_v8i8_v8bf16(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB64_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB64_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB64_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB64_9
+; RV64ZVE32F-NEXT: j .LBB64_10
%ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i8> %idxs
%v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)
ret <8 x bfloat> %v
@@ -7271,18 +7463,66 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_12
+; RV64ZVE32F-NEXT: .LBB65_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_13
+; RV64ZVE32F-NEXT: .LBB65_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB65_5
+; RV64ZVE32F-NEXT: .LBB65_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB65_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_15
+; RV64ZVE32F-NEXT: .LBB65_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_16
+; RV64ZVE32F-NEXT: .LBB65_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB65_10
+; RV64ZVE32F-NEXT: .LBB65_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB65_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB65_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB65_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB65_2
+; RV64ZVE32F-NEXT: .LBB65_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7293,40 +7533,23 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB65_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB65_3
+; RV64ZVE32F-NEXT: .LBB65_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB65_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB65_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB65_4
+; RV64ZVE32F-NEXT: j .LBB65_5
+; RV64ZVE32F-NEXT: .LBB65_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -7335,10 +7558,9 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB65_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB65_7
+; RV64ZVE32F-NEXT: .LBB65_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7349,13 +7571,12 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB65_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB65_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB65_8
+; RV64ZVE32F-NEXT: .LBB65_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
@@ -7363,24 +7584,9 @@ define <8 x bfloat> @mgather_baseidx_sext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB65_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB65_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB65_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB65_9
+; RV64ZVE32F-NEXT: j .LBB65_10
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs
%v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)
@@ -7411,8 +7617,59 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_12
+; RV64ZVE32F-NEXT: .LBB66_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_13
+; RV64ZVE32F-NEXT: .LBB66_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB66_5
+; RV64ZVE32F-NEXT: .LBB66_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB66_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_15
+; RV64ZVE32F-NEXT: .LBB66_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_16
+; RV64ZVE32F-NEXT: .LBB66_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB66_10
+; RV64ZVE32F-NEXT: .LBB66_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: zext.b a1, a1
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB66_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB66_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -7420,10 +7677,9 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB66_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB66_2
+; RV64ZVE32F-NEXT: .LBB66_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7435,42 +7691,24 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB66_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB66_3
+; RV64ZVE32F-NEXT: .LBB66_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB66_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB66_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB66_4
+; RV64ZVE32F-NEXT: j .LBB66_5
+; RV64ZVE32F-NEXT: .LBB66_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -7480,10 +7718,9 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB66_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB66_7
+; RV64ZVE32F-NEXT: .LBB66_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7495,13 +7732,12 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB66_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB66_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB66_8
+; RV64ZVE32F-NEXT: .LBB66_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -7510,25 +7746,9 @@ define <8 x bfloat> @mgather_baseidx_zext_v8i8_v8bf16(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB66_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB66_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: zext.b a1, a1
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB66_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB66_9
+; RV64ZVE32F-NEXT: j .LBB66_10
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %eidxs
%v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)
@@ -7559,18 +7779,64 @@ define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_12
+; RV64ZVE32F-NEXT: .LBB67_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_13
+; RV64ZVE32F-NEXT: .LBB67_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB67_5
+; RV64ZVE32F-NEXT: .LBB67_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB67_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_15
+; RV64ZVE32F-NEXT: .LBB67_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_16
+; RV64ZVE32F-NEXT: .LBB67_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB67_10
+; RV64ZVE32F-NEXT: .LBB67_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 1
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB67_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB67_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB67_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB67_2
+; RV64ZVE32F-NEXT: .LBB67_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7580,38 +7846,22 @@ define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB67_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB67_3
+; RV64ZVE32F-NEXT: .LBB67_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB67_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB67_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB67_4
+; RV64ZVE32F-NEXT: j .LBB67_5
+; RV64ZVE32F-NEXT: .LBB67_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -7619,10 +7869,9 @@ define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB67_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB67_7
+; RV64ZVE32F-NEXT: .LBB67_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -7632,36 +7881,21 @@ define <8 x bfloat> @mgather_baseidx_v8bf16(ptr %base, <8 x i16> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB67_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB67_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB67_8
+; RV64ZVE32F-NEXT: .LBB67_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB67_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB67_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 1
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB67_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB67_9
+; RV64ZVE32F-NEXT: j .LBB67_10
%ptrs = getelementptr inbounds bfloat, ptr %base, <8 x i16> %idxs
%v = call <8 x bfloat> @llvm.masked.gather.v8bf16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x bfloat> %passthru)
ret <8 x bfloat> %v
@@ -8195,18 +8429,66 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_2: # %else
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_11
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_13
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_3: # %else5
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_4: # %cond.load7
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_5: # %else8
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_14
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_7: # %else14
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_8: # %else17
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB74_10
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_9: # %cond.load19
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_10: # %else20
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_11: # %cond.load
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_12: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8217,40 +8499,23 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_13: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_6: # %else5
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_8: # %else8
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB74_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB74_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_14: # %cond.load10
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
@@ -8259,10 +8524,9 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_15: # %cond.load13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8273,13 +8537,12 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_12: # %else14
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_14
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB74_8
+; RV64ZVE32F-ZVFH-NEXT: .LBB74_16: # %cond.load16
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
@@ -8287,42 +8550,75 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB74_16
-; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFH-NEXT: .LBB74_16: # %else20
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB74_9
+; RV64ZVE32F-ZVFH-NEXT: j .LBB74_10
;
; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_v8i8_v8f16:
; RV64ZVE32F-ZVFHMIN: # %bb.0:
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_11
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_13
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_3: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_4: # %cond.load7
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_5: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_14
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_7: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_8: # %else17
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB74_10
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_9: # %cond.load19
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_10: # %else20
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_11: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_12: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8333,40 +8629,23 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_4: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_13: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_6: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_8: # %else8
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB74_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB74_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_14: # %cond.load10
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -8375,10 +8654,9 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_15: # %cond.load13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8389,13 +8667,12 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_12: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_14
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB74_8
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_16: # %cond.load16
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
@@ -8403,24 +8680,9 @@ define <8 x half> @mgather_baseidx_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8 x i1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB74_16
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB74_16: # %else20
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB74_9
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB74_10
%ptrs = getelementptr inbounds half, ptr %base, <8 x i8> %idxs
%v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
ret <8 x half> %v
@@ -8452,18 +8714,66 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_11
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_13
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_3: # %else5
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_4: # %cond.load7
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_5: # %else8
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_14
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_7: # %else14
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_8: # %else17
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB75_10
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_9: # %cond.load19
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_10: # %else20
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_11: # %cond.load
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_12: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8474,40 +8784,23 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_13: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_6: # %else5
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_8: # %else8
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB75_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB75_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_14: # %cond.load10
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
@@ -8516,10 +8809,9 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_15: # %cond.load13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8530,13 +8822,12 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_12: # %else14
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_14
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB75_8
+; RV64ZVE32F-ZVFH-NEXT: .LBB75_16: # %cond.load16
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
@@ -8544,42 +8835,75 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB75_16
-; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFH-NEXT: .LBB75_16: # %else20
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB75_9
+; RV64ZVE32F-ZVFH-NEXT: j .LBB75_10
;
; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_sext_v8i8_v8f16:
; RV64ZVE32F-ZVFHMIN: # %bb.0:
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_11
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_13
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_3: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_4: # %cond.load7
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_5: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_14
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_7: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_8: # %else17
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB75_10
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_9: # %cond.load19
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_10: # %else20
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_11: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_12: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8590,40 +8914,23 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_4: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_13: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_6: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_8: # %else8
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB75_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB75_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_14: # %cond.load10
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -8632,10 +8939,9 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_15: # %cond.load13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8646,13 +8952,12 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_12: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_14
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB75_8
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_16: # %cond.load16
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
@@ -8660,24 +8965,9 @@ define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB75_16
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB75_16: # %else20
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB75_9
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB75_10
%eidxs = sext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs
%v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
@@ -8708,8 +8998,59 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_11
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_13
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_3: # %else5
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_4: # %cond.load7
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_5: # %else8
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_14
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_7: # %else14
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_8: # %else17
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB76_10
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_9: # %cond.load19
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFH-NEXT: zext.b a1, a1
+; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
+; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_10: # %else20
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_11: # %cond.load
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
@@ -8717,10 +9058,9 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_12: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8732,42 +9072,24 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_13: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_6: # %else5
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_8: # %else8
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB76_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB76_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_14: # %cond.load10
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
@@ -8777,10 +9099,9 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_15: # %cond.load13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8792,13 +9113,12 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_12: # %else14
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_14
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB76_8
+; RV64ZVE32F-ZVFH-NEXT: .LBB76_16: # %cond.load16
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
@@ -8807,33 +9127,68 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB76_16
-; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFH-NEXT: zext.b a1, a1
-; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFH-NEXT: .LBB76_16: # %else20
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB76_9
+; RV64ZVE32F-ZVFH-NEXT: j .LBB76_10
;
; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_zext_v8i8_v8f16:
; RV64ZVE32F-ZVFHMIN: # %bb.0:
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_11
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_13
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_3: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_4: # %cond.load7
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_5: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_14
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_7: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_8: # %else17
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB76_10
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_9: # %cond.load19
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a1, a1
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_10: # %else20
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_11: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -8841,10 +9196,9 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_12: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8856,42 +9210,24 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_4: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_13: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_6: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_8: # %else8
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB76_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB76_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_14: # %cond.load10
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -8901,10 +9237,9 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_15: # %cond.load13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8916,13 +9251,12 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_12: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_14
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB76_8
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_16: # %cond.load16
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -8931,25 +9265,9 @@ define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB76_16
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a1, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB76_16: # %else20
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB76_9
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB76_10
%eidxs = zext <8 x i8> %idxs to <8 x i16>
%ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %eidxs
%v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
@@ -8980,18 +9298,64 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_11
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_13
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_3: # %else5
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_4: # %cond.load7
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_5: # %else8
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_14
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_7: # %else14
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_8: # %else17
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB77_10
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_9: # %cond.load19
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_10: # %else20
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_11: # %cond.load
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_12: # %cond.load1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -9001,38 +9365,22 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_13: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v11, fa5
+; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_6: # %else5
+; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_8: # %else8
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB77_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB77_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_14: # %cond.load10
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
@@ -9040,10 +9388,9 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_10: # %else11
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_15: # %cond.load13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -9053,54 +9400,85 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_12: # %else14
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_14
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB77_8
+; RV64ZVE32F-ZVFH-NEXT: .LBB77_16: # %cond.load16
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a2)
; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v10, fa5
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_14: # %else17
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB77_16
-; RV64ZVE32F-ZVFH-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFH-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFH-NEXT: flh fa5, 0(a0)
-; RV64ZVE32F-ZVFH-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFH-NEXT: .LBB77_16: # %else20
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB77_9
+; RV64ZVE32F-ZVFH-NEXT: j .LBB77_10
;
; RV64ZVE32F-ZVFHMIN-LABEL: mgather_baseidx_v8f16:
; RV64ZVE32F-ZVFHMIN: # %bb.0:
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_11
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_13
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_3: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_4: # %cond.load7
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_5: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_14
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_7: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_8: # %else17
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB77_10
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_9: # %cond.load19
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
+; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_10: # %else20
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_11: # %cond.load
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_12: # %cond.load1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -9110,38 +9488,22 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_4: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_13: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_6: # %else5
+; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_8: # %else8
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB77_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB77_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_14: # %cond.load10
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
@@ -9149,10 +9511,9 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_10: # %else11
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_15: # %cond.load13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -9162,36 +9523,21 @@ define <8 x half> @mgather_baseidx_v8f16(ptr %base, <8 x i16> %idxs, <8 x i1> %m
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_12: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_14
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB77_8
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_16: # %cond.load16
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: lh a2, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_14: # %else17
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB77_16
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a1, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a0, a0, a1
-; RV64ZVE32F-ZVFHMIN-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB77_16: # %else20
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB77_9
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB77_10
%ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %idxs
%v = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
ret <8 x half> %v
@@ -9540,18 +9886,66 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_12
+; RV64ZVE32F-NEXT: .LBB84_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_13
+; RV64ZVE32F-NEXT: .LBB84_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_5
+; RV64ZVE32F-NEXT: .LBB84_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB84_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_15
+; RV64ZVE32F-NEXT: .LBB84_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_16
+; RV64ZVE32F-NEXT: .LBB84_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB84_10
+; RV64ZVE32F-NEXT: .LBB84_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: flw fa5, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB84_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB84_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB84_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_2
+; RV64ZVE32F-NEXT: .LBB84_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9562,40 +9956,23 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB84_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_3
+; RV64ZVE32F-NEXT: .LBB84_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB84_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB84_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_4
+; RV64ZVE32F-NEXT: j .LBB84_5
+; RV64ZVE32F-NEXT: .LBB84_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -9604,10 +9981,9 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB84_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_7
+; RV64ZVE32F-NEXT: .LBB84_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9618,13 +9994,12 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB84_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_8
+; RV64ZVE32F-NEXT: .LBB84_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
@@ -9632,24 +10007,9 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB84_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB84_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB84_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB84_9
+; RV64ZVE32F-NEXT: j .LBB84_10
%ptrs = getelementptr inbounds float, ptr %base, <8 x i8> %idxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
ret <8 x float> %v
@@ -9680,18 +10040,66 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_12
+; RV64ZVE32F-NEXT: .LBB85_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_13
+; RV64ZVE32F-NEXT: .LBB85_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB85_5
+; RV64ZVE32F-NEXT: .LBB85_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB85_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_15
+; RV64ZVE32F-NEXT: .LBB85_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_16
+; RV64ZVE32F-NEXT: .LBB85_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB85_10
+; RV64ZVE32F-NEXT: .LBB85_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: flw fa5, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB85_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB85_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB85_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB85_2
+; RV64ZVE32F-NEXT: .LBB85_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9702,40 +10110,23 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB85_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB85_3
+; RV64ZVE32F-NEXT: .LBB85_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB85_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB85_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB85_4
+; RV64ZVE32F-NEXT: j .LBB85_5
+; RV64ZVE32F-NEXT: .LBB85_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -9744,10 +10135,9 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB85_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB85_7
+; RV64ZVE32F-NEXT: .LBB85_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9758,13 +10148,12 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB85_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB85_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB85_8
+; RV64ZVE32F-NEXT: .LBB85_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
@@ -9772,24 +10161,9 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB85_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB85_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB85_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB85_9
+; RV64ZVE32F-NEXT: j .LBB85_10
%eidxs = sext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
@@ -9822,8 +10196,59 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_12
+; RV64ZVE32F-NEXT: .LBB86_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_13
+; RV64ZVE32F-NEXT: .LBB86_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB86_5
+; RV64ZVE32F-NEXT: .LBB86_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB86_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_15
+; RV64ZVE32F-NEXT: .LBB86_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_16
+; RV64ZVE32F-NEXT: .LBB86_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB86_10
+; RV64ZVE32F-NEXT: .LBB86_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: zext.b a1, a1
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: flw fa5, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB86_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB86_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -9831,10 +10256,9 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB86_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB86_2
+; RV64ZVE32F-NEXT: .LBB86_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9846,42 +10270,24 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB86_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB86_3
+; RV64ZVE32F-NEXT: .LBB86_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB86_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB86_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB86_4
+; RV64ZVE32F-NEXT: j .LBB86_5
+; RV64ZVE32F-NEXT: .LBB86_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -9891,10 +10297,9 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB86_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB86_7
+; RV64ZVE32F-NEXT: .LBB86_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9906,13 +10311,12 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB86_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB86_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB86_8
+; RV64ZVE32F-NEXT: .LBB86_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -9921,25 +10325,9 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB86_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB86_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: zext.b a1, a1
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB86_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB86_9
+; RV64ZVE32F-NEXT: j .LBB86_10
%eidxs = zext <8 x i8> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
@@ -9972,8 +10360,57 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_12
+; RV64ZVE32F-NEXT: .LBB87_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_13
+; RV64ZVE32F-NEXT: .LBB87_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB87_5
+; RV64ZVE32F-NEXT: .LBB87_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB87_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_15
+; RV64ZVE32F-NEXT: .LBB87_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_16
+; RV64ZVE32F-NEXT: .LBB87_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB87_10
+; RV64ZVE32F-NEXT: .LBB87_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: flw fa5, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB87_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB87_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -9981,10 +10418,9 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB87_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB87_2
+; RV64ZVE32F-NEXT: .LBB87_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -9995,40 +10431,23 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB87_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB87_3
+; RV64ZVE32F-NEXT: .LBB87_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB87_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB87_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB87_4
+; RV64ZVE32F-NEXT: j .LBB87_5
+; RV64ZVE32F-NEXT: .LBB87_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10037,10 +10456,9 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB87_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB87_7
+; RV64ZVE32F-NEXT: .LBB87_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10051,13 +10469,12 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB87_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB87_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB87_8
+; RV64ZVE32F-NEXT: .LBB87_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
@@ -10065,24 +10482,9 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB87_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB87_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB87_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB87_9
+; RV64ZVE32F-NEXT: j .LBB87_10
%ptrs = getelementptr inbounds float, ptr %base, <8 x i16> %idxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
ret <8 x float> %v
@@ -10114,8 +10516,57 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_12
+; RV64ZVE32F-NEXT: .LBB88_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_13
+; RV64ZVE32F-NEXT: .LBB88_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB88_5
+; RV64ZVE32F-NEXT: .LBB88_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB88_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_15
+; RV64ZVE32F-NEXT: .LBB88_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_16
+; RV64ZVE32F-NEXT: .LBB88_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB88_10
+; RV64ZVE32F-NEXT: .LBB88_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 2
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: flw fa5, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB88_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB88_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -10123,10 +10574,9 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB88_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB88_2
+; RV64ZVE32F-NEXT: .LBB88_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10137,40 +10587,23 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB88_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB88_3
+; RV64ZVE32F-NEXT: .LBB88_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB88_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB88_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB88_4
+; RV64ZVE32F-NEXT: j .LBB88_5
+; RV64ZVE32F-NEXT: .LBB88_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10179,10 +10612,9 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB88_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB88_7
+; RV64ZVE32F-NEXT: .LBB88_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10193,13 +10625,12 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB88_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB88_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB88_8
+; RV64ZVE32F-NEXT: .LBB88_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
@@ -10207,24 +10638,9 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB88_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB88_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 2
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB88_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB88_9
+; RV64ZVE32F-NEXT: j .LBB88_10
%eidxs = sext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
@@ -10257,8 +10673,59 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_12
+; RV64ZVE32F-NEXT: .LBB89_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_13
+; RV64ZVE32F-NEXT: .LBB89_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB89_5
+; RV64ZVE32F-NEXT: .LBB89_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 46
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: .LBB89_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_15
+; RV64ZVE32F-NEXT: .LBB89_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_16
+; RV64ZVE32F-NEXT: .LBB89_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB89_10
+; RV64ZVE32F-NEXT: .LBB89_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 48
+; RV64ZVE32F-NEXT: srli a1, a1, 46
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: flw fa5, 0(a0)
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
+; RV64ZVE32F-NEXT: .LBB89_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB89_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
@@ -10267,10 +10734,9 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB89_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB89_2
+; RV64ZVE32F-NEXT: .LBB89_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10282,42 +10748,24 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 1
-; RV64ZVE32F-NEXT: .LBB89_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB89_3
+; RV64ZVE32F-NEXT: .LBB89_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
-; RV64ZVE32F-NEXT: .LBB89_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 46
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
-; RV64ZVE32F-NEXT: .LBB89_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB89_4
+; RV64ZVE32F-NEXT: j .LBB89_5
+; RV64ZVE32F-NEXT: .LBB89_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
@@ -10327,10 +10775,9 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
-; RV64ZVE32F-NEXT: .LBB89_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB89_7
+; RV64ZVE32F-NEXT: .LBB89_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10342,13 +10789,12 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB89_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB89_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB89_8
+; RV64ZVE32F-NEXT: .LBB89_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10357,25 +10803,9 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB89_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB89_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 48
-; RV64ZVE32F-NEXT: srli a1, a1, 46
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: flw fa5, 0(a0)
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB89_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB89_9
+; RV64ZVE32F-NEXT: j .LBB89_10
%eidxs = zext <8 x i16> %idxs to <8 x i32>
%ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %eidxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
@@ -10405,79 +10835,43 @@ define <8 x float> @mgather_baseidx_v8f32(ptr %base, <8 x i32> %idxs, <8 x i1> %
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB90_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
-; RV64ZVE32F-NEXT: .LBB90_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_12
+; RV64ZVE32F-NEXT: .LBB90_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB90_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1
-; RV64ZVE32F-NEXT: .LBB90_4: # %else2
+; RV64ZVE32F-NEXT: .LBB90_3: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB90_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v13, fa5
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 2
-; RV64ZVE32F-NEXT: .LBB90_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
+; RV64ZVE32F-NEXT: .LBB90_4: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB90_15
-; RV64ZVE32F-NEXT: # %bb.7: # %else8
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_13
+; RV64ZVE32F-NEXT: # %bb.5: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB90_16
-; RV64ZVE32F-NEXT: .LBB90_8: # %else11
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_14
+; RV64ZVE32F-NEXT: .LBB90_6: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB90_10
-; RV64ZVE32F-NEXT: .LBB90_9: # %cond.load13
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_15
+; RV64ZVE32F-NEXT: .LBB90_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_16
+; RV64ZVE32F-NEXT: .LBB90_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB90_10
+; RV64ZVE32F-NEXT: .LBB90_9: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
-; RV64ZVE32F-NEXT: .LBB90_10: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB90_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
-; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 6
-; RV64ZVE32F-NEXT: .LBB90_12: # %else17
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB90_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v12, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 2
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -10485,31 +10879,76 @@ define <8 x float> @mgather_baseidx_v8f32(ptr %base, <8 x i32> %idxs, <8 x i1> %
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 7
-; RV64ZVE32F-NEXT: .LBB90_14: # %else20
+; RV64ZVE32F-NEXT: .LBB90_10: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv2r.v v8, v10
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB90_15: # %cond.load7
+; RV64ZVE32F-NEXT: .LBB90_11: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, tu, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB90_2
+; RV64ZVE32F-NEXT: .LBB90_12: # %cond.load1
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB90_3
+; RV64ZVE32F-NEXT: j .LBB90_4
+; RV64ZVE32F-NEXT: .LBB90_13: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 3
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB90_8
-; RV64ZVE32F-NEXT: .LBB90_16: # %cond.load10
+; RV64ZVE32F-NEXT: beqz a2, .LBB90_6
+; RV64ZVE32F-NEXT: .LBB90_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
-; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB90_9
+; RV64ZVE32F-NEXT: beqz a2, .LBB90_7
+; RV64ZVE32F-NEXT: .LBB90_15: # %cond.load13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v12, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: beqz a2, .LBB90_8
+; RV64ZVE32F-NEXT: .LBB90_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v12, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: flw fa5, 0(a2)
+; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
+; RV64ZVE32F-NEXT: vsetivli zero, 7, e32, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 6
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB90_9
; RV64ZVE32F-NEXT: j .LBB90_10
%ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %idxs
%v = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %m, <8 x float> %passthru)
@@ -11116,90 +11555,106 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_12
+; RV64ZVE32F-NEXT: .LBB97_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_13
+; RV64ZVE32F-NEXT: .LBB97_3: # %else5
+; RV64ZVE32F-NEXT: andi a3, a2, 8
+; RV64ZVE32F-NEXT: beqz a3, .LBB97_5
+; RV64ZVE32F-NEXT: .LBB97_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: .LBB97_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a3, a2, 32
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_15
+; RV64ZVE32F-NEXT: .LBB97_7: # %else14
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_16
+; RV64ZVE32F-NEXT: .LBB97_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: beqz a2, .LBB97_10
+; RV64ZVE32F-NEXT: .LBB97_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a1, a1, a2
+; RV64ZVE32F-NEXT: fld fa7, 0(a1)
+; RV64ZVE32F-NEXT: .LBB97_10: # %else20
+; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
+; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
+; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
+; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
+; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
+; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
+; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
+; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB97_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_2: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a3, .LBB97_2
+; RV64ZVE32F-NEXT: .LBB97_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_4: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: beqz a3, .LBB97_3
+; RV64ZVE32F-NEXT: .LBB97_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_6: # %else5
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a3, .LBB97_4
+; RV64ZVE32F-NEXT: j .LBB97_5
+; RV64ZVE32F-NEXT: .LBB97_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_10: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a3, .LBB97_7
+; RV64ZVE32F-NEXT: .LBB97_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB97_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: beqz a3, .LBB97_8
+; RV64ZVE32F-NEXT: .LBB97_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB97_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB97_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a1, a1, a2
-; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB97_16: # %else20
-; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
-; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
-; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
-; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
-; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
-; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
-; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
-; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_9
+; RV64ZVE32F-NEXT: j .LBB97_10
%ptrs = getelementptr inbounds double, ptr %base, <8 x i8> %idxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
ret <8 x double> %v
@@ -11325,90 +11780,106 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_12
+; RV64ZVE32F-NEXT: .LBB98_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_13
+; RV64ZVE32F-NEXT: .LBB98_3: # %else5
+; RV64ZVE32F-NEXT: andi a3, a2, 8
+; RV64ZVE32F-NEXT: beqz a3, .LBB98_5
+; RV64ZVE32F-NEXT: .LBB98_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: .LBB98_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a3, a2, 32
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_15
+; RV64ZVE32F-NEXT: .LBB98_7: # %else14
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_16
+; RV64ZVE32F-NEXT: .LBB98_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: beqz a2, .LBB98_10
+; RV64ZVE32F-NEXT: .LBB98_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a1, a1, a2
+; RV64ZVE32F-NEXT: fld fa7, 0(a1)
+; RV64ZVE32F-NEXT: .LBB98_10: # %else20
+; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
+; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
+; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
+; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
+; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
+; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
+; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
+; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB98_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_2: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a3, .LBB98_2
+; RV64ZVE32F-NEXT: .LBB98_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_4: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: beqz a3, .LBB98_3
+; RV64ZVE32F-NEXT: .LBB98_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_6: # %else5
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a3, .LBB98_4
+; RV64ZVE32F-NEXT: j .LBB98_5
+; RV64ZVE32F-NEXT: .LBB98_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_10: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a3, .LBB98_7
+; RV64ZVE32F-NEXT: .LBB98_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB98_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: beqz a3, .LBB98_8
+; RV64ZVE32F-NEXT: .LBB98_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB98_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB98_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a1, a1, a2
-; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB98_16: # %else20
-; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
-; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
-; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
-; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
-; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
-; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
-; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
-; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_9
+; RV64ZVE32F-NEXT: j .LBB98_10
%eidxs = sext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
@@ -11536,17 +12007,65 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_12
+; RV64ZVE32F-NEXT: .LBB99_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_13
+; RV64ZVE32F-NEXT: .LBB99_3: # %else5
+; RV64ZVE32F-NEXT: andi a3, a2, 8
+; RV64ZVE32F-NEXT: beqz a3, .LBB99_5
+; RV64ZVE32F-NEXT: .LBB99_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: zext.b a3, a3
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: .LBB99_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a3, a2, 32
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_15
+; RV64ZVE32F-NEXT: .LBB99_7: # %else14
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_16
+; RV64ZVE32F-NEXT: .LBB99_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: beqz a2, .LBB99_10
+; RV64ZVE32F-NEXT: .LBB99_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a1, a1, a2
+; RV64ZVE32F-NEXT: fld fa7, 0(a1)
+; RV64ZVE32F-NEXT: .LBB99_10: # %else20
+; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
+; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
+; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
+; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
+; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
+; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
+; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
+; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB99_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: zext.b a3, a3
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_2: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a3, .LBB99_2
+; RV64ZVE32F-NEXT: .LBB99_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
@@ -11554,42 +12073,28 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_4: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: beqz a3, .LBB99_3
+; RV64ZVE32F-NEXT: .LBB99_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: zext.b a3, a3
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_6: # %else5
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: zext.b a3, a3
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a3, .LBB99_4
+; RV64ZVE32F-NEXT: j .LBB99_5
+; RV64ZVE32F-NEXT: .LBB99_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: zext.b a3, a3
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_10: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a3, .LBB99_7
+; RV64ZVE32F-NEXT: .LBB99_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
@@ -11597,37 +12102,19 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB99_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: beqz a3, .LBB99_8
+; RV64ZVE32F-NEXT: .LBB99_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: zext.b a3, a3
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB99_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB99_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a1, a1, a2
-; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB99_16: # %else20
-; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
-; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
-; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
-; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
-; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
-; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
-; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
-; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_9
+; RV64ZVE32F-NEXT: j .LBB99_10
%eidxs = zext <8 x i8> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
@@ -11756,91 +12243,107 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_12
+; RV64ZVE32F-NEXT: .LBB100_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_13
+; RV64ZVE32F-NEXT: .LBB100_3: # %else5
+; RV64ZVE32F-NEXT: andi a3, a2, 8
+; RV64ZVE32F-NEXT: beqz a3, .LBB100_5
+; RV64ZVE32F-NEXT: .LBB100_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: .LBB100_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a3, a2, 32
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_15
+; RV64ZVE32F-NEXT: .LBB100_7: # %else14
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_16
+; RV64ZVE32F-NEXT: .LBB100_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: beqz a2, .LBB100_10
+; RV64ZVE32F-NEXT: .LBB100_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a1, a1, a2
+; RV64ZVE32F-NEXT: fld fa7, 0(a1)
+; RV64ZVE32F-NEXT: .LBB100_10: # %else20
+; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
+; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
+; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
+; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
+; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
+; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
+; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
+; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB100_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_2: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a3, .LBB100_2
+; RV64ZVE32F-NEXT: .LBB100_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_4: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: beqz a3, .LBB100_3
+; RV64ZVE32F-NEXT: .LBB100_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_6: # %else5
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a3, .LBB100_4
+; RV64ZVE32F-NEXT: j .LBB100_5
+; RV64ZVE32F-NEXT: .LBB100_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_10: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a3, .LBB100_7
+; RV64ZVE32F-NEXT: .LBB100_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB100_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: beqz a3, .LBB100_8
+; RV64ZVE32F-NEXT: .LBB100_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB100_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB100_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a1, a1, a2
-; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB100_16: # %else20
-; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
-; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
-; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
-; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
-; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
-; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
-; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
-; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a2, .LBB100_9
+; RV64ZVE32F-NEXT: j .LBB100_10
%ptrs = getelementptr inbounds double, ptr %base, <8 x i16> %idxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
ret <8 x double> %v
@@ -11968,91 +12471,107 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_12
+; RV64ZVE32F-NEXT: .LBB101_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_13
+; RV64ZVE32F-NEXT: .LBB101_3: # %else5
+; RV64ZVE32F-NEXT: andi a3, a2, 8
+; RV64ZVE32F-NEXT: beqz a3, .LBB101_5
+; RV64ZVE32F-NEXT: .LBB101_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: .LBB101_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a3, a2, 32
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_15
+; RV64ZVE32F-NEXT: .LBB101_7: # %else14
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_16
+; RV64ZVE32F-NEXT: .LBB101_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_10
+; RV64ZVE32F-NEXT: .LBB101_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a1, a1, a2
+; RV64ZVE32F-NEXT: fld fa7, 0(a1)
+; RV64ZVE32F-NEXT: .LBB101_10: # %else20
+; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
+; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
+; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
+; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
+; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
+; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
+; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
+; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB101_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_2: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a3, .LBB101_2
+; RV64ZVE32F-NEXT: .LBB101_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_4: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: beqz a3, .LBB101_3
+; RV64ZVE32F-NEXT: .LBB101_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_6: # %else5
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a3, .LBB101_4
+; RV64ZVE32F-NEXT: j .LBB101_5
+; RV64ZVE32F-NEXT: .LBB101_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_10: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a3, .LBB101_7
+; RV64ZVE32F-NEXT: .LBB101_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB101_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: beqz a3, .LBB101_8
+; RV64ZVE32F-NEXT: .LBB101_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB101_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a1, a1, a2
-; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB101_16: # %else20
-; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
-; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
-; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
-; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
-; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
-; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
-; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
-; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_9
+; RV64ZVE32F-NEXT: j .LBB101_10
%eidxs = sext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
@@ -12182,18 +12701,66 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_12
+; RV64ZVE32F-NEXT: .LBB102_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_13
+; RV64ZVE32F-NEXT: .LBB102_3: # %else5
+; RV64ZVE32F-NEXT: andi a3, a2, 8
+; RV64ZVE32F-NEXT: beqz a3, .LBB102_5
+; RV64ZVE32F-NEXT: .LBB102_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: slli a3, a3, 48
+; RV64ZVE32F-NEXT: srli a3, a3, 45
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: .LBB102_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a3, a2, 32
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_15
+; RV64ZVE32F-NEXT: .LBB102_7: # %else14
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_16
+; RV64ZVE32F-NEXT: .LBB102_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_10
+; RV64ZVE32F-NEXT: .LBB102_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 45
+; RV64ZVE32F-NEXT: add a1, a1, a2
+; RV64ZVE32F-NEXT: fld fa7, 0(a1)
+; RV64ZVE32F-NEXT: .LBB102_10: # %else20
+; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
+; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
+; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
+; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
+; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
+; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
+; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
+; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB102_11: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 48
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_2: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a3, .LBB102_2
+; RV64ZVE32F-NEXT: .LBB102_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
@@ -12201,42 +12768,28 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_4: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: beqz a3, .LBB102_3
+; RV64ZVE32F-NEXT: .LBB102_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 48
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_6: # %else5
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 48
-; RV64ZVE32F-NEXT: srli a3, a3, 45
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a3, .LBB102_4
+; RV64ZVE32F-NEXT: j .LBB102_5
+; RV64ZVE32F-NEXT: .LBB102_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 48
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_10: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a3, .LBB102_7
+; RV64ZVE32F-NEXT: .LBB102_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
@@ -12244,37 +12797,19 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB102_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: beqz a3, .LBB102_8
+; RV64ZVE32F-NEXT: .LBB102_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
; RV64ZVE32F-NEXT: slli a3, a3, 48
; RV64ZVE32F-NEXT: srli a3, a3, 45
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB102_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 45
-; RV64ZVE32F-NEXT: add a1, a1, a2
-; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB102_16: # %else20
-; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
-; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
-; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
-; RV64ZVE32F-NEXT: fsd fa3, 24(a0)
-; RV64ZVE32F-NEXT: fsd fa4, 32(a0)
-; RV64ZVE32F-NEXT: fsd fa5, 40(a0)
-; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
-; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_9
+; RV64ZVE32F-NEXT: j .LBB102_10
%eidxs = zext <8 x i16> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
@@ -12400,71 +12935,45 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB103_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB103_2: # %else
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_12
+; RV64ZVE32F-NEXT: .LBB103_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
; RV64ZVE32F-NEXT: beqz a3, .LBB103_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB103_4: # %else2
+; RV64ZVE32F-NEXT: .LBB103_3: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB103_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB103_6: # %else5
+; RV64ZVE32F-NEXT: .LBB103_4: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: bnez a3, .LBB103_15
-; RV64ZVE32F-NEXT: # %bb.7: # %else8
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_13
+; RV64ZVE32F-NEXT: # %bb.5: # %else8
; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: bnez a3, .LBB103_16
-; RV64ZVE32F-NEXT: .LBB103_8: # %else11
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_14
+; RV64ZVE32F-NEXT: .LBB103_6: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB103_10
-; RV64ZVE32F-NEXT: .LBB103_9: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB103_10: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_15
+; RV64ZVE32F-NEXT: .LBB103_7: # %else14
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB103_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB103_12: # %else17
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_16
+; RV64ZVE32F-NEXT: .LBB103_8: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB103_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a2, .LBB103_10
+; RV64ZVE32F-NEXT: .LBB103_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB103_14: # %else20
+; RV64ZVE32F-NEXT: .LBB103_10: # %else20
; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
@@ -12474,23 +12983,59 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB103_15: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa3, 0(a3)
-; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB103_8
-; RV64ZVE32F-NEXT: .LBB103_16: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: .LBB103_11: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa0, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: beqz a3, .LBB103_2
+; RV64ZVE32F-NEXT: .LBB103_12: # %cond.load1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa1, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB103_3
+; RV64ZVE32F-NEXT: j .LBB103_4
+; RV64ZVE32F-NEXT: .LBB103_13: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa3, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 16
+; RV64ZVE32F-NEXT: beqz a3, .LBB103_6
+; RV64ZVE32F-NEXT: .LBB103_14: # %cond.load10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: bnez a3, .LBB103_9
+; RV64ZVE32F-NEXT: beqz a3, .LBB103_7
+; RV64ZVE32F-NEXT: .LBB103_15: # %cond.load13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa5, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: beqz a3, .LBB103_8
+; RV64ZVE32F-NEXT: .LBB103_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa6, 0(a3)
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: bnez a2, .LBB103_9
; RV64ZVE32F-NEXT: j .LBB103_10
%ptrs = getelementptr inbounds double, ptr %base, <8 x i32> %idxs
%v = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %m, <8 x double> %passthru)
@@ -12616,71 +13161,45 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB104_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB104_2: # %else
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_12
+; RV64ZVE32F-NEXT: .LBB104_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
; RV64ZVE32F-NEXT: beqz a3, .LBB104_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB104_4: # %else2
+; RV64ZVE32F-NEXT: .LBB104_3: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB104_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB104_6: # %else5
+; RV64ZVE32F-NEXT: .LBB104_4: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: bnez a3, .LBB104_15
-; RV64ZVE32F-NEXT: # %bb.7: # %else8
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_13
+; RV64ZVE32F-NEXT: # %bb.5: # %else8
; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: bnez a3, .LBB104_16
-; RV64ZVE32F-NEXT: .LBB104_8: # %else11
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_14
+; RV64ZVE32F-NEXT: .LBB104_6: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB104_10
-; RV64ZVE32F-NEXT: .LBB104_9: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB104_10: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_15
+; RV64ZVE32F-NEXT: .LBB104_7: # %else14
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB104_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
-; RV64ZVE32F-NEXT: slli a3, a3, 3
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB104_12: # %else17
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_16
+; RV64ZVE32F-NEXT: .LBB104_8: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB104_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a2, .LBB104_10
+; RV64ZVE32F-NEXT: .LBB104_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB104_14: # %else20
+; RV64ZVE32F-NEXT: .LBB104_10: # %else20
; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
@@ -12690,23 +13209,59 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB104_15: # %cond.load7
+; RV64ZVE32F-NEXT: .LBB104_11: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa0, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: beqz a3, .LBB104_2
+; RV64ZVE32F-NEXT: .LBB104_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa1, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB104_3
+; RV64ZVE32F-NEXT: j .LBB104_4
+; RV64ZVE32F-NEXT: .LBB104_13: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa3, 0(a3)
; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB104_8
-; RV64ZVE32F-NEXT: .LBB104_16: # %cond.load10
+; RV64ZVE32F-NEXT: beqz a3, .LBB104_6
+; RV64ZVE32F-NEXT: .LBB104_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: bnez a3, .LBB104_9
+; RV64ZVE32F-NEXT: beqz a3, .LBB104_7
+; RV64ZVE32F-NEXT: .LBB104_15: # %cond.load13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa5, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: beqz a3, .LBB104_8
+; RV64ZVE32F-NEXT: .LBB104_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 3
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa6, 0(a3)
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: bnez a2, .LBB104_9
; RV64ZVE32F-NEXT: j .LBB104_10
%eidxs = sext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs
@@ -12833,77 +13388,47 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v0
; RV64ZVE32F-NEXT: andi a3, a2, 1
-; RV64ZVE32F-NEXT: beqz a3, .LBB105_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
-; RV64ZVE32F-NEXT: slli a3, a3, 32
-; RV64ZVE32F-NEXT: srli a3, a3, 29
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa0, 0(a3)
-; RV64ZVE32F-NEXT: .LBB105_2: # %else
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_12
+; RV64ZVE32F-NEXT: .LBB105_2: # %else2
+; RV64ZVE32F-NEXT: andi a3, a2, 4
; RV64ZVE32F-NEXT: beqz a3, .LBB105_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-NEXT: slli a3, a3, 32
-; RV64ZVE32F-NEXT: srli a3, a3, 29
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa1, 0(a3)
-; RV64ZVE32F-NEXT: .LBB105_4: # %else2
+; RV64ZVE32F-NEXT: .LBB105_3: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a3, a2, 4
-; RV64ZVE32F-NEXT: beqz a3, .LBB105_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 32
; RV64ZVE32F-NEXT: srli a3, a3, 29
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa2, 0(a3)
-; RV64ZVE32F-NEXT: .LBB105_6: # %else5
+; RV64ZVE32F-NEXT: .LBB105_4: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a3, a2, 8
-; RV64ZVE32F-NEXT: bnez a3, .LBB105_15
-; RV64ZVE32F-NEXT: # %bb.7: # %else8
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_13
+; RV64ZVE32F-NEXT: # %bb.5: # %else8
; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: bnez a3, .LBB105_16
-; RV64ZVE32F-NEXT: .LBB105_8: # %else11
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_14
+; RV64ZVE32F-NEXT: .LBB105_6: # %else11
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: beqz a3, .LBB105_10
-; RV64ZVE32F-NEXT: .LBB105_9: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: slli a3, a3, 32
-; RV64ZVE32F-NEXT: srli a3, a3, 29
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB105_10: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_15
+; RV64ZVE32F-NEXT: .LBB105_7: # %else14
; RV64ZVE32F-NEXT: andi a3, a2, 64
-; RV64ZVE32F-NEXT: beqz a3, .LBB105_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
-; RV64ZVE32F-NEXT: slli a3, a3, 32
-; RV64ZVE32F-NEXT: srli a3, a3, 29
-; RV64ZVE32F-NEXT: add a3, a1, a3
-; RV64ZVE32F-NEXT: fld fa6, 0(a3)
-; RV64ZVE32F-NEXT: .LBB105_12: # %else17
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_16
+; RV64ZVE32F-NEXT: .LBB105_8: # %else17
; RV64ZVE32F-NEXT: andi a2, a2, -128
-; RV64ZVE32F-NEXT: beqz a2, .LBB105_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: beqz a2, .LBB105_10
+; RV64ZVE32F-NEXT: .LBB105_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
; RV64ZVE32F-NEXT: add a1, a1, a2
; RV64ZVE32F-NEXT: fld fa7, 0(a1)
-; RV64ZVE32F-NEXT: .LBB105_14: # %else20
+; RV64ZVE32F-NEXT: .LBB105_10: # %else20
; RV64ZVE32F-NEXT: fsd fa0, 0(a0)
; RV64ZVE32F-NEXT: fsd fa1, 8(a0)
; RV64ZVE32F-NEXT: fsd fa2, 16(a0)
@@ -12913,25 +13438,65 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: fsd fa6, 48(a0)
; RV64ZVE32F-NEXT: fsd fa7, 56(a0)
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB105_15: # %cond.load7
+; RV64ZVE32F-NEXT: .LBB105_11: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 32
+; RV64ZVE32F-NEXT: srli a3, a3, 29
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa0, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 2
+; RV64ZVE32F-NEXT: beqz a3, .LBB105_2
+; RV64ZVE32F-NEXT: .LBB105_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: slli a3, a3, 32
+; RV64ZVE32F-NEXT: srli a3, a3, 29
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa1, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 4
+; RV64ZVE32F-NEXT: bnez a3, .LBB105_3
+; RV64ZVE32F-NEXT: j .LBB105_4
+; RV64ZVE32F-NEXT: .LBB105_13: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 32
; RV64ZVE32F-NEXT: srli a3, a3, 29
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa3, 0(a3)
; RV64ZVE32F-NEXT: andi a3, a2, 16
-; RV64ZVE32F-NEXT: beqz a3, .LBB105_8
-; RV64ZVE32F-NEXT: .LBB105_16: # %cond.load10
+; RV64ZVE32F-NEXT: beqz a3, .LBB105_6
+; RV64ZVE32F-NEXT: .LBB105_14: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 32
; RV64ZVE32F-NEXT: srli a3, a3, 29
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa4, 0(a3)
; RV64ZVE32F-NEXT: andi a3, a2, 32
-; RV64ZVE32F-NEXT: bnez a3, .LBB105_9
+; RV64ZVE32F-NEXT: beqz a3, .LBB105_7
+; RV64ZVE32F-NEXT: .LBB105_15: # %cond.load13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 32
+; RV64ZVE32F-NEXT: srli a3, a3, 29
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa5, 0(a3)
+; RV64ZVE32F-NEXT: andi a3, a2, 64
+; RV64ZVE32F-NEXT: beqz a3, .LBB105_8
+; RV64ZVE32F-NEXT: .LBB105_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v8
+; RV64ZVE32F-NEXT: slli a3, a3, 32
+; RV64ZVE32F-NEXT: srli a3, a3, 29
+; RV64ZVE32F-NEXT: add a3, a1, a3
+; RV64ZVE32F-NEXT: fld fa6, 0(a3)
+; RV64ZVE32F-NEXT: andi a2, a2, -128
+; RV64ZVE32F-NEXT: bnez a2, .LBB105_9
; RV64ZVE32F-NEXT: j .LBB105_10
%eidxs = zext <8 x i32> %idxs to <8 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <8 x i64> %eidxs
@@ -13189,198 +13754,224 @@ define <16 x i8> @mgather_baseidx_v16i8(ptr %base, <16 x i8> %idxs, <16 x i1> %m
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB107_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_22
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB107_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_23
+; RV64ZVE32F-NEXT: .LBB107_2: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB107_6: # %else5
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_24
+; RV64ZVE32F-NEXT: .LBB107_3: # %else5
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_5
+; RV64ZVE32F-NEXT: .LBB107_4: # %cond.load7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB107_8: # %else8
+; RV64ZVE32F-NEXT: .LBB107_5: # %else8
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 4
-; RV64ZVE32F-NEXT: .LBB107_10: # %else11
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_25
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 5
-; RV64ZVE32F-NEXT: .LBB107_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_26
+; RV64ZVE32F-NEXT: .LBB107_7: # %else14
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 6
-; RV64ZVE32F-NEXT: .LBB107_14: # %else17
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_27
+; RV64ZVE32F-NEXT: .LBB107_8: # %else17
; RV64ZVE32F-NEXT: andi a2, a1, 128
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_10
+; RV64ZVE32F-NEXT: .LBB107_9: # %cond.load19
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 7
-; RV64ZVE32F-NEXT: .LBB107_16: # %else20
+; RV64ZVE32F-NEXT: .LBB107_10: # %else20
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 8
; RV64ZVE32F-NEXT: andi a2, a1, 256
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_18
-; RV64ZVE32F-NEXT: # %bb.17: # %cond.load22
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 9, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 8
-; RV64ZVE32F-NEXT: .LBB107_18: # %else23
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_28
+; RV64ZVE32F-NEXT: # %bb.11: # %else23
; RV64ZVE32F-NEXT: andi a2, a1, 512
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_20
-; RV64ZVE32F-NEXT: # %bb.19: # %cond.load25
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 10, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 9
-; RV64ZVE32F-NEXT: .LBB107_20: # %else26
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_29
+; RV64ZVE32F-NEXT: .LBB107_12: # %else26
; RV64ZVE32F-NEXT: andi a2, a1, 1024
-; RV64ZVE32F-NEXT: beqz a2, .LBB107_22
-; RV64ZVE32F-NEXT: # %bb.21: # %cond.load28
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 11, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 10
-; RV64ZVE32F-NEXT: .LBB107_22: # %else29
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_30
+; RV64ZVE32F-NEXT: .LBB107_13: # %else29
; RV64ZVE32F-NEXT: slli a2, a1, 52
-; RV64ZVE32F-NEXT: bgez a2, .LBB107_24
-; RV64ZVE32F-NEXT: # %bb.23: # %cond.load31
+; RV64ZVE32F-NEXT: bgez a2, .LBB107_15
+; RV64ZVE32F-NEXT: .LBB107_14: # %cond.load31
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 12, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 11
-; RV64ZVE32F-NEXT: .LBB107_24: # %else32
+; RV64ZVE32F-NEXT: .LBB107_15: # %else32
; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: slli a2, a1, 51
-; RV64ZVE32F-NEXT: bgez a2, .LBB107_26
-; RV64ZVE32F-NEXT: # %bb.25: # %cond.load34
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 12
-; RV64ZVE32F-NEXT: .LBB107_26: # %else35
+; RV64ZVE32F-NEXT: bltz a2, .LBB107_31
+; RV64ZVE32F-NEXT: # %bb.16: # %else35
; RV64ZVE32F-NEXT: slli a2, a1, 50
-; RV64ZVE32F-NEXT: bgez a2, .LBB107_28
-; RV64ZVE32F-NEXT: # %bb.27: # %cond.load37
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 13
-; RV64ZVE32F-NEXT: .LBB107_28: # %else38
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bltz a2, .LBB107_32
+; RV64ZVE32F-NEXT: .LBB107_17: # %else38
; RV64ZVE32F-NEXT: slli a2, a1, 49
-; RV64ZVE32F-NEXT: bgez a2, .LBB107_30
-; RV64ZVE32F-NEXT: # %bb.29: # %cond.load40
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: bgez a2, .LBB107_19
+; RV64ZVE32F-NEXT: .LBB107_18: # %cond.load40
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 14
-; RV64ZVE32F-NEXT: .LBB107_30: # %else41
+; RV64ZVE32F-NEXT: .LBB107_19: # %else41
; RV64ZVE32F-NEXT: lui a2, 1048568
; RV64ZVE32F-NEXT: and a1, a1, a2
-; RV64ZVE32F-NEXT: beqz a1, .LBB107_32
-; RV64ZVE32F-NEXT: # %bb.31: # %cond.load43
+; RV64ZVE32F-NEXT: beqz a1, .LBB107_21
+; RV64ZVE32F-NEXT: # %bb.20: # %cond.load43
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: add a0, a0, a1
; RV64ZVE32F-NEXT: lbu a0, 0(a0)
; RV64ZVE32F-NEXT: vmv.s.x v8, a0
; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 15
-; RV64ZVE32F-NEXT: .LBB107_32: # %else44
+; RV64ZVE32F-NEXT: .LBB107_21: # %else44
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv1r.v v8, v9
; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB107_22: # %cond.load
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_2
+; RV64ZVE32F-NEXT: .LBB107_23: # %cond.load1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_3
+; RV64ZVE32F-NEXT: .LBB107_24: # %cond.load4
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_4
+; RV64ZVE32F-NEXT: j .LBB107_5
+; RV64ZVE32F-NEXT: .LBB107_25: # %cond.load10
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_7
+; RV64ZVE32F-NEXT: .LBB107_26: # %cond.load13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 5
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_8
+; RV64ZVE32F-NEXT: .LBB107_27: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 6
+; RV64ZVE32F-NEXT: andi a2, a1, 128
+; RV64ZVE32F-NEXT: bnez a2, .LBB107_9
+; RV64ZVE32F-NEXT: j .LBB107_10
+; RV64ZVE32F-NEXT: .LBB107_28: # %cond.load22
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 9, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 8
+; RV64ZVE32F-NEXT: andi a2, a1, 512
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_12
+; RV64ZVE32F-NEXT: .LBB107_29: # %cond.load25
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 10, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 9
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: beqz a2, .LBB107_13
+; RV64ZVE32F-NEXT: .LBB107_30: # %cond.load28
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 11, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 10
+; RV64ZVE32F-NEXT: slli a2, a1, 52
+; RV64ZVE32F-NEXT: bltz a2, .LBB107_14
+; RV64ZVE32F-NEXT: j .LBB107_15
+; RV64ZVE32F-NEXT: .LBB107_31: # %cond.load34
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 12
+; RV64ZVE32F-NEXT: slli a2, a1, 50
+; RV64ZVE32F-NEXT: bgez a2, .LBB107_17
+; RV64ZVE32F-NEXT: .LBB107_32: # %cond.load37
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 13
+; RV64ZVE32F-NEXT: slli a2, a1, 49
+; RV64ZVE32F-NEXT: bltz a2, .LBB107_18
+; RV64ZVE32F-NEXT: j .LBB107_19
%ptrs = getelementptr inbounds i8, ptr %base, <16 x i8> %idxs
%v = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> %ptrs, i32 2, <16 x i1> %m, <16 x i8> %passthru)
ret <16 x i8> %v
@@ -13424,17 +14015,210 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_42
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_43
+; RV64ZVE32F-NEXT: .LBB108_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_44
+; RV64ZVE32F-NEXT: .LBB108_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_5
+; RV64ZVE32F-NEXT: .LBB108_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3
+; RV64ZVE32F-NEXT: .LBB108_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_45
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_46
+; RV64ZVE32F-NEXT: .LBB108_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_47
+; RV64ZVE32F-NEXT: .LBB108_8: # %else17
+; RV64ZVE32F-NEXT: andi a2, a1, 128
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_10
+; RV64ZVE32F-NEXT: .LBB108_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 7
+; RV64ZVE32F-NEXT: .LBB108_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 8
+; RV64ZVE32F-NEXT: andi a2, a1, 256
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_48
+; RV64ZVE32F-NEXT: # %bb.11: # %else23
+; RV64ZVE32F-NEXT: andi a2, a1, 512
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_49
+; RV64ZVE32F-NEXT: .LBB108_12: # %else26
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_50
+; RV64ZVE32F-NEXT: .LBB108_13: # %else29
+; RV64ZVE32F-NEXT: slli a2, a1, 52
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_15
+; RV64ZVE32F-NEXT: .LBB108_14: # %cond.load31
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v13
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v13, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 12, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 11
+; RV64ZVE32F-NEXT: .LBB108_15: # %else32
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 51
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_51
+; RV64ZVE32F-NEXT: # %bb.16: # %else35
+; RV64ZVE32F-NEXT: slli a2, a1, 50
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_52
+; RV64ZVE32F-NEXT: .LBB108_17: # %else38
+; RV64ZVE32F-NEXT: slli a2, a1, 49
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_19
+; RV64ZVE32F-NEXT: .LBB108_18: # %cond.load40
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v13
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v13, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 14
+; RV64ZVE32F-NEXT: .LBB108_19: # %else41
+; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 16
+; RV64ZVE32F-NEXT: slli a2, a1, 48
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_53
+; RV64ZVE32F-NEXT: # %bb.20: # %else44
+; RV64ZVE32F-NEXT: slli a2, a1, 47
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_54
+; RV64ZVE32F-NEXT: .LBB108_21: # %else47
+; RV64ZVE32F-NEXT: slli a2, a1, 46
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_55
+; RV64ZVE32F-NEXT: .LBB108_22: # %else50
+; RV64ZVE32F-NEXT: slli a2, a1, 45
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_56
+; RV64ZVE32F-NEXT: .LBB108_23: # %else53
+; RV64ZVE32F-NEXT: slli a2, a1, 44
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_25
+; RV64ZVE32F-NEXT: .LBB108_24: # %cond.load55
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 20, e8, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 19
+; RV64ZVE32F-NEXT: .LBB108_25: # %else56
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 43
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_57
+; RV64ZVE32F-NEXT: # %bb.26: # %else59
+; RV64ZVE32F-NEXT: slli a2, a1, 42
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_58
+; RV64ZVE32F-NEXT: .LBB108_27: # %else62
+; RV64ZVE32F-NEXT: slli a2, a1, 41
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_59
+; RV64ZVE32F-NEXT: .LBB108_28: # %else65
+; RV64ZVE32F-NEXT: slli a2, a1, 40
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_30
+; RV64ZVE32F-NEXT: .LBB108_29: # %cond.load67
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 24, e8, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 23
+; RV64ZVE32F-NEXT: .LBB108_30: # %else68
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 8
+; RV64ZVE32F-NEXT: slli a2, a1, 39
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_60
+; RV64ZVE32F-NEXT: # %bb.31: # %else71
+; RV64ZVE32F-NEXT: slli a2, a1, 38
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_61
+; RV64ZVE32F-NEXT: .LBB108_32: # %else74
+; RV64ZVE32F-NEXT: slli a2, a1, 37
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_62
+; RV64ZVE32F-NEXT: .LBB108_33: # %else77
+; RV64ZVE32F-NEXT: slli a2, a1, 36
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_35
+; RV64ZVE32F-NEXT: .LBB108_34: # %cond.load79
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 28, e8, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 27
+; RV64ZVE32F-NEXT: .LBB108_35: # %else80
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 35
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_63
+; RV64ZVE32F-NEXT: # %bb.36: # %else83
+; RV64ZVE32F-NEXT: slli a2, a1, 34
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_64
+; RV64ZVE32F-NEXT: .LBB108_37: # %else86
+; RV64ZVE32F-NEXT: slli a2, a1, 33
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_39
+; RV64ZVE32F-NEXT: .LBB108_38: # %cond.load88
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 31, e8, m2, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 30
+; RV64ZVE32F-NEXT: .LBB108_39: # %else89
+; RV64ZVE32F-NEXT: lui a2, 524288
+; RV64ZVE32F-NEXT: and a1, a1, a2
+; RV64ZVE32F-NEXT: beqz a1, .LBB108_41
+; RV64ZVE32F-NEXT: # %bb.40: # %cond.load91
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lbu a0, 0(a0)
+; RV64ZVE32F-NEXT: li a1, 32
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 31
+; RV64ZVE32F-NEXT: .LBB108_41: # %else92
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv2r.v v8, v10
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB108_42: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: .LBB108_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_2
+; RV64ZVE32F-NEXT: .LBB108_43: # %cond.load1
; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
@@ -13443,46 +14227,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1
-; RV64ZVE32F-NEXT: .LBB108_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_3
+; RV64ZVE32F-NEXT: .LBB108_44: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v13, a2
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 2
-; RV64ZVE32F-NEXT: .LBB108_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3
-; RV64ZVE32F-NEXT: .LBB108_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_4
+; RV64ZVE32F-NEXT: j .LBB108_5
+; RV64ZVE32F-NEXT: .LBB108_45: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 4
-; RV64ZVE32F-NEXT: .LBB108_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_7
+; RV64ZVE32F-NEXT: .LBB108_46: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
@@ -13491,46 +14259,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 5
-; RV64ZVE32F-NEXT: .LBB108_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_8
+; RV64ZVE32F-NEXT: .LBB108_47: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v13
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 6
-; RV64ZVE32F-NEXT: .LBB108_14: # %else17
; RV64ZVE32F-NEXT: andi a2, a1, 128
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 7
-; RV64ZVE32F-NEXT: .LBB108_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 8
-; RV64ZVE32F-NEXT: andi a2, a1, 256
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_18
-; RV64ZVE32F-NEXT: # %bb.17: # %cond.load22
+; RV64ZVE32F-NEXT: bnez a2, .LBB108_9
+; RV64ZVE32F-NEXT: j .LBB108_10
+; RV64ZVE32F-NEXT: .LBB108_48: # %cond.load22
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 9, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 8
-; RV64ZVE32F-NEXT: .LBB108_18: # %else23
; RV64ZVE32F-NEXT: andi a2, a1, 512
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_20
-; RV64ZVE32F-NEXT: # %bb.19: # %cond.load25
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_12
+; RV64ZVE32F-NEXT: .LBB108_49: # %cond.load25
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
@@ -13539,46 +14291,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 10, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 9
-; RV64ZVE32F-NEXT: .LBB108_20: # %else26
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: beqz a2, .LBB108_13
+; RV64ZVE32F-NEXT: .LBB108_50: # %cond.load28
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 1024
-; RV64ZVE32F-NEXT: beqz a2, .LBB108_22
-; RV64ZVE32F-NEXT: # %bb.21: # %cond.load28
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v14, a2
+; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 11, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 10
-; RV64ZVE32F-NEXT: .LBB108_22: # %else29
+; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 10
; RV64ZVE32F-NEXT: slli a2, a1, 52
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_24
-; RV64ZVE32F-NEXT: # %bb.23: # %cond.load31
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v13
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v13, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 12, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 11
-; RV64ZVE32F-NEXT: .LBB108_24: # %else32
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 51
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_26
-; RV64ZVE32F-NEXT: # %bb.25: # %cond.load34
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_14
+; RV64ZVE32F-NEXT: j .LBB108_15
+; RV64ZVE32F-NEXT: .LBB108_51: # %cond.load34
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 12
-; RV64ZVE32F-NEXT: .LBB108_26: # %else35
; RV64ZVE32F-NEXT: slli a2, a1, 50
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_28
-; RV64ZVE32F-NEXT: # %bb.27: # %cond.load37
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_17
+; RV64ZVE32F-NEXT: .LBB108_52: # %cond.load37
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
@@ -13587,30 +14323,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v13, a2
; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 13
-; RV64ZVE32F-NEXT: .LBB108_28: # %else38
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 2
; RV64ZVE32F-NEXT: slli a2, a1, 49
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_30
-; RV64ZVE32F-NEXT: # %bb.29: # %cond.load40
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_18
+; RV64ZVE32F-NEXT: j .LBB108_19
+; RV64ZVE32F-NEXT: .LBB108_53: # %cond.load43
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v13, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 14
-; RV64ZVE32F-NEXT: .LBB108_30: # %else41
-; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 16
-; RV64ZVE32F-NEXT: slli a2, a1, 48
-; RV64ZVE32F-NEXT: bltz a2, .LBB108_63
-; RV64ZVE32F-NEXT: # %bb.31: # %else44
+; RV64ZVE32F-NEXT: vmv.s.x v9, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 15
; RV64ZVE32F-NEXT: slli a2, a1, 47
-; RV64ZVE32F-NEXT: bltz a2, .LBB108_64
-; RV64ZVE32F-NEXT: .LBB108_32: # %else47
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_21
+; RV64ZVE32F-NEXT: .LBB108_54: # %cond.load46
+; RV64ZVE32F-NEXT: vsetivli zero, 17, e8, m2, tu, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v12, a2
+; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 16
; RV64ZVE32F-NEXT: slli a2, a1, 46
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_34
-; RV64ZVE32F-NEXT: .LBB108_33: # %cond.load49
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_22
+; RV64ZVE32F-NEXT: .LBB108_55: # %cond.load49
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -13619,46 +14355,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 18, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 17
-; RV64ZVE32F-NEXT: .LBB108_34: # %else50
+; RV64ZVE32F-NEXT: slli a2, a1, 45
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_23
+; RV64ZVE32F-NEXT: .LBB108_56: # %cond.load52
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: slli a2, a1, 45
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_36
-; RV64ZVE32F-NEXT: # %bb.35: # %cond.load52
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 19, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 18
-; RV64ZVE32F-NEXT: .LBB108_36: # %else53
; RV64ZVE32F-NEXT: slli a2, a1, 44
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_38
-; RV64ZVE32F-NEXT: # %bb.37: # %cond.load55
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 20, e8, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 19
-; RV64ZVE32F-NEXT: .LBB108_38: # %else56
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 43
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_40
-; RV64ZVE32F-NEXT: # %bb.39: # %cond.load58
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_24
+; RV64ZVE32F-NEXT: j .LBB108_25
+; RV64ZVE32F-NEXT: .LBB108_57: # %cond.load58
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 21, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 20
-; RV64ZVE32F-NEXT: .LBB108_40: # %else59
; RV64ZVE32F-NEXT: slli a2, a1, 42
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_42
-; RV64ZVE32F-NEXT: # %bb.41: # %cond.load61
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_27
+; RV64ZVE32F-NEXT: .LBB108_58: # %cond.load61
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
@@ -13667,46 +14387,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 22, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 21
-; RV64ZVE32F-NEXT: .LBB108_42: # %else62
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: slli a2, a1, 41
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_44
-; RV64ZVE32F-NEXT: # %bb.43: # %cond.load64
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_28
+; RV64ZVE32F-NEXT: .LBB108_59: # %cond.load64
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 23, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 22
-; RV64ZVE32F-NEXT: .LBB108_44: # %else65
; RV64ZVE32F-NEXT: slli a2, a1, 40
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_46
-; RV64ZVE32F-NEXT: # %bb.45: # %cond.load67
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 24, e8, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 23
-; RV64ZVE32F-NEXT: .LBB108_46: # %else68
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 8
-; RV64ZVE32F-NEXT: slli a2, a1, 39
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_48
-; RV64ZVE32F-NEXT: # %bb.47: # %cond.load70
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_29
+; RV64ZVE32F-NEXT: j .LBB108_30
+; RV64ZVE32F-NEXT: .LBB108_60: # %cond.load70
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 25, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 24
-; RV64ZVE32F-NEXT: .LBB108_48: # %else71
; RV64ZVE32F-NEXT: slli a2, a1, 38
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_50
-; RV64ZVE32F-NEXT: # %bb.49: # %cond.load73
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_32
+; RV64ZVE32F-NEXT: .LBB108_61: # %cond.load73
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -13715,46 +14419,30 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 26, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 25
-; RV64ZVE32F-NEXT: .LBB108_50: # %else74
+; RV64ZVE32F-NEXT: slli a2, a1, 37
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_33
+; RV64ZVE32F-NEXT: .LBB108_62: # %cond.load76
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: slli a2, a1, 37
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_52
-; RV64ZVE32F-NEXT: # %bb.51: # %cond.load76
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 27, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 26
-; RV64ZVE32F-NEXT: .LBB108_52: # %else77
; RV64ZVE32F-NEXT: slli a2, a1, 36
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_54
-; RV64ZVE32F-NEXT: # %bb.53: # %cond.load79
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 28, e8, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 27
-; RV64ZVE32F-NEXT: .LBB108_54: # %else80
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 35
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_56
-; RV64ZVE32F-NEXT: # %bb.55: # %cond.load82
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_34
+; RV64ZVE32F-NEXT: j .LBB108_35
+; RV64ZVE32F-NEXT: .LBB108_63: # %cond.load82
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 29, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 28
-; RV64ZVE32F-NEXT: .LBB108_56: # %else83
; RV64ZVE32F-NEXT: slli a2, a1, 34
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_58
-; RV64ZVE32F-NEXT: # %bb.57: # %cond.load85
+; RV64ZVE32F-NEXT: bgez a2, .LBB108_37
+; RV64ZVE32F-NEXT: .LBB108_64: # %cond.load85
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -13763,57 +14451,9 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
; RV64ZVE32F-NEXT: vsetivli zero, 30, e8, m2, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 29
-; RV64ZVE32F-NEXT: .LBB108_58: # %else86
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: slli a2, a1, 33
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_60
-; RV64ZVE32F-NEXT: # %bb.59: # %cond.load88
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 31, e8, m2, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 30
-; RV64ZVE32F-NEXT: .LBB108_60: # %else89
-; RV64ZVE32F-NEXT: lui a2, 524288
-; RV64ZVE32F-NEXT: and a1, a1, a2
-; RV64ZVE32F-NEXT: beqz a1, .LBB108_62
-; RV64ZVE32F-NEXT: # %bb.61: # %cond.load91
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: li a1, 32
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 31
-; RV64ZVE32F-NEXT: .LBB108_62: # %else92
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv2r.v v8, v10
-; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB108_63: # %cond.load43
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 15
-; RV64ZVE32F-NEXT: slli a2, a1, 47
-; RV64ZVE32F-NEXT: bgez a2, .LBB108_32
-; RV64ZVE32F-NEXT: .LBB108_64: # %cond.load46
-; RV64ZVE32F-NEXT: vsetivli zero, 17, e8, m2, tu, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v12, a2
-; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 16
-; RV64ZVE32F-NEXT: slli a2, a1, 46
-; RV64ZVE32F-NEXT: bltz a2, .LBB108_33
-; RV64ZVE32F-NEXT: j .LBB108_34
+; RV64ZVE32F-NEXT: bltz a2, .LBB108_38
+; RV64ZVE32F-NEXT: j .LBB108_39
%ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs
%v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru)
ret <32 x i8> %v
@@ -15219,8 +15859,87 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64ZVE32F-NEXT: vsm.v v0, (a2)
; RV64ZVE32F-NEXT: ld a1, 8(sp)
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB132_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB132_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB132_11
+; RV64ZVE32F-NEXT: .LBB132_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB132_12
+; RV64ZVE32F-NEXT: .LBB132_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB132_5
+; RV64ZVE32F-NEXT: .LBB132_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: vmv.x.s a4, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a5, v10
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 4
+; RV64ZVE32F-NEXT: vmv.x.s a6, v10
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 5
+; RV64ZVE32F-NEXT: vmv.x.s a7, v10
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 6
+; RV64ZVE32F-NEXT: vmv.x.s t0, v9
+; RV64ZVE32F-NEXT: vmv.v.x v9, a4
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; RV64ZVE32F-NEXT: lbu a2, 0(a2)
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: .LBB132_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB132_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB132_14
+; RV64ZVE32F-NEXT: .LBB132_7: # %else14
+; RV64ZVE32F-NEXT: andi a1, a1, 64
+; RV64ZVE32F-NEXT: beqz a1, .LBB132_9
+; RV64ZVE32F-NEXT: .LBB132_8: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a4, v8
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a5, v8
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4
+; RV64ZVE32F-NEXT: vmv.x.s a6, v8
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 5
+; RV64ZVE32F-NEXT: vmv.x.s a7, v8
+; RV64ZVE32F-NEXT: vmv.v.x v8, a3
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lbu a0, 0(a0)
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
+; RV64ZVE32F-NEXT: .LBB132_9: # %else17
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: addi sp, sp, 16
+; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 0
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB132_10: # %cond.load
+; RV64ZVE32F-NEXT: .cfi_restore_state
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
@@ -15245,10 +15964,9 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: .LBB132_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB132_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB132_2
+; RV64ZVE32F-NEXT: .LBB132_11: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -15274,47 +15992,17 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: .LBB132_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB132_3
+; RV64ZVE32F-NEXT: .LBB132_12: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB132_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v11
-; RV64ZVE32F-NEXT: vmv.x.s a4, v9
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 3
-; RV64ZVE32F-NEXT: vmv.x.s a5, v11
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 4
-; RV64ZVE32F-NEXT: vmv.x.s a6, v11
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v9, 5
-; RV64ZVE32F-NEXT: vmv.x.s a7, v11
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 6
-; RV64ZVE32F-NEXT: vmv.x.s t0, v9
-; RV64ZVE32F-NEXT: vmv.v.x v9, a4
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
-; RV64ZVE32F-NEXT: lbu a2, 0(a2)
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a5
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: .LBB132_6: # %else5
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB132_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: vmv.x.s a4, v9
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a5, v10
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 4
; RV64ZVE32F-NEXT: vmv.x.s a6, v10
@@ -15323,60 +16011,19 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 6
; RV64ZVE32F-NEXT: vmv.x.s t0, v9
; RV64ZVE32F-NEXT: vmv.v.x v9, a4
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: lbu a2, 0(a2)
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a5
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: .LBB132_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB132_13
-; RV64ZVE32F-NEXT: # %bb.9: # %else11
-; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB132_14
-; RV64ZVE32F-NEXT: .LBB132_10: # %else14
-; RV64ZVE32F-NEXT: andi a1, a1, 64
-; RV64ZVE32F-NEXT: beqz a1, .LBB132_12
-; RV64ZVE32F-NEXT: .LBB132_11: # %cond.load16
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 2
-; RV64ZVE32F-NEXT: vmv.x.s a4, v8
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 3
-; RV64ZVE32F-NEXT: vmv.x.s a5, v8
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4
-; RV64ZVE32F-NEXT: vmv.x.s a6, v8
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 5
-; RV64ZVE32F-NEXT: vmv.x.s a7, v8
-; RV64ZVE32F-NEXT: vmv.v.x v8, a3
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lbu a0, 0(a0)
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: .LBB132_12: # %else17
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: addi sp, sp, 16
-; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 0
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB132_4
+; RV64ZVE32F-NEXT: j .LBB132_5
; RV64ZVE32F-NEXT: .LBB132_13: # %cond.load10
-; RV64ZVE32F-NEXT: .cfi_restore_state
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
@@ -15401,7 +16048,7 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB132_10
+; RV64ZVE32F-NEXT: beqz a2, .LBB132_7
; RV64ZVE32F-NEXT: .LBB132_14: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
@@ -15429,8 +16076,8 @@ define <7 x i8> @mgather_baseidx_v7i8(ptr %base, <7 x i8> %idxs, <7 x i1> %m, <7
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, t0
; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32F-NEXT: andi a1, a1, 64
-; RV64ZVE32F-NEXT: bnez a1, .LBB132_11
-; RV64ZVE32F-NEXT: j .LBB132_12
+; RV64ZVE32F-NEXT: bnez a1, .LBB132_8
+; RV64ZVE32F-NEXT: j .LBB132_9
%ptrs = getelementptr inbounds i8, ptr %base, <7 x i8> %idxs
%v = call <7 x i8> @llvm.masked.gather.v7i8.v7p0(<7 x ptr> %ptrs, i32 1, <7 x i1> %m, <7 x i8> %passthru)
ret <7 x i8> %v
@@ -15462,8 +16109,57 @@ define <8 x i16> @mgather_baseidx_and_v8i16_v8i16(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vand.vx v8, v8, a2
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_11
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_12
+; RV64ZVE32F-NEXT: .LBB133_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_13
+; RV64ZVE32F-NEXT: .LBB133_3: # %else5
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB133_5
+; RV64ZVE32F-NEXT: .LBB133_4: # %cond.load7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 49
+; RV64ZVE32F-NEXT: srli a2, a2, 48
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: lh a2, 0(a2)
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
+; RV64ZVE32F-NEXT: .LBB133_5: # %else8
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_14
+; RV64ZVE32F-NEXT: # %bb.6: # %else11
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_15
+; RV64ZVE32F-NEXT: .LBB133_7: # %else14
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_16
+; RV64ZVE32F-NEXT: .LBB133_8: # %else17
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: beqz a1, .LBB133_10
+; RV64ZVE32F-NEXT: .LBB133_9: # %cond.load19
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v8
+; RV64ZVE32F-NEXT: slli a1, a1, 49
+; RV64ZVE32F-NEXT: srli a1, a1, 48
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: lh a0, 0(a0)
+; RV64ZVE32F-NEXT: vmv.s.x v8, a0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
+; RV64ZVE32F-NEXT: .LBB133_10: # %else20
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv1r.v v8, v9
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB133_11: # %cond.load
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 49
; RV64ZVE32F-NEXT: srli a2, a2, 48
@@ -15471,10 +16167,9 @@ define <8 x i16> @mgather_baseidx_and_v8i16_v8i16(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: lh a2, 0(a2)
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
-; RV64ZVE32F-NEXT: .LBB133_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
+; RV64ZVE32F-NEXT: beqz a2, .LBB133_2
+; RV64ZVE32F-NEXT: .LBB133_12: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -15485,40 +16180,23 @@ define <8 x i16> @mgather_baseidx_and_v8i16_v8i16(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 1
-; RV64ZVE32F-NEXT: .LBB133_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB133_3
+; RV64ZVE32F-NEXT: .LBB133_13: # %cond.load4
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.load4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 49
; RV64ZVE32F-NEXT: srli a2, a2, 48
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v11, a2
+; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v11, 2
-; RV64ZVE32F-NEXT: .LBB133_6: # %else5
+; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 49
-; RV64ZVE32F-NEXT: srli a2, a2, 48
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: lh a2, 0(a2)
-; RV64ZVE32F-NEXT: vmv.s.x v10, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3
-; RV64ZVE32F-NEXT: .LBB133_8: # %else8
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.load10
+; RV64ZVE32F-NEXT: bnez a2, .LBB133_4
+; RV64ZVE32F-NEXT: j .LBB133_5
+; RV64ZVE32F-NEXT: .LBB133_14: # %cond.load10
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 49
; RV64ZVE32F-NEXT: srli a2, a2, 48
@@ -15527,10 +16205,9 @@ define <8 x i16> @mgather_baseidx_and_v8i16_v8i16(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 4
-; RV64ZVE32F-NEXT: .LBB133_10: # %else11
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.load13
+; RV64ZVE32F-NEXT: beqz a2, .LBB133_7
+; RV64ZVE32F-NEXT: .LBB133_15: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -15541,13 +16218,12 @@ define <8 x i16> @mgather_baseidx_and_v8i16_v8i16(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 5
-; RV64ZVE32F-NEXT: .LBB133_12: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB133_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.load16
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: beqz a2, .LBB133_8
+; RV64ZVE32F-NEXT: .LBB133_16: # %cond.load16
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 49
; RV64ZVE32F-NEXT: srli a2, a2, 48
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -15555,24 +16231,9 @@ define <8 x i16> @mgather_baseidx_and_v8i16_v8i16(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: vmv.s.x v10, a2
; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 6
-; RV64ZVE32F-NEXT: .LBB133_14: # %else17
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB133_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v8
-; RV64ZVE32F-NEXT: slli a1, a1, 49
-; RV64ZVE32F-NEXT: srli a1, a1, 48
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: lh a0, 0(a0)
-; RV64ZVE32F-NEXT: vmv.s.x v8, a0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslideup.vi v9, v8, 7
-; RV64ZVE32F-NEXT: .LBB133_16: # %else20
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv1r.v v8, v9
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bnez a1, .LBB133_9
+; RV64ZVE32F-NEXT: j .LBB133_10
%eidxs = and <8 x i16> %idxs, splat (i16 32767)
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %eidxs
%v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index 43e0046394647..366d2e881d919 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -486,16 +486,48 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB9_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_11
+; RV64ZVE32F-NEXT: .LBB9_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_12
+; RV64ZVE32F-NEXT: .LBB9_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB9_5
+; RV64ZVE32F-NEXT: .LBB9_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB9_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_14
+; RV64ZVE32F-NEXT: .LBB9_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_15
+; RV64ZVE32F-NEXT: .LBB9_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB9_16
+; RV64ZVE32F-NEXT: .LBB9_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB9_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vse8.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB9_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB9_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB9_2
+; RV64ZVE32F-NEXT: .LBB9_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -503,43 +535,28 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB9_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB9_3
+; RV64ZVE32F-NEXT: .LBB9_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB9_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB9_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB9_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB9_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB9_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB9_4
+; RV64ZVE32F-NEXT: j .LBB9_5
+; RV64ZVE32F-NEXT: .LBB9_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB9_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB9_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB9_7
+; RV64ZVE32F-NEXT: .LBB9_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -547,27 +564,21 @@ define void @mscatter_baseidx_v8i8(<8 x i8> %val, ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB9_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB9_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB9_16
-; RV64ZVE32F-NEXT: .LBB9_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB9_8
; RV64ZVE32F-NEXT: .LBB9_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB9_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB9_9
; RV64ZVE32F-NEXT: .LBB9_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -991,17 +1002,50 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB18_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_11
+; RV64ZVE32F-NEXT: .LBB18_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_12
+; RV64ZVE32F-NEXT: .LBB18_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB18_5
+; RV64ZVE32F-NEXT: .LBB18_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB18_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_14
+; RV64ZVE32F-NEXT: .LBB18_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_15
+; RV64ZVE32F-NEXT: .LBB18_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB18_16
+; RV64ZVE32F-NEXT: .LBB18_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB18_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB18_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB18_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB18_2
+; RV64ZVE32F-NEXT: .LBB18_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1010,36 +1054,21 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB18_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB18_3
+; RV64ZVE32F-NEXT: .LBB18_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB18_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB18_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB18_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB18_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB18_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB18_4
+; RV64ZVE32F-NEXT: j .LBB18_5
+; RV64ZVE32F-NEXT: .LBB18_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
@@ -1047,10 +1076,9 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB18_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB18_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB18_7
+; RV64ZVE32F-NEXT: .LBB18_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1059,28 +1087,22 @@ define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB18_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB18_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB18_16
-; RV64ZVE32F-NEXT: .LBB18_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB18_8
; RV64ZVE32F-NEXT: .LBB18_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB18_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB18_9
; RV64ZVE32F-NEXT: .LBB18_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -1117,17 +1139,50 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB19_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_11
+; RV64ZVE32F-NEXT: .LBB19_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_12
+; RV64ZVE32F-NEXT: .LBB19_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB19_5
+; RV64ZVE32F-NEXT: .LBB19_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB19_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_14
+; RV64ZVE32F-NEXT: .LBB19_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_15
+; RV64ZVE32F-NEXT: .LBB19_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB19_16
+; RV64ZVE32F-NEXT: .LBB19_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB19_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB19_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB19_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB19_2
+; RV64ZVE32F-NEXT: .LBB19_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1136,36 +1191,21 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB19_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB19_3
+; RV64ZVE32F-NEXT: .LBB19_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB19_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB19_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB19_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB19_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB19_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB19_4
+; RV64ZVE32F-NEXT: j .LBB19_5
+; RV64ZVE32F-NEXT: .LBB19_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
@@ -1173,10 +1213,9 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB19_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB19_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB19_7
+; RV64ZVE32F-NEXT: .LBB19_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1185,28 +1224,22 @@ define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB19_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB19_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB19_16
-; RV64ZVE32F-NEXT: .LBB19_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB19_8
; RV64ZVE32F-NEXT: .LBB19_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB19_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB19_9
; RV64ZVE32F-NEXT: .LBB19_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -1242,18 +1275,52 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB20_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_11
+; RV64ZVE32F-NEXT: .LBB20_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_12
+; RV64ZVE32F-NEXT: .LBB20_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB20_5
+; RV64ZVE32F-NEXT: .LBB20_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB20_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_14
+; RV64ZVE32F-NEXT: .LBB20_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_15
+; RV64ZVE32F-NEXT: .LBB20_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB20_16
+; RV64ZVE32F-NEXT: .LBB20_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB20_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB20_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB20_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB20_2
+; RV64ZVE32F-NEXT: .LBB20_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1263,38 +1330,22 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB20_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB20_3
+; RV64ZVE32F-NEXT: .LBB20_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB20_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB20_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB20_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB20_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB20_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB20_4
+; RV64ZVE32F-NEXT: j .LBB20_5
+; RV64ZVE32F-NEXT: .LBB20_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
@@ -1303,10 +1354,9 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB20_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB20_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB20_7
+; RV64ZVE32F-NEXT: .LBB20_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1316,18 +1366,12 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB20_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB20_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB20_16
-; RV64ZVE32F-NEXT: .LBB20_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB20_8
; RV64ZVE32F-NEXT: .LBB20_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: zext.b a2, a2
@@ -1335,10 +1379,10 @@ define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB20_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB20_9
; RV64ZVE32F-NEXT: .LBB20_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -1375,17 +1419,50 @@ define void @mscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB21_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_11
+; RV64ZVE32F-NEXT: .LBB21_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_12
+; RV64ZVE32F-NEXT: .LBB21_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB21_5
+; RV64ZVE32F-NEXT: .LBB21_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB21_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_14
+; RV64ZVE32F-NEXT: .LBB21_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_15
+; RV64ZVE32F-NEXT: .LBB21_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB21_16
+; RV64ZVE32F-NEXT: .LBB21_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB21_10: # %cond.store
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB21_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB21_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB21_2
+; RV64ZVE32F-NEXT: .LBB21_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1394,46 +1471,30 @@ define void @mscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB21_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB21_3
+; RV64ZVE32F-NEXT: .LBB21_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB21_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB21_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB21_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB21_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB21_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB21_4
+; RV64ZVE32F-NEXT: j .LBB21_5
+; RV64ZVE32F-NEXT: .LBB21_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB21_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB21_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB21_7
+; RV64ZVE32F-NEXT: .LBB21_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -1442,28 +1503,22 @@ define void @mscatter_baseidx_v8i16(<8 x i16> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB21_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB21_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB21_16
-; RV64ZVE32F-NEXT: .LBB21_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB21_8
; RV64ZVE32F-NEXT: .LBB21_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB21_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB21_9
; RV64ZVE32F-NEXT: .LBB21_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -1834,17 +1889,50 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB29_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB29_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB29_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_11
+; RV64ZVE32F-NEXT: .LBB29_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_12
+; RV64ZVE32F-NEXT: .LBB29_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB29_5
+; RV64ZVE32F-NEXT: .LBB29_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB29_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_14
+; RV64ZVE32F-NEXT: .LBB29_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_15
+; RV64ZVE32F-NEXT: .LBB29_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB29_16
+; RV64ZVE32F-NEXT: .LBB29_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB29_10: # %cond.store
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vse32.v v8, (a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB29_2
+; RV64ZVE32F-NEXT: .LBB29_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -1853,37 +1941,22 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB29_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB29_3
+; RV64ZVE32F-NEXT: .LBB29_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB29_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB29_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB29_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB29_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB29_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB29_4
+; RV64ZVE32F-NEXT: j .LBB29_5
+; RV64ZVE32F-NEXT: .LBB29_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -1891,10 +1964,9 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB29_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB29_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB29_7
+; RV64ZVE32F-NEXT: .LBB29_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -1904,18 +1976,12 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB29_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB29_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB29_16
-; RV64ZVE32F-NEXT: .LBB29_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB29_8
; RV64ZVE32F-NEXT: .LBB29_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -1923,10 +1989,10 @@ define void @mscatter_baseidx_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB29_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB29_9
; RV64ZVE32F-NEXT: .LBB29_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -1963,17 +2029,50 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB30_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_11
+; RV64ZVE32F-NEXT: .LBB30_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_12
+; RV64ZVE32F-NEXT: .LBB30_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB30_5
+; RV64ZVE32F-NEXT: .LBB30_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB30_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_14
+; RV64ZVE32F-NEXT: .LBB30_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_15
+; RV64ZVE32F-NEXT: .LBB30_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB30_16
+; RV64ZVE32F-NEXT: .LBB30_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB30_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB30_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB30_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB30_2
+; RV64ZVE32F-NEXT: .LBB30_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -1982,37 +2081,22 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB30_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB30_3
+; RV64ZVE32F-NEXT: .LBB30_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB30_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB30_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB30_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB30_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB30_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB30_4
+; RV64ZVE32F-NEXT: j .LBB30_5
+; RV64ZVE32F-NEXT: .LBB30_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -2020,10 +2104,9 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB30_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB30_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB30_7
+; RV64ZVE32F-NEXT: .LBB30_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2033,18 +2116,12 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB30_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB30_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB30_16
-; RV64ZVE32F-NEXT: .LBB30_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB30_8
; RV64ZVE32F-NEXT: .LBB30_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -2052,10 +2129,10 @@ define void @mscatter_baseidx_sext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB30_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB30_9
; RV64ZVE32F-NEXT: .LBB30_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -2094,18 +2171,52 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB31_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_11
+; RV64ZVE32F-NEXT: .LBB31_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_12
+; RV64ZVE32F-NEXT: .LBB31_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB31_5
+; RV64ZVE32F-NEXT: .LBB31_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB31_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_14
+; RV64ZVE32F-NEXT: .LBB31_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_15
+; RV64ZVE32F-NEXT: .LBB31_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB31_16
+; RV64ZVE32F-NEXT: .LBB31_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB31_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB31_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB31_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB31_2
+; RV64ZVE32F-NEXT: .LBB31_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2115,39 +2226,23 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB31_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB31_3
+; RV64ZVE32F-NEXT: .LBB31_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB31_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB31_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB31_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB31_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB31_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB31_4
+; RV64ZVE32F-NEXT: j .LBB31_5
+; RV64ZVE32F-NEXT: .LBB31_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -2156,10 +2251,9 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB31_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB31_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB31_7
+; RV64ZVE32F-NEXT: .LBB31_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2170,18 +2264,12 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB31_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB31_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB31_16
-; RV64ZVE32F-NEXT: .LBB31_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB31_8
; RV64ZVE32F-NEXT: .LBB31_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: zext.b a2, a2
@@ -2190,10 +2278,10 @@ define void @mscatter_baseidx_zext_v8i8_v8i32(<8 x i32> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB31_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB31_9
; RV64ZVE32F-NEXT: .LBB31_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -2233,18 +2321,51 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB32_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_11
+; RV64ZVE32F-NEXT: .LBB32_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_12
+; RV64ZVE32F-NEXT: .LBB32_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB32_5
+; RV64ZVE32F-NEXT: .LBB32_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB32_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_14
+; RV64ZVE32F-NEXT: .LBB32_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_15
+; RV64ZVE32F-NEXT: .LBB32_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB32_16
+; RV64ZVE32F-NEXT: .LBB32_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB32_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB32_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB32_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB32_2
+; RV64ZVE32F-NEXT: .LBB32_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2253,37 +2374,22 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB32_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB32_3
+; RV64ZVE32F-NEXT: .LBB32_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB32_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB32_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB32_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB32_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB32_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB32_4
+; RV64ZVE32F-NEXT: j .LBB32_5
+; RV64ZVE32F-NEXT: .LBB32_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -2291,10 +2397,9 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB32_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB32_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB32_7
+; RV64ZVE32F-NEXT: .LBB32_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2304,18 +2409,12 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB32_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB32_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB32_16
-; RV64ZVE32F-NEXT: .LBB32_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB32_8
; RV64ZVE32F-NEXT: .LBB32_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -2323,10 +2422,10 @@ define void @mscatter_baseidx_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB32_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB32_9
; RV64ZVE32F-NEXT: .LBB32_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -2364,18 +2463,51 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB33_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_11
+; RV64ZVE32F-NEXT: .LBB33_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_12
+; RV64ZVE32F-NEXT: .LBB33_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB33_5
+; RV64ZVE32F-NEXT: .LBB33_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB33_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_14
+; RV64ZVE32F-NEXT: .LBB33_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_15
+; RV64ZVE32F-NEXT: .LBB33_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB33_16
+; RV64ZVE32F-NEXT: .LBB33_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB33_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB33_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB33_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB33_2
+; RV64ZVE32F-NEXT: .LBB33_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2384,37 +2516,22 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB33_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB33_3
+; RV64ZVE32F-NEXT: .LBB33_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB33_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB33_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB33_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB33_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB33_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB33_4
+; RV64ZVE32F-NEXT: j .LBB33_5
+; RV64ZVE32F-NEXT: .LBB33_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -2422,10 +2539,9 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB33_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB33_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB33_7
+; RV64ZVE32F-NEXT: .LBB33_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2435,18 +2551,12 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB33_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB33_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB33_16
-; RV64ZVE32F-NEXT: .LBB33_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB33_8
; RV64ZVE32F-NEXT: .LBB33_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -2454,10 +2564,10 @@ define void @mscatter_baseidx_sext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB33_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB33_9
; RV64ZVE32F-NEXT: .LBB33_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -2496,19 +2606,53 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB34_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_11
+; RV64ZVE32F-NEXT: .LBB34_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_12
+; RV64ZVE32F-NEXT: .LBB34_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB34_5
+; RV64ZVE32F-NEXT: .LBB34_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 46
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB34_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_14
+; RV64ZVE32F-NEXT: .LBB34_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_15
+; RV64ZVE32F-NEXT: .LBB34_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB34_16
+; RV64ZVE32F-NEXT: .LBB34_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB34_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB34_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB34_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB34_2
+; RV64ZVE32F-NEXT: .LBB34_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2518,39 +2662,23 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB34_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB34_3
+; RV64ZVE32F-NEXT: .LBB34_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB34_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB34_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB34_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 46
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB34_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB34_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB34_4
+; RV64ZVE32F-NEXT: j .LBB34_5
+; RV64ZVE32F-NEXT: .LBB34_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -2559,10 +2687,9 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB34_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB34_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB34_7
+; RV64ZVE32F-NEXT: .LBB34_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -2573,18 +2700,12 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB34_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB34_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB34_16
-; RV64ZVE32F-NEXT: .LBB34_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB34_8
; RV64ZVE32F-NEXT: .LBB34_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 48
@@ -2593,10 +2714,10 @@ define void @mscatter_baseidx_zext_v8i16_v8i32(<8 x i32> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB34_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB34_9
; RV64ZVE32F-NEXT: .LBB34_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -2633,17 +2754,50 @@ define void @mscatter_baseidx_v8i32(<8 x i32> %val, ptr %base, <8 x i32> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_11
+; RV64ZVE32F-NEXT: .LBB35_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_4
+; RV64ZVE32F-NEXT: .LBB35_3: # %cond.store3
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vse32.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB35_4: # %else4
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_13
+; RV64ZVE32F-NEXT: .LBB35_6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_14
+; RV64ZVE32F-NEXT: .LBB35_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_15
+; RV64ZVE32F-NEXT: .LBB35_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB35_16
+; RV64ZVE32F-NEXT: .LBB35_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB35_10: # %cond.store
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB35_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_2
+; RV64ZVE32F-NEXT: .LBB35_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
@@ -2651,83 +2805,56 @@ define void @mscatter_baseidx_v8i32(<8 x i32> %val, ptr %base, <8 x i32> %idxs,
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB35_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB35_3
+; RV64ZVE32F-NEXT: j .LBB35_4
+; RV64ZVE32F-NEXT: .LBB35_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB35_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-NEXT: .LBB35_13: # %cond.store7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB35_6: # %else4
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB35_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB35_14
-; RV64ZVE32F-NEXT: .LBB35_8: # %else8
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB35_10
-; RV64ZVE32F-NEXT: .LBB35_9: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB35_7
+; RV64ZVE32F-NEXT: .LBB35_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v12, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 5
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB35_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB35_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB35_16
-; RV64ZVE32F-NEXT: .LBB35_12: # %else14
-; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB35_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB35_8
-; RV64ZVE32F-NEXT: .LBB35_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB35_9
-; RV64ZVE32F-NEXT: j .LBB35_10
; RV64ZVE32F-NEXT: .LBB35_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v12, 2
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB35_12
+; RV64ZVE32F-NEXT: beqz a1, .LBB35_9
; RV64ZVE32F-NEXT: .LBB35_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v12, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -3422,81 +3549,94 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB42_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez t2, .LBB42_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_11
+; RV64ZVE32F-NEXT: .LBB42_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_12
+; RV64ZVE32F-NEXT: .LBB42_3: # %else4
+; RV64ZVE32F-NEXT: andi a0, a3, 8
+; RV64ZVE32F-NEXT: beqz a0, .LBB42_5
+; RV64ZVE32F-NEXT: .LBB42_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a7, 0(a0)
+; RV64ZVE32F-NEXT: .LBB42_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a0, a3, 16
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a0, a3, 32
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_14
+; RV64ZVE32F-NEXT: .LBB42_7: # %else10
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_15
+; RV64ZVE32F-NEXT: .LBB42_8: # %else12
+; RV64ZVE32F-NEXT: andi a0, a3, -128
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_16
+; RV64ZVE32F-NEXT: .LBB42_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB42_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB42_2: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
-; RV64ZVE32F-NEXT: beqz a0, .LBB42_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a0, .LBB42_2
+; RV64ZVE32F-NEXT: .LBB42_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB42_4: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: beqz a0, .LBB42_3
+; RV64ZVE32F-NEXT: .LBB42_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB42_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB42_6: # %else4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: beqz a0, .LBB42_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a7, 0(a0)
-; RV64ZVE32F-NEXT: .LBB42_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB42_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a0, .LBB42_4
+; RV64ZVE32F-NEXT: j .LBB42_5
+; RV64ZVE32F-NEXT: .LBB42_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
-; RV64ZVE32F-NEXT: .LBB42_10: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB42_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a0, .LBB42_7
+; RV64ZVE32F-NEXT: .LBB42_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB42_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a0, a3, 64
-; RV64ZVE32F-NEXT: bnez a0, .LBB42_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: bnez a0, .LBB42_16
-; RV64ZVE32F-NEXT: .LBB42_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a0, .LBB42_8
; RV64ZVE32F-NEXT: .LBB42_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB42_14
+; RV64ZVE32F-NEXT: beqz a0, .LBB42_9
; RV64ZVE32F-NEXT: .LBB42_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -3666,81 +3806,94 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB43_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez t2, .LBB43_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_11
+; RV64ZVE32F-NEXT: .LBB43_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_12
+; RV64ZVE32F-NEXT: .LBB43_3: # %else4
+; RV64ZVE32F-NEXT: andi a0, a3, 8
+; RV64ZVE32F-NEXT: beqz a0, .LBB43_5
+; RV64ZVE32F-NEXT: .LBB43_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a7, 0(a0)
+; RV64ZVE32F-NEXT: .LBB43_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a0, a3, 16
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a0, a3, 32
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_14
+; RV64ZVE32F-NEXT: .LBB43_7: # %else10
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_15
+; RV64ZVE32F-NEXT: .LBB43_8: # %else12
+; RV64ZVE32F-NEXT: andi a0, a3, -128
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_16
+; RV64ZVE32F-NEXT: .LBB43_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB43_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB43_2: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
-; RV64ZVE32F-NEXT: beqz a0, .LBB43_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a0, .LBB43_2
+; RV64ZVE32F-NEXT: .LBB43_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB43_4: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: beqz a0, .LBB43_3
+; RV64ZVE32F-NEXT: .LBB43_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB43_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB43_6: # %else4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: beqz a0, .LBB43_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a7, 0(a0)
-; RV64ZVE32F-NEXT: .LBB43_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB43_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a0, .LBB43_4
+; RV64ZVE32F-NEXT: j .LBB43_5
+; RV64ZVE32F-NEXT: .LBB43_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
-; RV64ZVE32F-NEXT: .LBB43_10: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB43_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a0, .LBB43_7
+; RV64ZVE32F-NEXT: .LBB43_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB43_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a0, a3, 64
-; RV64ZVE32F-NEXT: bnez a0, .LBB43_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: bnez a0, .LBB43_16
-; RV64ZVE32F-NEXT: .LBB43_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a0, .LBB43_8
; RV64ZVE32F-NEXT: .LBB43_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB43_14
+; RV64ZVE32F-NEXT: beqz a0, .LBB43_9
; RV64ZVE32F-NEXT: .LBB43_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -3912,18 +4065,50 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB44_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez t2, .LBB44_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_11
+; RV64ZVE32F-NEXT: .LBB44_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_12
+; RV64ZVE32F-NEXT: .LBB44_3: # %else4
+; RV64ZVE32F-NEXT: andi a0, a3, 8
+; RV64ZVE32F-NEXT: beqz a0, .LBB44_5
+; RV64ZVE32F-NEXT: .LBB44_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: zext.b a0, a0
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a7, 0(a0)
+; RV64ZVE32F-NEXT: .LBB44_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a0, a3, 16
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a0, a3, 32
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_14
+; RV64ZVE32F-NEXT: .LBB44_7: # %else10
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_15
+; RV64ZVE32F-NEXT: .LBB44_8: # %else12
+; RV64ZVE32F-NEXT: andi a0, a3, -128
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_16
+; RV64ZVE32F-NEXT: .LBB44_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB44_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: zext.b t2, t2
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB44_2: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
-; RV64ZVE32F-NEXT: beqz a0, .LBB44_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a0, .LBB44_2
+; RV64ZVE32F-NEXT: .LBB44_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
@@ -3931,42 +4116,28 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB44_4: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: beqz a0, .LBB44_3
+; RV64ZVE32F-NEXT: .LBB44_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB44_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: zext.b a0, a0
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB44_6: # %else4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: beqz a0, .LBB44_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: zext.b a0, a0
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a7, 0(a0)
-; RV64ZVE32F-NEXT: .LBB44_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB44_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a0, .LBB44_4
+; RV64ZVE32F-NEXT: j .LBB44_5
+; RV64ZVE32F-NEXT: .LBB44_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: zext.b a0, a0
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
-; RV64ZVE32F-NEXT: .LBB44_10: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB44_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a0, .LBB44_7
+; RV64ZVE32F-NEXT: .LBB44_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
@@ -3974,27 +4145,22 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB44_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a0, a3, 64
-; RV64ZVE32F-NEXT: bnez a0, .LBB44_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: bnez a0, .LBB44_16
-; RV64ZVE32F-NEXT: .LBB44_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a0, .LBB44_8
; RV64ZVE32F-NEXT: .LBB44_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: zext.b a0, a0
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB44_14
+; RV64ZVE32F-NEXT: beqz a0, .LBB44_9
; RV64ZVE32F-NEXT: .LBB44_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: zext.b a0, a0
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -4167,82 +4333,95 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB45_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez t2, .LBB45_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_11
+; RV64ZVE32F-NEXT: .LBB45_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_12
+; RV64ZVE32F-NEXT: .LBB45_3: # %else4
+; RV64ZVE32F-NEXT: andi a0, a3, 8
+; RV64ZVE32F-NEXT: beqz a0, .LBB45_5
+; RV64ZVE32F-NEXT: .LBB45_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a7, 0(a0)
+; RV64ZVE32F-NEXT: .LBB45_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a0, a3, 16
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a0, a3, 32
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_14
+; RV64ZVE32F-NEXT: .LBB45_7: # %else10
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_15
+; RV64ZVE32F-NEXT: .LBB45_8: # %else12
+; RV64ZVE32F-NEXT: andi a0, a3, -128
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_16
+; RV64ZVE32F-NEXT: .LBB45_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB45_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB45_2: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
-; RV64ZVE32F-NEXT: beqz a0, .LBB45_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a0, .LBB45_2
+; RV64ZVE32F-NEXT: .LBB45_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB45_4: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: beqz a0, .LBB45_3
+; RV64ZVE32F-NEXT: .LBB45_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB45_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB45_6: # %else4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: beqz a0, .LBB45_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a7, 0(a0)
-; RV64ZVE32F-NEXT: .LBB45_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB45_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a0, .LBB45_4
+; RV64ZVE32F-NEXT: j .LBB45_5
+; RV64ZVE32F-NEXT: .LBB45_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
-; RV64ZVE32F-NEXT: .LBB45_10: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB45_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a0, .LBB45_7
+; RV64ZVE32F-NEXT: .LBB45_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB45_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a0, a3, 64
-; RV64ZVE32F-NEXT: bnez a0, .LBB45_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: bnez a0, .LBB45_16
-; RV64ZVE32F-NEXT: .LBB45_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a0, .LBB45_8
; RV64ZVE32F-NEXT: .LBB45_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB45_14
+; RV64ZVE32F-NEXT: beqz a0, .LBB45_9
; RV64ZVE32F-NEXT: .LBB45_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -4414,82 +4593,95 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB46_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez t2, .LBB46_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_11
+; RV64ZVE32F-NEXT: .LBB46_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_12
+; RV64ZVE32F-NEXT: .LBB46_3: # %else4
+; RV64ZVE32F-NEXT: andi a0, a3, 8
+; RV64ZVE32F-NEXT: beqz a0, .LBB46_5
+; RV64ZVE32F-NEXT: .LBB46_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a7, 0(a0)
+; RV64ZVE32F-NEXT: .LBB46_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a0, a3, 16
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a0, a3, 32
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_14
+; RV64ZVE32F-NEXT: .LBB46_7: # %else10
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_15
+; RV64ZVE32F-NEXT: .LBB46_8: # %else12
+; RV64ZVE32F-NEXT: andi a0, a3, -128
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_16
+; RV64ZVE32F-NEXT: .LBB46_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB46_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB46_2: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
-; RV64ZVE32F-NEXT: beqz a0, .LBB46_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a0, .LBB46_2
+; RV64ZVE32F-NEXT: .LBB46_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB46_4: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: beqz a0, .LBB46_3
+; RV64ZVE32F-NEXT: .LBB46_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB46_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB46_6: # %else4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: beqz a0, .LBB46_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a7, 0(a0)
-; RV64ZVE32F-NEXT: .LBB46_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB46_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a0, .LBB46_4
+; RV64ZVE32F-NEXT: j .LBB46_5
+; RV64ZVE32F-NEXT: .LBB46_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
-; RV64ZVE32F-NEXT: .LBB46_10: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB46_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a0, .LBB46_7
+; RV64ZVE32F-NEXT: .LBB46_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB46_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a0, a3, 64
-; RV64ZVE32F-NEXT: bnez a0, .LBB46_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: bnez a0, .LBB46_16
-; RV64ZVE32F-NEXT: .LBB46_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a0, .LBB46_8
; RV64ZVE32F-NEXT: .LBB46_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB46_14
+; RV64ZVE32F-NEXT: beqz a0, .LBB46_9
; RV64ZVE32F-NEXT: .LBB46_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -4663,8 +4855,41 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB47_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez t2, .LBB47_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_11
+; RV64ZVE32F-NEXT: .LBB47_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_12
+; RV64ZVE32F-NEXT: .LBB47_3: # %else4
+; RV64ZVE32F-NEXT: andi a0, a3, 8
+; RV64ZVE32F-NEXT: beqz a0, .LBB47_5
+; RV64ZVE32F-NEXT: .LBB47_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: slli a0, a0, 48
+; RV64ZVE32F-NEXT: srli a0, a0, 45
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a7, 0(a0)
+; RV64ZVE32F-NEXT: .LBB47_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a0, a3, 16
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a0, a3, 32
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_14
+; RV64ZVE32F-NEXT: .LBB47_7: # %else10
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_15
+; RV64ZVE32F-NEXT: .LBB47_8: # %else12
+; RV64ZVE32F-NEXT: andi a0, a3, -128
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_16
+; RV64ZVE32F-NEXT: .LBB47_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB47_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t2, v8
; RV64ZVE32F-NEXT: ld a0, 0(a0)
@@ -4672,10 +4897,9 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: srli t2, t2, 45
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB47_2: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
-; RV64ZVE32F-NEXT: beqz a0, .LBB47_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a0, .LBB47_2
+; RV64ZVE32F-NEXT: .LBB47_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
@@ -4683,42 +4907,28 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: srli a0, a0, 45
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB47_4: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: beqz a0, .LBB47_3
+; RV64ZVE32F-NEXT: .LBB47_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB47_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 48
; RV64ZVE32F-NEXT: srli a0, a0, 45
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB47_6: # %else4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: beqz a0, .LBB47_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 48
-; RV64ZVE32F-NEXT: srli a0, a0, 45
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a7, 0(a0)
-; RV64ZVE32F-NEXT: .LBB47_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB47_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a0, .LBB47_4
+; RV64ZVE32F-NEXT: j .LBB47_5
+; RV64ZVE32F-NEXT: .LBB47_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 48
; RV64ZVE32F-NEXT: srli a0, a0, 45
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
-; RV64ZVE32F-NEXT: .LBB47_10: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB47_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a0, .LBB47_7
+; RV64ZVE32F-NEXT: .LBB47_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
@@ -4726,26 +4936,21 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: srli a0, a0, 45
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB47_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a0, a3, 64
-; RV64ZVE32F-NEXT: bnez a0, .LBB47_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: bnez a0, .LBB47_16
-; RV64ZVE32F-NEXT: .LBB47_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a0, .LBB47_8
; RV64ZVE32F-NEXT: .LBB47_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 48
; RV64ZVE32F-NEXT: srli a0, a0, 45
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB47_14
+; RV64ZVE32F-NEXT: beqz a0, .LBB47_9
; RV64ZVE32F-NEXT: .LBB47_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 48
; RV64ZVE32F-NEXT: srli a0, a0, 45
@@ -4916,89 +5121,96 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB48_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
-; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: slli t2, t2, 3
-; RV64ZVE32F-NEXT: add t2, a1, t2
-; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB48_2: # %else
+; RV64ZVE32F-NEXT: bnez t2, .LBB48_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB48_11
+; RV64ZVE32F-NEXT: .LBB48_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
; RV64ZVE32F-NEXT: beqz a0, .LBB48_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v10
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB48_4: # %else2
+; RV64ZVE32F-NEXT: .LBB48_3: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB48_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB48_6: # %else4
+; RV64ZVE32F-NEXT: .LBB48_4: # %else4
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: bnez a0, .LBB48_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
+; RV64ZVE32F-NEXT: bnez a0, .LBB48_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: bnez a0, .LBB48_14
-; RV64ZVE32F-NEXT: .LBB48_8: # %else8
+; RV64ZVE32F-NEXT: bnez a0, .LBB48_13
+; RV64ZVE32F-NEXT: .LBB48_6: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB48_10
-; RV64ZVE32F-NEXT: .LBB48_9: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB48_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB48_14
+; RV64ZVE32F-NEXT: .LBB48_7: # %else10
; RV64ZVE32F-NEXT: andi a0, a3, 64
; RV64ZVE32F-NEXT: bnez a0, .LBB48_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
+; RV64ZVE32F-NEXT: .LBB48_8: # %else12
; RV64ZVE32F-NEXT: andi a0, a3, -128
; RV64ZVE32F-NEXT: bnez a0, .LBB48_16
-; RV64ZVE32F-NEXT: .LBB48_12: # %else14
+; RV64ZVE32F-NEXT: .LBB48_9: # %else14
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB48_13: # %cond.store5
+; RV64ZVE32F-NEXT: .LBB48_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: ld a0, 0(a0)
+; RV64ZVE32F-NEXT: slli t2, t2, 3
+; RV64ZVE32F-NEXT: add t2, a1, t2
+; RV64ZVE32F-NEXT: sd a0, 0(t2)
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: beqz a0, .LBB48_2
+; RV64ZVE32F-NEXT: .LBB48_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a0, v10
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd t1, 0(a0)
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB48_3
+; RV64ZVE32F-NEXT: j .LBB48_4
+; RV64ZVE32F-NEXT: .LBB48_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a7, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB48_8
-; RV64ZVE32F-NEXT: .LBB48_14: # %cond.store7
+; RV64ZVE32F-NEXT: beqz a0, .LBB48_6
+; RV64ZVE32F-NEXT: .LBB48_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: bnez a0, .LBB48_9
-; RV64ZVE32F-NEXT: j .LBB48_10
+; RV64ZVE32F-NEXT: beqz a0, .LBB48_7
+; RV64ZVE32F-NEXT: .LBB48_14: # %cond.store9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a5, 0(a0)
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: beqz a0, .LBB48_8
; RV64ZVE32F-NEXT: .LBB48_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB48_12
+; RV64ZVE32F-NEXT: beqz a0, .LBB48_9
; RV64ZVE32F-NEXT: .LBB48_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -5167,89 +5379,96 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB49_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
-; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: slli t2, t2, 3
-; RV64ZVE32F-NEXT: add t2, a1, t2
-; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB49_2: # %else
+; RV64ZVE32F-NEXT: bnez t2, .LBB49_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB49_11
+; RV64ZVE32F-NEXT: .LBB49_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
; RV64ZVE32F-NEXT: beqz a0, .LBB49_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v10
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB49_4: # %else2
+; RV64ZVE32F-NEXT: .LBB49_3: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB49_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB49_6: # %else4
+; RV64ZVE32F-NEXT: .LBB49_4: # %else4
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: bnez a0, .LBB49_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
+; RV64ZVE32F-NEXT: bnez a0, .LBB49_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: bnez a0, .LBB49_14
-; RV64ZVE32F-NEXT: .LBB49_8: # %else8
+; RV64ZVE32F-NEXT: bnez a0, .LBB49_13
+; RV64ZVE32F-NEXT: .LBB49_6: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB49_10
-; RV64ZVE32F-NEXT: .LBB49_9: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 3
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB49_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB49_14
+; RV64ZVE32F-NEXT: .LBB49_7: # %else10
; RV64ZVE32F-NEXT: andi a0, a3, 64
; RV64ZVE32F-NEXT: bnez a0, .LBB49_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
+; RV64ZVE32F-NEXT: .LBB49_8: # %else12
; RV64ZVE32F-NEXT: andi a0, a3, -128
; RV64ZVE32F-NEXT: bnez a0, .LBB49_16
-; RV64ZVE32F-NEXT: .LBB49_12: # %else14
+; RV64ZVE32F-NEXT: .LBB49_9: # %else14
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB49_13: # %cond.store5
+; RV64ZVE32F-NEXT: .LBB49_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: ld a0, 0(a0)
+; RV64ZVE32F-NEXT: slli t2, t2, 3
+; RV64ZVE32F-NEXT: add t2, a1, t2
+; RV64ZVE32F-NEXT: sd a0, 0(t2)
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: beqz a0, .LBB49_2
+; RV64ZVE32F-NEXT: .LBB49_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a0, v10
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd t1, 0(a0)
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB49_3
+; RV64ZVE32F-NEXT: j .LBB49_4
+; RV64ZVE32F-NEXT: .LBB49_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a7, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB49_8
-; RV64ZVE32F-NEXT: .LBB49_14: # %cond.store7
+; RV64ZVE32F-NEXT: beqz a0, .LBB49_6
+; RV64ZVE32F-NEXT: .LBB49_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: bnez a0, .LBB49_9
-; RV64ZVE32F-NEXT: j .LBB49_10
+; RV64ZVE32F-NEXT: beqz a0, .LBB49_7
+; RV64ZVE32F-NEXT: .LBB49_14: # %cond.store9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: slli a0, a0, 3
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a5, 0(a0)
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: beqz a0, .LBB49_8
; RV64ZVE32F-NEXT: .LBB49_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB49_12
+; RV64ZVE32F-NEXT: beqz a0, .LBB49_9
; RV64ZVE32F-NEXT: .LBB49_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -5419,96 +5638,103 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: ld a7, 24(a0)
; RV64ZVE32F-NEXT: ld a6, 32(a0)
; RV64ZVE32F-NEXT: andi t2, a3, 1
-; RV64ZVE32F-NEXT: beqz t2, .LBB50_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s t2, v8
-; RV64ZVE32F-NEXT: ld a0, 0(a0)
-; RV64ZVE32F-NEXT: slli t2, t2, 32
-; RV64ZVE32F-NEXT: srli t2, t2, 29
-; RV64ZVE32F-NEXT: add t2, a1, t2
-; RV64ZVE32F-NEXT: sd a0, 0(t2)
-; RV64ZVE32F-NEXT: .LBB50_2: # %else
+; RV64ZVE32F-NEXT: bnez t2, .LBB50_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB50_11
+; RV64ZVE32F-NEXT: .LBB50_2: # %else2
+; RV64ZVE32F-NEXT: andi a0, a3, 4
; RV64ZVE32F-NEXT: beqz a0, .LBB50_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v10
-; RV64ZVE32F-NEXT: slli a0, a0, 32
-; RV64ZVE32F-NEXT: srli a0, a0, 29
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd t1, 0(a0)
-; RV64ZVE32F-NEXT: .LBB50_4: # %else2
+; RV64ZVE32F-NEXT: .LBB50_3: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a0, a3, 4
-; RV64ZVE32F-NEXT: beqz a0, .LBB50_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 29
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd t0, 0(a0)
-; RV64ZVE32F-NEXT: .LBB50_6: # %else4
+; RV64ZVE32F-NEXT: .LBB50_4: # %else4
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a0, a3, 8
-; RV64ZVE32F-NEXT: bnez a0, .LBB50_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
+; RV64ZVE32F-NEXT: bnez a0, .LBB50_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: bnez a0, .LBB50_14
-; RV64ZVE32F-NEXT: .LBB50_8: # %else8
+; RV64ZVE32F-NEXT: bnez a0, .LBB50_13
+; RV64ZVE32F-NEXT: .LBB50_6: # %else8
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: beqz a0, .LBB50_10
-; RV64ZVE32F-NEXT: .LBB50_9: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
-; RV64ZVE32F-NEXT: slli a0, a0, 32
-; RV64ZVE32F-NEXT: srli a0, a0, 29
-; RV64ZVE32F-NEXT: add a0, a1, a0
-; RV64ZVE32F-NEXT: sd a5, 0(a0)
-; RV64ZVE32F-NEXT: .LBB50_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a0, .LBB50_14
+; RV64ZVE32F-NEXT: .LBB50_7: # %else10
; RV64ZVE32F-NEXT: andi a0, a3, 64
; RV64ZVE32F-NEXT: bnez a0, .LBB50_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
+; RV64ZVE32F-NEXT: .LBB50_8: # %else12
; RV64ZVE32F-NEXT: andi a0, a3, -128
; RV64ZVE32F-NEXT: bnez a0, .LBB50_16
-; RV64ZVE32F-NEXT: .LBB50_12: # %else14
+; RV64ZVE32F-NEXT: .LBB50_9: # %else14
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB50_13: # %cond.store5
+; RV64ZVE32F-NEXT: .LBB50_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s t2, v8
+; RV64ZVE32F-NEXT: ld a0, 0(a0)
+; RV64ZVE32F-NEXT: slli t2, t2, 32
+; RV64ZVE32F-NEXT: srli t2, t2, 29
+; RV64ZVE32F-NEXT: add t2, a1, t2
+; RV64ZVE32F-NEXT: sd a0, 0(t2)
+; RV64ZVE32F-NEXT: andi a0, a3, 2
+; RV64ZVE32F-NEXT: beqz a0, .LBB50_2
+; RV64ZVE32F-NEXT: .LBB50_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a0, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a0, v10
+; RV64ZVE32F-NEXT: slli a0, a0, 32
+; RV64ZVE32F-NEXT: srli a0, a0, 29
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd t1, 0(a0)
+; RV64ZVE32F-NEXT: andi a0, a3, 4
+; RV64ZVE32F-NEXT: bnez a0, .LBB50_3
+; RV64ZVE32F-NEXT: j .LBB50_4
+; RV64ZVE32F-NEXT: .LBB50_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 29
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a7, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, 16
-; RV64ZVE32F-NEXT: beqz a0, .LBB50_8
-; RV64ZVE32F-NEXT: .LBB50_14: # %cond.store7
+; RV64ZVE32F-NEXT: beqz a0, .LBB50_6
+; RV64ZVE32F-NEXT: .LBB50_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 29
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a6, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, 32
-; RV64ZVE32F-NEXT: bnez a0, .LBB50_9
-; RV64ZVE32F-NEXT: j .LBB50_10
+; RV64ZVE32F-NEXT: beqz a0, .LBB50_7
+; RV64ZVE32F-NEXT: .LBB50_14: # %cond.store9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a0, v8
+; RV64ZVE32F-NEXT: slli a0, a0, 32
+; RV64ZVE32F-NEXT: srli a0, a0, 29
+; RV64ZVE32F-NEXT: add a0, a1, a0
+; RV64ZVE32F-NEXT: sd a5, 0(a0)
+; RV64ZVE32F-NEXT: andi a0, a3, 64
+; RV64ZVE32F-NEXT: beqz a0, .LBB50_8
; RV64ZVE32F-NEXT: .LBB50_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 29
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a4, 0(a0)
; RV64ZVE32F-NEXT: andi a0, a3, -128
-; RV64ZVE32F-NEXT: beqz a0, .LBB50_12
+; RV64ZVE32F-NEXT: beqz a0, .LBB50_9
; RV64ZVE32F-NEXT: .LBB50_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 29
@@ -6140,8 +6366,44 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB58_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_11
+; RV64ZVE32F-NEXT: .LBB58_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_12
+; RV64ZVE32F-NEXT: .LBB58_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB58_5
+; RV64ZVE32F-NEXT: .LBB58_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-NEXT: slli a3, a3, 1
+; RV64ZVE32F-NEXT: add a3, a0, a3
+; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
+; RV64ZVE32F-NEXT: .LBB58_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_14
+; RV64ZVE32F-NEXT: .LBB58_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_15
+; RV64ZVE32F-NEXT: .LBB58_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB58_16
+; RV64ZVE32F-NEXT: .LBB58_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB58_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
@@ -6150,10 +6412,9 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB58_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB58_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB58_2
+; RV64ZVE32F-NEXT: .LBB58_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6164,41 +6425,23 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB58_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB58_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-NEXT: beqz a2, .LBB58_3
+; RV64ZVE32F-NEXT: .LBB58_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB58_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB58_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-NEXT: slli a3, a3, 1
-; RV64ZVE32F-NEXT: add a3, a0, a3
-; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB58_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB58_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB58_4
+; RV64ZVE32F-NEXT: j .LBB58_5
+; RV64ZVE32F-NEXT: .LBB58_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6208,10 +6451,9 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB58_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB58_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB58_7
+; RV64ZVE32F-NEXT: .LBB58_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6222,34 +6464,27 @@ define void @mscatter_baseidx_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB58_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB58_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB58_16
-; RV64ZVE32F-NEXT: .LBB58_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB58_8
; RV64ZVE32F-NEXT: .LBB58_15: # %cond.store11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB58_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB58_9
; RV64ZVE32F-NEXT: .LBB58_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -6285,8 +6520,44 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB59_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_11
+; RV64ZVE32F-NEXT: .LBB59_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_12
+; RV64ZVE32F-NEXT: .LBB59_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB59_5
+; RV64ZVE32F-NEXT: .LBB59_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-NEXT: slli a3, a3, 1
+; RV64ZVE32F-NEXT: add a3, a0, a3
+; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
+; RV64ZVE32F-NEXT: .LBB59_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_14
+; RV64ZVE32F-NEXT: .LBB59_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_15
+; RV64ZVE32F-NEXT: .LBB59_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB59_16
+; RV64ZVE32F-NEXT: .LBB59_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB59_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
@@ -6295,10 +6566,9 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB59_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB59_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB59_2
+; RV64ZVE32F-NEXT: .LBB59_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6309,41 +6579,23 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB59_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB59_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-NEXT: beqz a2, .LBB59_3
+; RV64ZVE32F-NEXT: .LBB59_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB59_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB59_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-NEXT: slli a3, a3, 1
-; RV64ZVE32F-NEXT: add a3, a0, a3
-; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB59_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB59_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB59_4
+; RV64ZVE32F-NEXT: j .LBB59_5
+; RV64ZVE32F-NEXT: .LBB59_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6353,10 +6605,9 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB59_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB59_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB59_7
+; RV64ZVE32F-NEXT: .LBB59_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6367,34 +6618,27 @@ define void @mscatter_baseidx_sext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB59_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB59_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB59_16
-; RV64ZVE32F-NEXT: .LBB59_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB59_8
; RV64ZVE32F-NEXT: .LBB59_15: # %cond.store11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB59_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB59_9
; RV64ZVE32F-NEXT: .LBB59_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -6429,8 +6673,45 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB60_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_11
+; RV64ZVE32F-NEXT: .LBB60_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_12
+; RV64ZVE32F-NEXT: .LBB60_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB60_5
+; RV64ZVE32F-NEXT: .LBB60_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-NEXT: zext.b a2, a3
+; RV64ZVE32F-NEXT: slli a2, a2, 1
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
+; RV64ZVE32F-NEXT: .LBB60_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_14
+; RV64ZVE32F-NEXT: .LBB60_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_15
+; RV64ZVE32F-NEXT: .LBB60_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB60_16
+; RV64ZVE32F-NEXT: .LBB60_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB60_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
@@ -6440,10 +6721,9 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB60_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB60_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB60_2
+; RV64ZVE32F-NEXT: .LBB60_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6455,43 +6735,24 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB60_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB60_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-NEXT: beqz a2, .LBB60_3
+; RV64ZVE32F-NEXT: .LBB60_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: zext.b a2, a3
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB60_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB60_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-NEXT: zext.b a2, a3
-; RV64ZVE32F-NEXT: slli a2, a2, 1
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB60_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB60_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB60_4
+; RV64ZVE32F-NEXT: j .LBB60_5
+; RV64ZVE32F-NEXT: .LBB60_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6502,10 +6763,9 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB60_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB60_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB60_7
+; RV64ZVE32F-NEXT: .LBB60_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -6517,35 +6777,28 @@ define void @mscatter_baseidx_zext_v8i8_v8bf16(<8 x bfloat> %val, ptr %base, <8
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB60_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB60_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB60_16
-; RV64ZVE32F-NEXT: .LBB60_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB60_8
; RV64ZVE32F-NEXT: .LBB60_15: # %cond.store11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: zext.b a2, a3
; RV64ZVE32F-NEXT: slli a2, a2, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsh fa5, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB60_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB60_9
; RV64ZVE32F-NEXT: .LBB60_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: zext.b a1, a2
@@ -6581,63 +6834,81 @@ define void @mscatter_baseidx_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i16> %id
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB61_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
-; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-NEXT: slli a3, a3, 1
-; RV64ZVE32F-NEXT: add a3, a0, a3
-; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB61_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB61_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_11
+; RV64ZVE32F-NEXT: .LBB61_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_12
+; RV64ZVE32F-NEXT: .LBB61_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB61_5
+; RV64ZVE32F-NEXT: .LBB61_4: # %cond.store5
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB61_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB61_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-NEXT: .LBB61_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_14
+; RV64ZVE32F-NEXT: .LBB61_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_15
+; RV64ZVE32F-NEXT: .LBB61_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB61_16
+; RV64ZVE32F-NEXT: .LBB61_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB61_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-NEXT: slli a3, a3, 1
+; RV64ZVE32F-NEXT: add a3, a0, a3
+; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB61_2
+; RV64ZVE32F-NEXT: .LBB61_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB61_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB61_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB61_3
+; RV64ZVE32F-NEXT: .LBB61_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB61_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB61_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB61_4
+; RV64ZVE32F-NEXT: j .LBB61_5
+; RV64ZVE32F-NEXT: .LBB61_13: # %cond.store7
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vmv.x.s a3, v9
@@ -6645,10 +6916,9 @@ define void @mscatter_baseidx_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i16> %id
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB61_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB61_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB61_7
+; RV64ZVE32F-NEXT: .LBB61_14: # %cond.store9
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -6658,33 +6928,27 @@ define void @mscatter_baseidx_v8bf16(<8 x bfloat> %val, ptr %base, <8 x i16> %id
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-NEXT: .LBB61_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB61_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB61_16
-; RV64ZVE32F-NEXT: .LBB61_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB61_8
; RV64ZVE32F-NEXT: .LBB61_15: # %cond.store11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-NEXT: slli a3, a3, 1
; RV64ZVE32F-NEXT: add a3, a0, a3
; RV64ZVE32F-NEXT: fsh fa5, 0(a3)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB61_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB61_9
; RV64ZVE32F-NEXT: .LBB61_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-NEXT: slli a2, a2, 1
@@ -7212,17 +7476,50 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_10
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_11
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_3: # %else4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_4: # %cond.store5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_5: # %else6
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_13
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_14
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_7: # %else10
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_8: # %else12
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB68_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_9: # %else14
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_10: # %cond.store
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_11: # %cond.store1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7231,36 +7528,21 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_12: # %cond.store3
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_6: # %else4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_8: # %else6
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB68_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_13: # %cond.store7
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
@@ -7268,10 +7550,9 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB68_14: # %cond.store9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7280,28 +7561,22 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_12: # %else10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB68_15
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB68_16
-; RV64ZVE32F-ZVFH-NEXT: .LBB68_14: # %else14
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB68_8
; RV64ZVE32F-ZVFH-NEXT: .LBB68_15: # %cond.store11
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB68_14
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB68_9
; RV64ZVE32F-ZVFH-NEXT: .LBB68_16: # %cond.store13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 7
@@ -7315,8 +7590,44 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_10
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_11
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_3: # %else4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_4: # %cond.store5
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
+; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_5: # %else6
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_13
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_14
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_7: # %else10
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_8: # %else12
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB68_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_9: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_10: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
@@ -7325,10 +7636,9 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_11: # %cond.store1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7339,41 +7649,23 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_4: # %else2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_12: # %cond.store3
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_6: # %else4
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
-; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_8: # %else6
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB68_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_13: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7383,10 +7675,9 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_10: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_14: # %cond.store9
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7397,34 +7688,27 @@ define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i8> %i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_12: # %else10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB68_15
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB68_16
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_14: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB68_8
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_15: # %cond.store11
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB68_14
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB68_9
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB68_16: # %cond.store13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -7460,17 +7744,50 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_10
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_11
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_3: # %else4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_4: # %cond.store5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_5: # %else6
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_13
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_14
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_7: # %else10
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_8: # %else12
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB69_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_9: # %else14
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_10: # %cond.store
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_11: # %cond.store1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7479,36 +7796,21 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_12: # %cond.store3
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_6: # %else4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_8: # %else6
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB69_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_13: # %cond.store7
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
@@ -7516,10 +7818,9 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB69_14: # %cond.store9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7528,28 +7829,22 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_12: # %else10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB69_15
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB69_16
-; RV64ZVE32F-ZVFH-NEXT: .LBB69_14: # %else14
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB69_8
; RV64ZVE32F-ZVFH-NEXT: .LBB69_15: # %cond.store11
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB69_14
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB69_9
; RV64ZVE32F-ZVFH-NEXT: .LBB69_16: # %cond.store13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 7
@@ -7563,8 +7858,44 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_10
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_11
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_3: # %else4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_4: # %cond.store5
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
+; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_5: # %else6
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_13
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_14
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_7: # %else10
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_8: # %else12
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB69_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_9: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_10: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
@@ -7573,10 +7904,9 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_11: # %cond.store1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7587,41 +7917,23 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_4: # %else2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_12: # %cond.store3
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_6: # %else4
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
-; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_8: # %else6
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB69_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_13: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7631,10 +7943,9 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_10: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_14: # %cond.store9
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7645,34 +7956,27 @@ define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_12: # %else10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB69_15
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB69_16
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_14: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB69_8
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_15: # %cond.store11
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB69_14
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB69_9
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB69_16: # %cond.store13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -7707,18 +8011,52 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_10
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_11
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_3: # %else4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_4: # %cond.store5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_5: # %else6
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_13
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_14
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_7: # %else10
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_8: # %else12
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB70_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_9: # %else14
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_10: # %cond.store
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_11: # %cond.store1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7728,38 +8066,22 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_12: # %cond.store3
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_6: # %else4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_8: # %else6
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB70_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_13: # %cond.store7
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
@@ -7768,10 +8090,9 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB70_14: # %cond.store9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7781,18 +8102,12 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_12: # %else10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB70_15
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB70_16
-; RV64ZVE32F-ZVFH-NEXT: .LBB70_14: # %else14
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB70_8
; RV64ZVE32F-ZVFH-NEXT: .LBB70_15: # %cond.store11
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFH-NEXT: zext.b a2, a2
@@ -7800,10 +8115,10 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB70_14
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB70_9
; RV64ZVE32F-ZVFH-NEXT: .LBB70_16: # %cond.store13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 7
@@ -7818,8 +8133,45 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_10
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_11
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_3: # %else4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_4: # %cond.store5
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a3
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_5: # %else6
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_13
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_14
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_7: # %else10
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_8: # %else12
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB70_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_9: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_10: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
@@ -7829,10 +8181,9 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_11: # %cond.store1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7844,43 +8195,24 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_4: # %else2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_12: # %cond.store3
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a3
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_6: # %else4
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a3
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_8: # %else6
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB70_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_13: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7891,10 +8223,9 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_10: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_14: # %cond.store9
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -7906,35 +8237,28 @@ define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, ptr %base, <8 x i
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_12: # %else10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB70_15
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB70_16
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_14: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB70_8
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_15: # %cond.store11
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a2, a3
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a2)
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB70_14
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB70_9
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB70_16: # %cond.store13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: zext.b a1, a2
@@ -7970,17 +8294,50 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_2
-; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_10
+; RV64ZVE32F-ZVFH-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_11
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_2: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_12
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_3: # %else4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_4: # %cond.store5
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
+; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
+; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_5: # %else6
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_13
+; RV64ZVE32F-ZVFH-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_14
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_7: # %else10
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_15
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_8: # %else12
+; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB71_16
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_9: # %else14
+; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_10: # %cond.store
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v8, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_2: # %else
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_4
-; RV64ZVE32F-ZVFH-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_2
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_11: # %cond.store1
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -7989,46 +8346,30 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_4: # %else2
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_3
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_12: # %cond.store3
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_6
-; RV64ZVE32F-ZVFH-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
-; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
-; RV64ZVE32F-ZVFH-NEXT: vse16.v v11, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_6: # %else4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_8
-; RV64ZVE32F-ZVFH-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_8: # %else6
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_10
-; RV64ZVE32F-ZVFH-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_4
+; RV64ZVE32F-ZVFH-NEXT: j .LBB71_5
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_13: # %cond.store7
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_10: # %else8
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_12
-; RV64ZVE32F-ZVFH-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_7
+; RV64ZVE32F-ZVFH-NEXT: .LBB71_14: # %cond.store9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
@@ -8037,28 +8378,22 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_12: # %else10
-; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFH-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFH-NEXT: bnez a2, .LBB71_15
-; RV64ZVE32F-ZVFH-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: bnez a1, .LBB71_16
-; RV64ZVE32F-ZVFH-NEXT: .LBB71_14: # %else14
-; RV64ZVE32F-ZVFH-NEXT: ret
+; RV64ZVE32F-ZVFH-NEXT: beqz a2, .LBB71_8
; RV64ZVE32F-ZVFH-NEXT: .LBB71_15: # %cond.store11
-; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFH-NEXT: slli a2, a2, 1
; RV64ZVE32F-ZVFH-NEXT: add a2, a0, a2
; RV64ZVE32F-ZVFH-NEXT: vse16.v v10, (a2)
; RV64ZVE32F-ZVFH-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB71_14
+; RV64ZVE32F-ZVFH-NEXT: beqz a1, .LBB71_9
; RV64ZVE32F-ZVFH-NEXT: .LBB71_16: # %cond.store13
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 1
+; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v9, v9, 3
; RV64ZVE32F-ZVFH-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFH-NEXT: vslidedown.vi v8, v8, 7
@@ -8072,8 +8407,44 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_2
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_10
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.1: # %else
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_11
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_2: # %else2
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_12
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_3: # %else4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_4: # %cond.store5
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
+; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
+; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_5: # %else6
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_13
+; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_14
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_7: # %else10
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_15
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_8: # %else12
+; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB71_16
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_9: # %else14
+; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_10: # %cond.store
; RV64ZVE32F-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v9
@@ -8081,10 +8452,9 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_2: # %else
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_4
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_2
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_11: # %cond.store1
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
@@ -8095,40 +8465,23 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_4: # %else2
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_6
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_3
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_12: # %cond.store3
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_6: # %else4
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 8
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_8
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
-; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
-; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
-; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_8: # %else6
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 16
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_10
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_4
+; RV64ZVE32F-ZVFHMIN-NEXT: j .LBB71_5
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_13: # %cond.store7
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v9
@@ -8136,10 +8489,9 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_10: # %else8
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 32
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_12
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_7
+; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_14: # %cond.store9
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -8149,33 +8501,27 @@ define void @mscatter_baseidx_v8f16(<8 x half> %val, ptr %base, <8 x i16> %idxs,
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_12: # %else10
-; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-ZVFHMIN-NEXT: andi a2, a1, 64
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a2, .LBB71_15
-; RV64ZVE32F-ZVFHMIN-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: bnez a1, .LBB71_16
-; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_14: # %else14
-; RV64ZVE32F-ZVFHMIN-NEXT: ret
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a2, .LBB71_8
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_15: # %cond.store11
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v9
+; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a2
; RV64ZVE32F-ZVFHMIN-NEXT: slli a3, a3, 1
; RV64ZVE32F-ZVFHMIN-NEXT: add a3, a0, a3
; RV64ZVE32F-ZVFHMIN-NEXT: fsh fa5, 0(a3)
; RV64ZVE32F-ZVFHMIN-NEXT: andi a1, a1, -128
-; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB71_14
+; RV64ZVE32F-ZVFHMIN-NEXT: beqz a1, .LBB71_9
; RV64ZVE32F-ZVFHMIN-NEXT: .LBB71_16: # %cond.store13
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v8, 7
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 1
+; RV64ZVE32F-ZVFHMIN-NEXT: vslidedown.vi v8, v9, 3
; RV64ZVE32F-ZVFHMIN-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-ZVFHMIN-NEXT: fmv.h.x fa5, a1
; RV64ZVE32F-ZVFHMIN-NEXT: slli a2, a2, 1
@@ -8491,17 +8837,50 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB78_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_11
+; RV64ZVE32F-NEXT: .LBB78_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_12
+; RV64ZVE32F-NEXT: .LBB78_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB78_5
+; RV64ZVE32F-NEXT: .LBB78_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB78_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_14
+; RV64ZVE32F-NEXT: .LBB78_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_15
+; RV64ZVE32F-NEXT: .LBB78_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB78_16
+; RV64ZVE32F-NEXT: .LBB78_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB78_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB78_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB78_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB78_2
+; RV64ZVE32F-NEXT: .LBB78_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8510,37 +8889,22 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB78_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB78_3
+; RV64ZVE32F-NEXT: .LBB78_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB78_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB78_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB78_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB78_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB78_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB78_4
+; RV64ZVE32F-NEXT: j .LBB78_5
+; RV64ZVE32F-NEXT: .LBB78_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -8548,10 +8912,9 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB78_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB78_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB78_7
+; RV64ZVE32F-NEXT: .LBB78_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8561,18 +8924,12 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB78_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB78_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB78_16
-; RV64ZVE32F-NEXT: .LBB78_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB78_8
; RV64ZVE32F-NEXT: .LBB78_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -8580,10 +8937,10 @@ define void @mscatter_baseidx_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x i8> %
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB78_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB78_9
; RV64ZVE32F-NEXT: .LBB78_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -8620,17 +8977,50 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB79_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_11
+; RV64ZVE32F-NEXT: .LBB79_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_12
+; RV64ZVE32F-NEXT: .LBB79_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB79_5
+; RV64ZVE32F-NEXT: .LBB79_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB79_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_14
+; RV64ZVE32F-NEXT: .LBB79_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_15
+; RV64ZVE32F-NEXT: .LBB79_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB79_16
+; RV64ZVE32F-NEXT: .LBB79_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB79_10: # %cond.store
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB79_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB79_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB79_2
+; RV64ZVE32F-NEXT: .LBB79_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8639,37 +9029,22 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB79_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB79_3
+; RV64ZVE32F-NEXT: .LBB79_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB79_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB79_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB79_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB79_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB79_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB79_4
+; RV64ZVE32F-NEXT: j .LBB79_5
+; RV64ZVE32F-NEXT: .LBB79_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -8677,10 +9052,9 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB79_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB79_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB79_7
+; RV64ZVE32F-NEXT: .LBB79_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8690,18 +9064,12 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB79_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB79_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB79_16
-; RV64ZVE32F-NEXT: .LBB79_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB79_8
; RV64ZVE32F-NEXT: .LBB79_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -8709,10 +9077,10 @@ define void @mscatter_baseidx_sext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB79_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB79_9
; RV64ZVE32F-NEXT: .LBB79_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -8751,18 +9119,52 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB80_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_11
+; RV64ZVE32F-NEXT: .LBB80_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_12
+; RV64ZVE32F-NEXT: .LBB80_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB80_5
+; RV64ZVE32F-NEXT: .LBB80_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB80_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_14
+; RV64ZVE32F-NEXT: .LBB80_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_15
+; RV64ZVE32F-NEXT: .LBB80_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB80_16
+; RV64ZVE32F-NEXT: .LBB80_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB80_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB80_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB80_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB80_2
+; RV64ZVE32F-NEXT: .LBB80_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8772,39 +9174,23 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB80_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB80_3
+; RV64ZVE32F-NEXT: .LBB80_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB80_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB80_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB80_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB80_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB80_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB80_4
+; RV64ZVE32F-NEXT: j .LBB80_5
+; RV64ZVE32F-NEXT: .LBB80_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -8813,10 +9199,9 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB80_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB80_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB80_7
+; RV64ZVE32F-NEXT: .LBB80_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8827,18 +9212,12 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB80_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB80_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB80_16
-; RV64ZVE32F-NEXT: .LBB80_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB80_8
; RV64ZVE32F-NEXT: .LBB80_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: zext.b a2, a2
@@ -8847,10 +9226,10 @@ define void @mscatter_baseidx_zext_v8i8_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB80_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB80_9
; RV64ZVE32F-NEXT: .LBB80_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -8890,18 +9269,51 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB81_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_11
+; RV64ZVE32F-NEXT: .LBB81_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_12
+; RV64ZVE32F-NEXT: .LBB81_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB81_5
+; RV64ZVE32F-NEXT: .LBB81_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB81_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_14
+; RV64ZVE32F-NEXT: .LBB81_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_15
+; RV64ZVE32F-NEXT: .LBB81_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB81_16
+; RV64ZVE32F-NEXT: .LBB81_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB81_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB81_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB81_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB81_2
+; RV64ZVE32F-NEXT: .LBB81_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8910,37 +9322,22 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB81_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB81_3
+; RV64ZVE32F-NEXT: .LBB81_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB81_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB81_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB81_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB81_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB81_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB81_4
+; RV64ZVE32F-NEXT: j .LBB81_5
+; RV64ZVE32F-NEXT: .LBB81_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -8948,10 +9345,9 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB81_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB81_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB81_7
+; RV64ZVE32F-NEXT: .LBB81_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -8961,18 +9357,12 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB81_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB81_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB81_16
-; RV64ZVE32F-NEXT: .LBB81_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB81_8
; RV64ZVE32F-NEXT: .LBB81_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -8980,10 +9370,10 @@ define void @mscatter_baseidx_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x i16>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB81_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB81_9
; RV64ZVE32F-NEXT: .LBB81_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -9021,18 +9411,51 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB82_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_11
+; RV64ZVE32F-NEXT: .LBB82_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_12
+; RV64ZVE32F-NEXT: .LBB82_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB82_5
+; RV64ZVE32F-NEXT: .LBB82_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB82_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_14
+; RV64ZVE32F-NEXT: .LBB82_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_15
+; RV64ZVE32F-NEXT: .LBB82_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB82_16
+; RV64ZVE32F-NEXT: .LBB82_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB82_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB82_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB82_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB82_2
+; RV64ZVE32F-NEXT: .LBB82_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -9041,37 +9464,22 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB82_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB82_3
+; RV64ZVE32F-NEXT: .LBB82_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB82_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB82_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB82_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB82_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB82_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB82_4
+; RV64ZVE32F-NEXT: j .LBB82_5
+; RV64ZVE32F-NEXT: .LBB82_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -9079,10 +9487,9 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB82_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB82_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB82_7
+; RV64ZVE32F-NEXT: .LBB82_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -9092,18 +9499,12 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB82_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB82_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB82_16
-; RV64ZVE32F-NEXT: .LBB82_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB82_8
; RV64ZVE32F-NEXT: .LBB82_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
@@ -9111,10 +9512,10 @@ define void @mscatter_baseidx_sext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB82_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB82_9
; RV64ZVE32F-NEXT: .LBB82_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -9153,8 +9554,43 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB83_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_11
+; RV64ZVE32F-NEXT: .LBB83_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_12
+; RV64ZVE32F-NEXT: .LBB83_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB83_5
+; RV64ZVE32F-NEXT: .LBB83_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 46
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v11, (a2)
+; RV64ZVE32F-NEXT: .LBB83_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_14
+; RV64ZVE32F-NEXT: .LBB83_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_15
+; RV64ZVE32F-NEXT: .LBB83_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB83_16
+; RV64ZVE32F-NEXT: .LBB83_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB83_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 48
@@ -9162,10 +9598,9 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB83_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB83_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB83_2
+; RV64ZVE32F-NEXT: .LBB83_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -9175,39 +9610,23 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB83_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB83_3
+; RV64ZVE32F-NEXT: .LBB83_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB83_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 46
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB83_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB83_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 46
-; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB83_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB83_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB83_4
+; RV64ZVE32F-NEXT: j .LBB83_5
+; RV64ZVE32F-NEXT: .LBB83_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
@@ -9216,10 +9635,9 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB83_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB83_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB83_7
+; RV64ZVE32F-NEXT: .LBB83_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -9230,18 +9648,12 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB83_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB83_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB83_16
-; RV64ZVE32F-NEXT: .LBB83_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB83_8
; RV64ZVE32F-NEXT: .LBB83_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 48
@@ -9250,10 +9662,10 @@ define void @mscatter_baseidx_zext_v8i16_v8f32(<8 x float> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB83_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB83_9
; RV64ZVE32F-NEXT: .LBB83_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -9290,17 +9702,50 @@ define void @mscatter_baseidx_v8f32(<8 x float> %val, ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_11
+; RV64ZVE32F-NEXT: .LBB84_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_4
+; RV64ZVE32F-NEXT: .LBB84_3: # %cond.store3
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vse32.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB84_4: # %else4
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_13
+; RV64ZVE32F-NEXT: .LBB84_6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_14
+; RV64ZVE32F-NEXT: .LBB84_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_15
+; RV64ZVE32F-NEXT: .LBB84_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB84_16
+; RV64ZVE32F-NEXT: .LBB84_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB84_10: # %cond.store
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB84_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_2
+; RV64ZVE32F-NEXT: .LBB84_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
@@ -9308,83 +9753,56 @@ define void @mscatter_baseidx_v8f32(<8 x float> %val, ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB84_4: # %else2
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB84_3
+; RV64ZVE32F-NEXT: j .LBB84_4
+; RV64ZVE32F-NEXT: .LBB84_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: slli a2, a2, 2
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB84_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
+; RV64ZVE32F-NEXT: .LBB84_13: # %cond.store7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 2
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB84_6: # %else4
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB84_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB84_14
-; RV64ZVE32F-NEXT: .LBB84_8: # %else8
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB84_10
-; RV64ZVE32F-NEXT: .LBB84_9: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB84_7
+; RV64ZVE32F-NEXT: .LBB84_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v12, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 5
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB84_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB84_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB84_16
-; RV64ZVE32F-NEXT: .LBB84_12: # %else14
-; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB84_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse32.v v11, (a2)
-; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB84_8
-; RV64ZVE32F-NEXT: .LBB84_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 4
-; RV64ZVE32F-NEXT: slli a2, a2, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
-; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB84_9
-; RV64ZVE32F-NEXT: j .LBB84_10
; RV64ZVE32F-NEXT: .LBB84_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v12, 2
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6
; RV64ZVE32F-NEXT: slli a2, a2, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vse32.v v12, (a2)
+; RV64ZVE32F-NEXT: vse32.v v10, (a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB84_12
+; RV64ZVE32F-NEXT: beqz a1, .LBB84_9
; RV64ZVE32F-NEXT: .LBB84_16: # %cond.store13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v12, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7
@@ -9923,80 +10341,93 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB91_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_11
+; RV64ZVE32F-NEXT: .LBB91_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_12
+; RV64ZVE32F-NEXT: .LBB91_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB91_5
+; RV64ZVE32F-NEXT: .LBB91_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: .LBB91_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_14
+; RV64ZVE32F-NEXT: .LBB91_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_15
+; RV64ZVE32F-NEXT: .LBB91_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB91_16
+; RV64ZVE32F-NEXT: .LBB91_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB91_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB91_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB91_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB91_2
+; RV64ZVE32F-NEXT: .LBB91_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB91_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB91_3
+; RV64ZVE32F-NEXT: .LBB91_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB91_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB91_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB91_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: .LBB91_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB91_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB91_4
+; RV64ZVE32F-NEXT: j .LBB91_5
+; RV64ZVE32F-NEXT: .LBB91_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
-; RV64ZVE32F-NEXT: .LBB91_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB91_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB91_7
+; RV64ZVE32F-NEXT: .LBB91_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB91_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB91_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB91_16
-; RV64ZVE32F-NEXT: .LBB91_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB91_8
; RV64ZVE32F-NEXT: .LBB91_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB91_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB91_9
; RV64ZVE32F-NEXT: .LBB91_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -10117,80 +10548,93 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB92_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_11
+; RV64ZVE32F-NEXT: .LBB92_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_12
+; RV64ZVE32F-NEXT: .LBB92_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB92_5
+; RV64ZVE32F-NEXT: .LBB92_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: .LBB92_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_14
+; RV64ZVE32F-NEXT: .LBB92_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_15
+; RV64ZVE32F-NEXT: .LBB92_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB92_16
+; RV64ZVE32F-NEXT: .LBB92_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB92_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB92_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB92_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB92_2
+; RV64ZVE32F-NEXT: .LBB92_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB92_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB92_3
+; RV64ZVE32F-NEXT: .LBB92_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB92_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB92_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB92_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: .LBB92_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB92_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB92_4
+; RV64ZVE32F-NEXT: j .LBB92_5
+; RV64ZVE32F-NEXT: .LBB92_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
-; RV64ZVE32F-NEXT: .LBB92_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB92_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB92_7
+; RV64ZVE32F-NEXT: .LBB92_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB92_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB92_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB92_16
-; RV64ZVE32F-NEXT: .LBB92_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB92_8
; RV64ZVE32F-NEXT: .LBB92_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB92_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB92_9
; RV64ZVE32F-NEXT: .LBB92_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -10313,17 +10757,49 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB93_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_11
+; RV64ZVE32F-NEXT: .LBB93_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_12
+; RV64ZVE32F-NEXT: .LBB93_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB93_5
+; RV64ZVE32F-NEXT: .LBB93_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: zext.b a2, a2
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: .LBB93_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_14
+; RV64ZVE32F-NEXT: .LBB93_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_15
+; RV64ZVE32F-NEXT: .LBB93_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB93_16
+; RV64ZVE32F-NEXT: .LBB93_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB93_10: # %cond.store
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB93_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB93_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB93_2
+; RV64ZVE32F-NEXT: .LBB93_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10331,42 +10807,28 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB93_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB93_3
+; RV64ZVE32F-NEXT: .LBB93_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB93_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB93_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB93_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: zext.b a2, a2
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: .LBB93_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB93_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB93_4
+; RV64ZVE32F-NEXT: j .LBB93_5
+; RV64ZVE32F-NEXT: .LBB93_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
-; RV64ZVE32F-NEXT: .LBB93_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB93_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB93_7
+; RV64ZVE32F-NEXT: .LBB93_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10374,26 +10836,21 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB93_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB93_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB93_16
-; RV64ZVE32F-NEXT: .LBB93_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB93_8
; RV64ZVE32F-NEXT: .LBB93_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: zext.b a2, a2
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB93_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB93_9
; RV64ZVE32F-NEXT: .LBB93_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: zext.b a1, a1
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -10518,81 +10975,94 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB94_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_11
+; RV64ZVE32F-NEXT: .LBB94_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_12
+; RV64ZVE32F-NEXT: .LBB94_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB94_5
+; RV64ZVE32F-NEXT: .LBB94_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: .LBB94_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_14
+; RV64ZVE32F-NEXT: .LBB94_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_15
+; RV64ZVE32F-NEXT: .LBB94_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB94_16
+; RV64ZVE32F-NEXT: .LBB94_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB94_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB94_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB94_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB94_2
+; RV64ZVE32F-NEXT: .LBB94_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB94_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB94_3
+; RV64ZVE32F-NEXT: .LBB94_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB94_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB94_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB94_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: .LBB94_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB94_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB94_4
+; RV64ZVE32F-NEXT: j .LBB94_5
+; RV64ZVE32F-NEXT: .LBB94_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
-; RV64ZVE32F-NEXT: .LBB94_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB94_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB94_7
+; RV64ZVE32F-NEXT: .LBB94_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB94_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB94_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB94_16
-; RV64ZVE32F-NEXT: .LBB94_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB94_8
; RV64ZVE32F-NEXT: .LBB94_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB94_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB94_9
; RV64ZVE32F-NEXT: .LBB94_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -10715,81 +11185,94 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB95_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_11
+; RV64ZVE32F-NEXT: .LBB95_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_12
+; RV64ZVE32F-NEXT: .LBB95_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB95_5
+; RV64ZVE32F-NEXT: .LBB95_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: .LBB95_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_14
+; RV64ZVE32F-NEXT: .LBB95_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_15
+; RV64ZVE32F-NEXT: .LBB95_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB95_16
+; RV64ZVE32F-NEXT: .LBB95_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB95_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB95_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB95_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB95_2
+; RV64ZVE32F-NEXT: .LBB95_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB95_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB95_3
+; RV64ZVE32F-NEXT: .LBB95_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB95_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB95_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB95_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: .LBB95_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB95_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB95_4
+; RV64ZVE32F-NEXT: j .LBB95_5
+; RV64ZVE32F-NEXT: .LBB95_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
-; RV64ZVE32F-NEXT: .LBB95_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB95_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB95_7
+; RV64ZVE32F-NEXT: .LBB95_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB95_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB95_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB95_16
-; RV64ZVE32F-NEXT: .LBB95_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB95_8
; RV64ZVE32F-NEXT: .LBB95_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB95_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB95_9
; RV64ZVE32F-NEXT: .LBB95_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -10914,18 +11397,50 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB96_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_11
+; RV64ZVE32F-NEXT: .LBB96_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_12
+; RV64ZVE32F-NEXT: .LBB96_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB96_5
+; RV64ZVE32F-NEXT: .LBB96_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: slli a2, a2, 48
+; RV64ZVE32F-NEXT: srli a2, a2, 45
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: .LBB96_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_13
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_14
+; RV64ZVE32F-NEXT: .LBB96_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_15
+; RV64ZVE32F-NEXT: .LBB96_8: # %else12
+; RV64ZVE32F-NEXT: andi a1, a1, -128
+; RV64ZVE32F-NEXT: bnez a1, .LBB96_16
+; RV64ZVE32F-NEXT: .LBB96_9: # %else14
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB96_10: # %cond.store
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB96_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB96_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB96_2
+; RV64ZVE32F-NEXT: .LBB96_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10933,42 +11448,28 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB96_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB96_3
+; RV64ZVE32F-NEXT: .LBB96_12: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB96_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB96_6: # %else4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB96_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 48
-; RV64ZVE32F-NEXT: srli a2, a2, 45
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: .LBB96_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB96_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: bnez a2, .LBB96_4
+; RV64ZVE32F-NEXT: j .LBB96_5
+; RV64ZVE32F-NEXT: .LBB96_13: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
-; RV64ZVE32F-NEXT: .LBB96_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB96_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB96_7
+; RV64ZVE32F-NEXT: .LBB96_14: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
@@ -10976,26 +11477,21 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB96_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: bnez a2, .LBB96_15
-; RV64ZVE32F-NEXT: # %bb.13: # %else12
-; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: bnez a1, .LBB96_16
-; RV64ZVE32F-NEXT: .LBB96_14: # %else14
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: beqz a2, .LBB96_8
; RV64ZVE32F-NEXT: .LBB96_15: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: slli a2, a2, 48
; RV64ZVE32F-NEXT: srli a2, a2, 45
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB96_14
+; RV64ZVE32F-NEXT: beqz a1, .LBB96_9
; RV64ZVE32F-NEXT: .LBB96_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 48
; RV64ZVE32F-NEXT: srli a1, a1, 45
@@ -11117,88 +11613,95 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB97_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB97_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_11
+; RV64ZVE32F-NEXT: .LBB97_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB97_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB97_4: # %else2
+; RV64ZVE32F-NEXT: .LBB97_3: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB97_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB97_6: # %else4
+; RV64ZVE32F-NEXT: .LBB97_4: # %else4
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB97_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB97_14
-; RV64ZVE32F-NEXT: .LBB97_8: # %else8
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_13
+; RV64ZVE32F-NEXT: .LBB97_6: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB97_10
-; RV64ZVE32F-NEXT: .LBB97_9: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB97_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_14
+; RV64ZVE32F-NEXT: .LBB97_7: # %else10
; RV64ZVE32F-NEXT: andi a2, a1, 64
; RV64ZVE32F-NEXT: bnez a2, .LBB97_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
+; RV64ZVE32F-NEXT: .LBB97_8: # %else12
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: bnez a1, .LBB97_16
-; RV64ZVE32F-NEXT: .LBB97_12: # %else14
+; RV64ZVE32F-NEXT: .LBB97_9: # %else14
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB97_13: # %cond.store5
+; RV64ZVE32F-NEXT: .LBB97_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB97_2
+; RV64ZVE32F-NEXT: .LBB97_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB97_3
+; RV64ZVE32F-NEXT: j .LBB97_4
+; RV64ZVE32F-NEXT: .LBB97_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB97_8
-; RV64ZVE32F-NEXT: .LBB97_14: # %cond.store7
+; RV64ZVE32F-NEXT: beqz a2, .LBB97_6
+; RV64ZVE32F-NEXT: .LBB97_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB97_9
-; RV64ZVE32F-NEXT: j .LBB97_10
+; RV64ZVE32F-NEXT: beqz a2, .LBB97_7
+; RV64ZVE32F-NEXT: .LBB97_14: # %cond.store9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: beqz a2, .LBB97_8
; RV64ZVE32F-NEXT: .LBB97_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB97_12
+; RV64ZVE32F-NEXT: beqz a1, .LBB97_9
; RV64ZVE32F-NEXT: .LBB97_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -11318,88 +11821,95 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB98_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB98_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_11
+; RV64ZVE32F-NEXT: .LBB98_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB98_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB98_4: # %else2
+; RV64ZVE32F-NEXT: .LBB98_3: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB98_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB98_6: # %else4
+; RV64ZVE32F-NEXT: .LBB98_4: # %else4
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB98_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB98_14
-; RV64ZVE32F-NEXT: .LBB98_8: # %else8
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_13
+; RV64ZVE32F-NEXT: .LBB98_6: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB98_10
-; RV64ZVE32F-NEXT: .LBB98_9: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 3
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB98_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_14
+; RV64ZVE32F-NEXT: .LBB98_7: # %else10
; RV64ZVE32F-NEXT: andi a2, a1, 64
; RV64ZVE32F-NEXT: bnez a2, .LBB98_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
+; RV64ZVE32F-NEXT: .LBB98_8: # %else12
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: bnez a1, .LBB98_16
-; RV64ZVE32F-NEXT: .LBB98_12: # %else14
+; RV64ZVE32F-NEXT: .LBB98_9: # %else14
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB98_13: # %cond.store5
+; RV64ZVE32F-NEXT: .LBB98_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB98_2
+; RV64ZVE32F-NEXT: .LBB98_11: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB98_3
+; RV64ZVE32F-NEXT: j .LBB98_4
+; RV64ZVE32F-NEXT: .LBB98_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB98_8
-; RV64ZVE32F-NEXT: .LBB98_14: # %cond.store7
+; RV64ZVE32F-NEXT: beqz a2, .LBB98_6
+; RV64ZVE32F-NEXT: .LBB98_13: # %cond.store7
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB98_9
-; RV64ZVE32F-NEXT: j .LBB98_10
+; RV64ZVE32F-NEXT: beqz a2, .LBB98_7
+; RV64ZVE32F-NEXT: .LBB98_14: # %cond.store9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: beqz a2, .LBB98_8
; RV64ZVE32F-NEXT: .LBB98_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB98_12
+; RV64ZVE32F-NEXT: beqz a1, .LBB98_9
; RV64ZVE32F-NEXT: .LBB98_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
; RV64ZVE32F-NEXT: add a0, a0, a1
@@ -11520,95 +12030,102 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB99_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
-; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v8
-; RV64ZVE32F-NEXT: slli a2, a2, 32
-; RV64ZVE32F-NEXT: srli a2, a2, 29
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
-; RV64ZVE32F-NEXT: .LBB99_2: # %else
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_10
+; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_11
+; RV64ZVE32F-NEXT: .LBB99_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB99_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: slli a2, a2, 32
-; RV64ZVE32F-NEXT: srli a2, a2, 29
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
-; RV64ZVE32F-NEXT: .LBB99_4: # %else2
+; RV64ZVE32F-NEXT: .LBB99_3: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB99_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa2, 0(a2)
-; RV64ZVE32F-NEXT: .LBB99_6: # %else4
+; RV64ZVE32F-NEXT: .LBB99_4: # %else4
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 4
; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: bnez a2, .LBB99_13
-; RV64ZVE32F-NEXT: # %bb.7: # %else6
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_12
+; RV64ZVE32F-NEXT: # %bb.5: # %else6
; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: bnez a2, .LBB99_14
-; RV64ZVE32F-NEXT: .LBB99_8: # %else8
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_13
+; RV64ZVE32F-NEXT: .LBB99_6: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB99_10
-; RV64ZVE32F-NEXT: .LBB99_9: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 32
-; RV64ZVE32F-NEXT: srli a2, a2, 29
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
-; RV64ZVE32F-NEXT: .LBB99_10: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_14
+; RV64ZVE32F-NEXT: .LBB99_7: # %else10
; RV64ZVE32F-NEXT: andi a2, a1, 64
; RV64ZVE32F-NEXT: bnez a2, .LBB99_15
-; RV64ZVE32F-NEXT: # %bb.11: # %else12
+; RV64ZVE32F-NEXT: .LBB99_8: # %else12
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: bnez a1, .LBB99_16
-; RV64ZVE32F-NEXT: .LBB99_12: # %else14
+; RV64ZVE32F-NEXT: .LBB99_9: # %else14
; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB99_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: slli a2, a2, 32
-; RV64ZVE32F-NEXT: srli a2, a2, 29
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB99_8
-; RV64ZVE32F-NEXT: .LBB99_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: .LBB99_10: # %cond.store
+; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa0, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: beqz a2, .LBB99_2
+; RV64ZVE32F-NEXT: .LBB99_11: # %cond.store1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 32
+; RV64ZVE32F-NEXT: srli a2, a2, 29
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa1, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB99_3
+; RV64ZVE32F-NEXT: j .LBB99_4
+; RV64ZVE32F-NEXT: .LBB99_12: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 32
+; RV64ZVE32F-NEXT: srli a2, a2, 29
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa3, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: beqz a2, .LBB99_6
+; RV64ZVE32F-NEXT: .LBB99_13: # %cond.store7
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: slli a2, a2, 32
+; RV64ZVE32F-NEXT: srli a2, a2, 29
+; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa4, 0(a2)
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: bnez a2, .LBB99_9
-; RV64ZVE32F-NEXT: j .LBB99_10
+; RV64ZVE32F-NEXT: beqz a2, .LBB99_7
+; RV64ZVE32F-NEXT: .LBB99_14: # %cond.store9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
+; RV64ZVE32F-NEXT: vmv.x.s a2, v8
+; RV64ZVE32F-NEXT: slli a2, a2, 32
+; RV64ZVE32F-NEXT: srli a2, a2, 29
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: beqz a2, .LBB99_8
; RV64ZVE32F-NEXT: .LBB99_15: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa6, 0(a2)
; RV64ZVE32F-NEXT: andi a1, a1, -128
-; RV64ZVE32F-NEXT: beqz a1, .LBB99_12
+; RV64ZVE32F-NEXT: beqz a1, .LBB99_9
; RV64ZVE32F-NEXT: .LBB99_16: # %cond.store13
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 3
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 32
; RV64ZVE32F-NEXT: srli a1, a1, 29
@@ -11851,16 +12368,109 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_22
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_23
+; RV64ZVE32F-NEXT: .LBB101_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_24
+; RV64ZVE32F-NEXT: .LBB101_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_5
+; RV64ZVE32F-NEXT: .LBB101_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB101_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_25
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_26
+; RV64ZVE32F-NEXT: .LBB101_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_27
+; RV64ZVE32F-NEXT: .LBB101_8: # %else12
+; RV64ZVE32F-NEXT: andi a2, a1, 128
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_10
+; RV64ZVE32F-NEXT: .LBB101_9: # %cond.store13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 7
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB101_10: # %else14
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 8
+; RV64ZVE32F-NEXT: andi a2, a1, 256
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_28
+; RV64ZVE32F-NEXT: # %bb.11: # %else16
+; RV64ZVE32F-NEXT: andi a2, a1, 512
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_29
+; RV64ZVE32F-NEXT: .LBB101_12: # %else18
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_30
+; RV64ZVE32F-NEXT: .LBB101_13: # %else20
+; RV64ZVE32F-NEXT: slli a2, a1, 52
+; RV64ZVE32F-NEXT: bgez a2, .LBB101_15
+; RV64ZVE32F-NEXT: .LBB101_14: # %cond.store21
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB101_15: # %else22
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 51
+; RV64ZVE32F-NEXT: bltz a2, .LBB101_31
+; RV64ZVE32F-NEXT: # %bb.16: # %else24
+; RV64ZVE32F-NEXT: slli a2, a1, 50
+; RV64ZVE32F-NEXT: bltz a2, .LBB101_32
+; RV64ZVE32F-NEXT: .LBB101_17: # %else26
+; RV64ZVE32F-NEXT: slli a2, a1, 49
+; RV64ZVE32F-NEXT: bgez a2, .LBB101_19
+; RV64ZVE32F-NEXT: .LBB101_18: # %cond.store27
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 14
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v10, (a2)
+; RV64ZVE32F-NEXT: .LBB101_19: # %else28
+; RV64ZVE32F-NEXT: lui a2, 1048568
+; RV64ZVE32F-NEXT: and a1, a1, a2
+; RV64ZVE32F-NEXT: beqz a1, .LBB101_21
+; RV64ZVE32F-NEXT: # %bb.20: # %cond.store29
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v9
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: vse8.v v8, (a0)
+; RV64ZVE32F-NEXT: .LBB101_21: # %else30
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB101_22: # %cond.store
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB101_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_2
+; RV64ZVE32F-NEXT: .LBB101_23: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -11868,43 +12478,28 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_3
+; RV64ZVE32F-NEXT: .LBB101_24: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB101_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_4
+; RV64ZVE32F-NEXT: j .LBB101_5
+; RV64ZVE32F-NEXT: .LBB101_25: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 4
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB101_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_7
+; RV64ZVE32F-NEXT: .LBB101_26: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -11912,43 +12507,28 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 5
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB101_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_8
+; RV64ZVE32F-NEXT: .LBB101_27: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 6
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB101_14: # %else12
; RV64ZVE32F-NEXT: andi a2, a1, 128
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 7
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_16: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 8
-; RV64ZVE32F-NEXT: andi a2, a1, 256
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_18
-; RV64ZVE32F-NEXT: # %bb.17: # %cond.store15
+; RV64ZVE32F-NEXT: bnez a2, .LBB101_9
+; RV64ZVE32F-NEXT: j .LBB101_10
+; RV64ZVE32F-NEXT: .LBB101_28: # %cond.store15
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_18: # %else16
; RV64ZVE32F-NEXT: andi a2, a1, 512
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_20
-; RV64ZVE32F-NEXT: # %bb.19: # %cond.store17
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_12
+; RV64ZVE32F-NEXT: .LBB101_29: # %cond.store17
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -11956,43 +12536,28 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_20: # %else18
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: beqz a2, .LBB101_13
+; RV64ZVE32F-NEXT: .LBB101_30: # %cond.store19
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 1024
-; RV64ZVE32F-NEXT: beqz a2, .LBB101_22
-; RV64ZVE32F-NEXT: # %bb.21: # %cond.store19
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: .LBB101_22: # %else20
-; RV64ZVE32F-NEXT: slli a2, a1, 52
-; RV64ZVE32F-NEXT: bgez a2, .LBB101_24
-; RV64ZVE32F-NEXT: # %bb.23: # %cond.store21
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_24: # %else22
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 51
-; RV64ZVE32F-NEXT: bgez a2, .LBB101_26
-; RV64ZVE32F-NEXT: # %bb.25: # %cond.store23
+; RV64ZVE32F-NEXT: slli a2, a1, 52
+; RV64ZVE32F-NEXT: bltz a2, .LBB101_14
+; RV64ZVE32F-NEXT: j .LBB101_15
+; RV64ZVE32F-NEXT: .LBB101_31: # %cond.store23
; RV64ZVE32F-NEXT: vmv.x.s a2, v9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_26: # %else24
; RV64ZVE32F-NEXT: slli a2, a1, 50
-; RV64ZVE32F-NEXT: bgez a2, .LBB101_28
-; RV64ZVE32F-NEXT: # %bb.27: # %cond.store25
+; RV64ZVE32F-NEXT: bgez a2, .LBB101_17
+; RV64ZVE32F-NEXT: .LBB101_32: # %cond.store25
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
@@ -12000,31 +12565,9 @@ define void @mscatter_baseidx_v16i8(<16 x i8> %val, ptr %base, <16 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 13
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_28: # %else26
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 2
; RV64ZVE32F-NEXT: slli a2, a1, 49
-; RV64ZVE32F-NEXT: bgez a2, .LBB101_30
-; RV64ZVE32F-NEXT: # %bb.29: # %cond.store27
-; RV64ZVE32F-NEXT: vmv.x.s a2, v9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 14
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v10, (a2)
-; RV64ZVE32F-NEXT: .LBB101_30: # %else28
-; RV64ZVE32F-NEXT: lui a2, 1048568
-; RV64ZVE32F-NEXT: and a1, a1, a2
-; RV64ZVE32F-NEXT: beqz a1, .LBB101_32
-; RV64ZVE32F-NEXT: # %bb.31: # %cond.store29
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: vse8.v v8, (a0)
-; RV64ZVE32F-NEXT: .LBB101_32: # %else30
-; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: bltz a2, .LBB101_18
+; RV64ZVE32F-NEXT: j .LBB101_19
%ptrs = getelementptr inbounds i8, ptr %base, <16 x i8> %idxs
call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> %val, <16 x ptr> %ptrs, i32 1, <16 x i1> %m)
ret void
@@ -12063,16 +12606,202 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_2
-; RV64ZVE32F-NEXT: # %bb.1: # %cond.store
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_42
+; RV64ZVE32F-NEXT: # %bb.1: # %else
+; RV64ZVE32F-NEXT: andi a2, a1, 2
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_43
+; RV64ZVE32F-NEXT: .LBB102_2: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_44
+; RV64ZVE32F-NEXT: .LBB102_3: # %else4
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_5
+; RV64ZVE32F-NEXT: .LBB102_4: # %cond.store5
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 3
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB102_5: # %else6
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 4
+; RV64ZVE32F-NEXT: andi a2, a1, 16
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_45
+; RV64ZVE32F-NEXT: # %bb.6: # %else8
+; RV64ZVE32F-NEXT: andi a2, a1, 32
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_46
+; RV64ZVE32F-NEXT: .LBB102_7: # %else10
+; RV64ZVE32F-NEXT: andi a2, a1, 64
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_47
+; RV64ZVE32F-NEXT: .LBB102_8: # %else12
+; RV64ZVE32F-NEXT: andi a2, a1, 128
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_10
+; RV64ZVE32F-NEXT: .LBB102_9: # %cond.store13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 7
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB102_10: # %else14
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 8
+; RV64ZVE32F-NEXT: andi a2, a1, 256
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_48
+; RV64ZVE32F-NEXT: # %bb.11: # %else16
+; RV64ZVE32F-NEXT: andi a2, a1, 512
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_49
+; RV64ZVE32F-NEXT: .LBB102_12: # %else18
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_50
+; RV64ZVE32F-NEXT: .LBB102_13: # %else20
+; RV64ZVE32F-NEXT: slli a2, a1, 52
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_15
+; RV64ZVE32F-NEXT: .LBB102_14: # %cond.store21
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 11
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v13, (a2)
+; RV64ZVE32F-NEXT: .LBB102_15: # %else22
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 51
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_51
+; RV64ZVE32F-NEXT: # %bb.16: # %else24
+; RV64ZVE32F-NEXT: slli a2, a1, 50
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_52
+; RV64ZVE32F-NEXT: .LBB102_17: # %else26
+; RV64ZVE32F-NEXT: slli a2, a1, 49
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_19
+; RV64ZVE32F-NEXT: .LBB102_18: # %cond.store27
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v13
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 14
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vse8.v v13, (a2)
+; RV64ZVE32F-NEXT: .LBB102_19: # %else28
+; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 16
+; RV64ZVE32F-NEXT: slli a2, a1, 48
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_53
+; RV64ZVE32F-NEXT: # %bb.20: # %else30
+; RV64ZVE32F-NEXT: slli a2, a1, 47
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_54
+; RV64ZVE32F-NEXT: .LBB102_21: # %else32
+; RV64ZVE32F-NEXT: slli a2, a1, 46
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_55
+; RV64ZVE32F-NEXT: .LBB102_22: # %else34
+; RV64ZVE32F-NEXT: slli a2, a1, 45
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_56
+; RV64ZVE32F-NEXT: .LBB102_23: # %else36
+; RV64ZVE32F-NEXT: slli a2, a1, 44
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_25
+; RV64ZVE32F-NEXT: .LBB102_24: # %cond.store37
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 19
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB102_25: # %else38
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 43
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_57
+; RV64ZVE32F-NEXT: # %bb.26: # %else40
+; RV64ZVE32F-NEXT: slli a2, a1, 42
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_58
+; RV64ZVE32F-NEXT: .LBB102_27: # %else42
+; RV64ZVE32F-NEXT: slli a2, a1, 41
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_59
+; RV64ZVE32F-NEXT: .LBB102_28: # %else44
+; RV64ZVE32F-NEXT: slli a2, a1, 40
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_30
+; RV64ZVE32F-NEXT: .LBB102_29: # %cond.store45
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 23
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB102_30: # %else46
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 8
+; RV64ZVE32F-NEXT: slli a2, a1, 39
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_60
+; RV64ZVE32F-NEXT: # %bb.31: # %else48
+; RV64ZVE32F-NEXT: slli a2, a1, 38
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_61
+; RV64ZVE32F-NEXT: .LBB102_32: # %else50
+; RV64ZVE32F-NEXT: slli a2, a1, 37
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_62
+; RV64ZVE32F-NEXT: .LBB102_33: # %else52
+; RV64ZVE32F-NEXT: slli a2, a1, 36
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_35
+; RV64ZVE32F-NEXT: .LBB102_34: # %cond.store53
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 27
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB102_35: # %else54
+; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
+; RV64ZVE32F-NEXT: slli a2, a1, 35
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_63
+; RV64ZVE32F-NEXT: # %bb.36: # %else56
+; RV64ZVE32F-NEXT: slli a2, a1, 34
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_64
+; RV64ZVE32F-NEXT: .LBB102_37: # %else58
+; RV64ZVE32F-NEXT: slli a2, a1, 33
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_39
+; RV64ZVE32F-NEXT: .LBB102_38: # %cond.store59
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 30
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
+; RV64ZVE32F-NEXT: .LBB102_39: # %else60
+; RV64ZVE32F-NEXT: lui a2, 524288
+; RV64ZVE32F-NEXT: and a1, a1, a2
+; RV64ZVE32F-NEXT: beqz a1, .LBB102_41
+; RV64ZVE32F-NEXT: # %bb.40: # %cond.store61
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 3
+; RV64ZVE32F-NEXT: vmv.x.s a1, v10
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 31
+; RV64ZVE32F-NEXT: add a0, a0, a1
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vse8.v v8, (a0)
+; RV64ZVE32F-NEXT: .LBB102_41: # %else62
+; RV64ZVE32F-NEXT: ret
+; RV64ZVE32F-NEXT: .LBB102_42: # %cond.store
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v8, (a2)
-; RV64ZVE32F-NEXT: .LBB102_2: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_4
-; RV64ZVE32F-NEXT: # %bb.3: # %cond.store1
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_2
+; RV64ZVE32F-NEXT: .LBB102_43: # %cond.store1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
@@ -12080,43 +12809,28 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_4: # %else2
+; RV64ZVE32F-NEXT: andi a2, a1, 4
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_3
+; RV64ZVE32F-NEXT: .LBB102_44: # %cond.store3
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 4
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_6
-; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 2
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_6: # %else4
-; RV64ZVE32F-NEXT: andi a2, a1, 8
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_8
-; RV64ZVE32F-NEXT: # %bb.7: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 3
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 2
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_8: # %else6
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 4
-; RV64ZVE32F-NEXT: andi a2, a1, 16
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_10
-; RV64ZVE32F-NEXT: # %bb.9: # %cond.store7
+; RV64ZVE32F-NEXT: andi a2, a1, 8
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_4
+; RV64ZVE32F-NEXT: j .LBB102_5
+; RV64ZVE32F-NEXT: .LBB102_45: # %cond.store7
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 4
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_10: # %else8
; RV64ZVE32F-NEXT: andi a2, a1, 32
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_12
-; RV64ZVE32F-NEXT: # %bb.11: # %cond.store9
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_7
+; RV64ZVE32F-NEXT: .LBB102_46: # %cond.store9
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
@@ -12124,43 +12838,28 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 5
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_12: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 2
; RV64ZVE32F-NEXT: andi a2, a1, 64
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_14
-; RV64ZVE32F-NEXT: # %bb.13: # %cond.store11
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_8
+; RV64ZVE32F-NEXT: .LBB102_47: # %cond.store11
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 6
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_14: # %else12
; RV64ZVE32F-NEXT: andi a2, a1, 128
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_16
-; RV64ZVE32F-NEXT: # %bb.15: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 7
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_16: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 8
-; RV64ZVE32F-NEXT: andi a2, a1, 256
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_18
-; RV64ZVE32F-NEXT: # %bb.17: # %cond.store15
+; RV64ZVE32F-NEXT: bnez a2, .LBB102_9
+; RV64ZVE32F-NEXT: j .LBB102_10
+; RV64ZVE32F-NEXT: .LBB102_48: # %cond.store15
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_18: # %else16
; RV64ZVE32F-NEXT: andi a2, a1, 512
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_20
-; RV64ZVE32F-NEXT: # %bb.19: # %cond.store17
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_12
+; RV64ZVE32F-NEXT: .LBB102_49: # %cond.store17
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
@@ -12168,43 +12867,28 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 9
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_20: # %else18
+; RV64ZVE32F-NEXT: andi a2, a1, 1024
+; RV64ZVE32F-NEXT: beqz a2, .LBB102_13
+; RV64ZVE32F-NEXT: .LBB102_50: # %cond.store19
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 2
-; RV64ZVE32F-NEXT: andi a2, a1, 1024
-; RV64ZVE32F-NEXT: beqz a2, .LBB102_22
-; RV64ZVE32F-NEXT: # %bb.21: # %cond.store19
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 10
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v14, (a2)
-; RV64ZVE32F-NEXT: .LBB102_22: # %else20
-; RV64ZVE32F-NEXT: slli a2, a1, 52
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_24
-; RV64ZVE32F-NEXT: # %bb.23: # %cond.store21
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 11
+; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 10
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_24: # %else22
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 51
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_26
-; RV64ZVE32F-NEXT: # %bb.25: # %cond.store23
+; RV64ZVE32F-NEXT: slli a2, a1, 52
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_14
+; RV64ZVE32F-NEXT: j .LBB102_15
+; RV64ZVE32F-NEXT: .LBB102_51: # %cond.store23
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 12
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_26: # %else24
; RV64ZVE32F-NEXT: slli a2, a1, 50
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_28
-; RV64ZVE32F-NEXT: # %bb.27: # %cond.store25
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_17
+; RV64ZVE32F-NEXT: .LBB102_52: # %cond.store25
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v13
@@ -12212,29 +12896,29 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 13
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_28: # %else26
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 2
; RV64ZVE32F-NEXT: slli a2, a1, 49
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_30
-; RV64ZVE32F-NEXT: # %bb.29: # %cond.store27
-; RV64ZVE32F-NEXT: vmv.x.s a2, v12
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_18
+; RV64ZVE32F-NEXT: j .LBB102_19
+; RV64ZVE32F-NEXT: .LBB102_53: # %cond.store29
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 3
+; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v13, v8, 14
+; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 15
; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v13, (a2)
-; RV64ZVE32F-NEXT: .LBB102_30: # %else28
-; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 16
-; RV64ZVE32F-NEXT: slli a2, a1, 48
-; RV64ZVE32F-NEXT: bltz a2, .LBB102_63
-; RV64ZVE32F-NEXT: # %bb.31: # %else30
+; RV64ZVE32F-NEXT: vse8.v v11, (a2)
; RV64ZVE32F-NEXT: slli a2, a1, 47
-; RV64ZVE32F-NEXT: bltz a2, .LBB102_64
-; RV64ZVE32F-NEXT: .LBB102_32: # %else32
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_21
+; RV64ZVE32F-NEXT: .LBB102_54: # %cond.store31
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
+; RV64ZVE32F-NEXT: vmv.x.s a2, v10
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 16
+; RV64ZVE32F-NEXT: add a2, a0, a2
+; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; RV64ZVE32F-NEXT: vse8.v v12, (a2)
; RV64ZVE32F-NEXT: slli a2, a1, 46
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_34
-; RV64ZVE32F-NEXT: .LBB102_33: # %cond.store33
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_22
+; RV64ZVE32F-NEXT: .LBB102_55: # %cond.store33
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -12243,46 +12927,30 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_34: # %else34
+; RV64ZVE32F-NEXT: slli a2, a1, 45
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_23
+; RV64ZVE32F-NEXT: .LBB102_56: # %cond.store35
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: slli a2, a1, 45
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_36
-; RV64ZVE32F-NEXT: # %bb.35: # %cond.store35
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 18
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_36: # %else36
; RV64ZVE32F-NEXT: slli a2, a1, 44
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_38
-; RV64ZVE32F-NEXT: # %bb.37: # %cond.store37
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 19
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_38: # %else38
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 43
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_40
-; RV64ZVE32F-NEXT: # %bb.39: # %cond.store39
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_24
+; RV64ZVE32F-NEXT: j .LBB102_25
+; RV64ZVE32F-NEXT: .LBB102_57: # %cond.store39
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 20
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_40: # %else40
; RV64ZVE32F-NEXT: slli a2, a1, 42
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_42
-; RV64ZVE32F-NEXT: # %bb.41: # %cond.store41
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_27
+; RV64ZVE32F-NEXT: .LBB102_58: # %cond.store41
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v11, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v12
@@ -12291,46 +12959,30 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_42: # %else42
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 2
; RV64ZVE32F-NEXT: slli a2, a1, 41
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_44
-; RV64ZVE32F-NEXT: # %bb.43: # %cond.store43
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_28
+; RV64ZVE32F-NEXT: .LBB102_59: # %cond.store43
+; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64ZVE32F-NEXT: vslidedown.vi v12, v11, 2
+; RV64ZVE32F-NEXT: vmv.x.s a2, v12
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 22
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_44: # %else44
; RV64ZVE32F-NEXT: slli a2, a1, 40
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_46
-; RV64ZVE32F-NEXT: # %bb.45: # %cond.store45
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 23
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_46: # %else46
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 8
-; RV64ZVE32F-NEXT: slli a2, a1, 39
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_48
-; RV64ZVE32F-NEXT: # %bb.47: # %cond.store47
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_29
+; RV64ZVE32F-NEXT: j .LBB102_30
+; RV64ZVE32F-NEXT: .LBB102_60: # %cond.store47
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 24
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_48: # %else48
; RV64ZVE32F-NEXT: slli a2, a1, 38
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_50
-; RV64ZVE32F-NEXT: # %bb.49: # %cond.store49
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_32
+; RV64ZVE32F-NEXT: .LBB102_61: # %cond.store49
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -12339,46 +12991,30 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_50: # %else50
+; RV64ZVE32F-NEXT: slli a2, a1, 37
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_33
+; RV64ZVE32F-NEXT: .LBB102_62: # %cond.store51
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 2
-; RV64ZVE32F-NEXT: slli a2, a1, 37
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_52
-; RV64ZVE32F-NEXT: # %bb.51: # %cond.store51
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 26
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_52: # %else52
; RV64ZVE32F-NEXT: slli a2, a1, 36
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_54
-; RV64ZVE32F-NEXT: # %bb.53: # %cond.store53
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 27
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_54: # %else54
-; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 4
-; RV64ZVE32F-NEXT: slli a2, a1, 35
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_56
-; RV64ZVE32F-NEXT: # %bb.55: # %cond.store55
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_34
+; RV64ZVE32F-NEXT: j .LBB102_35
+; RV64ZVE32F-NEXT: .LBB102_63: # %cond.store55
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 28
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_56: # %else56
; RV64ZVE32F-NEXT: slli a2, a1, 34
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_58
-; RV64ZVE32F-NEXT: # %bb.57: # %cond.store57
+; RV64ZVE32F-NEXT: bgez a2, .LBB102_37
+; RV64ZVE32F-NEXT: .LBB102_64: # %cond.store57
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v11
@@ -12387,53 +13023,9 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_58: # %else58
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 2
; RV64ZVE32F-NEXT: slli a2, a1, 33
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_60
-; RV64ZVE32F-NEXT: # %bb.59: # %cond.store59
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 30
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: .LBB102_60: # %else60
-; RV64ZVE32F-NEXT: lui a2, 524288
-; RV64ZVE32F-NEXT: and a1, a1, a2
-; RV64ZVE32F-NEXT: beqz a1, .LBB102_62
-; RV64ZVE32F-NEXT: # %bb.61: # %cond.store61
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1
-; RV64ZVE32F-NEXT: vmv.x.s a1, v10
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 31
-; RV64ZVE32F-NEXT: add a0, a0, a1
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vse8.v v8, (a0)
-; RV64ZVE32F-NEXT: .LBB102_62: # %else62
-; RV64ZVE32F-NEXT: ret
-; RV64ZVE32F-NEXT: .LBB102_63: # %cond.store29
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 1
-; RV64ZVE32F-NEXT: vmv.x.s a2, v11
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 15
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vse8.v v11, (a2)
-; RV64ZVE32F-NEXT: slli a2, a1, 47
-; RV64ZVE32F-NEXT: bgez a2, .LBB102_32
-; RV64ZVE32F-NEXT: .LBB102_64: # %cond.store31
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a2, v10
-; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 16
-; RV64ZVE32F-NEXT: add a2, a0, a2
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64ZVE32F-NEXT: vse8.v v12, (a2)
-; RV64ZVE32F-NEXT: slli a2, a1, 46
-; RV64ZVE32F-NEXT: bltz a2, .LBB102_33
-; RV64ZVE32F-NEXT: j .LBB102_34
+; RV64ZVE32F-NEXT: bltz a2, .LBB102_38
+; RV64ZVE32F-NEXT: j .LBB102_39
%ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs
call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> %val, <32 x ptr> %ptrs, i32 1, <32 x i1> %m)
ret void
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index f5bebd1208195..680e0d3a9e649 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -350,12 +350,6 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVZIP-ZVL2048-NEXT: vzip.vv v9, v8, v10
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, m1, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v9, v12
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v8, 4
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 6
; ZVZIP-ZVL2048-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
@@ -10757,19 +10751,6 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVZIP-ZVL2048-NEXT: vzip.vv v11, v10, v9
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf4, ta, ma
; ZVZIP-ZVL2048-NEXT: vzip.vv v8, v11, v12
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v8, 8
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v9, 2
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v9, 4
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 12, e8, mf8, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 10
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 14, e8, mf8, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 12
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 6
-; ZVZIP-ZVL2048-NEXT: vsetivli zero, 16, e8, mf8, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 14
; ZVZIP-ZVL2048-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
ret <16 x i8> %res
@@ -11287,7 +11268,7 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e32, mf2, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 4
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v9, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 6
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e32, mf2, ta, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 6
; ZVZIP-ZVL2048-NEXT: ret
@@ -12233,15 +12214,15 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 4
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 3
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 1
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 5
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 6
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 5
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 6
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 6
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 7
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 7
; ZVZIP-ZVL2048-NEXT: ret
@@ -12401,15 +12382,15 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 4
; ZVZIP-ZVL2048-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 3
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 1
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 5
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 5, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v11, v10, 2
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v10, v12, 6
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 6, e16, mf4, tu, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 5
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 7, e16, mf4, tu, ma
-; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v11, 6
-; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v10, 3
+; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v10, 6
+; ZVZIP-ZVL2048-NEXT: vslidedown.vi v9, v12, 7
; ZVZIP-ZVL2048-NEXT: vsetivli zero, 8, e16, mf4, ta, ma
; ZVZIP-ZVL2048-NEXT: vslideup.vi v8, v9, 7
; ZVZIP-ZVL2048-NEXT: ret
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