[clang] [llvm] [RISCV][P-Ext] Add builtins and IR intrinsics for packed shifts. (PR #225968)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 15:53:47 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-backend-x86
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
The packed shift instructions use 5-bit shift amounts regardless of element width. The C intrinsic should match this which means we can't use C shift operators to implement them.
---
Patch is 68.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225968.diff
9 Files Affected:
- (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+19)
- (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+37)
- (modified) clang/lib/Headers/riscv_packed_simd.h (+23-36)
- (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+120-272)
- (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+5)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+15-3)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+15-15)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+58-4)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+144-18)
``````````diff
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 9065e9e363a56..046692899b237 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -203,6 +203,25 @@ def paas_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int
def pasa_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, short>)">;
def pasa_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">;
+// Packed Shifts (32-bit)
+def psll_s_u8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<4, unsigned char>, unsigned int)">;
+def psll_s_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>, unsigned int)">;
+def psrl_s_u8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<4, unsigned char>, unsigned int)">;
+def psrl_s_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>, unsigned int)">;
+def psra_s_i8x4 : RISCVBuiltin<"_Vector<4, signed char>(_Vector<4, signed char>, unsigned int)">;
+def psra_s_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, unsigned int)">;
+
+// Packed Shifts (64-bit)
+def psll_s_u8x8 : RISCVBuiltin<"_Vector<8, unsigned char>(_Vector<8, unsigned char>, unsigned int)">;
+def psll_s_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned short>, unsigned int)">;
+def psll_s_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, unsigned int)">;
+def psrl_s_u8x8 : RISCVBuiltin<"_Vector<8, unsigned char>(_Vector<8, unsigned char>, unsigned int)">;
+def psrl_s_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned short>, unsigned int)">;
+def psrl_s_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, unsigned int)">;
+def psra_s_i8x8 : RISCVBuiltin<"_Vector<8, signed char>(_Vector<8, signed char>, unsigned int)">;
+def psra_s_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, unsigned int)">;
+def psra_s_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, unsigned int)">;
+
// Packed Absolute Value and Absolute Difference (32-bit)
def pabd_i8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<4, signed char>, _Vector<4, signed char>)">;
def pabd_i16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, short>, _Vector<2, short>)">;
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 82c69f5d87dcf..b1892d6e09278 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1239,6 +1239,22 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_pasa_x_i16x2:
case RISCV::BI__builtin_riscv_pasa_x_i16x4:
case RISCV::BI__builtin_riscv_pasa_x_i32x2:
+ // Packed Shift
+ case RISCV::BI__builtin_riscv_psll_s_u8x4:
+ case RISCV::BI__builtin_riscv_psll_s_u16x2:
+ case RISCV::BI__builtin_riscv_psll_s_u8x8:
+ case RISCV::BI__builtin_riscv_psll_s_u16x4:
+ case RISCV::BI__builtin_riscv_psll_s_u32x2:
+ case RISCV::BI__builtin_riscv_psrl_s_u8x4:
+ case RISCV::BI__builtin_riscv_psrl_s_u16x2:
+ case RISCV::BI__builtin_riscv_psrl_s_u8x8:
+ case RISCV::BI__builtin_riscv_psrl_s_u16x4:
+ case RISCV::BI__builtin_riscv_psrl_s_u32x2:
+ case RISCV::BI__builtin_riscv_psra_s_i8x4:
+ case RISCV::BI__builtin_riscv_psra_s_i16x2:
+ case RISCV::BI__builtin_riscv_psra_s_i8x8:
+ case RISCV::BI__builtin_riscv_psra_s_i16x4:
+ case RISCV::BI__builtin_riscv_psra_s_i32x2:
// Packed Absolute Value and Absolute Difference
case RISCV::BI__builtin_riscv_pabd_i8x4:
case RISCV::BI__builtin_riscv_pabd_i16x2:
@@ -1390,6 +1406,27 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_pasa_x_i32x2:
ID = Intrinsic::riscv_pasa;
break;
+ case RISCV::BI__builtin_riscv_psll_s_u8x4:
+ case RISCV::BI__builtin_riscv_psll_s_u16x2:
+ case RISCV::BI__builtin_riscv_psll_s_u8x8:
+ case RISCV::BI__builtin_riscv_psll_s_u16x4:
+ case RISCV::BI__builtin_riscv_psll_s_u32x2:
+ ID = Intrinsic::riscv_psll;
+ break;
+ case RISCV::BI__builtin_riscv_psrl_s_u8x4:
+ case RISCV::BI__builtin_riscv_psrl_s_u16x2:
+ case RISCV::BI__builtin_riscv_psrl_s_u8x8:
+ case RISCV::BI__builtin_riscv_psrl_s_u16x4:
+ case RISCV::BI__builtin_riscv_psrl_s_u32x2:
+ ID = Intrinsic::riscv_psrl;
+ break;
+ case RISCV::BI__builtin_riscv_psra_s_i8x4:
+ case RISCV::BI__builtin_riscv_psra_s_i16x2:
+ case RISCV::BI__builtin_riscv_psra_s_i8x8:
+ case RISCV::BI__builtin_riscv_psra_s_i16x4:
+ case RISCV::BI__builtin_riscv_psra_s_i32x2:
+ ID = Intrinsic::riscv_psra;
+ break;
case RISCV::BI__builtin_riscv_pabd_i8x4:
case RISCV::BI__builtin_riscv_pabd_i16x2:
case RISCV::BI__builtin_riscv_pabd_i8x8:
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index 2cee5987c1dac..53062e62f17a1 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -41,15 +41,6 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return splat(ty, __x); \
}
-#define __packed_shift(name, ty, op, mask) \
- static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
- unsigned __rs2) { \
- return __rs1 op(__rs2 & (mask)); \
- }
-#define __packed_shift8(name, ty, op) __packed_shift(name, ty, op, 0x7)
-#define __packed_shift16(name, ty, op) __packed_shift(name, ty, op, 0xf)
-#define __packed_shift32(name, ty, op) __packed_shift(name, ty, op, 0x1f)
-
#define __packed_scalar_binary_op(name, ty, scalar_ty, op, splat) \
static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
scalar_ty __rs2) { \
@@ -610,29 +601,29 @@ __packed_cmp(pmsgeu_u32x2, uint32x2_t, uint32x2_t, >=)
__packed_cmp(pmsle_u32x2, int32x2_t, uint32x2_t, <=)
__packed_cmp(pmsleu_u32x2, uint32x2_t, uint32x2_t, <=)
-/* Packed Shifts (32-bit) */
-__packed_shift8(psll_s_u8x4, uint8x4_t, <<)
-__packed_shift8(psll_s_i8x4, int8x4_t, <<)
-__packed_shift16(psll_s_u16x2, uint16x2_t, <<)
-__packed_shift16(psll_s_i16x2, int16x2_t, <<)
-__packed_shift8(psrl_s_u8x4, uint8x4_t, >>)
-__packed_shift16(psrl_s_u16x2, uint16x2_t, >>)
-__packed_shift8(psra_s_i8x4, int8x4_t, >>)
-__packed_shift16(psra_s_i16x2, int16x2_t, >>)
-
-/* Packed Shifts (64-bit) */
-__packed_shift8(psll_s_u8x8, uint8x8_t, <<)
-__packed_shift8(psll_s_i8x8, int8x8_t, <<)
-__packed_shift16(psll_s_u16x4, uint16x4_t, <<)
-__packed_shift16(psll_s_i16x4, int16x4_t, <<)
-__packed_shift32(psll_s_u32x2, uint32x2_t, <<)
-__packed_shift32(psll_s_i32x2, int32x2_t, <<)
-__packed_shift8(psrl_s_u8x8, uint8x8_t, >>)
-__packed_shift16(psrl_s_u16x4, uint16x4_t, >>)
-__packed_shift32(psrl_s_u32x2, uint32x2_t, >>)
-__packed_shift8(psra_s_i8x8, int8x8_t, >>)
-__packed_shift16(psra_s_i16x4, int16x4_t, >>)
-__packed_shift32(psra_s_i32x2, int32x2_t, >>)
+/* Packed Shift (32-bit) */
+__packed_binary_builtin_mixed(psll_s_u8x4, uint8x4_t, uint8x4_t, unsigned int, __builtin_riscv_psll_s_u8x4)
+__packed_binary_builtin_mixed(psll_s_i8x4, int8x4_t, int8x4_t, unsigned int, __builtin_riscv_psll_s_u8x4)
+__packed_binary_builtin_mixed(psll_s_u16x2, uint16x2_t, uint16x2_t, unsigned int, __builtin_riscv_psll_s_u16x2)
+__packed_binary_builtin_mixed(psll_s_i16x2, int16x2_t, int16x2_t, unsigned int, __builtin_riscv_psll_s_u16x2)
+__packed_binary_builtin_mixed(psrl_s_u8x4, uint8x4_t, uint8x4_t, unsigned int, __builtin_riscv_psrl_s_u8x4)
+__packed_binary_builtin_mixed(psrl_s_u16x2, uint16x2_t, uint16x2_t, unsigned int, __builtin_riscv_psrl_s_u16x2)
+__packed_binary_builtin_mixed(psra_s_i8x4, int8x4_t, int8x4_t, unsigned int, __builtin_riscv_psra_s_i8x4)
+__packed_binary_builtin_mixed(psra_s_i16x2, int16x2_t, int16x2_t, unsigned int, __builtin_riscv_psra_s_i16x2)
+
+/* Packed Shift (64-bit) */
+__packed_binary_builtin_mixed(psll_s_u8x8, uint8x8_t, uint8x8_t, unsigned int, __builtin_riscv_psll_s_u8x8)
+__packed_binary_builtin_mixed(psll_s_i8x8, int8x8_t, int8x8_t, unsigned int, __builtin_riscv_psll_s_u8x8)
+__packed_binary_builtin_mixed(psll_s_u16x4, uint16x4_t, uint16x4_t, unsigned int, __builtin_riscv_psll_s_u16x4)
+__packed_binary_builtin_mixed(psll_s_i16x4, int16x4_t, int16x4_t, unsigned int, __builtin_riscv_psll_s_u16x4)
+__packed_binary_builtin_mixed(psll_s_u32x2, uint32x2_t, uint32x2_t, unsigned int, __builtin_riscv_psll_s_u32x2)
+__packed_binary_builtin_mixed(psll_s_i32x2, int32x2_t, int32x2_t, unsigned int, __builtin_riscv_psll_s_u32x2)
+__packed_binary_builtin_mixed(psrl_s_u8x8, uint8x8_t, uint8x8_t, unsigned int, __builtin_riscv_psrl_s_u8x8)
+__packed_binary_builtin_mixed(psrl_s_u16x4, uint16x4_t, uint16x4_t, unsigned int, __builtin_riscv_psrl_s_u16x4)
+__packed_binary_builtin_mixed(psrl_s_u32x2, uint32x2_t, uint32x2_t, unsigned int, __builtin_riscv_psrl_s_u32x2)
+__packed_binary_builtin_mixed(psra_s_i8x8, int8x8_t, int8x8_t, unsigned int, __builtin_riscv_psra_s_i8x8)
+__packed_binary_builtin_mixed(psra_s_i16x4, int16x4_t, int16x4_t, unsigned int, __builtin_riscv_psra_s_i16x4)
+__packed_binary_builtin_mixed(psra_s_i32x2, int32x2_t, int32x2_t, unsigned int, __builtin_riscv_psra_s_i32x2)
/* Packed Saturating and Rounding Shifts (32-bit) */
__packed_binary_builtin_mixed(pssha_s_i16x2, int16x2_t, int16x2_t, int, __builtin_riscv_pssha_s_i16x2)
@@ -1313,10 +1304,6 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t)
#undef __packed_splat4
#undef __packed_splat8
#undef __packed_splat
-#undef __packed_shift
-#undef __packed_shift8
-#undef __packed_shift16
-#undef __packed_shift32
#undef __packed_scalar_binary_op
#undef __packed_binary_op
#undef __packed_unary_op
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 0792df58dbfb4..c24f7971a4aa1 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -4082,25 +4082,17 @@ uint32x2_t test_pmsleu_u32x2(uint32x2_t a, uint32x2_t b) {
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*:]]
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
-// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
-// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
-// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
+// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psll.v4i8(<4 x i8> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
//
// RV64-LABEL: define dso_local i32 @test_psll_s_i8x4(
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
-// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
-// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
-// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psll.v4i8(<4 x i8> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_psll_s_i8x4(int8x4_t a, unsigned shamt) {
return __riscv_psll_s_i8x4(a, shamt);
@@ -4110,25 +4102,17 @@ int8x4_t test_psll_s_i8x4(int8x4_t a, unsigned shamt) {
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*:]]
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
-// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
-// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
-// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
+// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psll.v4i8(<4 x i8> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
//
// RV64-LABEL: define dso_local i32 @test_psll_s_u8x4(
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
-// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
-// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
-// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psll.v4i8(<4 x i8> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
//
uint8x4_t test_psll_s_u8x4(uint8x4_t a, unsigned shamt) {
return __riscv_psll_s_u8x4(a, shamt);
@@ -4138,25 +4122,17 @@ uint8x4_t test_psll_s_u8x4(uint8x4_t a, unsigned shamt) {
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*:]]
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
-// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
-// RV32-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
-// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
+// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psll.v2i16(<2 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
//
// RV64-LABEL: define dso_local i32 @test_psll_s_i16x2(
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
-// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
-// RV64-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
-// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psll.v2i16(<2 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
//
int16x2_t test_psll_s_i16x2(int16x2_t a, unsigned shamt) {
return __riscv_psll_s_i16x2(a, shamt);
@@ -4166,25 +4142,17 @@ int16x2_t test_psll_s_i16x2(int16x2_t a, unsigned shamt) {
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*:]]
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
-// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
-// RV32-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
-// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
+// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psll.v2i16(<2 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
//
// RV64-LABEL: define dso_local i32 @test_psll_s_u16x2(
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
-// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
-// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
-// RV64-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
-// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
-// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psll.v2i16(<2 x i16> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
//
uint16x2_t test_psll_s_u16x2(uint16x2_t a, unsigned shamt) {
return __riscv_psll_s_u16x2(a, shamt);
@@ -4194,25 +4162,17 @@ uint16x2_t test_psll_s_u16x2(uint16x2_t a, unsigned shamt) {
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*:]]
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
-// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
-// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
-// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV32-NEXT: [[SHR_I:%.*]] = ashr <4 x i8> [[TMP0]], [[SH_PROM_I]]
-// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHR_I]] to i32
-// RV32-NEXT: ret i32 [[TMP4]]
+// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psra.v4i8(<4 x i8> [[TMP0]], i32 [[SHAMT]])
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
//
// RV64-LABEL: define dso_local i32 @test_psra_s_i8x4(
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
// RV64-NEXT: [[ENTRY:.*:]]
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
-// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
-// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
-// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
-// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
-// RV64-NEXT: [[SHR_I:%.*]] = ashr <4 x i8> [[TMP0]], [[SH_PROM_I]]
-// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHR_I]] to i32
-// RV64-NEXT: ret i32 [[TMP4]]
+// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psra.v4i8(<4 x i8> [[TMP0]], i32 [[SHAMT]])
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
//
int8x4_t test_psra_s_i8x4(int8x4_t a, unsigned shamt) {
return __riscv_psra_s_i8x4(a, shamt);
@@ -4222,25 +4182,17 @@ int8x4_t test_psra_s_i8x4(int8x4_t a, unsigned shamt) {
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
// RV32-NEXT: [[ENTRY:.*...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225968
More information about the llvm-commits
mailing list