[llvm] [GlobalISel] Use register class constrain in copy propagation (PR #201148)
Igor Wodiany via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 12:52:06 PDT 2026
https://github.com/IgWod updated https://github.com/llvm/llvm-project/pull/201148
>From 4844147bb0767904eb04977ef1be0ebe6d4e928c Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Mon, 13 Apr 2026 10:55:56 +0100
Subject: [PATCH] [GlobalISel] Use register class constrain in copy propagation
Instead of completely disallowing sub-registers in copy propagation constrain source register using register classes.
This is a follow up on #188781.
Assisted-by: Claude Code
---
.../CodeGen/GlobalISel/InstructionSelect.cpp | 28 +-
.../AArch64/Atomics/aarch64-atomicrmw-lse2.ll | 1770 ++++-----
.../Atomics/aarch64-atomicrmw-lse2_lse128.ll | 120 +-
.../AArch64/Atomics/aarch64-atomicrmw-lsfe.ll | 172 +-
.../aarch64-atomicrmw-outline_atomics.ll | 150 +-
.../AArch64/Atomics/aarch64-atomicrmw-rcpc.ll | 1770 ++++-----
.../Atomics/aarch64-atomicrmw-rcpc3.ll | 1770 ++++-----
.../Atomics/aarch64-atomicrmw-v8_1a.ll | 120 +-
.../AArch64/Atomics/aarch64-atomicrmw-v8a.ll | 1770 ++++-----
.../Atomics/aarch64-atomicrmw-v8a_fp.ll | 120 +-
.../AArch64/GlobalISel/arm64-atomic.ll | 3323 +++++++++++------
.../AArch64/GlobalISel/contract-store.mir | 3 +-
.../GlobalISel/load-addressing-modes.mir | 44 +-
.../GlobalISel/load-wro-addressing-modes.mir | 5 +-
.../GlobalISel/opt-fold-and-tbz-tbnz.mir | 15 +-
.../GlobalISel/opt-fold-ext-tbz-tbnz.mir | 10 +-
.../GlobalISel/opt-fold-shift-tbz-tbnz.mir | 25 +-
.../GlobalISel/opt-fold-trunc-tbz-tbnz.mir | 5 +-
.../GlobalISel/opt-fold-xor-tbz-tbnz.mir | 25 +-
...galizer-lowering-swap-compare-operands.mir | 30 +-
.../GlobalISel/select-arith-extended-reg.mir | 25 +-
.../GlobalISel/select-blockaddress.mir | 6 +-
.../CodeGen/AArch64/GlobalISel/select-cmp.mir | 5 +-
.../AArch64/GlobalISel/select-constant.mir | 18 +-
.../CodeGen/AArch64/GlobalISel/select-dup.mir | 8 +-
.../AArch64/GlobalISel/select-extload.mir | 5 +-
.../GlobalISel/select-gv-cmodel-large.mir | 20 +-
.../GlobalISel/select-gv-cmodel-tiny.mir | 12 +-
.../GlobalISel/select-implicit-def.mir | 21 +-
.../GlobalISel/select-insert-extract.mir | 19 +-
.../AArch64/GlobalISel/select-int-ext.mir | 203 +-
.../GlobalISel/select-int-ptr-casts.mir | 16 +-
.../AArch64/GlobalISel/select-load.mir | 20 +-
.../AArch64/GlobalISel/select-ptr-add.mir | 15 +-
.../select-redundant-zext-of-load.mir | 10 +-
.../GlobalISel/select-redundant-zext.mir | 5 +-
.../GlobalISel/select-shuffle-vector.mir | 60 +-
.../AArch64/GlobalISel/select-store.mir | 20 +-
.../AArch64/GlobalISel/select-trunc.mir | 40 +-
.../GlobalISel/select-zext-as-copy.mir | 7 +-
.../AArch64/GlobalISel/select-zextload.mir | 5 +-
.../CodeGen/AArch64/GlobalISel/select.mir | 61 +-
.../GlobalISel/sext-inreg-ldrow-16b.mir | 5 +-
.../GlobalISel/store-addressing-modes.mir | 16 +-
.../GlobalISel/store-wro-addressing-modes.mir | 5 +-
.../AArch64/GlobalISel/subreg-copy.mir | 10 +-
.../GlobalISel/widen-narrow-tbz-tbnz.mir | 5 +-
.../xro-addressing-mode-constant.mir | 5 +-
llvm/test/CodeGen/AArch64/popcount.ll | 26 +-
llvm/test/CodeGen/AArch64/ptrauth-isel.ll | 9 +-
.../AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll | 116 +-
.../GlobalISel/dropped_debug_info_assert.ll | 30 +-
.../global-atomic-fadd.f32-no-rtn.ll | 181 +-
.../GlobalISel/global-atomic-fadd.f32-rtn.ll | 133 +-
.../AMDGPU/GlobalISel/inst-select-and.mir | 9 +-
.../AMDGPU/GlobalISel/inst-select-anyext.mir | 11 +-
.../AMDGPU/GlobalISel/inst-select-copy.mir | 10 +-
.../AMDGPU/GlobalISel/inst-select-fabs.mir | 60 +-
.../AMDGPU/GlobalISel/inst-select-fneg.mir | 60 +-
.../GlobalISel/inst-select-fract.f64.mir | 20 +-
.../AMDGPU/GlobalISel/inst-select-freeze.mir | 20 +-
.../AMDGPU/GlobalISel/inst-select-or.mir | 9 +-
...st-select-pseudo-scalar-transcendental.mir | 78 +-
.../AMDGPU/GlobalISel/inst-select-sext.mir | 14 +-
.../GlobalISel/inst-select-store-local.mir | 51 +
.../GlobalISel/inst-select-unmerge-values.mir | 10 +-
.../AMDGPU/GlobalISel/inst-select-xor.mir | 9 +-
.../AMDGPU/GlobalISel/inst-select-zext.mir | 9 +-
.../llvm.amdgcn.make.buffer.rsrc.ll | 80 +-
.../llvm.amdgcn.raw.buffer.atomic.cmpswap.ll | 99 +-
.../llvm.amdgcn.raw.buffer.load.tfe.ll | 16 +-
.../llvm.amdgcn.raw.buffer.store.ll | 10 +-
...vm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll | 33 +-
.../llvm.amdgcn.raw.ptr.buffer.store.ll | 5 +-
.../GlobalISel/llvm.amdgcn.s.buffer.load.ll | 586 ++-
...lvm.amdgcn.struct.buffer.atomic.cmpswap.ll | 99 +-
.../llvm.amdgcn.struct.buffer.load.tfe.ll | 16 +-
...amdgcn.struct.ptr.buffer.atomic.cmpswap.ll | 33 +-
.../CodeGen/AMDGPU/GlobalISel/trunc-brc.ll | 122 +-
llvm/test/CodeGen/AMDGPU/div_i128.ll | 615 ++-
llvm/test/CodeGen/AMDGPU/div_v2i128.ll | 220 +-
.../isel-amdgcn-cs-chain-intrinsic-w32.ll | 100 +-
.../isel-amdgcn-cs-chain-intrinsic-w64.ll | 50 +-
...-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll | 88 +-
.../AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll | 16 +-
...rlapping-tuple-copy-implicit-op-failure.ll | 76 +-
.../ARM/GlobalISel/arm-instruction-select.mir | 477 ++-
.../ARM/GlobalISel/thumb-select-br.mir | 26 +-
.../ARM/GlobalISel/thumb-select-exts.mir | 189 +-
.../GlobalISel/thumb-select-load-store.mir | 59 +-
.../ARM/GlobalISel/thumb-select-select.mir | 31 +-
.../X86/GlobalISel/isel-fp64-to-sint-x86.mir | 7 +-
.../CodeGen/X86/GlobalISel/select-copy.mir | 14 +-
.../X86/GlobalISel/select-ext-x86-64.mir | 88 +-
.../CodeGen/X86/GlobalISel/select-ext.mir | 147 +-
.../X86/GlobalISel/select-fadd-scalar.mir | 126 +-
.../CodeGen/X86/GlobalISel/select-fcmp.mir | 436 +--
.../X86/GlobalISel/select-fconstant.mir | 58 +-
.../X86/GlobalISel/select-fdiv-scalar.mir | 126 +-
.../X86/GlobalISel/select-fmul-scalar.mir | 126 +-
.../X86/GlobalISel/select-fpext-scalar.mir | 12 +-
.../X86/GlobalISel/select-fptrunc-scalar.mir | 11 +-
.../X86/GlobalISel/select-fsub-scalar.mir | 126 +-
.../select-memop-scalar-unordered.mir | 966 +++--
.../X86/GlobalISel/select-memop-scalar.mir | 966 +++--
.../CodeGen/X86/GlobalISel/select-phi.mir | 18 +-
.../CodeGen/X86/GlobalISel/select-trunc.mir | 60 +-
.../X86/GlobalISel/select-unmerge-vec512.mir | 20 +-
.../X86/GlobalISel/x86-select-ptrtoint.mir | 22 +-
.../X86/GlobalISel/x86_64-select-fptosi.mir | 88 +-
.../X86/GlobalISel/x86_64-select-ptrtoint.mir | 43 +-
.../X86/GlobalISel/x86_64-select-sitofp.mir | 40 +-
.../X86/GlobalISel/x86_64-select-zext.mir | 9 +-
113 files changed, 10343 insertions(+), 8999 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
index c4baeb75597a69..bf5cadb1547ccf 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -239,6 +239,8 @@ bool InstructionSelectImpl::selectMachineFunction(MachineFunction &MF) {
}
}
+ const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
+
for (MachineBasicBlock &MBB : MF) {
if (MBB.empty())
continue;
@@ -262,20 +264,38 @@ bool InstructionSelectImpl::selectMachineFunction(MachineFunction &MF) {
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
unsigned SrcSubIdx = MI.getOperand(1).getSubReg();
- if (!SrcReg.isVirtual() || !DstReg.isVirtual() || SrcSubIdx)
+ if (!SrcReg.isVirtual() || !DstReg.isVirtual())
continue;
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
- if (SrcRC == DstRC) {
- MRI.replaceRegWith(DstReg, SrcReg);
+ const TargetRegisterClass *ConstrainRC =
+ SrcSubIdx ? TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx)
+ : DstRC;
+
+ // SubstVirtReg pushes the subreg index onto every use of DstReg. If any
+ // such use is a COPY into a physical register, the result is a
+ // cross-class physreg COPY that copyPhysReg may not be able to lower
+ // (e.g. $al = COPY $eax). Restrict subreg propagation to the case where
+ // every use of DstReg is a COPY into a virtual register.
+ if (SrcSubIdx &&
+ !llvm::all_of(MRI.use_nodbg_instructions(DstReg),
+ [](const MachineInstr &UseMI) {
+ return UseMI.isCopy() &&
+ UseMI.getOperand(0).getReg().isVirtual();
+ }))
+ continue;
+
+ if (ConstrainRC && MRI.constrainRegClass(SrcReg, ConstrainRC)) {
+ for (MachineOperand &MO :
+ llvm::make_early_inc_range(MRI.reg_operands(DstReg)))
+ MO.substVirtReg(SrcReg, SrcSubIdx, TRI);
MI.eraseFromParent();
}
}
}
#ifndef NDEBUG
- const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
// Now that selection is complete, there are no more generic vregs. Verify
// that the size of the now-constrained vreg is unchanged and that it has a
// register class.
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
index dfce1fbe0d30f1..e5e2b604b10693 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
@@ -80,10 +80,10 @@ define dso_local i8 @atomicrmw_xchg_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
; -O1: ldxrh w0, [x8]
@@ -94,10 +94,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acquire:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acquire:
; -O1: ldaxrh w0, [x8]
@@ -108,10 +108,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_release:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_release:
; -O1: ldxrh w0, [x8]
@@ -122,10 +122,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
; -O1: ldaxrh w0, [x8]
@@ -136,10 +136,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
; -O1: ldaxrh w0, [x8]
@@ -150,10 +150,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
; -O1: ldxr w0, [x8]
@@ -164,10 +164,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acquire:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acquire:
; -O1: ldaxr w0, [x8]
@@ -178,10 +178,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_release:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_release:
; -O1: ldxr w0, [x8]
@@ -192,10 +192,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
; -O1: ldaxr w0, [x8]
@@ -206,10 +206,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
; -O1: ldaxr w0, [x8]
@@ -220,10 +220,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -234,10 +234,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acquire:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -248,10 +248,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_release:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -262,10 +262,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -276,10 +276,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -680,11 +680,11 @@ define dso_local i8 @atomicrmw_add_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_monotonic:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -696,11 +696,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acquire:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -712,11 +712,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_release:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -728,11 +728,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acq_rel:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -744,11 +744,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_seq_cst:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -760,11 +760,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_monotonic:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -776,11 +776,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acquire:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -792,11 +792,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_release:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -808,11 +808,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acq_rel:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -824,11 +824,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_seq_cst:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -840,11 +840,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_monotonic:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -856,11 +856,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acquire:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -872,11 +872,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_release:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -888,11 +888,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acq_rel:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -904,11 +904,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_seq_cst:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -1445,11 +1445,11 @@ define dso_local i8 @atomicrmw_sub_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_monotonic:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1461,11 +1461,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acquire:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1477,11 +1477,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_release:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1493,11 +1493,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1509,11 +1509,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1525,11 +1525,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_monotonic:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -1541,11 +1541,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acquire:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -1557,11 +1557,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_release:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -1573,11 +1573,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -1589,11 +1589,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -1605,11 +1605,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_monotonic:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -1621,11 +1621,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acquire:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -1637,11 +1637,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_release:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -1653,11 +1653,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -1669,11 +1669,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2200,11 +2200,11 @@ define dso_local i8 @atomicrmw_and_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_monotonic:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2216,11 +2216,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acquire:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2232,11 +2232,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_release:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2248,11 +2248,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acq_rel:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2264,11 +2264,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_seq_cst:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2280,11 +2280,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_monotonic:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2296,11 +2296,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acquire:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2312,11 +2312,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_release:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2328,11 +2328,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acq_rel:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2344,11 +2344,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_seq_cst:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2360,11 +2360,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_monotonic:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -2376,11 +2376,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acquire:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -2392,11 +2392,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_release:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -2408,11 +2408,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acq_rel:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -2424,11 +2424,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_seq_cst:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2985,12 +2985,12 @@ define dso_local i8 @atomicrmw_nand_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_monotonic:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3003,12 +3003,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acquire:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3021,12 +3021,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_release:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3039,12 +3039,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3057,12 +3057,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3075,12 +3075,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_monotonic:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3093,12 +3093,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acquire:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3111,12 +3111,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_release:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3129,12 +3129,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -3147,12 +3147,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -3165,12 +3165,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_monotonic:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -3183,12 +3183,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acquire:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -3201,12 +3201,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_release:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -3219,12 +3219,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -3237,12 +3237,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -3870,11 +3870,11 @@ define dso_local i8 @atomicrmw_or_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_monotonic:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3886,11 +3886,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acquire:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3902,11 +3902,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_release:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3918,11 +3918,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acq_rel:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3934,11 +3934,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_seq_cst:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3950,11 +3950,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_monotonic:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3966,11 +3966,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acquire:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3982,11 +3982,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_release:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3998,11 +3998,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acq_rel:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4014,11 +4014,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_seq_cst:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4030,11 +4030,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_monotonic:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4046,11 +4046,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acquire:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4062,11 +4062,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_release:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4078,11 +4078,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acq_rel:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4094,11 +4094,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_seq_cst:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -4645,11 +4645,11 @@ define dso_local i8 @atomicrmw_xor_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_monotonic:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -4661,11 +4661,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acquire:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -4677,11 +4677,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_release:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -4693,11 +4693,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -4709,11 +4709,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -4725,11 +4725,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_monotonic:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -4741,11 +4741,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acquire:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -4757,11 +4757,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_release:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -4773,11 +4773,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4789,11 +4789,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4805,11 +4805,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_monotonic:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4821,11 +4821,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acquire:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4837,11 +4837,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_release:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4853,11 +4853,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4869,11 +4869,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -5440,13 +5440,13 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -5460,13 +5460,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -5480,13 +5480,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -5500,13 +5500,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -5520,13 +5520,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -5540,12 +5540,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -5558,12 +5558,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -5576,12 +5576,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -5594,12 +5594,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -5612,12 +5612,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -5630,12 +5630,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -5648,12 +5648,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -5666,12 +5666,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -5684,12 +5684,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -5702,12 +5702,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -6405,13 +6405,13 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -6425,13 +6425,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -6445,13 +6445,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -6465,13 +6465,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -6485,13 +6485,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -6505,12 +6505,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -6523,12 +6523,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -6541,12 +6541,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -6559,12 +6559,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -6577,12 +6577,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -6595,12 +6595,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -6613,12 +6613,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -6631,12 +6631,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -6649,12 +6649,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -6667,12 +6667,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -7370,12 +7370,12 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -7389,12 +7389,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -7408,12 +7408,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -7427,12 +7427,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -7446,12 +7446,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -7465,12 +7465,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -7483,12 +7483,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -7501,12 +7501,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -7519,12 +7519,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -7537,12 +7537,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -7555,12 +7555,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -7573,12 +7573,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -7591,12 +7591,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -7609,12 +7609,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -7627,12 +7627,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -8325,12 +8325,12 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -8344,12 +8344,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -8363,12 +8363,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -8382,12 +8382,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -8401,12 +8401,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -8420,12 +8420,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -8438,12 +8438,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -8456,12 +8456,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -8474,12 +8474,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -8492,12 +8492,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -8510,12 +8510,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -8528,12 +8528,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -8546,12 +8546,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -8564,12 +8564,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -8582,12 +8582,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
index a939581680ab09..f0b45976ebd88b 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
@@ -2010,10 +2010,10 @@ define dso_local i8 @atomicrmw_nand_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_monotonic:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: cash w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: cash w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: and w10, w8, w1
@@ -2026,10 +2026,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acquire:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: casah w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casah w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: and w10, w8, w1
@@ -2042,10 +2042,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_release:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: caslh w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: caslh w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: and w10, w8, w1
@@ -2058,10 +2058,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: casalh w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casalh w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: and w10, w8, w1
@@ -2074,10 +2074,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: casalh w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casalh w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: and w10, w8, w1
@@ -2090,10 +2090,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_monotonic:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: cas w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: cas w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: and w10, w8, w1
@@ -2106,10 +2106,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acquire:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casa w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casa w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: and w10, w8, w1
@@ -2122,10 +2122,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_release:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casl w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casl w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: and w10, w8, w1
@@ -2138,10 +2138,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casal w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casal w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: and w10, w8, w1
@@ -2154,10 +2154,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casal w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casal w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: and w10, w8, w1
@@ -2170,10 +2170,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_monotonic:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: cas x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: cas x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: and x10, x8, x1
@@ -2186,10 +2186,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acquire:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casa x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casa x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: and x10, x8, x1
@@ -2202,10 +2202,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_release:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casl x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casl x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: and x10, x8, x1
@@ -2218,10 +2218,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casal x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casal x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: and x10, x8, x1
@@ -2234,10 +2234,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casal x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casal x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: and x10, x8, x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
index c5561fc4c4d15e..35b84b672f8b35 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lsfe.ll
@@ -504,114 +504,142 @@ define dso_local bfloat @atomicrmw_fsub_bfloat_aligned_seq_cst(ptr %ptr, bfloat
ret bfloat %r
}
-define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_monotonic:
-; CHECK: fneg s0, s0
-; CHECK: ldfadd s0, s0, [x0]
+define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %value) {
+; -O0-LABEL: atomicrmw_fsub_float_aligned_monotonic:
+; -O0: ldaxr w8, [x10]
+; -O0: cmp w8, w11
+; -O0: stlxr w9, w12, [x10]
+; -O0: subs w9, w8, w9
+;
+; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
+; -O1: ldxr w8, [x0]
+; -O1: stxr w9, w8, [x0]
%r = atomicrmw fsub ptr %ptr, float %value monotonic, align 4
ret float %r
}
-define dso_local void @atomicrmw_fsub_float_aligned_monotonic_unused(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_monotonic_unused:
-; CHECK: fneg s0, s0
-; CHECK: ldfadd s0, s0, [x0]
- %r = atomicrmw fsub ptr %ptr, float %value monotonic, align 4
- ret void
-}
-
-define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_acquire:
-; CHECK: fneg s0, s0
-; CHECK: ldfadda s0, s0, [x0]
+define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %value) {
+; -O0-LABEL: atomicrmw_fsub_float_aligned_acquire:
+; -O0: ldaxr w8, [x10]
+; -O0: cmp w8, w11
+; -O0: stlxr w9, w12, [x10]
+; -O0: subs w9, w8, w9
+;
+; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
+; -O1: ldaxr w8, [x0]
+; -O1: stxr w9, w8, [x0]
%r = atomicrmw fsub ptr %ptr, float %value acquire, align 4
ret float %r
}
-define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_release:
-; CHECK: fneg s0, s0
-; CHECK: ldfaddl s0, s0, [x0]
+define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %value) {
+; -O0-LABEL: atomicrmw_fsub_float_aligned_release:
+; -O0: ldaxr w8, [x10]
+; -O0: cmp w8, w11
+; -O0: stlxr w9, w12, [x10]
+; -O0: subs w9, w8, w9
+;
+; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
+; -O1: ldxr w8, [x0]
+; -O1: stlxr w9, w8, [x0]
%r = atomicrmw fsub ptr %ptr, float %value release, align 4
ret float %r
}
-define dso_local void @atomicrmw_fsub_float_aligned_release_unused(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_release_unused:
-; CHECK: fneg s0, s0
-; CHECK: ldfaddl s0, s0, [x0]
- %r = atomicrmw fsub ptr %ptr, float %value release, align 4
- ret void
-}
-
-define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
-; CHECK: fneg s0, s0
-; CHECK: ldfaddal s0, s0, [x0]
+define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %value) {
+; -O0-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
+; -O0: ldaxr w8, [x10]
+; -O0: cmp w8, w11
+; -O0: stlxr w9, w12, [x10]
+; -O0: subs w9, w8, w9
+;
+; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
+; -O1: ldaxr w8, [x0]
+; -O1: stlxr w9, w8, [x0]
%r = atomicrmw fsub ptr %ptr, float %value acq_rel, align 4
ret float %r
}
-define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
-; CHECK: fneg s0, s0
-; CHECK: ldfaddal s0, s0, [x0]
+define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %value) {
+; -O0-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
+; -O0: ldaxr w8, [x10]
+; -O0: cmp w8, w11
+; -O0: stlxr w9, w12, [x10]
+; -O0: subs w9, w8, w9
+;
+; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
+; -O1: ldaxr w8, [x0]
+; -O1: stlxr w9, w8, [x0]
%r = atomicrmw fsub ptr %ptr, float %value seq_cst, align 4
ret float %r
}
-define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_monotonic:
-; CHECK: fneg d0, d0
-; CHECK: ldfadd d0, d0, [x0]
+define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, double %value) {
+; -O0-LABEL: atomicrmw_fsub_double_aligned_monotonic:
+; -O0: ldaxr x8, [x10]
+; -O0: cmp x8, x11
+; -O0: stlxr w9, x12, [x10]
+; -O0: subs x9, x8, x9
+;
+; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
+; -O1: ldxr x8, [x0]
+; -O1: stxr w9, x8, [x0]
%r = atomicrmw fsub ptr %ptr, double %value monotonic, align 8
ret double %r
}
-define dso_local void @atomicrmw_fsub_double_aligned_monotonic_unused(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_monotonic_unused:
-; CHECK: fneg d0, d0
-; CHECK: ldfadd d0, d0, [x0]
- %r = atomicrmw fsub ptr %ptr, double %value monotonic, align 8
- ret void
-}
-
-define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_acquire:
-; CHECK: fneg d0, d0
-; CHECK: ldfadda d0, d0, [x0]
+define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double %value) {
+; -O0-LABEL: atomicrmw_fsub_double_aligned_acquire:
+; -O0: ldaxr x8, [x10]
+; -O0: cmp x8, x11
+; -O0: stlxr w9, x12, [x10]
+; -O0: subs x9, x8, x9
+;
+; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
+; -O1: ldaxr x8, [x0]
+; -O1: stxr w9, x8, [x0]
%r = atomicrmw fsub ptr %ptr, double %value acquire, align 8
ret double %r
}
-define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_release:
-; CHECK: fneg d0, d0
-; CHECK: ldfaddl d0, d0, [x0]
+define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double %value) {
+; -O0-LABEL: atomicrmw_fsub_double_aligned_release:
+; -O0: ldaxr x8, [x10]
+; -O0: cmp x8, x11
+; -O0: stlxr w9, x12, [x10]
+; -O0: subs x9, x8, x9
+;
+; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
+; -O1: ldxr x8, [x0]
+; -O1: stlxr w9, x8, [x0]
%r = atomicrmw fsub ptr %ptr, double %value release, align 8
ret double %r
}
-define dso_local void @atomicrmw_fsub_double_aligned_release_unused(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_release_unused:
-; CHECK: fneg d0, d0
-; CHECK: ldfaddl d0, d0, [x0]
- %r = atomicrmw fsub ptr %ptr, double %value release, align 8
- ret void
-}
-
-define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
-; CHECK: fneg d0, d0
-; CHECK: ldfaddal d0, d0, [x0]
+define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double %value) {
+; -O0-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
+; -O0: ldaxr x8, [x10]
+; -O0: cmp x8, x11
+; -O0: stlxr w9, x12, [x10]
+; -O0: subs x9, x8, x9
+;
+; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
+; -O1: ldaxr x8, [x0]
+; -O1: stlxr w9, x8, [x0]
%r = atomicrmw fsub ptr %ptr, double %value acq_rel, align 8
ret double %r
}
-define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) #0 {
-; CHECK-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
-; CHECK: fneg d0, d0
-; CHECK: ldfaddal d0, d0, [x0]
+define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double %value) {
+; -O0-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
+; -O0: ldaxr x8, [x10]
+; -O0: cmp x8, x11
+; -O0: stlxr w9, x12, [x10]
+; -O0: subs x9, x8, x9
+;
+; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
+; -O1: ldaxr x8, [x0]
+; -O1: stlxr w9, x8, [x0]
%r = atomicrmw fsub ptr %ptr, double %value seq_cst, align 8
ret double %r
}
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
index f91e54be0bca64..e1769370dbea49 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
@@ -2233,7 +2233,7 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas2_relax
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2249,7 +2249,7 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas2_acq
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2265,7 +2265,7 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas2_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2281,7 +2281,7 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2297,7 +2297,7 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2313,7 +2313,7 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas4_relax
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2329,7 +2329,7 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas4_acq
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2345,7 +2345,7 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas4_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2361,7 +2361,7 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2377,7 +2377,7 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0: and w8, w0, w8
; -O0: mvn w1, w8
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2393,7 +2393,7 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: and x8, x0, x8
; -O0: mvn x1, x8
; -O0: bl __aarch64_cas8_relax
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -2409,7 +2409,7 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: and x8, x0, x8
; -O0: mvn x1, x8
; -O0: bl __aarch64_cas8_acq
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -2425,7 +2425,7 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: and x8, x0, x8
; -O0: mvn x1, x8
; -O0: bl __aarch64_cas8_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -2441,7 +2441,7 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: and x8, x0, x8
; -O0: mvn x1, x8
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -2457,7 +2457,7 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: and x8, x0, x8
; -O0: mvn x1, x8
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -4109,7 +4109,7 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas2_relax
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -4127,7 +4127,7 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas2_acq
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -4145,7 +4145,7 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas2_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -4163,7 +4163,7 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -4181,7 +4181,7 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -4198,7 +4198,7 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas4_relax
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -4214,7 +4214,7 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas4_acq
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -4230,7 +4230,7 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas4_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_max_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -4246,7 +4246,7 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4262,7 +4262,7 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, gt
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4278,7 +4278,7 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, gt
; -O0: bl __aarch64_cas8_relax
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4294,7 +4294,7 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, gt
; -O0: bl __aarch64_cas8_acq
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4310,7 +4310,7 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, gt
; -O0: bl __aarch64_cas8_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_max_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4326,7 +4326,7 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, gt
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4342,7 +4342,7 @@ define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, gt
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -5004,7 +5004,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas2_relax
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -5022,7 +5022,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas2_acq
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -5040,7 +5040,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas2_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -5058,7 +5058,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -5076,7 +5076,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, sxth
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -5093,7 +5093,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas4_relax
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -5109,7 +5109,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas4_acq
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -5125,7 +5125,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas4_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -5141,7 +5141,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -5157,7 +5157,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, le
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -5173,7 +5173,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, le
; -O0: bl __aarch64_cas8_relax
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -5189,7 +5189,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, le
; -O0: bl __aarch64_cas8_acq
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -5205,7 +5205,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, le
; -O0: bl __aarch64_cas8_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -5221,7 +5221,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, le
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -5237,7 +5237,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, le
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -5898,7 +5898,7 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas2_relax
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -5915,7 +5915,7 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas2_acq
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -5932,7 +5932,7 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas2_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -5949,7 +5949,7 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -5966,7 +5966,7 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -5983,7 +5983,7 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas4_relax
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -5999,7 +5999,7 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas4_acq
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -6015,7 +6015,7 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas4_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -6031,7 +6031,7 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -6047,7 +6047,7 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, hi
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -6063,7 +6063,7 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, hi
; -O0: bl __aarch64_cas8_relax
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -6079,7 +6079,7 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, hi
; -O0: bl __aarch64_cas8_acq
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -6095,7 +6095,7 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, hi
; -O0: bl __aarch64_cas8_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -6111,7 +6111,7 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, hi
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -6127,7 +6127,7 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, hi
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -6783,7 +6783,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas2_relax
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -6800,7 +6800,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas2_acq
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -6817,7 +6817,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas2_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -6834,7 +6834,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -6851,7 +6851,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w8, uxth
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas2_acq_rel
-; -O0: subs w8, w8, w9, uxth
+; -O0: subs w8, w8, w0, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -6868,7 +6868,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas4_relax
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -6884,7 +6884,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas4_acq
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -6900,7 +6900,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas4_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -6916,7 +6916,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -6932,7 +6932,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0: subs w9, w0, w8
; -O0: csel w1, w0, w8, ls
; -O0: bl __aarch64_cas4_acq_rel
-; -O0: subs w8, w8, w9
+; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -6948,7 +6948,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, ls
; -O0: bl __aarch64_cas8_relax
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -6964,7 +6964,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, ls
; -O0: bl __aarch64_cas8_acq
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -6980,7 +6980,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, ls
; -O0: bl __aarch64_cas8_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -6996,7 +6996,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, ls
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -7012,7 +7012,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0: subs x9, x0, x8
; -O0: csel x1, x0, x8, ls
; -O0: bl __aarch64_cas8_acq_rel
-; -O0: subs x8, x8, x9
+; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
index 22bfedb7adaa4c..a33d4851238a73 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
@@ -80,10 +80,10 @@ define dso_local i8 @atomicrmw_xchg_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
; -O1: ldxrh w0, [x8]
@@ -94,10 +94,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acquire:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acquire:
; -O1: ldaxrh w0, [x8]
@@ -108,10 +108,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_release:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_release:
; -O1: ldxrh w0, [x8]
@@ -122,10 +122,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
; -O1: ldaxrh w0, [x8]
@@ -136,10 +136,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
; -O1: ldaxrh w0, [x8]
@@ -150,10 +150,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
; -O1: ldxr w0, [x8]
@@ -164,10 +164,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acquire:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acquire:
; -O1: ldaxr w0, [x8]
@@ -178,10 +178,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_release:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_release:
; -O1: ldxr w0, [x8]
@@ -192,10 +192,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
; -O1: ldaxr w0, [x8]
@@ -206,10 +206,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
; -O1: ldaxr w0, [x8]
@@ -220,10 +220,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -234,10 +234,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acquire:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -248,10 +248,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_release:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -262,10 +262,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -276,10 +276,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -680,11 +680,11 @@ define dso_local i8 @atomicrmw_add_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_monotonic:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -696,11 +696,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acquire:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -712,11 +712,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_release:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -728,11 +728,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acq_rel:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -744,11 +744,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_seq_cst:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -760,11 +760,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_monotonic:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -776,11 +776,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acquire:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -792,11 +792,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_release:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -808,11 +808,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acq_rel:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -824,11 +824,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_seq_cst:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -840,11 +840,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_monotonic:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -856,11 +856,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acquire:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -872,11 +872,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_release:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -888,11 +888,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acq_rel:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -904,11 +904,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_seq_cst:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -1445,11 +1445,11 @@ define dso_local i8 @atomicrmw_sub_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_monotonic:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1461,11 +1461,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acquire:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1477,11 +1477,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_release:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1493,11 +1493,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1509,11 +1509,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1525,11 +1525,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_monotonic:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -1541,11 +1541,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acquire:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -1557,11 +1557,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_release:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -1573,11 +1573,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -1589,11 +1589,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -1605,11 +1605,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_monotonic:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -1621,11 +1621,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acquire:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -1637,11 +1637,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_release:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -1653,11 +1653,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -1669,11 +1669,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2200,11 +2200,11 @@ define dso_local i8 @atomicrmw_and_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_monotonic:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2216,11 +2216,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acquire:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2232,11 +2232,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_release:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2248,11 +2248,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acq_rel:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2264,11 +2264,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_seq_cst:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2280,11 +2280,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_monotonic:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2296,11 +2296,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acquire:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2312,11 +2312,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_release:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2328,11 +2328,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acq_rel:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2344,11 +2344,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_seq_cst:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2360,11 +2360,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_monotonic:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -2376,11 +2376,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acquire:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -2392,11 +2392,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_release:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -2408,11 +2408,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acq_rel:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -2424,11 +2424,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_seq_cst:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2985,12 +2985,12 @@ define dso_local i8 @atomicrmw_nand_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_monotonic:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3003,12 +3003,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acquire:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3021,12 +3021,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_release:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3039,12 +3039,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3057,12 +3057,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3075,12 +3075,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_monotonic:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3093,12 +3093,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acquire:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3111,12 +3111,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_release:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3129,12 +3129,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -3147,12 +3147,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -3165,12 +3165,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_monotonic:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -3183,12 +3183,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acquire:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -3201,12 +3201,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_release:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -3219,12 +3219,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -3237,12 +3237,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -3870,11 +3870,11 @@ define dso_local i8 @atomicrmw_or_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_monotonic:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3886,11 +3886,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acquire:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3902,11 +3902,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_release:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3918,11 +3918,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acq_rel:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3934,11 +3934,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_seq_cst:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3950,11 +3950,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_monotonic:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3966,11 +3966,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acquire:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3982,11 +3982,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_release:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3998,11 +3998,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acq_rel:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4014,11 +4014,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_seq_cst:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4030,11 +4030,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_monotonic:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4046,11 +4046,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acquire:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4062,11 +4062,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_release:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4078,11 +4078,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acq_rel:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4094,11 +4094,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_seq_cst:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -4645,11 +4645,11 @@ define dso_local i8 @atomicrmw_xor_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_monotonic:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -4661,11 +4661,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acquire:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -4677,11 +4677,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_release:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -4693,11 +4693,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -4709,11 +4709,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -4725,11 +4725,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_monotonic:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -4741,11 +4741,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acquire:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -4757,11 +4757,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_release:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -4773,11 +4773,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4789,11 +4789,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4805,11 +4805,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_monotonic:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4821,11 +4821,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acquire:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4837,11 +4837,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_release:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4853,11 +4853,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4869,11 +4869,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -5440,13 +5440,13 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -5460,13 +5460,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -5480,13 +5480,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -5500,13 +5500,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -5520,13 +5520,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -5540,12 +5540,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -5558,12 +5558,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -5576,12 +5576,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -5594,12 +5594,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -5612,12 +5612,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -5630,12 +5630,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -5648,12 +5648,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -5666,12 +5666,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -5684,12 +5684,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -5702,12 +5702,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -6405,13 +6405,13 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -6425,13 +6425,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -6445,13 +6445,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -6465,13 +6465,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -6485,13 +6485,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -6505,12 +6505,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -6523,12 +6523,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -6541,12 +6541,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -6559,12 +6559,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -6577,12 +6577,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -6595,12 +6595,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -6613,12 +6613,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -6631,12 +6631,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -6649,12 +6649,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -6667,12 +6667,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -7370,12 +7370,12 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -7389,12 +7389,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -7408,12 +7408,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -7427,12 +7427,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -7446,12 +7446,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -7465,12 +7465,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -7483,12 +7483,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -7501,12 +7501,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -7519,12 +7519,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -7537,12 +7537,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -7555,12 +7555,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -7573,12 +7573,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -7591,12 +7591,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -7609,12 +7609,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -7627,12 +7627,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -8325,12 +8325,12 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -8344,12 +8344,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -8363,12 +8363,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -8382,12 +8382,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -8401,12 +8401,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -8420,12 +8420,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -8438,12 +8438,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -8456,12 +8456,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -8474,12 +8474,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -8492,12 +8492,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -8510,12 +8510,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -8528,12 +8528,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -8546,12 +8546,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -8564,12 +8564,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -8582,12 +8582,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
index 2b2ca83652df9c..08037918add05f 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
@@ -80,10 +80,10 @@ define dso_local i8 @atomicrmw_xchg_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
; -O1: ldxrh w0, [x8]
@@ -94,10 +94,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acquire:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acquire:
; -O1: ldaxrh w0, [x8]
@@ -108,10 +108,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_release:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_release:
; -O1: ldxrh w0, [x8]
@@ -122,10 +122,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
; -O1: ldaxrh w0, [x8]
@@ -136,10 +136,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
; -O1: ldaxrh w0, [x8]
@@ -150,10 +150,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
; -O1: ldxr w0, [x8]
@@ -164,10 +164,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acquire:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acquire:
; -O1: ldaxr w0, [x8]
@@ -178,10 +178,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_release:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_release:
; -O1: ldxr w0, [x8]
@@ -192,10 +192,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
; -O1: ldaxr w0, [x8]
@@ -206,10 +206,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
; -O1: ldaxr w0, [x8]
@@ -220,10 +220,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -234,10 +234,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acquire:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -248,10 +248,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_release:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -262,10 +262,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -276,10 +276,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -680,11 +680,11 @@ define dso_local i8 @atomicrmw_add_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_monotonic:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -696,11 +696,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acquire:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -712,11 +712,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_release:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -728,11 +728,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acq_rel:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -744,11 +744,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_seq_cst:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -760,11 +760,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_monotonic:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -776,11 +776,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acquire:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -792,11 +792,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_release:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -808,11 +808,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acq_rel:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -824,11 +824,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_seq_cst:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -840,11 +840,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_monotonic:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -856,11 +856,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acquire:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -872,11 +872,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_release:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -888,11 +888,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acq_rel:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -904,11 +904,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_seq_cst:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -1445,11 +1445,11 @@ define dso_local i8 @atomicrmw_sub_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_monotonic:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1461,11 +1461,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acquire:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1477,11 +1477,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_release:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1493,11 +1493,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1509,11 +1509,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1525,11 +1525,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_monotonic:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -1541,11 +1541,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acquire:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -1557,11 +1557,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_release:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -1573,11 +1573,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -1589,11 +1589,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -1605,11 +1605,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_monotonic:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -1621,11 +1621,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acquire:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -1637,11 +1637,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_release:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -1653,11 +1653,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -1669,11 +1669,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2200,11 +2200,11 @@ define dso_local i8 @atomicrmw_and_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_monotonic:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2216,11 +2216,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acquire:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2232,11 +2232,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_release:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2248,11 +2248,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acq_rel:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2264,11 +2264,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_seq_cst:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2280,11 +2280,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_monotonic:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2296,11 +2296,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acquire:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2312,11 +2312,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_release:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2328,11 +2328,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acq_rel:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2344,11 +2344,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_seq_cst:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2360,11 +2360,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_monotonic:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -2376,11 +2376,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acquire:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -2392,11 +2392,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_release:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -2408,11 +2408,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acq_rel:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -2424,11 +2424,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_seq_cst:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2985,12 +2985,12 @@ define dso_local i8 @atomicrmw_nand_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_monotonic:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3003,12 +3003,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acquire:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3021,12 +3021,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_release:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3039,12 +3039,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3057,12 +3057,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3075,12 +3075,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_monotonic:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3093,12 +3093,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acquire:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3111,12 +3111,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_release:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3129,12 +3129,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -3147,12 +3147,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -3165,12 +3165,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_monotonic:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -3183,12 +3183,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acquire:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -3201,12 +3201,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_release:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -3219,12 +3219,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -3237,12 +3237,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -3870,11 +3870,11 @@ define dso_local i8 @atomicrmw_or_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_monotonic:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3886,11 +3886,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acquire:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3902,11 +3902,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_release:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3918,11 +3918,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acq_rel:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3934,11 +3934,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_seq_cst:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3950,11 +3950,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_monotonic:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3966,11 +3966,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acquire:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3982,11 +3982,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_release:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3998,11 +3998,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acq_rel:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4014,11 +4014,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_seq_cst:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4030,11 +4030,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_monotonic:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4046,11 +4046,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acquire:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4062,11 +4062,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_release:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4078,11 +4078,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acq_rel:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4094,11 +4094,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_seq_cst:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -4645,11 +4645,11 @@ define dso_local i8 @atomicrmw_xor_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_monotonic:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -4661,11 +4661,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acquire:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -4677,11 +4677,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_release:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -4693,11 +4693,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -4709,11 +4709,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -4725,11 +4725,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_monotonic:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -4741,11 +4741,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acquire:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -4757,11 +4757,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_release:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -4773,11 +4773,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4789,11 +4789,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4805,11 +4805,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_monotonic:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4821,11 +4821,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acquire:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4837,11 +4837,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_release:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4853,11 +4853,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4869,11 +4869,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -5440,13 +5440,13 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -5460,13 +5460,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -5480,13 +5480,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -5500,13 +5500,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -5520,13 +5520,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -5540,12 +5540,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -5558,12 +5558,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -5576,12 +5576,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -5594,12 +5594,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -5612,12 +5612,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -5630,12 +5630,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -5648,12 +5648,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -5666,12 +5666,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -5684,12 +5684,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -5702,12 +5702,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -6405,13 +6405,13 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -6425,13 +6425,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -6445,13 +6445,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -6465,13 +6465,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -6485,13 +6485,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -6505,12 +6505,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -6523,12 +6523,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -6541,12 +6541,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -6559,12 +6559,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -6577,12 +6577,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -6595,12 +6595,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -6613,12 +6613,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -6631,12 +6631,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -6649,12 +6649,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -6667,12 +6667,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -7370,12 +7370,12 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -7389,12 +7389,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -7408,12 +7408,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -7427,12 +7427,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -7446,12 +7446,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -7465,12 +7465,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -7483,12 +7483,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -7501,12 +7501,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -7519,12 +7519,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -7537,12 +7537,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -7555,12 +7555,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -7573,12 +7573,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -7591,12 +7591,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -7609,12 +7609,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -7627,12 +7627,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -8325,12 +8325,12 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -8344,12 +8344,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -8363,12 +8363,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -8382,12 +8382,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -8401,12 +8401,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -8420,12 +8420,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -8438,12 +8438,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -8456,12 +8456,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -8474,12 +8474,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -8492,12 +8492,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -8510,12 +8510,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -8528,12 +8528,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -8546,12 +8546,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -8564,12 +8564,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -8582,12 +8582,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
index 2066946da96b19..5094276c9d3686 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
@@ -2070,10 +2070,10 @@ define dso_local i8 @atomicrmw_nand_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_monotonic:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: cash w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: cash w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: and w10, w8, w1
@@ -2086,10 +2086,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acquire:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: casah w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casah w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: and w10, w8, w1
@@ -2102,10 +2102,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_release:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: caslh w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: caslh w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: and w10, w8, w1
@@ -2118,10 +2118,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: casalh w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casalh w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: and w10, w8, w1
@@ -2134,10 +2134,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
-; -O0: and w9, w8, w9
-; -O0: mvn w9, w9
-; -O0: casalh w10, w9, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casalh w8, w10, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: and w10, w8, w1
@@ -2150,10 +2150,10 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_monotonic:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: cas w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: cas w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: and w10, w8, w1
@@ -2166,10 +2166,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acquire:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casa w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casa w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: and w10, w8, w1
@@ -2182,10 +2182,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_release:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casl w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casl w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: and w10, w8, w1
@@ -2198,10 +2198,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casal w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casal w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: and w10, w8, w1
@@ -2214,10 +2214,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
-; -O0: and w8, w10, w8
-; -O0: mvn w8, w8
-; -O0: casal w9, w8, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w8, w9, w8
+; -O0: mvn w10, w8
+; -O0: casal w8, w10, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: and w10, w8, w1
@@ -2230,10 +2230,10 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_monotonic:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: cas x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: cas x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: and x10, x8, x1
@@ -2246,10 +2246,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acquire:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casa x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casa x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: and x10, x8, x1
@@ -2262,10 +2262,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_release:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casl x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casl x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: and x10, x8, x1
@@ -2278,10 +2278,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casal x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casal x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: and x10, x8, x1
@@ -2294,10 +2294,10 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
-; -O0: and x8, x10, x8
-; -O0: mvn x8, x8
-; -O0: casal x9, x8, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x8, x9, x8
+; -O0: mvn x10, x8
+; -O0: casal x8, x10, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: and x10, x8, x1
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
index 8f4b30bd906385..1894f8401faa7c 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
@@ -80,10 +80,10 @@ define dso_local i8 @atomicrmw_xchg_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_monotonic:
; -O1: ldxrh w0, [x8]
@@ -94,10 +94,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acquire:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acquire:
; -O1: ldaxrh w0, [x8]
@@ -108,10 +108,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_release:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_release:
; -O1: ldxrh w0, [x8]
@@ -122,10 +122,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_acq_rel:
; -O1: ldaxrh w0, [x8]
@@ -136,10 +136,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xchg_i16_aligned_seq_cst:
; -O1: ldaxrh w0, [x8]
@@ -150,10 +150,10 @@ define dso_local i16 @atomicrmw_xchg_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_monotonic:
; -O1: ldxr w0, [x8]
@@ -164,10 +164,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acquire:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acquire:
; -O1: ldaxr w0, [x8]
@@ -178,10 +178,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_release:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_release:
; -O1: ldxr w0, [x8]
@@ -192,10 +192,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_acq_rel:
; -O1: ldaxr w0, [x8]
@@ -206,10 +206,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xchg_i32_aligned_seq_cst:
; -O1: ldaxr w0, [x8]
@@ -220,10 +220,10 @@ define dso_local i32 @atomicrmw_xchg_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -234,10 +234,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acquire:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -248,10 +248,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_release:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -262,10 +262,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -276,10 +276,10 @@ define dso_local i64 @atomicrmw_xchg_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xchg_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xchg_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -680,11 +680,11 @@ define dso_local i8 @atomicrmw_add_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_monotonic:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -696,11 +696,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acquire:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -712,11 +712,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_release:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -728,11 +728,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_acq_rel:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -744,11 +744,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_add_i16_aligned_seq_cst:
-; -O0: add w12, w9, w8, uxth
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: add w12, w8, w9, uxth
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_add_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -760,11 +760,11 @@ define dso_local i16 @atomicrmw_add_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_monotonic:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -776,11 +776,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acquire:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -792,11 +792,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_release:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -808,11 +808,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_acq_rel:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -824,11 +824,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_add_i32_aligned_seq_cst:
-; -O0: add w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: add w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_add_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -840,11 +840,11 @@ define dso_local i32 @atomicrmw_add_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_monotonic:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -856,11 +856,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acquire:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -872,11 +872,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_release:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -888,11 +888,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_acq_rel:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -904,11 +904,11 @@ define dso_local i64 @atomicrmw_add_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_add_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_add_i64_aligned_seq_cst:
-; -O0: add x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: add x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_add_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -1445,11 +1445,11 @@ define dso_local i8 @atomicrmw_sub_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_monotonic:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -1461,11 +1461,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acquire:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -1477,11 +1477,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_release:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -1493,11 +1493,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -1509,11 +1509,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
-; -O0: subs w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_sub_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -1525,11 +1525,11 @@ define dso_local i16 @atomicrmw_sub_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_monotonic:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -1541,11 +1541,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acquire:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -1557,11 +1557,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_release:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -1573,11 +1573,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -1589,11 +1589,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
-; -O0: subs w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_sub_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -1605,11 +1605,11 @@ define dso_local i32 @atomicrmw_sub_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_monotonic:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -1621,11 +1621,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acquire:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -1637,11 +1637,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_release:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -1653,11 +1653,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -1669,11 +1669,11 @@ define dso_local i64 @atomicrmw_sub_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_sub_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
-; -O0: subs x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_sub_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2200,11 +2200,11 @@ define dso_local i8 @atomicrmw_and_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_monotonic:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -2216,11 +2216,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acquire:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -2232,11 +2232,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_release:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -2248,11 +2248,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_acq_rel:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -2264,11 +2264,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_and_i16_aligned_seq_cst:
-; -O0: and w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_and_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -2280,11 +2280,11 @@ define dso_local i16 @atomicrmw_and_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_monotonic:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2296,11 +2296,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acquire:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2312,11 +2312,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_release:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2328,11 +2328,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_acq_rel:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2344,11 +2344,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_and_i32_aligned_seq_cst:
-; -O0: and w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: and w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_and_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2360,11 +2360,11 @@ define dso_local i32 @atomicrmw_and_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_monotonic:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -2376,11 +2376,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acquire:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -2392,11 +2392,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_release:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -2408,11 +2408,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_acq_rel:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -2424,11 +2424,11 @@ define dso_local i64 @atomicrmw_and_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_and_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_and_i64_aligned_seq_cst:
-; -O0: and x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: and x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_and_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -2985,12 +2985,12 @@ define dso_local i8 @atomicrmw_nand_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_monotonic:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3003,12 +3003,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acquire:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3021,12 +3021,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_release:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3039,12 +3039,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3057,12 +3057,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
-; -O0: and w9, w8, w9
-; -O0: mvn w12, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: and w8, w9, w8
+; -O0: mvn w12, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_nand_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3075,12 +3075,12 @@ define dso_local i16 @atomicrmw_nand_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_monotonic:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3093,12 +3093,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acquire:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3111,12 +3111,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_release:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3129,12 +3129,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -3147,12 +3147,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
-; -O0: and w8, w10, w8
+; -O0: and w8, w9, w8
; -O0: mvn w12, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_nand_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -3165,12 +3165,12 @@ define dso_local i32 @atomicrmw_nand_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_monotonic:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -3183,12 +3183,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acquire:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -3201,12 +3201,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_release:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -3219,12 +3219,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -3237,12 +3237,12 @@ define dso_local i64 @atomicrmw_nand_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_nand_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
-; -O0: and x8, x10, x8
+; -O0: and x8, x9, x8
; -O0: mvn x12, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_nand_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -3870,11 +3870,11 @@ define dso_local i8 @atomicrmw_or_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_monotonic:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -3886,11 +3886,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_monotonic(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acquire:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -3902,11 +3902,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_release:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -3918,11 +3918,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_acq_rel:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -3934,11 +3934,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_or_i16_aligned_seq_cst:
-; -O0: orr w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: orr w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_or_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -3950,11 +3950,11 @@ define dso_local i16 @atomicrmw_or_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_monotonic:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -3966,11 +3966,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_monotonic(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acquire:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -3982,11 +3982,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_release:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -3998,11 +3998,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_acq_rel:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4014,11 +4014,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_or_i32_aligned_seq_cst:
-; -O0: orr w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: orr w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_or_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4030,11 +4030,11 @@ define dso_local i32 @atomicrmw_or_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_monotonic:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4046,11 +4046,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_monotonic(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acquire:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4062,11 +4062,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_release:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4078,11 +4078,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_acq_rel:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4094,11 +4094,11 @@ define dso_local i64 @atomicrmw_or_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_or_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_or_i64_aligned_seq_cst:
-; -O0: orr x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: orr x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_or_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -4645,11 +4645,11 @@ define dso_local i8 @atomicrmw_xor_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_monotonic:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_monotonic:
; -O1: ldxrh w8, [x0]
@@ -4661,11 +4661,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acquire:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acquire:
; -O1: ldaxrh w8, [x0]
@@ -4677,11 +4677,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_release:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_release:
; -O1: ldxrh w8, [x0]
@@ -4693,11 +4693,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_acq_rel:
; -O1: ldaxrh w8, [x0]
@@ -4709,11 +4709,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
-; -O0: eor w12, w8, w9
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: eor w12, w9, w8
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_xor_i16_aligned_seq_cst:
; -O1: ldaxrh w8, [x0]
@@ -4725,11 +4725,11 @@ define dso_local i16 @atomicrmw_xor_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_monotonic:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -4741,11 +4741,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acquire:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -4757,11 +4757,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_release:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -4773,11 +4773,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -4789,11 +4789,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
-; -O0: eor w12, w10, w8
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: eor w12, w9, w8
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_xor_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -4805,11 +4805,11 @@ define dso_local i32 @atomicrmw_xor_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_monotonic:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -4821,11 +4821,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acquire:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -4837,11 +4837,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_release:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -4853,11 +4853,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -4869,11 +4869,11 @@ define dso_local i64 @atomicrmw_xor_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_xor_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
-; -O0: eor x12, x10, x8
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: eor x12, x9, x8
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_xor_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -5440,13 +5440,13 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -5460,13 +5460,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -5480,13 +5480,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -5500,13 +5500,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -5520,13 +5520,13 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, gt
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -5540,12 +5540,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -5558,12 +5558,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -5576,12 +5576,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -5594,12 +5594,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -5612,12 +5612,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_max_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, gt
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, gt
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_max_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -5630,12 +5630,12 @@ define dso_local i32 @atomicrmw_max_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -5648,12 +5648,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -5666,12 +5666,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -5684,12 +5684,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -5702,12 +5702,12 @@ define dso_local i64 @atomicrmw_max_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_max_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_max_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, gt
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, gt
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_max_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -6405,13 +6405,13 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
; -O1: ldxrh w9, [x0]
@@ -6425,13 +6425,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
; -O1: ldaxrh w9, [x0]
@@ -6445,13 +6445,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
; -O1: ldxrh w9, [x0]
@@ -6465,13 +6465,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
; -O1: ldaxrh w9, [x0]
@@ -6485,13 +6485,13 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w8
-; -O0: subs w10, w10, w9, sxth
-; -O0: csel w12, w8, w9, le
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: sxth w10, w9
+; -O0: subs w10, w10, w8, sxth
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
; -O1: ldaxrh w9, [x0]
@@ -6505,12 +6505,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -6523,12 +6523,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -6541,12 +6541,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -6559,12 +6559,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -6577,12 +6577,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, le
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, le
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -6595,12 +6595,12 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -6613,12 +6613,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -6631,12 +6631,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -6649,12 +6649,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -6667,12 +6667,12 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, le
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, le
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -7370,12 +7370,12 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -7389,12 +7389,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -7408,12 +7408,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -7427,12 +7427,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -7446,12 +7446,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, hi
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -7465,12 +7465,12 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -7483,12 +7483,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -7501,12 +7501,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -7519,12 +7519,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -7537,12 +7537,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, hi
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, hi
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umax_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -7555,12 +7555,12 @@ define dso_local i32 @atomicrmw_umax_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -7573,12 +7573,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -7591,12 +7591,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -7609,12 +7609,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -7627,12 +7627,12 @@ define dso_local i64 @atomicrmw_umax_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umax_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, hi
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, hi
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umax_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
@@ -8325,12 +8325,12 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_monotonic:
; -O1: and w9, w1, #0xffff
@@ -8344,12 +8344,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acquire:
; -O1: and w9, w1, #0xffff
@@ -8363,12 +8363,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_release:
; -O1: and w9, w1, #0xffff
@@ -8382,12 +8382,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
; -O1: and w9, w1, #0xffff
@@ -8401,12 +8401,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
-; -O0: subs w10, w10, w9, uxth
-; -O0: csel w12, w8, w9, ls
-; -O0: ldaxrh w10, [x11]
-; -O0: cmp w10, w8, uxth
-; -O0: stlxrh w9, w12, [x11]
-; -O0: subs w9, w9, w10, uxth
+; -O0: subs w10, w10, w8, uxth
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxrh w8, [x11]
+; -O0: cmp w8, w9, uxth
+; -O0: stlxrh w10, w12, [x11]
+; -O0: subs w9, w9, w8, uxth
;
; -O1-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
; -O1: and w9, w1, #0xffff
@@ -8420,12 +8420,12 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -8438,12 +8438,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -8456,12 +8456,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
@@ -8474,12 +8474,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -8492,12 +8492,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
-; -O0: subs w9, w10, w8
-; -O0: csel w12, w10, w8, ls
-; -O0: ldaxr w9, [x11]
-; -O0: cmp w9, w10
-; -O0: stlxr w8, w12, [x11]
-; -O0: subs w9, w9, w10
+; -O0: subs w10, w9, w8
+; -O0: csel w12, w9, w8, ls
+; -O0: ldaxr w8, [x11]
+; -O0: cmp w8, w9
+; -O0: stlxr w10, w12, [x11]
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -8510,12 +8510,12 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
@@ -8528,12 +8528,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
@@ -8546,12 +8546,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
@@ -8564,12 +8564,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
@@ -8582,12 +8582,12 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
-; -O0: subs x9, x10, x8
-; -O0: csel x12, x10, x8, ls
-; -O0: ldaxr x9, [x11]
-; -O0: cmp x9, x10
-; -O0: stlxr w8, x12, [x11]
-; -O0: subs x9, x9, x10
+; -O0: subs x10, x9, x8
+; -O0: csel x12, x9, x8, ls
+; -O0: ldaxr x8, [x11]
+; -O0: cmp x8, x9
+; -O0: stlxr w10, x12, [x11]
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
index d71231059c3b30..18864f12eb6b0a 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a_fp.ll
@@ -183,7 +183,7 @@ define dso_local float @atomicrmw_fadd_float_aligned_monotonic(ptr %ptr, float %
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -197,7 +197,7 @@ define dso_local float @atomicrmw_fadd_float_aligned_acquire(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -211,7 +211,7 @@ define dso_local float @atomicrmw_fadd_float_aligned_release(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_release:
; -O1: ldxr w8, [x0]
@@ -225,7 +225,7 @@ define dso_local float @atomicrmw_fadd_float_aligned_acq_rel(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -239,7 +239,7 @@ define dso_local float @atomicrmw_fadd_float_aligned_seq_cst(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fadd_float_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -253,7 +253,7 @@ define dso_local double @atomicrmw_fadd_double_aligned_monotonic(ptr %ptr, doubl
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_monotonic:
; -O1: ldxr x8, [x0]
@@ -267,7 +267,7 @@ define dso_local double @atomicrmw_fadd_double_aligned_acquire(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acquire:
; -O1: ldaxr x8, [x0]
@@ -281,7 +281,7 @@ define dso_local double @atomicrmw_fadd_double_aligned_release(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_release:
; -O1: ldxr x8, [x0]
@@ -295,7 +295,7 @@ define dso_local double @atomicrmw_fadd_double_aligned_acq_rel(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_acq_rel:
; -O1: ldaxr x8, [x0]
@@ -309,7 +309,7 @@ define dso_local double @atomicrmw_fadd_double_aligned_seq_cst(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fadd_double_aligned_seq_cst:
; -O1: ldaxr x8, [x0]
@@ -688,7 +688,7 @@ define dso_local float @atomicrmw_fsub_float_aligned_monotonic(ptr %ptr, float %
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -702,7 +702,7 @@ define dso_local float @atomicrmw_fsub_float_aligned_acquire(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -716,7 +716,7 @@ define dso_local float @atomicrmw_fsub_float_aligned_release(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_release:
; -O1: ldxr w8, [x0]
@@ -730,7 +730,7 @@ define dso_local float @atomicrmw_fsub_float_aligned_acq_rel(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -744,7 +744,7 @@ define dso_local float @atomicrmw_fsub_float_aligned_seq_cst(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fsub_float_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -758,7 +758,7 @@ define dso_local double @atomicrmw_fsub_double_aligned_monotonic(ptr %ptr, doubl
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_monotonic:
; -O1: ldxr x8, [x0]
@@ -772,7 +772,7 @@ define dso_local double @atomicrmw_fsub_double_aligned_acquire(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acquire:
; -O1: ldaxr x8, [x0]
@@ -786,7 +786,7 @@ define dso_local double @atomicrmw_fsub_double_aligned_release(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_release:
; -O1: ldxr x8, [x0]
@@ -800,7 +800,7 @@ define dso_local double @atomicrmw_fsub_double_aligned_acq_rel(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_acq_rel:
; -O1: ldaxr x8, [x0]
@@ -814,7 +814,7 @@ define dso_local double @atomicrmw_fsub_double_aligned_seq_cst(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fsub_double_aligned_seq_cst:
; -O1: ldaxr x8, [x0]
@@ -1193,7 +1193,7 @@ define dso_local float @atomicrmw_fmax_float_aligned_monotonic(ptr %ptr, float %
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -1207,7 +1207,7 @@ define dso_local float @atomicrmw_fmax_float_aligned_acquire(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -1221,7 +1221,7 @@ define dso_local float @atomicrmw_fmax_float_aligned_release(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_release:
; -O1: ldxr w8, [x0]
@@ -1235,7 +1235,7 @@ define dso_local float @atomicrmw_fmax_float_aligned_acq_rel(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -1249,7 +1249,7 @@ define dso_local float @atomicrmw_fmax_float_aligned_seq_cst(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmax_float_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -1263,7 +1263,7 @@ define dso_local double @atomicrmw_fmax_double_aligned_monotonic(ptr %ptr, doubl
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_monotonic:
; -O1: ldxr x8, [x0]
@@ -1277,7 +1277,7 @@ define dso_local double @atomicrmw_fmax_double_aligned_acquire(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acquire:
; -O1: ldaxr x8, [x0]
@@ -1291,7 +1291,7 @@ define dso_local double @atomicrmw_fmax_double_aligned_release(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_release:
; -O1: ldxr x8, [x0]
@@ -1305,7 +1305,7 @@ define dso_local double @atomicrmw_fmax_double_aligned_acq_rel(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_acq_rel:
; -O1: ldaxr x8, [x0]
@@ -1319,7 +1319,7 @@ define dso_local double @atomicrmw_fmax_double_aligned_seq_cst(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmax_double_aligned_seq_cst:
; -O1: ldaxr x8, [x0]
@@ -1698,7 +1698,7 @@ define dso_local float @atomicrmw_fmin_float_aligned_monotonic(ptr %ptr, float %
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -1712,7 +1712,7 @@ define dso_local float @atomicrmw_fmin_float_aligned_acquire(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -1726,7 +1726,7 @@ define dso_local float @atomicrmw_fmin_float_aligned_release(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_release:
; -O1: ldxr w8, [x0]
@@ -1740,7 +1740,7 @@ define dso_local float @atomicrmw_fmin_float_aligned_acq_rel(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -1754,7 +1754,7 @@ define dso_local float @atomicrmw_fmin_float_aligned_seq_cst(ptr %ptr, float %va
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmin_float_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -1768,7 +1768,7 @@ define dso_local double @atomicrmw_fmin_double_aligned_monotonic(ptr %ptr, doubl
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_monotonic:
; -O1: ldxr x8, [x0]
@@ -1782,7 +1782,7 @@ define dso_local double @atomicrmw_fmin_double_aligned_acquire(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acquire:
; -O1: ldaxr x8, [x0]
@@ -1796,7 +1796,7 @@ define dso_local double @atomicrmw_fmin_double_aligned_release(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_release:
; -O1: ldxr x8, [x0]
@@ -1810,7 +1810,7 @@ define dso_local double @atomicrmw_fmin_double_aligned_acq_rel(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_acq_rel:
; -O1: ldaxr x8, [x0]
@@ -1824,7 +1824,7 @@ define dso_local double @atomicrmw_fmin_double_aligned_seq_cst(ptr %ptr, double
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmin_double_aligned_seq_cst:
; -O1: ldaxr x8, [x0]
@@ -2203,7 +2203,7 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_monotonic(ptr %ptr, flo
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2217,7 +2217,7 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acquire(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2231,7 +2231,7 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_release(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2245,7 +2245,7 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_acq_rel(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2259,7 +2259,7 @@ define dso_local float @atomicrmw_fmaximum_float_aligned_seq_cst(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fmaximum_float_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2273,7 +2273,7 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_monotonic(ptr %ptr, d
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_monotonic:
; -O1: ldxr x8, [x0]
@@ -2287,7 +2287,7 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acquire(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acquire:
; -O1: ldaxr x8, [x0]
@@ -2301,7 +2301,7 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_release(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_release:
; -O1: ldxr x8, [x0]
@@ -2315,7 +2315,7 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_acq_rel(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_acq_rel:
; -O1: ldaxr x8, [x0]
@@ -2329,7 +2329,7 @@ define dso_local double @atomicrmw_fmaximum_double_aligned_seq_cst(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fmaximum_double_aligned_seq_cst:
; -O1: ldaxr x8, [x0]
@@ -2708,7 +2708,7 @@ define dso_local float @atomicrmw_fminimum_float_aligned_monotonic(ptr %ptr, flo
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_monotonic:
; -O1: ldxr w8, [x0]
@@ -2722,7 +2722,7 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acquire(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acquire:
; -O1: ldaxr w8, [x0]
@@ -2736,7 +2736,7 @@ define dso_local float @atomicrmw_fminimum_float_aligned_release(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_release:
; -O1: ldxr w8, [x0]
@@ -2750,7 +2750,7 @@ define dso_local float @atomicrmw_fminimum_float_aligned_acq_rel(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
@@ -2764,7 +2764,7 @@ define dso_local float @atomicrmw_fminimum_float_aligned_seq_cst(ptr %ptr, float
; -O0: ldaxr w8, [x10]
; -O0: cmp w8, w11
; -O0: stlxr w9, w12, [x10]
-; -O0: subs w8, w8, w9
+; -O0: subs w9, w8, w9
;
; -O1-LABEL: atomicrmw_fminimum_float_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
@@ -2778,7 +2778,7 @@ define dso_local double @atomicrmw_fminimum_double_aligned_monotonic(ptr %ptr, d
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_monotonic:
; -O1: ldxr x8, [x0]
@@ -2792,7 +2792,7 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acquire(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acquire:
; -O1: ldaxr x8, [x0]
@@ -2806,7 +2806,7 @@ define dso_local double @atomicrmw_fminimum_double_aligned_release(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_release:
; -O1: ldxr x8, [x0]
@@ -2820,7 +2820,7 @@ define dso_local double @atomicrmw_fminimum_double_aligned_acq_rel(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_acq_rel:
; -O1: ldaxr x8, [x0]
@@ -2834,7 +2834,7 @@ define dso_local double @atomicrmw_fminimum_double_aligned_seq_cst(ptr %ptr, dou
; -O0: ldaxr x8, [x10]
; -O0: cmp x8, x11
; -O0: stlxr w9, x12, [x10]
-; -O0: subs x8, x8, x9
+; -O0: subs x9, x8, x9
;
; -O1-LABEL: atomicrmw_fminimum_double_aligned_seq_cst:
; -O1: ldaxr x8, [x0]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 6da7795f8b5e81..aa4182a7fbf813 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -496,25 +496,24 @@ define i32 @fetch_and_nand(ptr %p) #0 {
; CHECK-NOLSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB6_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: and w8, w10, #0x7
+; CHECK-NOLSE-O0-NEXT: and w8, w9, #0x7
; CHECK-NOLSE-O0-NEXT: mvn w12, w8
; CHECK-NOLSE-O0-NEXT: LBB6_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB6_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
; CHECK-NOLSE-O0-NEXT: b.ne LBB6_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB6_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB6_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB6_2
; CHECK-NOLSE-O0-NEXT: LBB6_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB6_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB6_5
; CHECK-NOLSE-O0-NEXT: b LBB6_1
@@ -539,11 +538,9 @@ define i32 @fetch_and_nand(ptr %p) #0 {
; CHECK-OUTLINE-O0-NEXT: and w8, w0, #0x7
; CHECK-OUTLINE-O0-NEXT: mvn w1, w8
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_rel
-; CHECK-OUTLINE-O0-NEXT: ldr w9, [sp, #8] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w8, w0
-; CHECK-OUTLINE-O0-NEXT: mov w0, w8
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9
+; CHECK-OUTLINE-O0-NEXT: subs w8, w0, w8
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: b.eq LBB6_2
; CHECK-OUTLINE-O0-NEXT: b LBB6_1
@@ -577,15 +574,14 @@ define i32 @fetch_and_nand(ptr %p) #0 {
; CHECK-LSE-O0-NEXT: b LBB6_1
; CHECK-LSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-LSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-LSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-LSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-LSE-O0-NEXT: and w8, w10, #0x7
-; CHECK-LSE-O0-NEXT: mvn w8, w8
-; CHECK-LSE-O0-NEXT: mov x9, x10
-; CHECK-LSE-O0-NEXT: casl w9, w8, [x11]
+; CHECK-LSE-O0-NEXT: and w8, w9, #0x7
+; CHECK-LSE-O0-NEXT: mvn w10, w8
; CHECK-LSE-O0-NEXT: mov x8, x9
+; CHECK-LSE-O0-NEXT: casl w8, w10, [x11]
; CHECK-LSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-LSE-O0-NEXT: subs w9, w9, w10
+; CHECK-LSE-O0-NEXT: subs w9, w8, w9
; CHECK-LSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-LSE-O0-NEXT: b.eq LBB6_2
; CHECK-LSE-O0-NEXT: b LBB6_1
@@ -634,25 +630,24 @@ define i64 @fetch_and_nand_64(ptr %p) #0 {
; CHECK-NOLSE-O0-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB7_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: and x8, x10, #0x7
+; CHECK-NOLSE-O0-NEXT: and x8, x9, #0x7
; CHECK-NOLSE-O0-NEXT: mvn x12, x8
; CHECK-NOLSE-O0-NEXT: LBB7_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB7_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB7_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB7_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB7_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB7_2
; CHECK-NOLSE-O0-NEXT: LBB7_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB7_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #8] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB7_5
; CHECK-NOLSE-O0-NEXT: b LBB7_1
@@ -677,11 +672,9 @@ define i64 @fetch_and_nand_64(ptr %p) #0 {
; CHECK-OUTLINE-O0-NEXT: and x8, x0, #0x7
; CHECK-OUTLINE-O0-NEXT: mvn x1, x8
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_acq_rel
-; CHECK-OUTLINE-O0-NEXT: ldr x9, [sp] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-O0-NEXT: mov x0, x8
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs x8, x8, x9
+; CHECK-OUTLINE-O0-NEXT: subs x8, x0, x8
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #24] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: b.eq LBB7_2
; CHECK-OUTLINE-O0-NEXT: b LBB7_1
@@ -715,15 +708,14 @@ define i64 @fetch_and_nand_64(ptr %p) #0 {
; CHECK-LSE-O0-NEXT: b LBB7_1
; CHECK-LSE-O0-NEXT: LBB7_1: ; %atomicrmw.start
; CHECK-LSE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-LSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-LSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-LSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-LSE-O0-NEXT: and x8, x10, #0x7
-; CHECK-LSE-O0-NEXT: mvn x8, x8
-; CHECK-LSE-O0-NEXT: mov x9, x10
-; CHECK-LSE-O0-NEXT: casal x9, x8, [x11]
+; CHECK-LSE-O0-NEXT: and x8, x9, #0x7
+; CHECK-LSE-O0-NEXT: mvn x10, x8
; CHECK-LSE-O0-NEXT: mov x8, x9
+; CHECK-LSE-O0-NEXT: casal x8, x10, [x11]
; CHECK-LSE-O0-NEXT: str x8, [sp, #8] ; 8-byte Spill
-; CHECK-LSE-O0-NEXT: subs x9, x9, x10
+; CHECK-LSE-O0-NEXT: subs x9, x8, x9
; CHECK-LSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-LSE-O0-NEXT: b.eq LBB7_2
; CHECK-LSE-O0-NEXT: b LBB7_1
@@ -768,25 +760,24 @@ define i32 @fetch_and_or(ptr %p) #0 {
; CHECK-NOLSE-O0-NEXT: LBB8_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB8_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: mov w8, #5 ; =0x5
-; CHECK-NOLSE-O0-NEXT: orr w12, w10, w8
+; CHECK-NOLSE-O0-NEXT: orr w12, w9, w8
; CHECK-NOLSE-O0-NEXT: LBB8_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB8_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
; CHECK-NOLSE-O0-NEXT: b.ne LBB8_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB8_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB8_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB8_2
; CHECK-NOLSE-O0-NEXT: LBB8_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB8_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB8_5
; CHECK-NOLSE-O0-NEXT: b LBB8_1
@@ -842,24 +833,23 @@ define i64 @fetch_and_or_64(ptr %p) #0 {
; CHECK-NOLSE-O0-NEXT: LBB9_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB9_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: orr x12, x10, #0x7
+; CHECK-NOLSE-O0-NEXT: orr x12, x9, #0x7
; CHECK-NOLSE-O0-NEXT: LBB9_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB9_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB9_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB9_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB9_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB9_2
; CHECK-NOLSE-O0-NEXT: LBB9_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB9_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #8] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB9_5
; CHECK-NOLSE-O0-NEXT: b LBB9_1
@@ -3240,27 +3230,26 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: b LBB40_1
; CHECK-NOLSE-O0-NEXT: LBB40_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB40_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB37_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: add w12, w9, w8, uxth
-; CHECK-NOLSE-O0-NEXT: LBB40_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB40_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add w12, w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: LBB37_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB37_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB40_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB37_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB40_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB40_2
-; CHECK-NOLSE-O0-NEXT: LBB40_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB40_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB37_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB37_2
+; CHECK-NOLSE-O0-NEXT: LBB37_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB37_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB40_5
; CHECK-NOLSE-O0-NEXT: b LBB40_1
@@ -3333,26 +3322,25 @@ define i16 @atomicrmw_xchg_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: b LBB41_1
; CHECK-NOLSE-O0-NEXT: LBB41_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB41_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB38_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w12, [sp, #24] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: LBB41_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB41_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB41_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB38_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB41_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB41_2
-; CHECK-NOLSE-O0-NEXT: LBB41_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB41_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB38_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB38_2
+; CHECK-NOLSE-O0-NEXT: LBB38_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB38_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB41_5
; CHECK-NOLSE-O0-NEXT: b LBB41_1
@@ -3426,27 +3414,26 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: b LBB42_1
; CHECK-NOLSE-O0-NEXT: LBB42_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB42_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB39_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: subs w12, w8, w9
-; CHECK-NOLSE-O0-NEXT: LBB42_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB42_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: subs w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB39_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB39_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB42_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB39_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB42_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB42_2
-; CHECK-NOLSE-O0-NEXT: LBB42_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB42_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB39_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB39_2
+; CHECK-NOLSE-O0-NEXT: LBB39_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB39_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB42_5
; CHECK-NOLSE-O0-NEXT: b LBB42_1
@@ -3524,27 +3511,26 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: b LBB43_1
; CHECK-NOLSE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB43_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB40_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: and w12, w8, w9
-; CHECK-NOLSE-O0-NEXT: LBB43_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB43_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: and w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB40_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB40_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB43_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB40_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB43_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB43_2
-; CHECK-NOLSE-O0-NEXT: LBB43_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB43_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB40_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB40_2
+; CHECK-NOLSE-O0-NEXT: LBB40_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB40_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB43_5
; CHECK-NOLSE-O0-NEXT: b LBB43_1
@@ -3622,27 +3608,26 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: b LBB44_1
; CHECK-NOLSE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB44_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB41_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: orr w12, w8, w9
-; CHECK-NOLSE-O0-NEXT: LBB44_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB44_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: orr w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB41_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB41_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB44_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB41_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB44_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB44_2
-; CHECK-NOLSE-O0-NEXT: LBB44_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB44_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB41_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB41_2
+; CHECK-NOLSE-O0-NEXT: LBB41_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB41_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB44_5
; CHECK-NOLSE-O0-NEXT: b LBB44_1
@@ -3716,27 +3701,26 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: b LBB45_1
; CHECK-NOLSE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB45_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB42_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: eor w12, w8, w9
-; CHECK-NOLSE-O0-NEXT: LBB45_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB45_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: eor w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB42_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB42_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB45_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB42_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB45_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB45_2
-; CHECK-NOLSE-O0-NEXT: LBB45_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB45_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB42_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB42_2
+; CHECK-NOLSE-O0-NEXT: LBB42_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB42_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB45_5
; CHECK-NOLSE-O0-NEXT: b LBB45_1
@@ -3810,36 +3794,35 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB46_1
-; CHECK-NOLSE-O0-NEXT: LBB46_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB43_1
+; CHECK-NOLSE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB46_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB43_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: sxth w10, w8
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, le
-; CHECK-NOLSE-O0-NEXT: LBB46_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB46_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: sxth w10, w9
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w8, sxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, le
+; CHECK-NOLSE-O0-NEXT: LBB43_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB43_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB46_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB43_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB46_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB46_2
-; CHECK-NOLSE-O0-NEXT: LBB46_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB46_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB43_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB43_2
+; CHECK-NOLSE-O0-NEXT: LBB43_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB43_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB46_5
-; CHECK-NOLSE-O0-NEXT: b LBB46_1
-; CHECK-NOLSE-O0-NEXT: LBB46_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB43_5
+; CHECK-NOLSE-O0-NEXT: b LBB43_1
+; CHECK-NOLSE-O0-NEXT: LBB43_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
@@ -3855,8 +3838,8 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB46_1
-; CHECK-OUTLINE-O0-NEXT: LBB46_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: b LBB43_1
+; CHECK-OUTLINE-O0-NEXT: LBB43_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
@@ -3867,15 +3850,13 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, le
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_acq
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w9, w0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
-; CHECK-OUTLINE-O0-NEXT: mov w0, w9
-; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9, uxth
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB46_2
-; CHECK-OUTLINE-O0-NEXT: b LBB46_1
-; CHECK-OUTLINE-O0-NEXT: LBB46_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB43_2
+; CHECK-OUTLINE-O0-NEXT: b LBB43_1
+; CHECK-OUTLINE-O0-NEXT: LBB43_2: ; %atomicrmw.end
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
@@ -3897,28 +3878,28 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O1-LABEL: atomicrmw_max_i16:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB47_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
; CHECK-NOLSE-O1-NEXT: sxth w9, w8
; CHECK-NOLSE-O1-NEXT: cmp w9, w1, sxth
; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, gt
; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB47_1
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB44_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
; CHECK-OUTLINE-O1-LABEL: atomicrmw_max_i16:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: LBB47_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldxrh w8, [x0]
; CHECK-OUTLINE-O1-NEXT: sxth w9, w8
; CHECK-OUTLINE-O1-NEXT: cmp w9, w1, sxth
; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, gt
; CHECK-OUTLINE-O1-NEXT: stlxrh w10, w9, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB47_1
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB44_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
@@ -3931,36 +3912,35 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB47_1
-; CHECK-NOLSE-O0-NEXT: LBB47_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB44_1
+; CHECK-NOLSE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB47_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB44_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: sxth w10, w8
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, gt
-; CHECK-NOLSE-O0-NEXT: LBB47_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB47_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: sxth w10, w9
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w8, sxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, gt
+; CHECK-NOLSE-O0-NEXT: LBB44_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB44_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB47_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB44_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB47_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB47_2
-; CHECK-NOLSE-O0-NEXT: LBB47_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB47_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB44_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB44_2
+; CHECK-NOLSE-O0-NEXT: LBB44_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB44_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB47_5
-; CHECK-NOLSE-O0-NEXT: b LBB47_1
-; CHECK-NOLSE-O0-NEXT: LBB47_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB44_5
+; CHECK-NOLSE-O0-NEXT: b LBB44_1
+; CHECK-NOLSE-O0-NEXT: LBB44_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
@@ -3976,8 +3956,8 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB47_1
-; CHECK-OUTLINE-O0-NEXT: LBB47_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: b LBB44_1
+; CHECK-OUTLINE-O0-NEXT: LBB44_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
@@ -3988,15 +3968,13 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, gt
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_rel
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w9, w0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
-; CHECK-OUTLINE-O0-NEXT: mov w0, w9
-; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9, uxth
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB47_2
-; CHECK-OUTLINE-O0-NEXT: b LBB47_1
-; CHECK-OUTLINE-O0-NEXT: LBB47_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB44_2
+; CHECK-OUTLINE-O0-NEXT: b LBB44_1
+; CHECK-OUTLINE-O0-NEXT: LBB44_2: ; %atomicrmw.end
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
@@ -4019,14 +3997,14 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O1-LABEL: atomicrmw_umin_i16:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: and w9, w1, #0xffff
-; CHECK-NOLSE-O1-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldaxrh w8, [x0]
; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
; CHECK-NOLSE-O1-NEXT: cmp w8, w9
; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, lo
; CHECK-NOLSE-O1-NEXT: stlxrh w11, w10, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB48_1
+; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB45_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
@@ -4034,14 +4012,14 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O1-LABEL: atomicrmw_umin_i16:
; CHECK-OUTLINE-O1: ; %bb.0:
; CHECK-OUTLINE-O1-NEXT: and w9, w1, #0xffff
-; CHECK-OUTLINE-O1-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldaxrh w8, [x0]
; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, lo
; CHECK-OUTLINE-O1-NEXT: stlxrh w11, w10, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB48_1
+; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB45_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
@@ -4054,36 +4032,35 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB48_1
-; CHECK-NOLSE-O0-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB45_1
+; CHECK-NOLSE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB48_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB45_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: uxth w10, w8
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ls
-; CHECK-NOLSE-O0-NEXT: LBB48_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB48_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: uxth w10, w9
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w8, uxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, ls
+; CHECK-NOLSE-O0-NEXT: LBB45_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB45_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB48_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB45_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB48_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB48_2
-; CHECK-NOLSE-O0-NEXT: LBB48_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB48_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB45_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB45_2
+; CHECK-NOLSE-O0-NEXT: LBB45_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB45_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB48_5
-; CHECK-NOLSE-O0-NEXT: b LBB48_1
-; CHECK-NOLSE-O0-NEXT: LBB48_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB45_5
+; CHECK-NOLSE-O0-NEXT: b LBB45_1
+; CHECK-NOLSE-O0-NEXT: LBB45_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
@@ -4099,8 +4076,8 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB48_1
-; CHECK-OUTLINE-O0-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: b LBB45_1
+; CHECK-OUTLINE-O0-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
@@ -4111,15 +4088,13 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, ls
; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w9, w0
-; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
-; CHECK-OUTLINE-O0-NEXT: mov w0, w9
-; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9, uxth
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB48_2
-; CHECK-OUTLINE-O0-NEXT: b LBB48_1
-; CHECK-OUTLINE-O0-NEXT: LBB48_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB45_2
+; CHECK-OUTLINE-O0-NEXT: b LBB45_1
+; CHECK-OUTLINE-O0-NEXT: LBB45_2: ; %atomicrmw.end
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
@@ -4142,14 +4117,14 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O1-LABEL: atomicrmw_umax_i16:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: and w9, w1, #0xffff
-; CHECK-NOLSE-O1-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
; CHECK-NOLSE-O1-NEXT: cmp w8, w9
; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, hi
; CHECK-NOLSE-O1-NEXT: stxrh w11, w10, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB49_1
+; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB46_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
@@ -4157,14 +4132,14 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O1-LABEL: atomicrmw_umax_i16:
; CHECK-OUTLINE-O1: ; %bb.0:
; CHECK-OUTLINE-O1-NEXT: and w9, w1, #0xffff
-; CHECK-OUTLINE-O1-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldxrh w8, [x0]
; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, hi
; CHECK-OUTLINE-O1-NEXT: stxrh w11, w10, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB49_1
+; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB46_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
@@ -4177,41 +4152,40 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB49_1
-; CHECK-NOLSE-O0-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB46_1
+; CHECK-NOLSE-O0-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB49_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB46_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: uxth w10, w8
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
-; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, hi
-; CHECK-NOLSE-O0-NEXT: LBB49_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB49_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: uxth w10, w9
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w8, uxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, hi
+; CHECK-NOLSE-O0-NEXT: LBB46_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB46_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
-; CHECK-NOLSE-O0-NEXT: b.ne LBB49_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB46_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB49_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB49_2
-; CHECK-NOLSE-O0-NEXT: LBB49_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB49_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: uxth w9, w8
-; CHECK-NOLSE-O0-NEXT: mov w8, w10
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB46_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB46_2
+; CHECK-NOLSE-O0-NEXT: LBB46_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB46_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w9
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB49_5
-; CHECK-NOLSE-O0-NEXT: b LBB49_1
-; CHECK-NOLSE-O0-NEXT: LBB49_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB46_5
+; CHECK-NOLSE-O0-NEXT: b LBB46_1
+; CHECK-NOLSE-O0-NEXT: LBB46_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_umax_i16:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_min_i16:
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
@@ -4222,17 +4196,17 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB49_1
-; CHECK-OUTLINE-O0-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: b LBB46_1
+; CHECK-OUTLINE-O0-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: uxth w9, w0
-; CHECK-OUTLINE-O0-NEXT: subs w9, w9, w8, uxth
-; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, hi
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_relax
+; CHECK-OUTLINE-O0-NEXT: sxth w9, w0
+; CHECK-OUTLINE-O0-NEXT: subs w9, w9, w8, sxth
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, le
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_acq
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: mov w9, w0
; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #12] ; 4-byte Spill
@@ -4240,147 +4214,979 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O0-NEXT: mov w0, w9
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9, uxth
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB49_2
-; CHECK-OUTLINE-O0-NEXT: b LBB49_1
-; CHECK-OUTLINE-O0-NEXT: LBB49_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB46_2
+; CHECK-OUTLINE-O0-NEXT: b LBB46_1
+; CHECK-OUTLINE-O0-NEXT: LBB46_2: ; %atomicrmw.end
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_umax_i16:
+; CHECK-LSE-O1-LABEL: atomicrmw_min_i16:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldumaxh w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ldsminah w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_umax_i16:
+; CHECK-LSE-O0-LABEL: atomicrmw_min_i16:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldumaxh w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ldsminah w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw umax ptr %ptr, i16 %rhs monotonic
+ %res = atomicrmw min ptr %ptr, i16 %rhs acquire
ret i16 %res
}
-define i32 @atomicrmw_add_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_add_i32:
+define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_max_i16:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB50_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB47_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: add w9, w8, w1
-; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB50_1
+; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
+; CHECK-NOLSE-O1-NEXT: sxth w9, w8
+; CHECK-NOLSE-O1-NEXT: cmp w9, w1, sxth
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, gt
+; CHECK-NOLSE-O1-NEXT: stlxrh w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB47_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_add_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_max_i16:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov w0, w1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd4_acq_rel
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB47_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldxrh w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: sxth w9, w8
+; CHECK-OUTLINE-O1-NEXT: cmp w9, w1, sxth
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, gt
+; CHECK-OUTLINE-O1-NEXT: stlxrh w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB47_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i16:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB50_1
-; CHECK-NOLSE-O0-NEXT: LBB50_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB47_1
+; CHECK-NOLSE-O0-NEXT: LBB47_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB50_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB47_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: add w12, w10, w8
-; CHECK-NOLSE-O0-NEXT: LBB50_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB50_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: sxth w10, w8
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, gt
+; CHECK-NOLSE-O0-NEXT: LBB47_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB47_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB50_4
+; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB47_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB50_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB50_2
-; CHECK-NOLSE-O0-NEXT: LBB50_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB50_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB47_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB47_2
+; CHECK-NOLSE-O0-NEXT: LBB47_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB47_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w8
+; CHECK-NOLSE-O0-NEXT: mov w8, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB50_5
-; CHECK-NOLSE-O0-NEXT: b LBB50_1
-; CHECK-NOLSE-O0-NEXT: LBB50_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB47_5
+; CHECK-NOLSE-O0-NEXT: b LBB47_1
+; CHECK-NOLSE-O0-NEXT: LBB47_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_add_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_max_i16:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov w0, w1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd4_acq_rel
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: ret
-;
-; CHECK-LSE-O1-LABEL: atomicrmw_add_i32:
-; CHECK-LSE-O1: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB47_1
+; CHECK-OUTLINE-O0-NEXT: LBB47_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: sxth w9, w0
+; CHECK-OUTLINE-O0-NEXT: subs w9, w9, w8, sxth
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, gt
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_rel
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: mov w9, w0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
+; CHECK-OUTLINE-O0-NEXT: mov w0, w9
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9, uxth
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB47_2
+; CHECK-OUTLINE-O0-NEXT: b LBB47_1
+; CHECK-OUTLINE-O0-NEXT: LBB47_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_max_i16:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: ldsmaxlh w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_max_i16:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: ldsmaxlh w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw max ptr %ptr, i16 %rhs release
+ ret i16 %res
+}
+
+define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umin_i16:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: and w9, w1, #0xffff
+; CHECK-NOLSE-O1-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldaxrh w8, [x0]
+; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-NOLSE-O1-NEXT: cmp w8, w9
+; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, lo
+; CHECK-NOLSE-O1-NEXT: stlxrh w11, w10, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB48_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_umin_i16:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: and w9, w1, #0xffff
+; CHECK-OUTLINE-O1-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldaxrh w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
+; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, lo
+; CHECK-OUTLINE-O1-NEXT: stlxrh w11, w10, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB48_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i16:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB48_1
+; CHECK-NOLSE-O0-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB48_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: uxth w10, w8
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ls
+; CHECK-NOLSE-O0-NEXT: LBB48_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB48_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB48_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB48_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB48_2
+; CHECK-NOLSE-O0-NEXT: LBB48_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB48_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w8
+; CHECK-NOLSE-O0-NEXT: mov w8, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB48_5
+; CHECK-NOLSE-O0-NEXT: b LBB48_1
+; CHECK-NOLSE-O0-NEXT: LBB48_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_umin_i16:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB48_1
+; CHECK-OUTLINE-O0-NEXT: LBB48_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: uxth w9, w0
+; CHECK-OUTLINE-O0-NEXT: subs w9, w9, w8, uxth
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, ls
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_acq_rel
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: mov w9, w0
+; CHECK-OUTLINE-O0-NEXT: str w9, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
+; CHECK-OUTLINE-O0-NEXT: mov w0, w9
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9, uxth
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB48_2
+; CHECK-OUTLINE-O0-NEXT: b LBB48_1
+; CHECK-OUTLINE-O0-NEXT: LBB48_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_umin_i16:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: lduminalh w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_umin_i16:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: lduminalh w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw umin ptr %ptr, i16 %rhs seq_cst
+ ret i16 %res
+}
+
+define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umax_i16:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: and w9, w1, #0xffff
+; CHECK-NOLSE-O1-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
+; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-NOLSE-O1-NEXT: cmp w8, w9
+; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, hi
+; CHECK-NOLSE-O1-NEXT: stxrh w11, w10, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB49_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_umax_i16:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: and w9, w1, #0xffff
+; CHECK-OUTLINE-O1-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldxrh w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
+; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, hi
+; CHECK-OUTLINE-O1-NEXT: stxrh w11, w10, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB49_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i16:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldrh w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB49_1
+; CHECK-NOLSE-O0-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB49_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: uxth w10, w8
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
+; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, hi
+; CHECK-NOLSE-O0-NEXT: LBB49_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB49_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxrh w10, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w10, w8, uxth
+; CHECK-NOLSE-O0-NEXT: b.ne LBB49_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB49_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxrh w9, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w9, LBB49_2
+; CHECK-NOLSE-O0-NEXT: LBB49_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB49_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w10, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: uxth w9, w8
+; CHECK-NOLSE-O0-NEXT: mov w8, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10, uxth
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB49_5
+; CHECK-NOLSE-O0-NEXT: b LBB49_1
+; CHECK-NOLSE-O0-NEXT: LBB49_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_umax_i16:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldrh w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB49_1
+; CHECK-OUTLINE-O0-NEXT: LBB49_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: uxth w9, w0
+; CHECK-OUTLINE-O0-NEXT: subs w9, w9, w8, uxth
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, hi
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas2_relax
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: uxth w8, w8
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w0, uxth
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB49_2
+; CHECK-OUTLINE-O0-NEXT: b LBB49_1
+; CHECK-OUTLINE-O0-NEXT: LBB49_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_umax_i16:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: ldumaxh w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_umax_i16:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: ldumaxh w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw umax ptr %ptr, i16 %rhs monotonic
+ ret i16 %res
+}
+
+define i32 @atomicrmw_add_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_add_i32:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: LBB50_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: add w9, w8, w1
+; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB50_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_add_i32:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mov w0, w1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd4_acq_rel
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i32:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB50_1
+; CHECK-NOLSE-O0-NEXT: LBB50_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB47_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB47_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB47_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB47_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB47_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB47_2
+; CHECK-NOLSE-O0-NEXT: LBB47_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB47_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB50_5
+; CHECK-NOLSE-O0-NEXT: b LBB50_1
+; CHECK-NOLSE-O0-NEXT: LBB50_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_add_i32:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov w0, w1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd4_acq_rel
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_add_i32:
+; CHECK-LSE-O1: ; %bb.0:
; CHECK-LSE-O1-NEXT: ldaddal w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_add_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_add_i32:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: ldaddal w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw add ptr %ptr, i32 %rhs seq_cst
+ ret i32 %res
+}
+
+define i32 @atomicrmw_xchg_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i32:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: mov x8, x0
+; CHECK-NOLSE-O1-NEXT: LBB51_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldxr w0, [x8]
+; CHECK-NOLSE-O1-NEXT: stxr w9, w1, [x8]
+; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB51_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i32:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mov w0, w1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_swp4_relax
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i32:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB51_1
+; CHECK-NOLSE-O0-NEXT: LBB51_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB48_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w12, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: LBB51_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB51_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB48_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB48_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB48_2
+; CHECK-NOLSE-O0-NEXT: LBB48_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB48_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB51_5
+; CHECK-NOLSE-O0-NEXT: b LBB51_1
+; CHECK-NOLSE-O0-NEXT: LBB51_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_xchg_i32:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov w0, w1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_swp4_relax
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i32:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: swp w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i32:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: swp w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw xchg ptr %ptr, i32 %rhs monotonic
+ ret i32 %res
+}
+
+define i32 @atomicrmw_sub_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_sub_i32:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: LBB52_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: sub w9, w8, w1
+; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB52_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_sub_i32:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: neg w0, w1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd4_acq
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i32:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB52_1
+; CHECK-NOLSE-O0-NEXT: LBB52_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB49_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: subs w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB49_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB49_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB49_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB49_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB49_2
+; CHECK-NOLSE-O0-NEXT: LBB49_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB49_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB52_5
+; CHECK-NOLSE-O0-NEXT: b LBB52_1
+; CHECK-NOLSE-O0-NEXT: LBB52_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_sub_i32:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov w9, w1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: mov w8, wzr
+; CHECK-OUTLINE-O0-NEXT: subs w0, w8, w9
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd4_acq
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_sub_i32:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: neg w8, w1
+; CHECK-LSE-O1-NEXT: ldadda w8, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_sub_i32:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: neg w8, w1
+; CHECK-LSE-O0-NEXT: ldadda w8, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw sub ptr %ptr, i32 %rhs acquire
+ ret i32 %res
+}
+
+define i32 @atomicrmw_and_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_and_i32:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: LBB53_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: and w9, w8, w1
+; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB53_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_and_i32:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mvn w0, w1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldclr4_rel
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i32:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB53_1
+; CHECK-NOLSE-O0-NEXT: LBB53_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB50_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: and w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB50_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB50_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB50_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB50_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB50_2
+; CHECK-NOLSE-O0-NEXT: LBB50_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB50_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB53_5
+; CHECK-NOLSE-O0-NEXT: b LBB53_1
+; CHECK-NOLSE-O0-NEXT: LBB53_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_and_i32:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov w9, w1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: mov w8, #-1 ; =0xffffffff
+; CHECK-OUTLINE-O0-NEXT: eor w0, w8, w9
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldclr4_rel
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_and_i32:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: mvn w8, w1
+; CHECK-LSE-O1-NEXT: ldclrl w8, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_and_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldaddal w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: mvn w8, w1
+; CHECK-LSE-O0-NEXT: ldclrl w8, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw and ptr %ptr, i32 %rhs release
+ ret i32 %res
+}
+
+define i32 @atomicrmw_or_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_or_i32:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: LBB54_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: orr w9, w8, w1
+; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB54_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_or_i32:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mov w0, w1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldset4_acq_rel
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i32:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB54_1
+; CHECK-NOLSE-O0-NEXT: LBB54_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB51_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: orr w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB51_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB51_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB51_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB51_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB51_2
+; CHECK-NOLSE-O0-NEXT: LBB51_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB51_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB54_5
+; CHECK-NOLSE-O0-NEXT: b LBB54_1
+; CHECK-NOLSE-O0-NEXT: LBB54_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_or_i32:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov w0, w1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldset4_acq_rel
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_or_i32:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: ldsetal w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_or_i32:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: ldsetal w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw or ptr %ptr, i32 %rhs seq_cst
+ ret i32 %res
+}
+
+define i32 @atomicrmw_xor_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_xor_i32:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: LBB55_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: eor w9, w8, w1
+; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB55_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_xor_i32:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mov w0, w1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldeor4_relax
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i32:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB55_1
+; CHECK-NOLSE-O0-NEXT: LBB55_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB52_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: eor w12, w9, w8
+; CHECK-NOLSE-O0-NEXT: LBB52_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB52_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB52_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB52_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB52_2
+; CHECK-NOLSE-O0-NEXT: LBB52_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB52_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB55_5
+; CHECK-NOLSE-O0-NEXT: b LBB55_1
+; CHECK-NOLSE-O0-NEXT: LBB55_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_xor_i32:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov w0, w1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldeor4_relax
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_xor_i32:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: ldeor w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_xor_i32:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: ldeor w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw add ptr %ptr, i32 %rhs seq_cst
+ %res = atomicrmw xor ptr %ptr, i32 %rhs monotonic
ret i32 %res
}
-define i32 @atomicrmw_xchg_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i32:
+define i32 @atomicrmw_min_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_min_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: mov x8, x0
-; CHECK-NOLSE-O1-NEXT: LBB51_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB56_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldxr w0, [x8]
-; CHECK-NOLSE-O1-NEXT: stxr w9, w1, [x8]
-; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB51_1
+; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp w8, w1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lt
+; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB53_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
-; CHECK-NOLSE-O1-NEXT: ; kill: def $w0 killed $w0 killed $x0
+; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_min_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov w0, w1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_swp4_relax
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB53_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lt
+; CHECK-OUTLINE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB53_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4388,91 +5194,111 @@ define i32 @atomicrmw_xchg_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB51_1
-; CHECK-NOLSE-O0-NEXT: LBB51_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB53_1
+; CHECK-NOLSE-O0-NEXT: LBB53_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB51_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB53_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w12, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: LBB51_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB51_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: subs w10, w9, w8
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, le
+; CHECK-NOLSE-O0-NEXT: LBB53_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB53_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB51_4
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB53_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB51_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB51_2
-; CHECK-NOLSE-O0-NEXT: LBB51_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB51_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB53_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB53_2
+; CHECK-NOLSE-O0-NEXT: LBB53_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB53_1 Depth=1
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB51_5
-; CHECK-NOLSE-O0-NEXT: b LBB51_1
-; CHECK-NOLSE-O0-NEXT: LBB51_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB53_5
+; CHECK-NOLSE-O0-NEXT: b LBB53_1
+; CHECK-NOLSE-O0-NEXT: LBB53_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_xchg_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_min_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov w0, w1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_swp4_relax
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB53_1
+; CHECK-OUTLINE-O0-NEXT: LBB53_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, le
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w8, w0, w8
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB53_2
+; CHECK-OUTLINE-O0-NEXT: b LBB53_1
+; CHECK-OUTLINE-O0-NEXT: LBB53_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_min_i32:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: swp w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ldsmina w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_min_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: swp w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ldsmina w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw xchg ptr %ptr, i32 %rhs monotonic
+ %res = atomicrmw min ptr %ptr, i32 %rhs acquire
ret i32 %res
}
-define i32 @atomicrmw_sub_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_sub_i32:
+define i32 @atomicrmw_max_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_max_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB52_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB54_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: sub w9, w8, w1
-; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB52_1
+; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp w8, w1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, gt
+; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB54_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_sub_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_max_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: neg w0, w1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd4_acq
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB54_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldxr w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, gt
+; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB54_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4480,96 +5306,111 @@ define i32 @atomicrmw_sub_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB52_1
-; CHECK-NOLSE-O0-NEXT: LBB52_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB54_1
+; CHECK-NOLSE-O0-NEXT: LBB54_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB52_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB54_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: subs w12, w10, w8
-; CHECK-NOLSE-O0-NEXT: LBB52_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB52_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: subs w10, w9, w8
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, gt
+; CHECK-NOLSE-O0-NEXT: LBB54_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB54_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB52_4
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB54_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB52_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB52_2
-; CHECK-NOLSE-O0-NEXT: LBB52_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB52_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB54_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB54_2
+; CHECK-NOLSE-O0-NEXT: LBB54_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB54_1 Depth=1
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB52_5
-; CHECK-NOLSE-O0-NEXT: b LBB52_1
-; CHECK-NOLSE-O0-NEXT: LBB52_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB54_5
+; CHECK-NOLSE-O0-NEXT: b LBB54_1
+; CHECK-NOLSE-O0-NEXT: LBB54_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_sub_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_max_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov w9, w1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w8, wzr
-; CHECK-OUTLINE-O0-NEXT: subs w0, w8, w9
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd4_acq
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB54_1
+; CHECK-OUTLINE-O0-NEXT: LBB54_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, gt
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_rel
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w8, w0, w8
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB54_2
+; CHECK-OUTLINE-O0-NEXT: b LBB54_1
+; CHECK-OUTLINE-O0-NEXT: LBB54_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_sub_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_max_i32:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: neg w8, w1
-; CHECK-LSE-O1-NEXT: ldadda w8, w0, [x0]
+; CHECK-LSE-O1-NEXT: ldsmaxl w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_sub_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_max_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: neg w8, w1
-; CHECK-LSE-O0-NEXT: ldadda w8, w0, [x0]
+; CHECK-LSE-O0-NEXT: ldsmaxl w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw sub ptr %ptr, i32 %rhs acquire
+ %res = atomicrmw max ptr %ptr, i32 %rhs release
ret i32 %res
}
-define i32 @atomicrmw_and_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_and_i32:
+define i32 @atomicrmw_umin_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umin_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB53_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB55_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: and w9, w8, w1
+; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp w8, w1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lo
; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB53_1
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB55_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_and_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_umin_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mvn w0, w1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldclr4_rel
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB55_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lo
+; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB55_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4577,96 +5418,111 @@ define i32 @atomicrmw_and_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB53_1
-; CHECK-NOLSE-O0-NEXT: LBB53_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB55_1
+; CHECK-NOLSE-O0-NEXT: LBB55_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB53_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB55_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: and w12, w10, w8
-; CHECK-NOLSE-O0-NEXT: LBB53_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB53_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: subs w10, w9, w8
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, ls
+; CHECK-NOLSE-O0-NEXT: LBB55_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB55_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB53_4
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB55_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB53_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB53_2
-; CHECK-NOLSE-O0-NEXT: LBB53_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB53_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB55_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB55_2
+; CHECK-NOLSE-O0-NEXT: LBB55_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB55_1 Depth=1
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB53_5
-; CHECK-NOLSE-O0-NEXT: b LBB53_1
-; CHECK-NOLSE-O0-NEXT: LBB53_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB55_5
+; CHECK-NOLSE-O0-NEXT: b LBB55_1
+; CHECK-NOLSE-O0-NEXT: LBB55_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_and_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_umin_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov w9, w1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w8, #-1 ; =0xffffffff
-; CHECK-OUTLINE-O0-NEXT: eor w0, w8, w9
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldclr4_rel
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB55_1
+; CHECK-OUTLINE-O0-NEXT: LBB55_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, ls
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w8, w0, w8
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB55_2
+; CHECK-OUTLINE-O0-NEXT: b LBB55_1
+; CHECK-OUTLINE-O0-NEXT: LBB55_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_and_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_umin_i32:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: mvn w8, w1
-; CHECK-LSE-O1-NEXT: ldclrl w8, w0, [x0]
+; CHECK-LSE-O1-NEXT: lduminal w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_and_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_umin_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: mvn w8, w1
-; CHECK-LSE-O0-NEXT: ldclrl w8, w0, [x0]
+; CHECK-LSE-O0-NEXT: lduminal w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw and ptr %ptr, i32 %rhs release
+ %res = atomicrmw umin ptr %ptr, i32 %rhs seq_cst
ret i32 %res
}
-define i32 @atomicrmw_or_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_or_i32:
+define i32 @atomicrmw_umax_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umax_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB54_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB56_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: orr w9, w8, w1
-; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB54_1
+; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp w8, w1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, hi
+; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB56_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_or_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_min_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov w0, w1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldset4_acq_rel
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB56_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lt
+; CHECK-OUTLINE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB56_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4674,92 +5530,111 @@ define i32 @atomicrmw_or_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB54_1
-; CHECK-NOLSE-O0-NEXT: LBB54_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB56_1
+; CHECK-NOLSE-O0-NEXT: LBB56_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB54_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB56_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: orr w12, w10, w8
-; CHECK-NOLSE-O0-NEXT: LBB54_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB54_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: subs w10, w9, w8
+; CHECK-NOLSE-O0-NEXT: csel w12, w9, w8, hi
+; CHECK-NOLSE-O0-NEXT: LBB56_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB56_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB54_4
+; CHECK-NOLSE-O0-NEXT: ldaxr w8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp w8, w9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB56_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB54_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB54_2
-; CHECK-NOLSE-O0-NEXT: LBB54_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB54_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB56_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, w12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB56_2
+; CHECK-NOLSE-O0-NEXT: LBB56_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB56_1 Depth=1
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: subs w9, w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB54_5
-; CHECK-NOLSE-O0-NEXT: b LBB54_1
-; CHECK-NOLSE-O0-NEXT: LBB54_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB56_5
+; CHECK-NOLSE-O0-NEXT: b LBB56_1
+; CHECK-NOLSE-O0-NEXT: LBB56_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_or_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_min_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov w0, w1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldset4_acq_rel
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB56_1
+; CHECK-OUTLINE-O0-NEXT: LBB56_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, hi
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_relax
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w8, w0, w8
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB56_2
+; CHECK-OUTLINE-O0-NEXT: b LBB56_1
+; CHECK-OUTLINE-O0-NEXT: LBB56_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_or_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_min_i32:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldsetal w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ldsmina w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_or_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_min_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldsetal w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ldsmina w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw or ptr %ptr, i32 %rhs seq_cst
+ %res = atomicrmw min ptr %ptr, i32 %rhs acquire
ret i32 %res
}
-define i32 @atomicrmw_xor_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_xor_i32:
+define i32 @atomicrmw_max_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_max_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB55_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB57_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: eor w9, w8, w1
-; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB55_1
+; CHECK-NOLSE-O1-NEXT: cmp w8, w1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, gt
+; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB57_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_xor_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_max_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov w0, w1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldeor4_relax
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB57_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldxr w8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, gt
+; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB57_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4767,93 +5642,114 @@ define i32 @atomicrmw_xor_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB55_1
-; CHECK-NOLSE-O0-NEXT: LBB55_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB57_1
+; CHECK-NOLSE-O0-NEXT: LBB57_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB55_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB57_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: eor w12, w10, w8
-; CHECK-NOLSE-O0-NEXT: LBB55_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB55_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: subs w9, w10, w8
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, gt
+; CHECK-NOLSE-O0-NEXT: LBB57_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB57_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB55_4
+; CHECK-NOLSE-O0-NEXT: b.ne LBB57_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB55_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB57_2 Depth=2
; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB55_2
-; CHECK-NOLSE-O0-NEXT: LBB55_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB55_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB57_2
+; CHECK-NOLSE-O0-NEXT: LBB57_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB57_1 Depth=1
; CHECK-NOLSE-O0-NEXT: mov w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB55_5
-; CHECK-NOLSE-O0-NEXT: b LBB55_1
-; CHECK-NOLSE-O0-NEXT: LBB55_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
+; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB57_5
+; CHECK-NOLSE-O0-NEXT: b LBB57_1
+; CHECK-NOLSE-O0-NEXT: LBB57_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_xor_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_max_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov w0, w1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldeor4_relax
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB57_1
+; CHECK-OUTLINE-O0-NEXT: LBB57_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, gt
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_rel
+; CHECK-OUTLINE-O0-NEXT: ldr w9, [sp, #8] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: mov w8, w0
+; CHECK-OUTLINE-O0-NEXT: mov w0, w8
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9
+; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB57_2
+; CHECK-OUTLINE-O0-NEXT: b LBB57_1
+; CHECK-OUTLINE-O0-NEXT: LBB57_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_xor_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_max_i32:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldeor w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ldsmaxl w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_xor_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_max_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldeor w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ldsmaxl w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw xor ptr %ptr, i32 %rhs monotonic
+ %res = atomicrmw max ptr %ptr, i32 %rhs release
ret i32 %res
}
-define i32 @atomicrmw_min_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_min_i32:
+define i32 @atomicrmw_umin_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umin_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB56_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB58_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
; CHECK-NOLSE-O1-NEXT: cmp w8, w1
-; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lt
-; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB56_1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lo
+; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB58_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_min_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_umin_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: LBB56_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: LBB58_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0]
; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
-; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lt
-; CHECK-OUTLINE-O1-NEXT: stxr w10, w9, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB56_1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lo
+; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB58_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4861,39 +5757,39 @@ define i32 @atomicrmw_min_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB56_1
-; CHECK-NOLSE-O0-NEXT: LBB56_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB58_1
+; CHECK-NOLSE-O0-NEXT: LBB58_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB56_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB58_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: subs w9, w10, w8
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, le
-; CHECK-NOLSE-O0-NEXT: LBB56_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB56_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ls
+; CHECK-NOLSE-O0-NEXT: LBB58_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB58_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB56_4
+; CHECK-NOLSE-O0-NEXT: b.ne LBB58_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB56_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB58_2 Depth=2
; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB56_2
-; CHECK-NOLSE-O0-NEXT: LBB56_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB56_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB58_2
+; CHECK-NOLSE-O0-NEXT: LBB58_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB58_1 Depth=1
; CHECK-NOLSE-O0-NEXT: mov w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB56_5
-; CHECK-NOLSE-O0-NEXT: b LBB56_1
-; CHECK-NOLSE-O0-NEXT: LBB56_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB58_5
+; CHECK-NOLSE-O0-NEXT: b LBB58_1
+; CHECK-NOLSE-O0-NEXT: LBB58_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_min_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_umin_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
@@ -4904,71 +5800,71 @@ define i32 @atomicrmw_min_i32(ptr %ptr, i32 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB56_1
-; CHECK-OUTLINE-O0-NEXT: LBB56_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: b LBB58_1
+; CHECK-OUTLINE-O0-NEXT: LBB58_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
-; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, le
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, ls
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldr w9, [sp, #8] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: mov w8, w0
; CHECK-OUTLINE-O0-NEXT: mov w0, w8
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB56_2
-; CHECK-OUTLINE-O0-NEXT: b LBB56_1
-; CHECK-OUTLINE-O0-NEXT: LBB56_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB58_2
+; CHECK-OUTLINE-O0-NEXT: b LBB58_1
+; CHECK-OUTLINE-O0-NEXT: LBB58_2: ; %atomicrmw.end
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_min_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_umin_i32:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldsmina w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: lduminal w1, w0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_min_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_umin_i32:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldsmina w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: lduminal w1, w0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw min ptr %ptr, i32 %rhs acquire
+ %res = atomicrmw umin ptr %ptr, i32 %rhs seq_cst
ret i32 %res
}
-define i32 @atomicrmw_max_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_max_i32:
+define i32 @atomicrmw_umax_i32(ptr %ptr, i32 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umax_i32:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB57_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB59_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
; CHECK-NOLSE-O1-NEXT: cmp w8, w1
-; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, gt
-; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB57_1
+; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, hi
+; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB59_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov w0, w8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_max_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_umax_i32:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: LBB57_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: LBB59_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldxr w8, [x0]
; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
-; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, gt
-; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB57_1
+; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, hi
+; CHECK-OUTLINE-O1-NEXT: stxr w10, w9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB59_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-OUTLINE-O1-NEXT: mov w0, w8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i32:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -4976,39 +5872,39 @@ define i32 @atomicrmw_max_i32(ptr %ptr, i32 %rhs) {
; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB57_1
-; CHECK-NOLSE-O0-NEXT: LBB57_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB59_1
+; CHECK-NOLSE-O0-NEXT: LBB59_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
-; CHECK-NOLSE-O0-NEXT: ; Child Loop BB57_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB59_2 Depth 2
; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: subs w9, w10, w8
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, gt
-; CHECK-NOLSE-O0-NEXT: LBB57_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB57_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, hi
+; CHECK-NOLSE-O0-NEXT: LBB59_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB59_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
; CHECK-NOLSE-O0-NEXT: cmp w9, w10
-; CHECK-NOLSE-O0-NEXT: b.ne LBB57_4
+; CHECK-NOLSE-O0-NEXT: b.ne LBB59_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB57_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB59_2 Depth=2
; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB57_2
-; CHECK-NOLSE-O0-NEXT: LBB57_4: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB57_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB59_2
+; CHECK-NOLSE-O0-NEXT: LBB59_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB59_1 Depth=1
; CHECK-NOLSE-O0-NEXT: mov w8, w9
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB57_5
-; CHECK-NOLSE-O0-NEXT: b LBB57_1
-; CHECK-NOLSE-O0-NEXT: LBB57_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB59_5
+; CHECK-NOLSE-O0-NEXT: b LBB59_1
+; CHECK-NOLSE-O0-NEXT: LBB59_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_max_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_umax_i32:
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
@@ -5019,300 +5915,348 @@ define i32 @atomicrmw_max_i32(ptr %ptr, i32 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB57_1
-; CHECK-OUTLINE-O0-NEXT: LBB57_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: b LBB59_1
+; CHECK-OUTLINE-O0-NEXT: LBB59_1: ; %atomicrmw.start
; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
-; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, gt
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_rel
+; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, hi
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_relax
; CHECK-OUTLINE-O0-NEXT: ldr w9, [sp, #8] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: mov w8, w0
; CHECK-OUTLINE-O0-NEXT: mov w0, w8
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9
; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB57_2
-; CHECK-OUTLINE-O0-NEXT: b LBB57_1
-; CHECK-OUTLINE-O0-NEXT: LBB57_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB59_2
+; CHECK-OUTLINE-O0-NEXT: b LBB59_1
+; CHECK-OUTLINE-O0-NEXT: LBB59_2: ; %atomicrmw.end
; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_max_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_umax_i32:
+; CHECK-LSE-O1: ; %bb.0:
+; CHECK-LSE-O1-NEXT: ldumax w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ret
+;
+; CHECK-LSE-O0-LABEL: atomicrmw_umax_i32:
+; CHECK-LSE-O0: ; %bb.0:
+; CHECK-LSE-O0-NEXT: ldumax w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ret
+ %res = atomicrmw umax ptr %ptr, i32 %rhs monotonic
+ ret i32 %res
+}
+
+define i64 @atomicrmw_add_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_add_i64:
+; CHECK-NOLSE-O1: ; %bb.0:
+; CHECK-NOLSE-O1-NEXT: LBB60_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: add x9, x8, x1
+; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB60_1
+; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-NOLSE-O1-NEXT: mov x0, x8
+; CHECK-NOLSE-O1-NEXT: ret
+;
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_add_i64:
+; CHECK-OUTLINE-O1: ; %bb.0:
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mov x0, x1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd8_acq_rel
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: ret
+;
+; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i64:
+; CHECK-NOLSE-O0: ; %bb.0:
+; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str x1, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
+; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB60_1
+; CHECK-NOLSE-O0-NEXT: LBB60_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NOLSE-O0-NEXT: ; Child Loop BB57_2 Depth 2
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: add x12, x9, x8
+; CHECK-NOLSE-O0-NEXT: LBB57_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB57_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
+; CHECK-NOLSE-O0-NEXT: b.ne LBB57_4
+; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB57_2 Depth=2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB57_2
+; CHECK-NOLSE-O0-NEXT: LBB57_4: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB57_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
+; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB60_5
+; CHECK-NOLSE-O0-NEXT: b LBB60_1
+; CHECK-NOLSE-O0-NEXT: LBB60_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr x0, [sp] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
+; CHECK-NOLSE-O0-NEXT: ret
+;
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_add_i64:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov x0, x1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd8_acq_rel
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: ret
+;
+; CHECK-LSE-O1-LABEL: atomicrmw_add_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldsmaxl w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: ldaddal x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_max_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_add_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldsmaxl w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: ldaddal x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw max ptr %ptr, i32 %rhs release
- ret i32 %res
+ %res = atomicrmw add ptr %ptr, i64 %rhs seq_cst
+ ret i64 %res
}
-define i32 @atomicrmw_umin_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_umin_i32:
+define i64 @atomicrmw_xchg_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i64:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB58_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB61_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: cmp w8, w1
-; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, lo
-; CHECK-NOLSE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB58_1
+; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: stxr w9, x1, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB61_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
-; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_umin_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: LBB58_1: ; %atomicrmw.start
-; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-OUTLINE-O1-NEXT: ldaxr w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
-; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, lo
-; CHECK-OUTLINE-O1-NEXT: stlxr w10, w9, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB58_1
-; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
-; CHECK-OUTLINE-O1-NEXT: mov w0, w8
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: mov x0, x1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_swp8_relax
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB58_1
-; CHECK-NOLSE-O0-NEXT: LBB58_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str x1, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
+; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB61_1
+; CHECK-NOLSE-O0-NEXT: LBB61_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB58_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: subs w9, w10, w8
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ls
-; CHECK-NOLSE-O0-NEXT: LBB58_2: ; %atomicrmw.start
-; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB58_1 Depth=1
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x12, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: LBB61_2: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB61_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB58_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB58_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB58_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB58_2
; CHECK-NOLSE-O0-NEXT: LBB58_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB58_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB58_5
-; CHECK-NOLSE-O0-NEXT: b LBB58_1
-; CHECK-NOLSE-O0-NEXT: LBB58_5: ; %atomicrmw.end
-; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
+; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB61_5
+; CHECK-NOLSE-O0-NEXT: b LBB61_1
+; CHECK-NOLSE-O0-NEXT: LBB61_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr x0, [sp] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_umin_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_xchg_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB58_1
-; CHECK-OUTLINE-O0-NEXT: LBB58_1: ; %atomicrmw.start
-; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
-; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, ls
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_acq_rel
-; CHECK-OUTLINE-O0-NEXT: ldr w9, [sp, #8] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w8, w0
-; CHECK-OUTLINE-O0-NEXT: mov w0, w8
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB58_2
-; CHECK-OUTLINE-O0-NEXT: b LBB58_1
-; CHECK-OUTLINE-O0-NEXT: LBB58_2: ; %atomicrmw.end
-; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov x0, x1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_swp8_relax
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_umin_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: lduminal w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: swp x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_umin_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: lduminal w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: swp x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw umin ptr %ptr, i32 %rhs seq_cst
- ret i32 %res
+ %res = atomicrmw xchg ptr %ptr, i64 %rhs monotonic
+ ret i64 %res
}
-define i32 @atomicrmw_umax_i32(ptr %ptr, i32 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_umax_i32:
+define i64 @atomicrmw_sub_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_sub_i64:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB59_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB62_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldxr w8, [x0]
-; CHECK-NOLSE-O1-NEXT: cmp w8, w1
-; CHECK-NOLSE-O1-NEXT: csel w9, w8, w1, hi
-; CHECK-NOLSE-O1-NEXT: stxr w10, w9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB59_1
+; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: sub x9, x8, x1
+; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB62_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
-; CHECK-NOLSE-O1-NEXT: mov w0, w8
+; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_umax_i32:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_sub_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: LBB59_1: ; %atomicrmw.start
-; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-OUTLINE-O1-NEXT: ldxr w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: cmp w8, w1
-; CHECK-OUTLINE-O1-NEXT: csel w9, w8, w1, hi
-; CHECK-OUTLINE-O1-NEXT: stxr w10, w9, [x0]
-; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB59_1
-; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
-; CHECK-OUTLINE-O1-NEXT: mov w0, w8
+; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
+; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O1-NEXT: mov x2, x0
+; CHECK-OUTLINE-O1-NEXT: neg x0, x1
+; CHECK-OUTLINE-O1-NEXT: mov x1, x2
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd8_acq
+; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_umax_i32:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB59_1
-; CHECK-NOLSE-O0-NEXT: LBB59_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: str x1, [sp, #16] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
+; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: b LBB62_1
+; CHECK-NOLSE-O0-NEXT: LBB62_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB59_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr w10, [sp, #28] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-NOLSE-O0-NEXT: subs w9, w10, w8
-; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, hi
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: subs x12, x9, x8
; CHECK-NOLSE-O0-NEXT: LBB59_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB59_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr w9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp w9, w10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB59_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB59_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, w12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB59_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB59_2
; CHECK-NOLSE-O0-NEXT: LBB59_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB59_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov w8, w9
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #12] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w10
-; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB59_5
-; CHECK-NOLSE-O0-NEXT: b LBB59_1
-; CHECK-NOLSE-O0-NEXT: LBB59_5: ; %atomicrmw.end
-; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
+; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
+; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
+; CHECK-NOLSE-O0-NEXT: b.eq LBB62_5
+; CHECK-NOLSE-O0-NEXT: b LBB62_1
+; CHECK-NOLSE-O0-NEXT: LBB62_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: ldr x0, [sp] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_umax_i32:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_sub_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #48
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 48
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: str w1, [sp, #24] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: ldr w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b LBB59_1
-; CHECK-OUTLINE-O0-NEXT: LBB59_1: ; %atomicrmw.start
-; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #28] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #16] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #8] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs w9, w0, w8
-; CHECK-OUTLINE-O0-NEXT: csel w1, w0, w8, hi
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas4_relax
-; CHECK-OUTLINE-O0-NEXT: ldr w9, [sp, #8] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov w8, w0
-; CHECK-OUTLINE-O0-NEXT: mov w0, w8
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #12] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs w8, w8, w9
-; CHECK-OUTLINE-O0-NEXT: str w0, [sp, #28] ; 4-byte Spill
-; CHECK-OUTLINE-O0-NEXT: b.eq LBB59_2
-; CHECK-OUTLINE-O0-NEXT: b LBB59_1
-; CHECK-OUTLINE-O0-NEXT: LBB59_2: ; %atomicrmw.end
-; CHECK-OUTLINE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Reload
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #48
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: mov x9, x1
+; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: mov x8, xzr
+; CHECK-OUTLINE-O0-NEXT: subs x0, x8, x9
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd8_acq
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_umax_i32:
+; CHECK-LSE-O1-LABEL: atomicrmw_sub_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldumax w1, w0, [x0]
+; CHECK-LSE-O1-NEXT: neg x8, x1
+; CHECK-LSE-O1-NEXT: ldadda x8, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_umax_i32:
+; CHECK-LSE-O0-LABEL: atomicrmw_sub_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldumax w1, w0, [x0]
+; CHECK-LSE-O0-NEXT: neg x8, x1
+; CHECK-LSE-O0-NEXT: ldadda x8, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw umax ptr %ptr, i32 %rhs monotonic
- ret i32 %res
+ %res = atomicrmw sub ptr %ptr, i64 %rhs acquire
+ ret i64 %res
}
-define i64 @atomicrmw_add_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_add_i64:
+define i64 @atomicrmw_and_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_and_i64:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB60_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB63_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
-; CHECK-NOLSE-O1-NEXT: add x9, x8, x1
+; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: and x9, x8, x1
; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB60_1
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB63_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_add_i64:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_and_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov x0, x1
+; CHECK-OUTLINE-O1-NEXT: mvn x0, x1
; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd8_acq_rel
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldclr8_rel
; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_add_i64:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -5320,38 +6264,37 @@ define i64 @atomicrmw_add_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: str x1, [sp, #16] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB60_1
-; CHECK-NOLSE-O0-NEXT: LBB60_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB63_1
+; CHECK-NOLSE-O0-NEXT: LBB63_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB60_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: add x12, x10, x8
+; CHECK-NOLSE-O0-NEXT: and x12, x9, x8
; CHECK-NOLSE-O0-NEXT: LBB60_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB60_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB60_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB60_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB60_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB60_2
; CHECK-NOLSE-O0-NEXT: LBB60_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB60_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB60_5
-; CHECK-NOLSE-O0-NEXT: b LBB60_1
-; CHECK-NOLSE-O0-NEXT: LBB60_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB63_5
+; CHECK-NOLSE-O0-NEXT: b LBB63_1
+; CHECK-NOLSE-O0-NEXT: LBB63_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_add_i64:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_and_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
@@ -5359,39 +6302,44 @@ define i64 @atomicrmw_add_i64(ptr %ptr, i64 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov x0, x1
+; CHECK-OUTLINE-O0-NEXT: mov x9, x1
; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd8_acq_rel
+; CHECK-OUTLINE-O0-NEXT: mov x8, #-1 ; =0xffffffffffffffff
+; CHECK-OUTLINE-O0-NEXT: eor x0, x8, x9
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldclr8_rel
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_add_i64:
+; CHECK-LSE-O1-LABEL: atomicrmw_and_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldaddal x1, x0, [x0]
+; CHECK-LSE-O1-NEXT: mvn x8, x1
+; CHECK-LSE-O1-NEXT: ldclrl x8, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_add_i64:
+; CHECK-LSE-O0-LABEL: atomicrmw_and_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldaddal x1, x0, [x0]
+; CHECK-LSE-O0-NEXT: mvn x8, x1
+; CHECK-LSE-O0-NEXT: ldclrl x8, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw add ptr %ptr, i64 %rhs seq_cst
+ %res = atomicrmw and ptr %ptr, i64 %rhs release
ret i64 %res
}
-define i64 @atomicrmw_xchg_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_xchg_i64:
+define i64 @atomicrmw_or_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_or_i64:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB61_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB64_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
-; CHECK-NOLSE-O1-NEXT: stxr w9, x1, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w9, LBB61_1
+; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: orr x9, x8, x1
+; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB64_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_xchg_i64:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_or_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
@@ -5400,11 +6348,11 @@ define i64 @atomicrmw_xchg_i64(ptr %ptr, i64 %rhs) {
; CHECK-OUTLINE-O1-NEXT: mov x2, x0
; CHECK-OUTLINE-O1-NEXT: mov x0, x1
; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_swp8_relax
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldset8_acq_rel
; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_xchg_i64:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -5412,37 +6360,37 @@ define i64 @atomicrmw_xchg_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: str x1, [sp, #16] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB61_1
-; CHECK-NOLSE-O0-NEXT: LBB61_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB64_1
+; CHECK-NOLSE-O0-NEXT: LBB64_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB61_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: ldr x12, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: orr x12, x9, x8
; CHECK-NOLSE-O0-NEXT: LBB61_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB61_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB61_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB61_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB61_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB61_2
; CHECK-NOLSE-O0-NEXT: LBB61_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB61_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB61_5
-; CHECK-NOLSE-O0-NEXT: b LBB61_1
-; CHECK-NOLSE-O0-NEXT: LBB61_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB64_5
+; CHECK-NOLSE-O0-NEXT: b LBB64_1
+; CHECK-NOLSE-O0-NEXT: LBB64_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_xchg_i64:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_or_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
@@ -5452,51 +6400,51 @@ define i64 @atomicrmw_xchg_i64(ptr %ptr, i64 %rhs) {
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: mov x0, x1
; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_swp8_relax
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldset8_acq_rel
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_xchg_i64:
+; CHECK-LSE-O1-LABEL: atomicrmw_or_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: swp x1, x0, [x0]
+; CHECK-LSE-O1-NEXT: ldsetal x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_xchg_i64:
+; CHECK-LSE-O0-LABEL: atomicrmw_or_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: swp x1, x0, [x0]
+; CHECK-LSE-O0-NEXT: ldsetal x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw xchg ptr %ptr, i64 %rhs monotonic
+ %res = atomicrmw or ptr %ptr, i64 %rhs seq_cst
ret i64 %res
}
-define i64 @atomicrmw_sub_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_sub_i64:
+define i64 @atomicrmw_xor_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_xor_i64:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB62_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB65_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
-; CHECK-NOLSE-O1-NEXT: sub x9, x8, x1
+; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: eor x9, x8, x1
; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0]
-; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB62_1
+; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB65_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_sub_i64:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_xor_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: neg x0, x1
+; CHECK-OUTLINE-O1-NEXT: mov x0, x1
; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldadd8_acq
+; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldeor8_relax
; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_sub_i64:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -5504,38 +6452,37 @@ define i64 @atomicrmw_sub_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: str x1, [sp, #16] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: ldr x8, [x0]
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: b LBB62_1
-; CHECK-NOLSE-O0-NEXT: LBB62_1: ; %atomicrmw.start
+; CHECK-NOLSE-O0-NEXT: b LBB65_1
+; CHECK-NOLSE-O0-NEXT: LBB65_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB62_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: subs x12, x10, x8
+; CHECK-NOLSE-O0-NEXT: eor x12, x9, x8
; CHECK-NOLSE-O0-NEXT: LBB62_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB62_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB62_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB62_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB62_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB62_2
; CHECK-NOLSE-O0-NEXT: LBB62_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB62_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: b.eq LBB62_5
-; CHECK-NOLSE-O0-NEXT: b LBB62_1
-; CHECK-NOLSE-O0-NEXT: LBB62_5: ; %atomicrmw.end
+; CHECK-NOLSE-O0-NEXT: b.eq LBB65_5
+; CHECK-NOLSE-O0-NEXT: b LBB65_1
+; CHECK-NOLSE-O0-NEXT: LBB65_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr x0, [sp] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_sub_i64:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_xor_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
@@ -5543,57 +6490,54 @@ define i64 @atomicrmw_sub_i64(ptr %ptr, i64 %rhs) {
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov x9, x1
+; CHECK-OUTLINE-O0-NEXT: mov x0, x1
; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov x8, xzr
-; CHECK-OUTLINE-O0-NEXT: subs x0, x8, x9
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldadd8_acq
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldeor8_relax
; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_sub_i64:
+; CHECK-LSE-O1-LABEL: atomicrmw_xor_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: neg x8, x1
-; CHECK-LSE-O1-NEXT: ldadda x8, x0, [x0]
+; CHECK-LSE-O1-NEXT: ldeor x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_sub_i64:
+; CHECK-LSE-O0-LABEL: atomicrmw_xor_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: neg x8, x1
-; CHECK-LSE-O0-NEXT: ldadda x8, x0, [x0]
+; CHECK-LSE-O0-NEXT: ldeor x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw sub ptr %ptr, i64 %rhs acquire
+ %res = atomicrmw xor ptr %ptr, i64 %rhs monotonic
ret i64 %res
}
-define i64 @atomicrmw_and_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_and_i64:
+define i64 @atomicrmw_min_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_min_i64:
; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: LBB63_1: ; %atomicrmw.start
+; CHECK-NOLSE-O1-NEXT: LBB66_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
-; CHECK-NOLSE-O1-NEXT: and x9, x8, x1
-; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
+; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp x8, x1
+; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, lt
+; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB63_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_and_i64:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_min_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mvn x0, x1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldclr8_rel
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB63_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp x8, x1
+; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, lt
+; CHECK-OUTLINE-O1-NEXT: stxr w10, x9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB63_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov x0, x8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_and_i64:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_min_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -5605,25 +6549,25 @@ define i64 @atomicrmw_and_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: LBB63_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB63_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: and x12, x10, x8
+; CHECK-NOLSE-O0-NEXT: subs x10, x9, x8
+; CHECK-NOLSE-O0-NEXT: csel x12, x9, x8, le
; CHECK-NOLSE-O0-NEXT: LBB63_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB63_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB63_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB63_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB63_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB63_2
; CHECK-NOLSE-O0-NEXT: LBB63_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB63_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB63_5
; CHECK-NOLSE-O0-NEXT: b LBB63_1
@@ -5632,65 +6576,80 @@ define i64 @atomicrmw_and_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_and_i64:
-; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_min_i64:
+; CHECK-OUTLINE-O0: ; %bb.0:
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #64
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 64
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #24] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str x1, [sp, #32] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB63_1
+; CHECK-OUTLINE-O0-NEXT: LBB63_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [sp, #40] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #24] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #32] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov x9, x1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov x8, #-1 ; =0xffffffffffffffff
-; CHECK-OUTLINE-O0-NEXT: eor x0, x8, x9
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldclr8_rel
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: subs x9, x0, x8
+; CHECK-OUTLINE-O0-NEXT: csel x1, x0, x8, le
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_acq
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs x8, x0, x8
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB63_2
+; CHECK-OUTLINE-O0-NEXT: b LBB63_1
+; CHECK-OUTLINE-O0-NEXT: LBB63_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #64
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_and_i64:
+; CHECK-LSE-O1-LABEL: atomicrmw_min_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: mvn x8, x1
-; CHECK-LSE-O1-NEXT: ldclrl x8, x0, [x0]
+; CHECK-LSE-O1-NEXT: ldsmina x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_and_i64:
+; CHECK-LSE-O0-LABEL: atomicrmw_min_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: mvn x8, x1
-; CHECK-LSE-O0-NEXT: ldclrl x8, x0, [x0]
+; CHECK-LSE-O0-NEXT: ldsmina x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw and ptr %ptr, i64 %rhs release
+ %res = atomicrmw min ptr %ptr, i64 %rhs acquire
ret i64 %res
}
-define i64 @atomicrmw_or_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_or_i64:
+define i64 @atomicrmw_max_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_max_i64:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: LBB64_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
-; CHECK-NOLSE-O1-NEXT: orr x9, x8, x1
+; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp x8, x1
+; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, gt
; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB64_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_or_i64:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_max_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov x0, x1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldset8_acq_rel
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB64_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldxr x8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp x8, x1
+; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, gt
+; CHECK-OUTLINE-O1-NEXT: stlxr w10, x9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB64_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov x0, x8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_or_i64:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_max_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -5702,25 +6661,25 @@ define i64 @atomicrmw_or_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: LBB64_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB64_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: orr x12, x10, x8
+; CHECK-NOLSE-O0-NEXT: subs x10, x9, x8
+; CHECK-NOLSE-O0-NEXT: csel x12, x9, x8, gt
; CHECK-NOLSE-O0-NEXT: LBB64_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB64_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB64_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB64_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB64_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB64_2
; CHECK-NOLSE-O0-NEXT: LBB64_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB64_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB64_5
; CHECK-NOLSE-O0-NEXT: b LBB64_1
@@ -5729,61 +6688,80 @@ define i64 @atomicrmw_or_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_or_i64:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_max_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #64
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 64
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #24] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str x1, [sp, #32] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB64_1
+; CHECK-OUTLINE-O0-NEXT: LBB64_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [sp, #40] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #24] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #32] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov x0, x1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldset8_acq_rel
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: subs x9, x0, x8
+; CHECK-OUTLINE-O0-NEXT: csel x1, x0, x8, gt
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_rel
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs x8, x0, x8
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB64_2
+; CHECK-OUTLINE-O0-NEXT: b LBB64_1
+; CHECK-OUTLINE-O0-NEXT: LBB64_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #64
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_or_i64:
+; CHECK-LSE-O1-LABEL: atomicrmw_max_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldsetal x1, x0, [x0]
+; CHECK-LSE-O1-NEXT: ldsmaxl x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_or_i64:
+; CHECK-LSE-O0-LABEL: atomicrmw_max_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldsetal x1, x0, [x0]
+; CHECK-LSE-O0-NEXT: ldsmaxl x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw or ptr %ptr, i64 %rhs seq_cst
+ %res = atomicrmw max ptr %ptr, i64 %rhs release
ret i64 %res
}
-define i64 @atomicrmw_xor_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_xor_i64:
+define i64 @atomicrmw_umin_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umin_i64:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: LBB65_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
-; CHECK-NOLSE-O1-NEXT: eor x9, x8, x1
-; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0]
+; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: cmp x8, x1
+; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, lo
+; CHECK-NOLSE-O1-NEXT: stlxr w10, x9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB65_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
; CHECK-NOLSE-O1-NEXT: mov x0, x8
; CHECK-NOLSE-O1-NEXT: ret
;
-; CHECK-OUTLINE-O1-LABEL: atomicrmw_xor_i64:
+; CHECK-OUTLINE-O1-LABEL: atomicrmw_umin_i64:
; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
-; CHECK-OUTLINE-O1-NEXT: .cfi_def_cfa_offset 16
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w30, -8
-; CHECK-OUTLINE-O1-NEXT: .cfi_offset w29, -16
-; CHECK-OUTLINE-O1-NEXT: mov x2, x0
-; CHECK-OUTLINE-O1-NEXT: mov x0, x1
-; CHECK-OUTLINE-O1-NEXT: mov x1, x2
-; CHECK-OUTLINE-O1-NEXT: bl ___aarch64_ldeor8_relax
-; CHECK-OUTLINE-O1-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-OUTLINE-O1-NEXT: LBB65_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-OUTLINE-O1-NEXT: cmp x8, x1
+; CHECK-OUTLINE-O1-NEXT: csel x9, x8, x1, lo
+; CHECK-OUTLINE-O1-NEXT: stlxr w10, x9, [x0]
+; CHECK-OUTLINE-O1-NEXT: cbnz w10, LBB65_1
+; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
+; CHECK-OUTLINE-O1-NEXT: mov x0, x8
; CHECK-OUTLINE-O1-NEXT: ret
;
-; CHECK-NOLSE-O0-LABEL: atomicrmw_xor_i64:
+; CHECK-NOLSE-O0-LABEL: atomicrmw_umin_i64:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: sub sp, sp, #32
; CHECK-NOLSE-O0-NEXT: .cfi_def_cfa_offset 32
@@ -5795,25 +6773,25 @@ define i64 @atomicrmw_xor_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: LBB65_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB65_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: eor x12, x10, x8
+; CHECK-NOLSE-O0-NEXT: subs x10, x9, x8
+; CHECK-NOLSE-O0-NEXT: csel x12, x9, x8, ls
; CHECK-NOLSE-O0-NEXT: LBB65_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB65_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB65_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB65_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB65_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB65_2
; CHECK-NOLSE-O0-NEXT: LBB65_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB65_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB65_5
; CHECK-NOLSE-O0-NEXT: b LBB65_1
@@ -5822,42 +6800,60 @@ define i64 @atomicrmw_xor_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
; CHECK-NOLSE-O0-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: atomicrmw_xor_i64:
+; CHECK-OUTLINE-O0-LABEL: atomicrmw_umin_i64:
; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #32
-; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
-; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 32
+; CHECK-OUTLINE-O0-NEXT: sub sp, sp, #64
+; CHECK-OUTLINE-O0-NEXT: stp x29, x30, [sp, #48] ; 16-byte Folded Spill
+; CHECK-OUTLINE-O0-NEXT: .cfi_def_cfa_offset 64
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w30, -8
; CHECK-OUTLINE-O0-NEXT: .cfi_offset w29, -16
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #24] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: str x1, [sp, #32] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [x0]
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b LBB65_1
+; CHECK-OUTLINE-O0-NEXT: LBB65_1: ; %atomicrmw.start
+; CHECK-OUTLINE-O0-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [sp, #40] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x2, [sp, #24] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #32] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: mov x0, x1
-; CHECK-OUTLINE-O0-NEXT: ldr x1, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_ldeor8_relax
-; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
-; CHECK-OUTLINE-O0-NEXT: add sp, sp, #32
+; CHECK-OUTLINE-O0-NEXT: subs x9, x0, x8
+; CHECK-OUTLINE-O0-NEXT: csel x1, x0, x8, ls
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_acq_rel
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #8] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: subs x8, x0, x8
+; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
+; CHECK-OUTLINE-O0-NEXT: b.eq LBB65_2
+; CHECK-OUTLINE-O0-NEXT: b LBB65_1
+; CHECK-OUTLINE-O0-NEXT: LBB65_2: ; %atomicrmw.end
+; CHECK-OUTLINE-O0-NEXT: ldr x0, [sp, #16] ; 8-byte Reload
+; CHECK-OUTLINE-O0-NEXT: ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; CHECK-OUTLINE-O0-NEXT: add sp, sp, #64
; CHECK-OUTLINE-O0-NEXT: ret
;
-; CHECK-LSE-O1-LABEL: atomicrmw_xor_i64:
+; CHECK-LSE-O1-LABEL: atomicrmw_umin_i64:
; CHECK-LSE-O1: ; %bb.0:
-; CHECK-LSE-O1-NEXT: ldeor x1, x0, [x0]
+; CHECK-LSE-O1-NEXT: lduminal x1, x0, [x0]
; CHECK-LSE-O1-NEXT: ret
;
-; CHECK-LSE-O0-LABEL: atomicrmw_xor_i64:
+; CHECK-LSE-O0-LABEL: atomicrmw_umin_i64:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldeor x1, x0, [x0]
+; CHECK-LSE-O0-NEXT: lduminal x1, x0, [x0]
; CHECK-LSE-O0-NEXT: ret
- %res = atomicrmw xor ptr %ptr, i64 %rhs monotonic
+ %res = atomicrmw umin ptr %ptr, i64 %rhs seq_cst
ret i64 %res
}
-define i64 @atomicrmw_min_i64(ptr %ptr, i64 %rhs) {
-; CHECK-NOLSE-O1-LABEL: atomicrmw_min_i64:
+define i64 @atomicrmw_umax_i64(ptr %ptr, i64 %rhs) {
+; CHECK-NOLSE-O1-LABEL: atomicrmw_umax_i64:
; CHECK-NOLSE-O1: ; %bb.0:
; CHECK-NOLSE-O1-NEXT: LBB66_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NOLSE-O1-NEXT: ldaxr x8, [x0]
+; CHECK-NOLSE-O1-NEXT: ldxr x8, [x0]
; CHECK-NOLSE-O1-NEXT: cmp x8, x1
-; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, lt
+; CHECK-NOLSE-O1-NEXT: csel x9, x8, x1, hi
; CHECK-NOLSE-O1-NEXT: stxr w10, x9, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w10, LBB66_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -5889,26 +6885,25 @@ define i64 @atomicrmw_min_i64(ptr %ptr, i64 %rhs) {
; CHECK-NOLSE-O0-NEXT: LBB66_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB66_2 Depth 2
-; CHECK-NOLSE-O0-NEXT: ldr x10, [sp, #24] ; 8-byte Reload
+; CHECK-NOLSE-O0-NEXT: ldr x9, [sp, #24] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #8] ; 8-byte Reload
; CHECK-NOLSE-O0-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
-; CHECK-NOLSE-O0-NEXT: subs x9, x10, x8
-; CHECK-NOLSE-O0-NEXT: csel x12, x10, x8, le
+; CHECK-NOLSE-O0-NEXT: subs x10, x9, x8
+; CHECK-NOLSE-O0-NEXT: csel x12, x9, x8, hi
; CHECK-NOLSE-O0-NEXT: LBB66_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB66_1 Depth=1
; CHECK-NOLSE-O0-NEXT: ; => This Inner Loop Header: Depth=2
-; CHECK-NOLSE-O0-NEXT: ldaxr x9, [x11]
-; CHECK-NOLSE-O0-NEXT: cmp x9, x10
+; CHECK-NOLSE-O0-NEXT: ldaxr x8, [x11]
+; CHECK-NOLSE-O0-NEXT: cmp x8, x9
; CHECK-NOLSE-O0-NEXT: b.ne LBB66_4
; CHECK-NOLSE-O0-NEXT: ; %bb.3: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB66_2 Depth=2
-; CHECK-NOLSE-O0-NEXT: stlxr w8, x12, [x11]
-; CHECK-NOLSE-O0-NEXT: cbnz w8, LBB66_2
+; CHECK-NOLSE-O0-NEXT: stlxr w10, x12, [x11]
+; CHECK-NOLSE-O0-NEXT: cbnz w10, LBB66_2
; CHECK-NOLSE-O0-NEXT: LBB66_4: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; in Loop: Header=BB66_1 Depth=1
-; CHECK-NOLSE-O0-NEXT: mov x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp] ; 8-byte Spill
-; CHECK-NOLSE-O0-NEXT: subs x9, x9, x10
+; CHECK-NOLSE-O0-NEXT: subs x9, x8, x9
; CHECK-NOLSE-O0-NEXT: str x8, [sp, #24] ; 8-byte Spill
; CHECK-NOLSE-O0-NEXT: b.eq LBB66_5
; CHECK-NOLSE-O0-NEXT: b LBB66_1
@@ -5936,13 +6931,11 @@ define i64 @atomicrmw_min_i64(ptr %ptr, i64 %rhs) {
; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #32] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #8] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: subs x9, x0, x8
-; CHECK-OUTLINE-O0-NEXT: csel x1, x0, x8, le
-; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_acq
-; CHECK-OUTLINE-O0-NEXT: ldr x9, [sp, #8] ; 8-byte Reload
-; CHECK-OUTLINE-O0-NEXT: mov x8, x0
-; CHECK-OUTLINE-O0-NEXT: mov x0, x8
+; CHECK-OUTLINE-O0-NEXT: csel x1, x0, x8, hi
+; CHECK-OUTLINE-O0-NEXT: bl ___aarch64_cas8_relax
+; CHECK-OUTLINE-O0-NEXT: ldr x8, [sp, #8] ; 8-byte Reload
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #16] ; 8-byte Spill
-; CHECK-OUTLINE-O0-NEXT: subs x8, x8, x9
+; CHECK-OUTLINE-O0-NEXT: subs x8, x0, x8
; CHECK-OUTLINE-O0-NEXT: str x0, [sp, #40] ; 8-byte Spill
; CHECK-OUTLINE-O0-NEXT: b.eq LBB66_2
; CHECK-OUTLINE-O0-NEXT: b LBB66_1
@@ -6829,29 +7822,17 @@ define { ptr, i1 } @cmpxchg_ptr(ptr %ptr, ptr %desired, ptr %new) {
}
define internal double @bitcast_to_double(ptr %ptr) {
-; CHECK-NOLSE-O1-LABEL: bitcast_to_double:
-; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: ldar x8, [x0]
-; CHECK-NOLSE-O1-NEXT: fmov d0, x8
-; CHECK-NOLSE-O1-NEXT: ret
-;
-; CHECK-OUTLINE-O1-LABEL: bitcast_to_double:
-; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: ldar x8, [x0]
-; CHECK-OUTLINE-O1-NEXT: fmov d0, x8
-; CHECK-OUTLINE-O1-NEXT: ret
-;
-; CHECK-NOLSE-O0-LABEL: bitcast_to_double:
-; CHECK-NOLSE-O0: ; %bb.0:
-; CHECK-NOLSE-O0-NEXT: ldar x0, [x0]
-; CHECK-NOLSE-O0-NEXT: fmov d0, x0
-; CHECK-NOLSE-O0-NEXT: ret
+; CHECK-NOLSE-LABEL: bitcast_to_double:
+; CHECK-NOLSE: ; %bb.0:
+; CHECK-NOLSE-NEXT: ldar x8, [x0]
+; CHECK-NOLSE-NEXT: fmov d0, x8
+; CHECK-NOLSE-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: bitcast_to_double:
-; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: ldar x0, [x0]
-; CHECK-OUTLINE-O0-NEXT: fmov d0, x0
-; CHECK-OUTLINE-O0-NEXT: ret
+; CHECK-OUTLINE-LABEL: bitcast_to_double:
+; CHECK-OUTLINE: ; %bb.0:
+; CHECK-OUTLINE-NEXT: ldar x8, [x0]
+; CHECK-OUTLINE-NEXT: fmov d0, x8
+; CHECK-OUTLINE-NEXT: ret
;
; CHECK-LSE-O1-LABEL: bitcast_to_double:
; CHECK-LSE-O1: ; %bb.0:
@@ -6861,8 +7842,8 @@ define internal double @bitcast_to_double(ptr %ptr) {
;
; CHECK-LSE-O0-LABEL: bitcast_to_double:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldar x0, [x0]
-; CHECK-LSE-O0-NEXT: fmov d0, x0
+; CHECK-LSE-O0-NEXT: ldar x8, [x0]
+; CHECK-LSE-O0-NEXT: fmov d0, x8
; CHECK-LSE-O0-NEXT: ret
%load = load atomic i64, ptr %ptr seq_cst, align 8
%bitcast = bitcast i64 %load to double
@@ -6870,29 +7851,17 @@ define internal double @bitcast_to_double(ptr %ptr) {
}
define internal float @bitcast_to_float(ptr %ptr) {
-; CHECK-NOLSE-O1-LABEL: bitcast_to_float:
-; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: ldar w8, [x0]
-; CHECK-NOLSE-O1-NEXT: fmov s0, w8
-; CHECK-NOLSE-O1-NEXT: ret
-;
-; CHECK-OUTLINE-O1-LABEL: bitcast_to_float:
-; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: ldar w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: fmov s0, w8
-; CHECK-OUTLINE-O1-NEXT: ret
-;
-; CHECK-NOLSE-O0-LABEL: bitcast_to_float:
-; CHECK-NOLSE-O0: ; %bb.0:
-; CHECK-NOLSE-O0-NEXT: ldar w0, [x0]
-; CHECK-NOLSE-O0-NEXT: fmov s0, w0
-; CHECK-NOLSE-O0-NEXT: ret
+; CHECK-NOLSE-LABEL: bitcast_to_float:
+; CHECK-NOLSE: ; %bb.0:
+; CHECK-NOLSE-NEXT: ldar w8, [x0]
+; CHECK-NOLSE-NEXT: fmov s0, w8
+; CHECK-NOLSE-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: bitcast_to_float:
-; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: ldar w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
-; CHECK-OUTLINE-O0-NEXT: ret
+; CHECK-OUTLINE-LABEL: bitcast_to_float:
+; CHECK-OUTLINE: ; %bb.0:
+; CHECK-OUTLINE-NEXT: ldar w8, [x0]
+; CHECK-OUTLINE-NEXT: fmov s0, w8
+; CHECK-OUTLINE-NEXT: ret
;
; CHECK-LSE-O1-LABEL: bitcast_to_float:
; CHECK-LSE-O1: ; %bb.0:
@@ -6902,8 +7871,8 @@ define internal float @bitcast_to_float(ptr %ptr) {
;
; CHECK-LSE-O0-LABEL: bitcast_to_float:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldar w0, [x0]
-; CHECK-LSE-O0-NEXT: fmov s0, w0
+; CHECK-LSE-O0-NEXT: ldar w8, [x0]
+; CHECK-LSE-O0-NEXT: fmov s0, w8
; CHECK-LSE-O0-NEXT: ret
%load = load atomic i32, ptr %ptr seq_cst, align 8
%bitcast = bitcast i32 %load to float
@@ -6911,33 +7880,19 @@ define internal float @bitcast_to_float(ptr %ptr) {
}
define internal half @bitcast_to_half(ptr %ptr) {
-; CHECK-NOLSE-O1-LABEL: bitcast_to_half:
-; CHECK-NOLSE-O1: ; %bb.0:
-; CHECK-NOLSE-O1-NEXT: ldarh w8, [x0]
-; CHECK-NOLSE-O1-NEXT: fmov s0, w8
-; CHECK-NOLSE-O1-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O1-NEXT: ret
-;
-; CHECK-OUTLINE-O1-LABEL: bitcast_to_half:
-; CHECK-OUTLINE-O1: ; %bb.0:
-; CHECK-OUTLINE-O1-NEXT: ldarh w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: fmov s0, w8
-; CHECK-OUTLINE-O1-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-O1-NEXT: ret
-;
-; CHECK-NOLSE-O0-LABEL: bitcast_to_half:
-; CHECK-NOLSE-O0: ; %bb.0:
-; CHECK-NOLSE-O0-NEXT: ldarh w0, [x0]
-; CHECK-NOLSE-O0-NEXT: fmov s0, w0
-; CHECK-NOLSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-NOLSE-O0-NEXT: ret
+; CHECK-NOLSE-LABEL: bitcast_to_half:
+; CHECK-NOLSE: ; %bb.0:
+; CHECK-NOLSE-NEXT: ldarh w8, [x0]
+; CHECK-NOLSE-NEXT: fmov s0, w8
+; CHECK-NOLSE-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-NOLSE-NEXT: ret
;
-; CHECK-OUTLINE-O0-LABEL: bitcast_to_half:
-; CHECK-OUTLINE-O0: ; %bb.0:
-; CHECK-OUTLINE-O0-NEXT: ldarh w0, [x0]
-; CHECK-OUTLINE-O0-NEXT: fmov s0, w0
-; CHECK-OUTLINE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
-; CHECK-OUTLINE-O0-NEXT: ret
+; CHECK-OUTLINE-LABEL: bitcast_to_half:
+; CHECK-OUTLINE: ; %bb.0:
+; CHECK-OUTLINE-NEXT: ldarh w8, [x0]
+; CHECK-OUTLINE-NEXT: fmov s0, w8
+; CHECK-OUTLINE-NEXT: ; kill: def $h0 killed $h0 killed $s0
+; CHECK-OUTLINE-NEXT: ret
;
; CHECK-LSE-O1-LABEL: bitcast_to_half:
; CHECK-LSE-O1: ; %bb.0:
@@ -6948,8 +7903,8 @@ define internal half @bitcast_to_half(ptr %ptr) {
;
; CHECK-LSE-O0-LABEL: bitcast_to_half:
; CHECK-LSE-O0: ; %bb.0:
-; CHECK-LSE-O0-NEXT: ldarh w0, [x0]
-; CHECK-LSE-O0-NEXT: fmov s0, w0
+; CHECK-LSE-O0-NEXT: ldarh w8, [x0]
+; CHECK-LSE-O0-NEXT: fmov s0, w8
; CHECK-LSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
; CHECK-LSE-O0-NEXT: ret
%load = load atomic i16, ptr %ptr seq_cst, align 8
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir
index 744b2b96be6253..ccf0ed5822803d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir
@@ -124,8 +124,7 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (dereferenceable load (<2 x i64>))
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub
+ ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (dereferenceable load (<2 x s64>))
; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[LDRQui]], 1
; CHECK-NEXT: STRDui [[DUPi64_]], [[COPY]], 0 :: (store (i64))
%0:gpr(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
index fc954bdc129c26..2b87b1f5feef73 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
@@ -106,8 +106,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADDXrr]], 0 :: (load (s64) from %ir.addr)
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDXrr]]
- ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[LDRXui]]
+ ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[LDRXui]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr(p0) = COPY $x0
@@ -536,8 +535,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 61, 60
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
- ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]]
+ ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[UBFMXri]]
; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 3, 0
; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[ADDXri]]
@@ -588,15 +586,13 @@ body: |
; CHECK-SLOW-LABEL: name: ldrhrox_more_than_one_mem_use_shl
; CHECK-SLOW: liveins: $x0, $x1, $x2, $w1, $x0
; CHECK-SLOW-NEXT: {{ $}}
- ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31
; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0
; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
- ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32
- ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-SLOW-NEXT: [[ADDXrx:%[0-9]+]]:gpr64sp = ADDXrx [[COPY4]], [[COPY3]], 1
+ ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
+ ; CHECK-SLOW-NEXT: [[ADDXrx:%[0-9]+]]:gpr64sp = ADDXrx [[COPY]], [[COPY2]], 1
; CHECK-SLOW-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))
; CHECK-SLOW-NEXT: [[LDRHHui1:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))
; CHECK-SLOW-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHui]], [[LDRHHui1]]
@@ -646,15 +642,13 @@ body: |
; CHECK-SLOW-LABEL: name: ldrhrox_more_than_one_use_shl
; CHECK-SLOW: liveins: $x0, $x1, $x2, $w1, $x0
; CHECK-SLOW-NEXT: {{ $}}
- ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-SLOW-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31
; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0
; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
- ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32
- ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
- ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-SLOW-NEXT: [[ADDXrx:%[0-9]+]]:gpr64sp = ADDXrx [[COPY4]], [[COPY3]], 1
+ ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
+ ; CHECK-SLOW-NEXT: [[ADDXrx:%[0-9]+]]:gpr64sp = ADDXrx [[COPY]], [[COPY2]], 1
; CHECK-SLOW-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))
; CHECK-SLOW-NEXT: [[LDRHHui1:%[0-9]+]]:gpr32 = LDRHHui [[ADDXrx]], 0 :: (load (s16))
; CHECK-SLOW-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRHHui]], [[LDRHHui1]]
@@ -691,8 +685,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 62, 61
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
- ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]]
+ ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[UBFMXri]]
; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY1]], [[COPY]], 0, 1 :: (load (s32) from %ir.addr)
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[LDRWroX]], 0
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
@@ -732,13 +725,11 @@ body: |
; CHECK-FAST-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-FAST-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 60, 59
; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK-FAST-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
- ; CHECK-FAST-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]]
+ ; CHECK-FAST-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY1]], [[UBFMXri]]
; CHECK-FAST-NEXT: [[LDRQroX:%[0-9]+]]:fpr128 = LDRQroX [[COPY1]], [[COPY]], 0, 1 :: (load (s128) from %ir.addr)
; CHECK-FAST-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 4, 0
- ; CHECK-FAST-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[LDRQroX]].dsub
- ; CHECK-FAST-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY [[COPY3]]
- ; CHECK-FAST-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY4]], [[ADDXri]]
+ ; CHECK-FAST-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[LDRQroX]].dsub
+ ; CHECK-FAST-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[ADDXri]]
; CHECK-FAST-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]
; CHECK-FAST-NEXT: RET_ReallyLR implicit [[ADDXrr2]]
;
@@ -751,11 +742,9 @@ body: |
; CHECK-SLOW-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr [[COPY1]], [[UBFMXri]]
; CHECK-SLOW-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADDXrr]], 0 :: (load (s128) from %ir.addr)
; CHECK-SLOW-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 4, 0
- ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[LDRQui]].dsub
- ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-SLOW-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY3]], [[ADDXri]]
- ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY [[ADDXrr]]
- ; CHECK-SLOW-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[COPY4]], [[ADDXrr1]]
+ ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[LDRQui]].dsub
+ ; CHECK-SLOW-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[ADDXri]]
+ ; CHECK-SLOW-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]]
; CHECK-SLOW-NEXT: RET_ReallyLR implicit [[ADDXrr2]]
%0:gpr(i64) = COPY $x0
%1:gpr(i64) = G_CONSTANT i64 4
@@ -825,8 +814,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[COPY]], 61, 60
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
- ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY2]], [[COPY]], 3
+ ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 3
; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY1]], [[COPY]], 0, 1 :: (load (s64) from %ir.addr)
; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 3, 0
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[LDRXroX]], [[ADDXri]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
index 65787cb431c40d..9a9401c32d539f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
@@ -425,9 +425,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %base:gpr64sp = COPY $x0
; CHECK-NEXT: %imp:gpr64 = IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %imp.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: %load:gpr64 = LDRXroW %base, [[COPY1]], 0, 1 :: (load (s64))
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %imp.sub_32
+ ; CHECK-NEXT: %load:gpr64 = LDRXroW %base, [[COPY]], 0, 1 :: (load (s64))
; CHECK-NEXT: $x1 = COPY %load
; CHECK-NEXT: RET_ReallyLR implicit $x1
%base:gpr(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
index 8b127d7982870f..270f3a775a23b5 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
@@ -15,9 +15,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -53,9 +52,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -91,9 +89,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %fold_me:gpr64sp = ANDXri %copy, 4098
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %fold_me.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
index 045130b6ba19dd..f0884cafb4f70c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
@@ -81,9 +81,8 @@ body: |
; CHECK-NEXT: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub
- ; CHECK-NEXT: %copy:gpr32all = COPY [[SUBREG_TO_REG]]
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy
- ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
+ ; CHECK-NEXT: %copy:gpr32 = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: TBNZW %copy, 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -118,9 +117,8 @@ body: |
; CHECK-NEXT: %copy:gpr32 = COPY $w0
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %zext.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
index 217c3a57addb1d..b19af1e3cd236a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
@@ -15,9 +15,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 2, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 2, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -53,9 +52,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %fold_me:gpr64 = UBFMXri %copy, 59, 58
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %fold_me.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -92,9 +90,8 @@ body: |
; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %fold_cst:gpr64 = MOVi64imm -5
; CHECK-NEXT: %fold_me:gpr64 = LSLVXr %copy, %fold_cst
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %fold_me.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %fold_me.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -131,9 +128,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %shl:gpr64 = UBFMXri %copy, 62, 61
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %shl.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %shl.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -173,9 +169,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 4, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 4, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
index b943a8e0bc2970..cb6082ce99380d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
@@ -14,9 +14,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
index 91f68858b8d364..80c46765461593 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
@@ -13,9 +13,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -55,9 +54,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -92,9 +90,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -168,9 +165,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -205,9 +201,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %copy.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBZW [[COPY1]], 3, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy.sub_32
+ ; CHECK-NEXT: TBZW [[COPY]], 3, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
index 315ca9360dca65..be25264b3707d6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir
@@ -33,10 +33,9 @@ body: |
; SELECT: liveins: $x0, $x1
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %reg:gpr64all = COPY $x0
- ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
- ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg.sub_32
; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
- ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY]], 32, implicit-def $nzcv
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
@@ -160,11 +159,10 @@ body: |
; SELECT: liveins: $x0, $x1
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %reg:gpr64all = COPY $x0
- ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32
- ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg.sub_32
; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567
; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
- ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY]], 32, implicit-def $nzcv
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
@@ -199,9 +197,8 @@ body: |
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
- ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
- ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 0, implicit-def $nzcv
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %and_lhs.sub_32
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY]], 0, implicit-def $nzcv
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
@@ -239,9 +236,8 @@ body: |
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
- ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
- ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 8, implicit-def $nzcv
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %and_lhs.sub_32
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY]], 8, implicit-def $nzcv
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
@@ -279,9 +275,8 @@ body: |
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %cmp_rhs:gpr64sp = COPY $x1
; SELECT-NEXT: %and_lhs:gpr64all = COPY $x0
- ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %and_lhs.sub_32
- ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 16, implicit-def $nzcv
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %and_lhs.sub_32
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY]], 16, implicit-def $nzcv
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
@@ -774,10 +769,9 @@ body: |
; SELECT-NEXT: {{ $}}
; SELECT-NEXT: %reg0:gpr64 = COPY $x0
; SELECT-NEXT: %and:gpr64common = ANDXri %reg0, 4103
- ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg0.sub_32
- ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+ ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0.sub_32
; SELECT-NEXT: %cmp_rhs:gpr64common = SBFMXri %and, 5, 63
- ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 1, implicit-def $nzcv
+ ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY]], 1, implicit-def $nzcv
; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; SELECT-NEXT: $w0 = COPY %cmp
; SELECT-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
index 49ed1f35b03af0..7c2f0f50e04d4f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
@@ -40,10 +40,9 @@ body: |
; CHECK: liveins: $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
- ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
+ ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY1]], 16
; CHECK-NEXT: $x3 = COPY %res
; CHECK-NEXT: RET_ReallyLR implicit $x3
%1:gpr(i64) = COPY $x1
@@ -676,11 +675,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+ ; CHECK-NEXT: STRXroX [[COPY2]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = COPY $w1
@@ -712,11 +710,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+ ; CHECK-NEXT: STRXroX [[COPY2]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = COPY $w1
@@ -748,11 +745,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+ ; CHECK-NEXT: STRXroX [[COPY2]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = COPY $w1
@@ -784,11 +780,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32
; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
+ ; CHECK-NEXT: STRXroX [[COPY2]], [[COPY]], %zext, 0, 1 :: (store (p0))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%1:gpr(i32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
index 8d0b835f941abb..71eb90ccb4dcb1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
@@ -32,8 +32,7 @@ body: |
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
; CHECK-NEXT: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
- ; CHECK-NEXT: STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
+ ; CHECK-NEXT: STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store (p0) into @addr)
; CHECK-NEXT: BR [[MOVaddrBA]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.block (ir-block-address-taken %ir-block.block):
@@ -57,8 +56,7 @@ body: |
; LARGE-PIC: bb.0 (%ir-block.0):
; LARGE-PIC-NEXT: [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
; LARGE-PIC-NEXT: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
- ; LARGE-PIC-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
- ; LARGE-PIC-NEXT: STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
+ ; LARGE-PIC-NEXT: STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store (p0) into @addr)
; LARGE-PIC-NEXT: BR [[MOVaddrBA]]
; LARGE-PIC-NEXT: {{ $}}
; LARGE-PIC-NEXT: bb.1.block (ir-block-address-taken %ir-block.block):
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
index cae8160f4a86c2..a9a6d30dddcbd1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
@@ -232,10 +232,9 @@ body: |
; CHECK: liveins: $w0, $w1, $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub
- ; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]]
+ ; CHECK-NEXT: %reg0:gpr32 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: %reg1:gpr32sp = COPY $w1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0
- ; CHECK-NEXT: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, [[COPY]], 10, implicit-def $nzcv
+ ; CHECK-NEXT: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, %reg0, 10, implicit-def $nzcv
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
; CHECK-NEXT: $w0 = COPY %cmp
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index ce07431ad35787..d0f21aa25bb948 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -30,11 +30,10 @@ body: |
bb.0:
; CHECK-LABEL: name: const_s8
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
- ; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0:gpr(i8) = G_CONSTANT i8 42
- %1:gpr(i32) = G_ANYEXT %0(i8)
- $w0 = COPY %1(i32)
+ ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]
+ %0:gpr(s8) = G_CONSTANT i8 42
+ %1:gpr(s32) = G_ANYEXT %0(s8)
+ $w0 = COPY %1(s32)
...
---
@@ -45,11 +44,10 @@ body: |
bb.0:
; CHECK-LABEL: name: const_s16
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
- ; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0:gpr(i16) = G_CONSTANT i16 42
- %1:gpr(i32) = G_ANYEXT %0(i16)
- $w0 = COPY %1(i32)
+ ; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]
+ %0:gpr(s16) = G_CONSTANT i16 42
+ %1:gpr(s32) = G_ANYEXT %0(s16)
+ $w0 = COPY %1(s32)
...
---
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
index 651efcbfd754ff..2de2898e4b12aa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir
@@ -383,9 +383,8 @@ body: |
; CHECK-LABEL: name: dup_v2p0
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
- ; CHECK-NEXT: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY]]
; CHECK-NEXT: $q0 = COPY [[DUPv2i64gpr]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:gpr(p0) = COPY $x0
@@ -445,8 +444,7 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
- ; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
+ ; CHECK-NEXT: %cst:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
index 9b14cedb66263d..24ee069358394b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
@@ -42,9 +42,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
%1:gpr(i16) = G_LOAD %0 :: (load (i16) from %ir.addr)
%2:gpr(i32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
index a6521f730bb9c4..5da1322403d0bc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
@@ -34,28 +34,24 @@ body: |
; STATIC: [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @foo1, 0
; STATIC-NEXT: [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) @foo1, 16
; STATIC-NEXT: [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) @foo1, 32
- ; STATIC-NEXT: [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) @foo1, 48
- ; STATIC-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY [[MOVKXi2]]
+ ; STATIC-NEXT: [[MOVKXi2:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) @foo1, 48
; STATIC-NEXT: [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @foo2, 0
; STATIC-NEXT: [[MOVKXi3:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi1]], target-flags(aarch64-g1, aarch64-nc) @foo2, 16
; STATIC-NEXT: [[MOVKXi4:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi3]], target-flags(aarch64-g2, aarch64-nc) @foo2, 32
- ; STATIC-NEXT: [[MOVKXi5:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @foo2, 48
- ; STATIC-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[MOVKXi5]]
- ; STATIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (i32) into %ir.retval)
- ; STATIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from @foo1)
- ; STATIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (i32) from @foo2)
+ ; STATIC-NEXT: [[MOVKXi5:%[0-9]+]]:gpr64common = MOVKXi [[MOVKXi4]], target-flags(aarch64-g3) @foo2, 48
+ ; STATIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (s32) into %ir.retval)
+ ; STATIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[MOVKXi2]], 0 :: (load (s32) from @foo1)
+ ; STATIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[MOVKXi5]], 0 :: (load (s32) from @foo2)
; STATIC-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; STATIC-NEXT: $w0 = COPY [[ADDWrr]]
; STATIC-NEXT: RET_ReallyLR implicit $w0
;
; PIC-LABEL: name: gv_large
; PIC: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @foo1, target-flags(aarch64-pageoff, aarch64-nc) @foo1
- ; PIC-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY [[MOVaddr]]
; PIC-NEXT: [[MOVaddr1:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @foo2, target-flags(aarch64-pageoff, aarch64-nc) @foo2
- ; PIC-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[MOVaddr1]]
- ; PIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (i32) into %ir.retval)
- ; PIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from @foo1)
- ; PIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (i32) from @foo2)
+ ; PIC-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (s32) into %ir.retval)
+ ; PIC-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[MOVaddr]], 0 :: (load (s32) from @foo1)
+ ; PIC-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[MOVaddr1]], 0 :: (load (s32) from @foo2)
; PIC-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; PIC-NEXT: $w0 = COPY [[ADDWrr]]
; PIC-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
index 1ba04037aa1339..668f3a4cebcd3e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir
@@ -30,13 +30,11 @@ constants:
body: |
bb.1:
; CHECK-LABEL: name: gv_tiny
- ; CHECK: [[ADR:%[0-9]+]]:gpr64 = ADR @foo1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY [[ADR]]
- ; CHECK-NEXT: [[ADR1:%[0-9]+]]:gpr64 = ADR @foo2
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[ADR1]]
- ; CHECK-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (i32) into %ir.retval)
- ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (i32) from @foo1)
- ; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load (i32) from @foo2)
+ ; CHECK: [[ADR:%[0-9]+]]:gpr64common = ADR @foo1
+ ; CHECK-NEXT: [[ADR1:%[0-9]+]]:gpr64common = ADR @foo2
+ ; CHECK-NEXT: STRWui $wzr, %stack.0.retval, 0 :: (store (s32) into %ir.retval)
+ ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ADR]], 0 :: (load (s32) from @foo1)
+ ; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADR1]], 0 :: (load (s32) from @foo2)
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
index 9a54a202003670..ec08d06de90ae7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
@@ -19,12 +19,12 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: implicit_def
- ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
- ; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
- %0(i32) = G_IMPLICIT_DEF
- %1(i32) = G_ADD %0, %0
- $w0 = COPY %1(i32)
+ ; CHECK: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[DEF]], [[DEF]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ %0(s32) = G_IMPLICIT_DEF
+ %1(s32) = G_ADD %0, %0
+ $w0 = COPY %1(s32)
...
---
name: implicit_def_copy
@@ -38,9 +38,8 @@ body: |
bb.0:
; CHECK-LABEL: name: implicit_def_copy
; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY [[DEF]]
- ; CHECK-NEXT: $w0 = COPY [[COPY]]
- %0(i32) = G_IMPLICIT_DEF
- %1(i32) = COPY %0(i32)
- $w0 = COPY %1(i32)
+ ; CHECK-NEXT: $w0 = COPY [[DEF]]
+ %0(s32) = G_IMPLICIT_DEF
+ %1(s32) = COPY %0(s32)
+ $w0 = COPY %1(s32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
index 04d5ce0160b730..9e35ce55f7d088 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
@@ -48,16 +48,15 @@ body: |
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY]], 0, 15
; CHECK-NEXT: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY]], 16, 15
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[BFMWri1]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %1:gpr(i32) = COPY $w0
- %2:gpr(i32) = COPY $w1
- %3:gpr(i16) = G_TRUNC %1(i32)
- %4:gpr(i16) = G_TRUNC %1(i32)
- %5:gpr(i32) = G_IMPLICIT_DEF
- %6:gpr(i32) = G_INSERT %5, %3(i16), 0
- %7:gpr(i32) = G_INSERT %6, %4(i16), 16
- %0:gpr(i32) = COPY %7(i32)
+ ; CHECK-NEXT: $w0 = COPY [[BFMWri1]]
+ %1:gpr(s32) = COPY $w0
+ %2:gpr(s32) = COPY $w1
+ %3:gpr(s16) = G_TRUNC %1(s32)
+ %4:gpr(s16) = G_TRUNC %1(s32)
+ %5:gpr(s32) = G_IMPLICIT_DEF
+ %6:gpr(s32) = G_INSERT %5, %3(s16), 0
+ %7:gpr(s32) = G_INSERT %6, %4(s16), 16
+ %0:gpr(s32) = COPY %7(s32)
$w0 = COPY %0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
index b4509f694861ab..8e9c3d6610dc2c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -43,13 +43,12 @@ body: |
; CHECK-LABEL: name: anyext_s64_from_s32
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
- ; CHECK-NEXT: $x0 = COPY [[INSERT_SUBREG]]
- %0(i32) = COPY $w0
- %1(i64) = G_ANYEXT %0
- $x0 = COPY %1(i64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[COPY]], %subreg.sub_32
+ ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
+ %0(s32) = COPY $w0
+ %1(s64) = G_ANYEXT %0
+ $x0 = COPY %1(s64)
...
---
@@ -69,12 +68,11 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %2:gpr(i32) = COPY $w0
- %0(i8) = G_TRUNC %2
- %1(i32) = G_ANYEXT %0
- $w0 = COPY %1(i32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY]]
+ %2:gpr(s32) = COPY $w0
+ %0(s8) = G_TRUNC %2
+ %1(s32) = G_ANYEXT %0
+ $w0 = COPY %1(s32)
...
---
@@ -94,13 +92,13 @@ body: |
; CHECK-LABEL: name: anyext_v8s16_from_v8s8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:fpr(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x i8>) = COPY $d0
- %1:fpr(<8 x i16>) = G_ANYEXT %0(<8 x i8>)
- $q0 = COPY %1(<8 x i16>)
+ %0:fpr(<8 x s8>) = COPY $d0
+ %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>)
+ $q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
@@ -121,13 +119,13 @@ body: |
; CHECK-LABEL: name: anyext_v4s32_from_v4s16
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:fpr(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x i16>) = COPY $d0
- %1:fpr(<4 x i32>) = G_ANYEXT %0(<4 x i16>)
- $q0 = COPY %1(<4 x i32>)
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
+ $q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
@@ -148,13 +146,13 @@ body: |
; CHECK-LABEL: name: anyext_v2s64_from_v2s32
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:fpr(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x i32>) = COPY $d0
- %1:fpr(<2 x i64>) = G_ANYEXT %0(<2 x i32>)
- $q0 = COPY %1(<2 x i64>)
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
+ $q0 = COPY %1(<2 x s64>)
RET_ReallyLR implicit $q0
...
@@ -178,9 +176,9 @@ body: |
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
- %0(i32) = COPY $w0
- %1(i64) = G_ZEXT %0
- $x0 = COPY %1(i64)
+ %0(s32) = COPY $w0
+ %1(s64) = G_ZEXT %0
+ $x0 = COPY %1(s64)
...
---
@@ -202,9 +200,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
- %2:gpr(i32) = COPY $w0
- %0(i16) = G_TRUNC %2
- %1(i32) = G_ZEXT %0
+ %2:gpr(s32) = COPY $w0
+ %0(s16) = G_TRUNC %2
+ %1(s32) = G_ZEXT %0
$w0 = COPY %1
...
@@ -227,10 +225,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
- %2:gpr(i32) = COPY $w0
- %0(i16) = G_TRUNC %2
- %1(i32) = G_ZEXT %0
- $w0 = COPY %1(i32)
+ %2:gpr(s32) = COPY $w0
+ %0(s16) = G_TRUNC %2
+ %1(s32) = G_ZEXT %0
+ $w0 = COPY %1(s32)
...
---
@@ -251,13 +249,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %2:gpr(i32) = COPY $w0
- %0(i8) = G_TRUNC %2
- %1(i16) = G_ZEXT %0
- %3:gpr(i32) = G_ANYEXT %1
- $w0 = COPY %3(i32)
+ ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
+ %2:gpr(s32) = COPY $w0
+ %0(s8) = G_TRUNC %2
+ %1(s16) = G_ZEXT %0
+ %3:gpr(s32) = G_ANYEXT %1
+ $w0 = COPY %3(s32)
...
---
@@ -277,13 +274,13 @@ body: |
; CHECK-LABEL: name: zext_v8s16_from_v8s8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[USHLLv8i8_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:fpr(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x i8>) = COPY $d0
- %1:fpr(<8 x i16>) = G_ZEXT %0(<8 x i8>)
- $q0 = COPY %1(<8 x i16>)
+ %0:fpr(<8 x s8>) = COPY $d0
+ %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>)
+ $q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
@@ -305,13 +302,13 @@ body: |
; CHECK-LABEL: name: zext_v4s32_from_v4s16
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[USHLLv4i16_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:fpr(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x i16>) = COPY $d0
- %1:fpr(<4 x i32>) = G_ZEXT %0(<4 x i16>)
- $q0 = COPY %1(<4 x i32>)
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+ $q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
@@ -332,13 +329,13 @@ body: |
; CHECK-LABEL: name: zext_v2s64_from_v2s32
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[USHLLv2i32_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:fpr(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x i32>) = COPY $d0
- %1:fpr(<2 x i64>) = G_ZEXT %0(<2 x i32>)
- $q0 = COPY %1(<2 x i64>)
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>)
+ $q0 = COPY %1(<2 x s64>)
RET_ReallyLR implicit $q0
...
@@ -359,13 +356,12 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
- ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32
+ ; CHECK-NEXT: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
; CHECK-NEXT: $x0 = COPY [[SBFMXri]]
- %0(i32) = COPY $w0
- %1(i64) = G_SEXT %0
- $x0 = COPY %1(i64)
+ %0(s32) = COPY $w0
+ %1(s64) = G_SEXT %0
+ $x0 = COPY %1(s64)
...
---
@@ -387,9 +383,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
- %2:gpr(i32) = COPY $w0
- %0(i16) = G_TRUNC %2
- %1(i32) = G_SEXT %0
+ %2:gpr(s32) = COPY $w0
+ %0(s16) = G_TRUNC %2
+ %1(s32) = G_SEXT %0
$w0 = COPY %1
...
@@ -412,10 +408,10 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
- %2:gpr(i32) = COPY $w0
- %0(i8) = G_TRUNC %2
- %1(i32) = G_SEXT %0
- $w0 = COPY %1(i32)
+ %2:gpr(s32) = COPY $w0
+ %0(s8) = G_TRUNC %2
+ %1(s32) = G_SEXT %0
+ $w0 = COPY %1(s32)
...
---
@@ -436,13 +432,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %2:gpr(i32) = COPY $w0
- %0(i8) = G_TRUNC %2
- %1(i16) = G_SEXT %0
- %3:gpr(i32) = G_ANYEXT %1
- $w0 = COPY %3(i32)
+ ; CHECK-NEXT: $w0 = COPY [[SBFMWri]]
+ %2:gpr(s32) = COPY $w0
+ %0(s8) = G_TRUNC %2
+ %1(s16) = G_SEXT %0
+ %3:gpr(s32) = G_ANYEXT %1
+ $w0 = COPY %3(s32)
...
---
@@ -462,13 +457,13 @@ body: |
; CHECK-LABEL: name: sext_v8s16_from_v8s8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[SSHLLv8i8_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:fpr(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<8 x i8>) = COPY $d0
- %1:fpr(<8 x i16>) = G_SEXT %0(<8 x i8>)
- $q0 = COPY %1(<8 x i16>)
+ %0:fpr(<8 x s8>) = COPY $d0
+ %1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>)
+ $q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
@@ -490,13 +485,13 @@ body: |
; CHECK-LABEL: name: sext_v4s32_from_v4s16
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[SSHLLv4i16_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:fpr(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x i16>) = COPY $d0
- %1:fpr(<4 x i32>) = G_SEXT %0(<4 x i16>)
- $q0 = COPY %1(<4 x i32>)
+ %0:fpr(<4 x s16>) = COPY $d0
+ %1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>)
+ $q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
@@ -517,11 +512,11 @@ body: |
; CHECK-LABEL: name: sext_v2s64_from_v2s32
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
- ; CHECK-NEXT: $q0 = COPY [[SSHLLv2i32_shift]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:fpr(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x i32>) = COPY $d0
- %1:fpr(<2 x i64>) = G_SEXT %0(<2 x i32>)
- $q0 = COPY %1(<2 x i64>)
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>)
+ $q0 = COPY %1(<2 x s64>)
RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index ac5575b88fc31f..0b43c6152f91bf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -70,9 +70,8 @@ body: |
; CHECK-LABEL: name: ptrtoint_s32_p0
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %ptr:gpr64 = COPY $x0
- ; CHECK-NEXT: %ptr2int:gpr64common = COPY %ptr
- ; CHECK-NEXT: %int:gpr32sp = COPY %ptr2int.sub_32
+ ; CHECK-NEXT: %ptr:gpr64common = COPY $x0
+ ; CHECK-NEXT: %int:gpr32sp = COPY %ptr.sub_32
; CHECK-NEXT: $w0 = COPY %int
; CHECK-NEXT: RET_ReallyLR implicit $w0
%ptr:gpr(p0) = COPY $x0
@@ -97,8 +96,7 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64 = COPY $x0
- ; CHECK-NEXT: %int:gpr32 = COPY %ptr.sub_32
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %int
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %ptr.sub_32
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
; CHECK-NEXT: $h0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
@@ -124,8 +122,7 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64 = COPY $x0
- ; CHECK-NEXT: %int:gpr32 = COPY %ptr.sub_32
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %int
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %ptr.sub_32
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
; CHECK-NEXT: $b0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $b0
@@ -150,9 +147,8 @@ body: |
; CHECK-LABEL: name: ptrtoint_s1_p0
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %ptr:gpr64 = COPY $x0
- ; CHECK-NEXT: %ptr2int:gpr64common = COPY %ptr
- ; CHECK-NEXT: %trunc:gpr32common = COPY %ptr2int.sub_32
+ ; CHECK-NEXT: %ptr:gpr64common = COPY $x0
+ ; CHECK-NEXT: %trunc:gpr32common = COPY %ptr.sub_32
; CHECK-NEXT: %ext:gpr32sp = ANDWri %trunc, 0
; CHECK-NEXT: $w0 = COPY %ext
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
index 09db59db840eff..955e5b16dafe99 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -130,9 +130,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16) from %ir.addr)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0(p0) = COPY $x0
%1(i16) = G_LOAD %0 :: (load (i16) from %ir.addr)
%2:gpr(i32) = G_ANYEXT %1
@@ -176,9 +175,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8) from %ir.addr)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
%0(p0) = COPY $x0
%1(i8) = G_LOAD %0 :: (load (i8) from %ir.addr)
%2:gpr(i32) = G_ANYEXT %1
@@ -286,9 +284,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (i16) from %ir.addr)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load (s16) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0(p0) = COPY $x0
%1(i64) = G_CONSTANT i64 64
%2(p0) = G_PTR_ADD %0, %1
@@ -316,9 +313,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (i8) from %ir.addr)
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load (s8) from %ir.addr)
+ ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
%0(p0) = COPY $x0
%1(i64) = G_CONSTANT i64 1
%2(p0) = G_PTR_ADD %0, %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
index 90fbb993cc6775..e00963fc978dca 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
@@ -10,9 +10,8 @@ body: |
; CHECK-LABEL: name: ptr_add
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 42, 0
; CHECK-NEXT: $x0 = COPY [[ADDXri]]
%0:gpr(p0) = COPY $x0
%1:gpr(i64) = G_CONSTANT i64 42
@@ -90,9 +89,8 @@ body: |
; CHECK-LABEL: name: ptr_add_neg_imm
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY1]], 10, 0, implicit-def dead $nzcv
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 10, 0, implicit-def dead $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXri]]
%0:gpr(p0) = COPY $x0
%1:gpr(i64) = G_CONSTANT i64 -10
@@ -110,9 +108,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %reg0:gpr32 = COPY $w0
- ; CHECK-NEXT: %ptr:gpr64 = COPY $x1
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY %ptr
- ; CHECK-NEXT: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18
+ ; CHECK-NEXT: %ptr:gpr64common = COPY $x1
+ ; CHECK-NEXT: %ptr_add:gpr64sp = ADDXrx %ptr, %reg0, 18
; CHECK-NEXT: $x0 = COPY %ptr_add
%reg0:gpr(i32) = COPY $w0
%ptr:gpr(p0) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
index 3f7dc2a8b7349c..37dc7aa400fa37 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext-of-load.mir
@@ -13,9 +13,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (i8))
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
+ ; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(p0) = COPY $x0
%2:gpr(i8) = G_LOAD %1(p0) :: (load (i8))
@@ -37,9 +36,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr(p0) = COPY $x0
%2:gpr(i16) = G_LOAD %1(p0) :: (load (i16))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
index f4ce1af7f5a27f..a597c5af40dffe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
@@ -97,9 +97,8 @@ body: |
; CHECK-LABEL: name: dont_fold_bitcast
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:gpr32all = COPY $w0
- ; CHECK-NEXT: %bitcast1:gpr32 = COPY %copy
- ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %bitcast1, 0
+ ; CHECK-NEXT: %copy:gpr32 = COPY $w0
+ ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0
; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
; CHECK-NEXT: $x0 = COPY %zext
; CHECK-NEXT: RET_ReallyLR implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
index 3c4ad7bceed9aa..e3c336c93e4b61 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
@@ -39,10 +39,6 @@ body: |
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_v2f32
- ; CHECK: constants:
- ; CHECK: - id: 0
- ; CHECK: value: '<8 x i8> <i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
- ; CHECK: alignment: 8
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
@@ -60,10 +56,10 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[TBLv16i8One]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
- %0:fpr(<2 x i32>) = COPY $d0
- %1:fpr(<2 x i32>) = COPY $d1
- %2:fpr(<2 x i32>) = G_SHUFFLE_VECTOR %0(<2 x i32>), %1, shufflemask(1, 0)
- $d0 = COPY %2(<2 x i32>)
+ %0:fpr(<2 x s32>) = COPY $d0
+ %1:fpr(<2 x s32>) = COPY $d1
+ %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0)
+ $d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0
...
@@ -78,22 +74,20 @@ body: |
liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_v4i32
- ; CHECK: constants:
- ; CHECK: value: '<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3>'
- ; CHECK: alignment: 16
- ; CHECK: isTargetSpecific: false
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
- ; CHECK-NEXT: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[COPY]], [[LDRQui]]
- ; CHECK-NEXT: $q0 = COPY [[TBLv16i8One]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
+ ; CHECK-NEXT: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
+ ; CHECK-NEXT: $q0 = COPY [[TBLv16i8Two]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x i32>) = COPY $q0
- %1:fpr(<4 x i32>) = COPY $q1
- %2:fpr(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(0, 1, 3, 0)
- $q0 = COPY %2(<4 x i32>)
+ %0:fpr(<4 x s32>) = COPY $q0
+ %1:fpr(<4 x s32>) = COPY $q1
+ %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0)
+ $q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
@@ -108,10 +102,6 @@ body: |
liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_tbl_v4i32
- ; CHECK: constants:
- ; CHECK: value: '<16 x i8> <i8 20, i8 21, i8 22, i8 23, i8 28, i8 29, i8 30, i8 31, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3>'
- ; CHECK: alignment: 16
- ; CHECK: isTargetSpecific: false
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
@@ -122,10 +112,10 @@ body: |
; CHECK-NEXT: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
; CHECK-NEXT: $q0 = COPY [[TBLv16i8Two]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<4 x i32>) = COPY $q0
- %1:fpr(<4 x i32>) = COPY $q1
- %2:fpr(<4 x i32>) = G_SHUFFLE_VECTOR %0(<4 x i32>), %1, shufflemask(5, 7, 1, 0)
- $q0 = COPY %2(<4 x i32>)
+ %0:fpr(<4 x s32>) = COPY $q0
+ %1:fpr(<4 x s32>) = COPY $q1
+ %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0)
+ $q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
@@ -140,22 +130,20 @@ body: |
liveins: $q0, $q1
; CHECK-LABEL: name: shuffle_v2i64
- ; CHECK: constants:
- ; CHECK: value: '<16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>'
- ; CHECK: alignment: 16
- ; CHECK: isTargetSpecific: false
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
- ; CHECK-NEXT: [[TBLv16i8One:%[0-9]+]]:fpr128 = TBLv16i8One [[COPY]], [[LDRQui]]
- ; CHECK-NEXT: $q0 = COPY [[TBLv16i8One]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE [[COPY]], %subreg.qsub0, [[COPY1]], %subreg.qsub1
+ ; CHECK-NEXT: [[TBLv16i8Two:%[0-9]+]]:fpr128 = TBLv16i8Two [[REG_SEQUENCE]], [[LDRQui]]
+ ; CHECK-NEXT: $q0 = COPY [[TBLv16i8Two]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
- %0:fpr(<2 x i64>) = COPY $q0
- %1:fpr(<2 x i64>) = COPY $q1
- %2:fpr(<2 x i64>) = G_SHUFFLE_VECTOR %0(<2 x i64>), %1, shufflemask(1, 0)
- $q0 = COPY %2(<2 x i64>)
+ %0:fpr(<2 x s64>) = COPY $q0
+ %1:fpr(<2 x s64>) = COPY $q1
+ %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(1, 0)
+ $q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
index 0d6dfd5da82c17..b3b6bf80146b89 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -269,9 +269,8 @@ body: |
; CHECK-LABEL: name: store_fi_s64_gpr
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
- ; CHECK-NEXT: STRXui [[COPY1]], %stack.0.ptr0, 0 :: (store (p0))
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store (p0))
%0(p0) = COPY $x0
%1(p0) = G_FRAME_INDEX %stack.0.ptr0
G_STORE %0, %1 :: (store (p0))
@@ -662,10 +661,9 @@ body: |
; CHECK-LABEL: name: store_adrp_add_low
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
- ; CHECK-NEXT: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store (p0) into @x)
+ ; CHECK-NEXT: STRXui %copy, %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x :: (store (p0) into @x)
%copy:gpr(p0) = COPY $x0
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
@@ -683,10 +681,9 @@ body: |
; CHECK-LABEL: name: store_adrp_add_low_foldable_offset
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %adrp:gpr64common = ADRP target-flags(aarch64-page) @x + 8
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
- ; CHECK-NEXT: STRXui [[COPY]], %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x + 8 :: (store (p0) into @x)
+ ; CHECK-NEXT: STRXui %copy, %adrp, target-flags(aarch64-pageoff, aarch64-nc) @x + 8 :: (store (p0) into @x)
%copy:gpr(p0) = COPY $x0
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x + 8
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x + 8
@@ -704,10 +701,9 @@ body: |
; CHECK-LABEL: name: store_adrp_add_low_unfoldable_offset
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:gpr64all = COPY $x0
+ ; CHECK-NEXT: %copy:gpr64 = COPY $x0
; CHECK-NEXT: %add_low:gpr64common = MOVaddr target-flags(aarch64-page) @x + 3, target-flags(aarch64-pageoff, aarch64-nc) @x + 3
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %copy
- ; CHECK-NEXT: STRXui [[COPY]], %add_low, 0 :: (store (p0) into @x)
+ ; CHECK-NEXT: STRXui %copy, %add_low, 0 :: (store (p0) into @x)
%copy:gpr(p0) = COPY $x0
%adrp:gpr64(p0) = ADRP target-flags(aarch64-page) @x + 3
%add_low:gpr(p0) = G_ADD_LOW %adrp(p0), target-flags(aarch64-pageoff, aarch64-nc) @x + 3
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index 43b92865f05726..671ea36e51d40a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -30,9 +30,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(i64) = COPY $x0
- %1(i32) = G_TRUNC %0
- $w0 = COPY %1(i32)
+ %0(s64) = COPY $x0
+ %1(s32) = G_TRUNC %0
+ $w0 = COPY %1(s32)
...
---
@@ -53,12 +53,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
- ; CHECK-NEXT: $w0 = COPY [[COPY2]]
- %0(i64) = COPY $x0
- %1(i8) = G_TRUNC %0
- %2:gpr(i32) = G_ANYEXT %1
- $w0 = COPY %2(i32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ %0(s64) = COPY $x0
+ %1(s8) = G_TRUNC %0
+ %2:gpr(s32) = G_ANYEXT %1
+ $w0 = COPY %2(s32)
...
---
@@ -78,12 +77,11 @@ body: |
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(i32) = COPY $w0
- %1(i8) = G_TRUNC %0
- %2:gpr(i32) = G_ANYEXT %1
- $w0 = COPY %2(i32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY]]
+ %0(s32) = COPY $w0
+ %1(s8) = G_TRUNC %0
+ %2:gpr(s32) = G_ANYEXT %1
+ $w0 = COPY %2(s32)
...
---
@@ -104,9 +102,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
; CHECK-NEXT: $x0 = COPY [[COPY1]]
- %0(i128) = COPY $q0
- %1(i64) = G_TRUNC %0
- $x0 = COPY %1(i64)
+ %0(s128) = COPY $q0
+ %1(s64) = G_TRUNC %0
+ $x0 = COPY %1(s64)
...
---
@@ -127,7 +125,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
; CHECK-NEXT: $w0 = COPY [[COPY1]]
- %0(i128) = COPY $q0
- %1(i32) = G_TRUNC %0
- $w0 = COPY %1(i32)
+ %0(s128) = COPY $q0
+ %1(s32) = G_TRUNC %0
+ $w0 = COPY %1(s32)
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
index e0964ac628db46..4723c2d8692669 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir
@@ -23,10 +23,9 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
- ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (i8))
- ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
- ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32
+ ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 4096
; CHECK-NEXT: $x0 = COPY [[ANDXri]]
%3:gpr(p0) = G_IMPLICIT_DEF
%2:gpr(i8) = G_LOAD %3(p0) :: (load (i8))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
index 3ca1335fe75244..66987057f53ee3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
@@ -31,9 +31,8 @@ body: |
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
- ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (i16))
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
+ ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
+ ; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
%0:gpr(p0) = COPY $x0
%1:gpr(i16) = G_LOAD %0 :: (load (i16))
%2:gpr(i32) = G_ZEXT %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index a3279537befa05..5828187a515d3a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -107,23 +107,20 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[CSINCWr]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY2]], implicit-def $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY1]], [[COPY1]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[CSINCWr1]]
- ; CHECK-NEXT: $w0 = COPY [[COPY3]]
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK-NEXT: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY4]], [[COPY4]], implicit-def $nzcv
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr2:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[CSINCWr2]]
- ; CHECK-NEXT: $w0 = COPY [[COPY5]]
- %0:gpr(i32) = COPY $w0
- %1:gpr(i32) = G_ICMP intpred(eq), %0, %0
- %6:gpr(i8) = G_TRUNC %1(i32)
- %9:gpr(i32) = G_ANYEXT %6
- $w0 = COPY %9(i32)
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr2]]
+ %0:gpr(s32) = COPY $w0
+ %1:gpr(s32) = G_ICMP intpred(eq), %0, %0
+ %6:gpr(s8) = G_TRUNC %1(s32)
+ %9:gpr(s32) = G_ANYEXT %6
+ $w0 = COPY %9(s32)
%2:gpr(i64) = COPY $x0
%3:gpr(i32) = G_ICMP intpred(uge), %2, %2
@@ -154,28 +151,24 @@ body: |
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[ORRWrr]]
- ; CHECK-NEXT: $w0 = COPY [[COPY1]]
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: nofpexcept FCMPDrr [[COPY2]], [[COPY2]], implicit-def $nzcv, implicit $fpcr
+ ; CHECK-NEXT: $w0 = COPY [[ORRWrr]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: nofpexcept FCMPDrr [[COPY1]], [[COPY1]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr2:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[CSINCWr2]]
- ; CHECK-NEXT: $w0 = COPY [[COPY3]]
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK-NEXT: nofpexcept FCMPSrr [[COPY4]], [[COPY4]], implicit-def $nzcv, implicit $fpcr
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr2]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
+ ; CHECK-NEXT: nofpexcept FCMPSrr [[COPY2]], [[COPY2]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr3:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 15, implicit $nzcv
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[CSINCWr3]]
- ; CHECK-NEXT: $w0 = COPY [[COPY5]]
- ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK-NEXT: nofpexcept FCMPDrr [[COPY6]], [[COPY6]], implicit-def $nzcv, implicit $fpcr
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr3]]
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: nofpexcept FCMPDrr [[COPY3]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[CSINCWr4:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 14, implicit $nzcv
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32all = COPY [[CSINCWr4]]
- ; CHECK-NEXT: $w0 = COPY [[COPY7]]
- %0:fpr(f32) = COPY $s0
- %1:gpr(i32) = G_FCMP floatpred(one), %0, %0
- %2:gpr(i8) = G_TRUNC %1(i32)
- %3:gpr(i32) = G_ANYEXT %2
- $w0 = COPY %3(i32)
+ ; CHECK-NEXT: $w0 = COPY [[CSINCWr4]]
+ %0:fpr(s32) = COPY $s0
+ %1:gpr(s32) = G_FCMP floatpred(one), %0, %0
+ %2:gpr(s8) = G_TRUNC %1(s32)
+ %3:gpr(s32) = G_ANYEXT %2
+ $w0 = COPY %3(s32)
%4:fpr(f64) = COPY $d0
%5:gpr(i32) = G_FCMP floatpred(uge), %4, %4
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir b/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
index 8e8e5dbcbdc496..ba055c80e097c7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
@@ -60,9 +60,8 @@ body: |
; CHECK-LABEL: name: check_sext_not_lost
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
- ; CHECK-NEXT: STRXui [[COPY1]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: STRXui [[COPY]], %stack.0.ptr.addr, 0 :: (store (p0) into %ir.ptr.addr)
; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load (p0) from %ir.ptr.addr)
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x
; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load (s32) from @x)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
index 78ee983ef52e27..381dacb13a1aff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
@@ -56,9 +56,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], [[COPY1]], 0, 0 :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: STRXroX [[COPY2]], [[COPY]], [[COPY1]], 0, 0 :: (store (p0) into %ir.addr)
%0:gpr(p0) = COPY $x0
%1:gpr(i64) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %0, %1
@@ -350,12 +349,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
- ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY1]], [[COPY]], 0, 1 :: (store (p0) into %ir.addr)
- %0:gpr(i64) = COPY $x0
- %1:gpr(i64) = G_CONSTANT i64 3
- %2:gpr(i64) = G_SHL %0, %1(i64)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+ ; CHECK-NEXT: STRXroX [[COPY2]], [[COPY1]], [[COPY]], 0, 1 :: (store (p0) into %ir.addr)
+ %0:gpr(s64) = COPY $x0
+ %1:gpr(s64) = G_CONSTANT i64 3
+ %2:gpr(s64) = G_SHL %0, %1(s64)
%3:gpr(p0) = COPY $x1
%ptr:gpr(p0) = G_PTR_ADD %3, %2
%4:gpr(p0) = COPY $x2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
index d418dd1e3a73f8..a7ee3e42fde685 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
@@ -67,9 +67,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %base:gpr64sp = COPY $x0
; CHECK-NEXT: %foo:gpr32 = COPY $w1
- ; CHECK-NEXT: %dst:gpr64all = COPY $x2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %dst
- ; CHECK-NEXT: STRXroW [[COPY]], %base, %foo, 1, 1 :: (store (p0))
+ ; CHECK-NEXT: %dst:gpr64 = COPY $x2
+ ; CHECK-NEXT: STRXroW %dst, %base, %foo, 1, 1 :: (store (p0))
%base:gpr(p0) = COPY $x0
%foo:gpr(i32) = COPY $w1
%ext:gpr(i64) = G_SEXT %foo(i32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
index e987d10135b77c..80a86511f8c96a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
@@ -14,9 +14,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (s128))
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRQui]].ssub
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
- ; CHECK-NEXT: TBNZW [[COPY2]], 0, %bb.1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRQui]].ssub
+ ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: RET_ReallyLR
@@ -49,9 +48,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (s128))
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY [[LDRQui]].dsub
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
- ; CHECK-NEXT: TBNZX [[COPY2]], 33, %bb.1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[LDRQui]].dsub
+ ; CHECK-NEXT: TBNZX [[COPY1]], 33, %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: RET_ReallyLR
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
index 405dd9045e5be4..6655b969894605 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
@@ -127,9 +127,8 @@ body: |
; CHECK-NEXT: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %wide:gpr64all = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %wide.sub_32
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.1
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %wide.sub_32
+ ; CHECK-NEXT: TBNZW [[COPY]], 0, %bb.1
; CHECK-NEXT: B %bb.0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir
index a232526bc0e5ad..dcd63ed6b67161 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir
@@ -196,9 +196,8 @@ body: |
; CHECK-LABEL: name: dont_use_xro_add_lsl
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %copy:gpr64 = COPY $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY %copy
- ; CHECK-NEXT: %addr:gpr64sp = ADDXri [[COPY]], 273, 12
+ ; CHECK-NEXT: %copy:gpr64common = COPY $x0
+ ; CHECK-NEXT: %addr:gpr64sp = ADDXri %copy, 273, 12
; CHECK-NEXT: %load:gpr64 = LDRXui %addr, 0 :: (volatile load (s64))
; CHECK-NEXT: RET_ReallyLR
%copy:gpr(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/popcount.ll b/llvm/test/CodeGen/AArch64/popcount.ll
index bb81776a7f6d66..feb9b1e3921deb 100644
--- a/llvm/test/CodeGen/AArch64/popcount.ll
+++ b/llvm/test/CodeGen/AArch64/popcount.ll
@@ -19,7 +19,6 @@ define i8 @popcount128(ptr nocapture nonnull readonly %0) {
; CHECKO0-NEXT: cnt v0.16b, v0.16b
; CHECKO0-NEXT: uaddlv h0, v0.16b
; CHECKO0-NEXT: // kill: def $q0 killed $h0
-; CHECKO0-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECKO0-NEXT: fmov w0, s0
; CHECKO0-NEXT: ret
;
@@ -80,7 +79,6 @@ define i8 @popcount128(ptr nocapture nonnull readonly %0) {
; GISELO0-NEXT: cnt v0.16b, v0.16b
; GISELO0-NEXT: uaddlv h0, v0.16b
; GISELO0-NEXT: // kill: def $q0 killed $h0
-; GISELO0-NEXT: // kill: def $s0 killed $s0 killed $q0
; GISELO0-NEXT: fmov w0, s0
; GISELO0-NEXT: ret
Entry:
@@ -110,7 +108,6 @@ define i16 @popcount256(ptr nocapture nonnull readonly %0) {
; CHECKO0-NEXT: cnt v1.16b, v1.16b
; CHECKO0-NEXT: uaddlv h1, v1.16b
; CHECKO0-NEXT: // kill: def $q1 killed $h1
-; CHECKO0-NEXT: // kill: def $s1 killed $s1 killed $q1
; CHECKO0-NEXT: fmov w0, s1
; CHECKO0-NEXT: mov w10, wzr
; CHECKO0-NEXT: mov w9, w0
@@ -119,7 +116,6 @@ define i16 @popcount256(ptr nocapture nonnull readonly %0) {
; CHECKO0-NEXT: cnt v0.16b, v0.16b
; CHECKO0-NEXT: uaddlv h0, v0.16b
; CHECKO0-NEXT: // kill: def $q0 killed $h0
-; CHECKO0-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECKO0-NEXT: fmov w0, s0
; CHECKO0-NEXT: mov w8, w0
; CHECKO0-NEXT: // kill: def $x10 killed $w10
@@ -232,7 +228,6 @@ define i16 @popcount256(ptr nocapture nonnull readonly %0) {
; GISELO0-NEXT: cnt v1.16b, v1.16b
; GISELO0-NEXT: uaddlv h1, v1.16b
; GISELO0-NEXT: // kill: def $q1 killed $h1
-; GISELO0-NEXT: // kill: def $s1 killed $s1 killed $q1
; GISELO0-NEXT: fmov w0, s1
; GISELO0-NEXT: mov w10, wzr
; GISELO0-NEXT: mov w9, w0
@@ -241,7 +236,6 @@ define i16 @popcount256(ptr nocapture nonnull readonly %0) {
; GISELO0-NEXT: cnt v0.16b, v0.16b
; GISELO0-NEXT: uaddlv h0, v0.16b
; GISELO0-NEXT: // kill: def $q0 killed $h0
-; GISELO0-NEXT: // kill: def $s0 killed $s0 killed $q0
; GISELO0-NEXT: fmov w0, s0
; GISELO0-NEXT: mov w8, w0
; GISELO0-NEXT: // kill: def $x10 killed $w10
@@ -269,7 +263,6 @@ define <1 x i128> @popcount1x128(<1 x i128> %0) {
; CHECKO0-NEXT: uaddlv h0, v0.16b
; CHECKO0-NEXT: // kill: def $q0 killed $h0
; CHECKO0-NEXT: mov x1, xzr
-; CHECKO0-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECKO0-NEXT: fmov w0, s0
; CHECKO0-NEXT: mov w8, wzr
; CHECKO0-NEXT: // kill: def $x0 killed $w0
@@ -338,7 +331,6 @@ define <1 x i128> @popcount1x128(<1 x i128> %0) {
; GISELO0-NEXT: uaddlv h0, v0.16b
; GISELO0-NEXT: // kill: def $q0 killed $h0
; GISELO0-NEXT: mov x1, xzr
-; GISELO0-NEXT: // kill: def $s0 killed $s0 killed $q0
; GISELO0-NEXT: fmov w0, s0
; GISELO0-NEXT: mov w8, wzr
; GISELO0-NEXT: // kill: def $x0 killed $w0
@@ -775,12 +767,11 @@ define i32 @ctpop_into_extract(ptr %p) {
; CHECKO0-NEXT: // implicit-def: $q1
; CHECKO0-NEXT: fmov d1, d0
; CHECKO0-NEXT: mov w8, v1.s[0]
-; CHECKO0-NEXT: mov w1, w8
-; CHECKO0-NEXT: fmov d1, x1
+; CHECKO0-NEXT: // kill: def $x8 killed $w8
+; CHECKO0-NEXT: fmov d1, x8
; CHECKO0-NEXT: cnt v1.8b, v1.8b
; CHECKO0-NEXT: uaddlv h1, v1.8b
; CHECKO0-NEXT: // kill: def $q1 killed $h1
-; CHECKO0-NEXT: // kill: def $s1 killed $s1 killed $q1
; CHECKO0-NEXT: fmov w8, s1
; CHECKO0-NEXT: // implicit-def: $q1
; CHECKO0-NEXT: fmov d1, d2
@@ -875,12 +866,11 @@ define i32 @ctpop_into_extract(ptr %p) {
; GISELO0-NEXT: // implicit-def: $q1
; GISELO0-NEXT: fmov d1, d0
; GISELO0-NEXT: mov w8, v1.s[0]
-; GISELO0-NEXT: mov w1, w8
-; GISELO0-NEXT: fmov d1, x1
+; GISELO0-NEXT: // kill: def $x8 killed $w8
+; GISELO0-NEXT: fmov d1, x8
; GISELO0-NEXT: cnt v1.8b, v1.8b
; GISELO0-NEXT: uaddlv h1, v1.8b
; GISELO0-NEXT: // kill: def $q1 killed $h1
-; GISELO0-NEXT: // kill: def $s1 killed $s1 killed $q1
; GISELO0-NEXT: fmov w8, s1
; GISELO0-NEXT: // implicit-def: $q1
; GISELO0-NEXT: fmov d1, d2
@@ -904,8 +894,8 @@ define <8 x i8> @bitcast_upper_bits(i32 %b, <8 x i8> %v) {
; CHECKO0: // %bb.0:
; CHECKO0-NEXT: fmov d1, d0
; CHECKO0-NEXT: mov w8, w0
-; CHECKO0-NEXT: mov w0, w8
-; CHECKO0-NEXT: fmov d0, x0
+; CHECKO0-NEXT: // kill: def $x8 killed $w8
+; CHECKO0-NEXT: fmov d0, x8
; CHECKO0-NEXT: add v0.8b, v0.8b, v1.8b
; CHECKO0-NEXT: ret
;
@@ -934,8 +924,8 @@ define <8 x i8> @bitcast_upper_bits(i32 %b, <8 x i8> %v) {
; GISELO0: // %bb.0:
; GISELO0-NEXT: fmov d1, d0
; GISELO0-NEXT: mov w8, w0
-; GISELO0-NEXT: mov w0, w8
-; GISELO0-NEXT: fmov d0, x0
+; GISELO0-NEXT: // kill: def $x8 killed $w8
+; GISELO0-NEXT: fmov d0, x8
; GISELO0-NEXT: add v0.8b, v0.8b, v1.8b
; GISELO0-NEXT: ret
%a = zext i32 %b to i64
diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
index 55c59eb62b64c2..9a870396384aa0 100644
--- a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
+++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll
@@ -238,19 +238,18 @@ define i64 @blend_and_sign_different_bbs(i64 %addr, i64 %cond) {
; GISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; GISEL-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @discvar
; GISEL-NEXT: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @discvar :: (dereferenceable load (i64) from @discvar)
- ; GISEL-NEXT: [[MOVKXi:%[0-9]+]]:gpr64noip = MOVKXi [[LDRXui]], 42, 48
+ ; GISEL-NEXT: [[MOVKXi:%[0-9]+]]:gpr64common_and_gpr64noip = MOVKXi [[LDRXui]], 42, 48
; GISEL-NEXT: CBZX [[COPY1]], %bb.3
; GISEL-NEXT: B %bb.2
; GISEL-NEXT: {{ $}}
; GISEL-NEXT: bb.2.next:
; GISEL-NEXT: successors: %bb.3(0x80000000)
; GISEL-NEXT: {{ $}}
- ; GISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY [[MOVKXi]]
- ; GISEL-NEXT: INLINEASM &nop, sideeffect attdialect, reguse:GPR64common, [[COPY2]]
+ ; GISEL-NEXT: INLINEASM &nop, sideeffect attdialect, reguse:GPR64common, [[MOVKXi]]
; GISEL-NEXT: {{ $}}
; GISEL-NEXT: bb.3.exit:
- ; GISEL-NEXT: [[COPY3:%[0-9]+]]:gpr64noip = COPY [[LDRXui]]
- ; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, [[COPY3]], implicit-def dead $x16, implicit-def dead $x17
+ ; GISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64noip = COPY [[LDRXui]]
+ ; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, [[COPY2]], implicit-def dead $x16, implicit-def dead $x17
; GISEL-NEXT: $x0 = COPY [[PAC]]
; GISEL-NEXT: RET_ReallyLR implicit $x0
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
index f3fbf2f2f344f3..76606ef900b0a9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
@@ -116,12 +116,9 @@ define void @atomicrmw_fmax_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
- ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
- ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
- ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
- ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub1
+ ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[COPY1]], [[COPY5]], implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_NE_U32_e64_]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
@@ -135,20 +132,20 @@ define void @atomicrmw_fmax_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
- ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
- ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
- ; GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
+ ; GFX10-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
+ ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY6]], implicit $exec
+ ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY7]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.7, align 8, addrspace 5)
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.7 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
; GFX10-NEXT: [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MAX_F64_e64_2:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub0
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub1
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.7, align 8, addrspace 5)
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.7 + 4, basealign 8, addrspace 5)
+ ; GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub0
+ ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub1
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY8]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.7, align 8, addrspace 5)
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY9]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.7 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: S_BRANCH %bb.5
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.4.atomicrmw.global:
@@ -178,12 +175,9 @@ define double @atomicrmw_fmax_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
- ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
- ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
- ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
- ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub1
+ ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[COPY1]], [[COPY5]], implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_NE_U32_e64_]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
@@ -198,20 +192,20 @@ define double @atomicrmw_fmax_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
- ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
- ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
- ; GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
+ ; GFX10-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
+ ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY6]], implicit $exec
+ ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY7]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.8, align 8, addrspace 5)
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.8 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
; GFX10-NEXT: [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MAX_F64_e64_2:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub0
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub1
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.8, align 8, addrspace 5)
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.8 + 4, basealign 8, addrspace 5)
+ ; GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub0
+ ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[V_MAX_F64_e64_2]].sub1
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY8]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.8, align 8, addrspace 5)
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY9]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.8 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: S_BRANCH %bb.5
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.4.atomicrmw.global:
@@ -227,10 +221,10 @@ define double @atomicrmw_fmax_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.6.atomicrmw.end:
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub1
- ; GFX10-NEXT: $vgpr0 = COPY [[COPY13]]
- ; GFX10-NEXT: $vgpr1 = COPY [[COPY14]]
+ ; GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
+ ; GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub1
+ ; GFX10-NEXT: $vgpr0 = COPY [[COPY10]]
+ ; GFX10-NEXT: $vgpr1 = COPY [[COPY11]]
; GFX10-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
%old = atomicrmw fmax ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
ret double %old
@@ -412,12 +406,9 @@ define void @atomicrmw_fmin_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
; GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
- ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
- ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
- ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
- ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub1
+ ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[COPY1]], [[COPY5]], implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_NE_U32_e64_]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
@@ -431,20 +422,20 @@ define void @atomicrmw_fmin_flat_f64_vv_noret(ptr %ptr, double %val) {
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
- ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
- ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
- ; GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
+ ; GFX10-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
+ ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY6]], implicit $exec
+ ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY7]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.7, align 8, addrspace 5)
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.7 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
; GFX10-NEXT: [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MIN_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub0
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub1
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.7, align 8, addrspace 5)
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.7 + 4, basealign 8, addrspace 5)
+ ; GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub0
+ ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub1
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY8]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.7, align 8, addrspace 5)
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY9]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.7 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: S_BRANCH %bb.5
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.4.atomicrmw.global:
@@ -474,12 +465,9 @@ define double @atomicrmw_fmin_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $src_private_base
- ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub0
- ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY4]].sub1
- ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY1]], [[COPY7]], implicit $exec
- ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]]
- ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]].sub1
+ ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[COPY1]], [[COPY5]], implicit $exec
+ ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_NE_U32_e64_]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX10-NEXT: S_BRANCH %bb.4
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.2.Flow:
@@ -494,20 +482,20 @@ define double @atomicrmw_fmin_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 0
- ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
- ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY9]], implicit $exec
- ; GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY10]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
+ ; GFX10-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B]]
+ ; GFX10-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], [[COPY6]], implicit $exec
+ ; GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY7]], 0, [[COPY]], [[V_CMP_NE_U64_e64_]], implicit $exec
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %ir.8, align 8, addrspace 5)
; GFX10-NEXT: [[BUFFER_LOAD_DWORD_OFFEN1:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %ir.8 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[BUFFER_LOAD_DWORD_OFFEN]], %subreg.sub0, [[BUFFER_LOAD_DWORD_OFFEN1]], %subreg.sub1
; GFX10-NEXT: [[V_MAX_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE2]], 0, [[REG_SEQUENCE2]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MAX_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_MAX_F64_e64 0, [[REG_SEQUENCE1]], 0, [[REG_SEQUENCE1]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_MIN_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MIN_F64_e64 0, [[V_MAX_F64_e64_]], 0, [[V_MAX_F64_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub0
- ; GFX10-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub1
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY11]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.8, align 8, addrspace 5)
- ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY12]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.8 + 4, basealign 8, addrspace 5)
+ ; GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub0
+ ; GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[V_MIN_F64_e64_]].sub1
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY8]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.8, align 8, addrspace 5)
+ ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFEN [[COPY9]], [[V_CNDMASK_B32_e64_]], $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.8 + 4, basealign 8, addrspace 5)
; GFX10-NEXT: S_BRANCH %bb.5
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.4.atomicrmw.global:
@@ -523,10 +511,10 @@ define double @atomicrmw_fmin_flat_f64_vv_ret(ptr %ptr, double %val) {
; GFX10-NEXT: SI_END_CF [[SI_ELSE]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: bb.6.atomicrmw.end:
- ; GFX10-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
- ; GFX10-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub1
- ; GFX10-NEXT: $vgpr0 = COPY [[COPY13]]
- ; GFX10-NEXT: $vgpr1 = COPY [[COPY14]]
+ ; GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub0
+ ; GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[PHI1]].sub1
+ ; GFX10-NEXT: $vgpr0 = COPY [[COPY10]]
+ ; GFX10-NEXT: $vgpr1 = COPY [[COPY11]]
; GFX10-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
%old = atomicrmw fmin ptr %ptr, double %val seq_cst, !amdgpu.no.fine.grained.memory !0
ret double %old
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
index 4e50269e889deb..3e7af78eb37c5e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
@@ -20,29 +20,23 @@ define amdgpu_kernel void @call_debug_loc() {
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5, debug-location !7
; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, debug-location !7
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[COPY8]], debug-location !7
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[COPY7]], debug-location !7
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[COPY6]], debug-location !7
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[COPY5]], debug-location !7
- ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[COPY4]], debug-location !7
- ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[COPY3]], debug-location !7
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF debug-location !7
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 10, debug-location !7
- ; CHECK-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY16]], [[COPY1]], implicit $exec, debug-location !7
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY10]], [[COPY1]], implicit $exec, debug-location !7
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 20, debug-location !7
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; CHECK-NEXT: [[V_LSHLREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY17]], [[COPY]], implicit $exec, debug-location !7
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; CHECK-NEXT: [[V_LSHLREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY11]], [[COPY]], implicit $exec, debug-location !7
; CHECK-NEXT: [[V_OR3_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR3_B32_e64 [[COPY2]], [[V_LSHLREV_B32_e64_]], [[V_LSHLREV_B32_e64_1]], implicit $exec, debug-location !7
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3, debug-location !7
- ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]], debug-location !7
- ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]], debug-location !7
- ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]], debug-location !7
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3, debug-location !7
+ ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY12]], debug-location !7
+ ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY8]], debug-location !7
+ ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY7]], debug-location !7
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY9]], debug-location !7
- ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]], debug-location !7
- ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]], debug-location !7
- ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]], debug-location !7
- ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]], debug-location !7
+ ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY6]], debug-location !7
+ ; CHECK-NEXT: $sgpr12 = COPY [[COPY5]], debug-location !7
+ ; CHECK-NEXT: $sgpr13 = COPY [[COPY4]], debug-location !7
+ ; CHECK-NEXT: $sgpr14 = COPY [[COPY3]], debug-location !7
; CHECK-NEXT: $sgpr15 = COPY [[DEF]], debug-location !7
; CHECK-NEXT: $vgpr31 = COPY [[V_OR3_B32_e64_]], debug-location !7
; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee, target-flags(amdgpu-gotprel32-hi) @callee, implicit-def $scc, debug-location !7
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
index cb6076191cbc95..80de2c78eaad63 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
@@ -71,28 +71,48 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX908-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec
- ; GFX908-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX908-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX908-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub1
; GFX908-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX908-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
- ; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX908-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX908-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
- ; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
- ; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX908-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
- ; GFX908-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX908-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX908-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
+ ; GFX908-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX908-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
+ ; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
+ ; GFX908-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY6]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
+ ; GFX908-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX908-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; GFX908-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY7]], [[DEF]], implicit $exec
+ ; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
+ ; GFX908-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_SET_INACTIVE_B32_]], 0, [[V_MOV_B32_dpp]], 0, 0, implicit $mode, implicit $exec
+ ; GFX908-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY9]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
+ ; GFX908-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[V_MOV_B32_dpp1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY10]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
+ ; GFX908-NEXT: [[V_ADD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_1]], 0, [[V_MOV_B32_dpp2]], 0, 0, implicit $mode, implicit $exec
+ ; GFX908-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
+ ; GFX908-NEXT: [[V_ADD_F32_e64_3:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_2]], 0, [[V_MOV_B32_dpp3]], 0, 0, implicit $mode, implicit $exec
+ ; GFX908-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
+ ; GFX908-NEXT: [[V_ADD_F32_e64_4:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_3]], 0, [[V_MOV_B32_dpp4]], 0, 0, implicit $mode, implicit $exec
+ ; GFX908-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX908-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
+ ; GFX908-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_4]], 0, [[V_MOV_B32_dpp5]], 0, 0, implicit $mode, implicit $exec
+ ; GFX908-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 63
+ ; GFX908-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_ADD_F32_e64_5]], [[S_MOV_B32_2]]
+ ; GFX908-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[V_READLANE_B32_]]
+ ; GFX908-NEXT: early-clobber %33:vgpr_32 = STRICT_WWM [[COPY14]], implicit $exec
+ ; GFX908-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX908-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY15]], implicit $exec
+ ; GFX908-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX908-NEXT: S_BRANCH %bb.3
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.3 (%ir-block.17):
; GFX908-NEXT: successors: %bb.4(0x80000000)
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX908-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], [[COPY10]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX908-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], %33, [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX908-NEXT: {{ $}}
; GFX908-NEXT: bb.4.Flow:
; GFX908-NEXT: successors: %bb.5(0x80000000)
@@ -120,28 +140,48 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX90A-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec
- ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX90A-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX90A-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub1
; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX90A-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
- ; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX90A-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX90A-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
- ; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
- ; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
- ; GFX90A-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
+ ; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX90A-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
+ ; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
+ ; GFX90A-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY6]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
+ ; GFX90A-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; GFX90A-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY7]], [[DEF]], implicit $exec
+ ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_SET_INACTIVE_B32_]], 0, [[V_MOV_B32_dpp]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY9]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[V_MOV_B32_dpp1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY10]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_1]], 0, [[V_MOV_B32_dpp2]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_3:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_2]], 0, [[V_MOV_B32_dpp3]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_4:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_3]], 0, [[V_MOV_B32_dpp4]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_4]], 0, [[V_MOV_B32_dpp5]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 63
+ ; GFX90A-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_ADD_F32_e64_5]], [[S_MOV_B32_2]]
+ ; GFX90A-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[V_READLANE_B32_]]
+ ; GFX90A-NEXT: early-clobber %33:vgpr_32 = STRICT_WWM [[COPY14]], implicit $exec
+ ; GFX90A-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY15]], implicit $exec
+ ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3 (%ir-block.17):
; GFX90A-NEXT: successors: %bb.4(0x80000000)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX90A-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], [[COPY10]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX90A-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], %33, [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.4.Flow:
; GFX90A-NEXT: successors: %bb.5(0x80000000)
@@ -169,28 +209,48 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX942-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec
- ; GFX942-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX942-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX942-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub1
; GFX942-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX942-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GFX942-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX942-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
- ; GFX942-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX942-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
- ; GFX942-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
- ; GFX942-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
- ; GFX942-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY11]], implicit $exec
- ; GFX942-NEXT: [[COPY12:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[COPY12]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX942-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
+ ; GFX942-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX942-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
+ ; GFX942-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
+ ; GFX942-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY6]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
+ ; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX942-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+ ; GFX942-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY7]], [[DEF]], implicit $exec
+ ; GFX942-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_SET_INACTIVE_B32_]], 0, [[V_MOV_B32_dpp]], 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY9]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[V_MOV_B32_dpp1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY10]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_ADD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_1]], 0, [[V_MOV_B32_dpp2]], 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_ADD_F32_e64_3:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_2]], 0, [[V_MOV_B32_dpp3]], 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_ADD_F32_e64_4:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_3]], 0, [[V_MOV_B32_dpp4]], 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_4]], 0, [[V_MOV_B32_dpp5]], 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 63
+ ; GFX942-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_ADD_F32_e64_5]], [[S_MOV_B32_2]]
+ ; GFX942-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[V_READLANE_B32_]]
+ ; GFX942-NEXT: early-clobber %32:vgpr_32 = STRICT_WWM [[COPY14]], implicit $exec
+ ; GFX942-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY15]], implicit $exec
+ ; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.3
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.3 (%ir-block.17):
; GFX942-NEXT: successors: %bb.4(0x80000000)
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX942-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], [[COPY10]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX942-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], %32, [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.4.Flow:
; GFX942-NEXT: successors: %bb.5(0x80000000)
@@ -222,19 +282,36 @@ define amdgpu_ps void @global_atomic_fadd_f32_saddr_no_rtn_atomicrmw(ptr addrspa
; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX11-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
- ; GFX11-NEXT: [[WAVE_REDUCE_FADD_PSEUDO_F32_:%[0-9]+]]:sgpr_32 = WAVE_REDUCE_FADD_PSEUDO_F32 [[COPY2]], 2, implicit $exec
- ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[WAVE_REDUCE_FADD_PSEUDO_F32_]]
- ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY7]], implicit $exec
- ; GFX11-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[COPY8]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX11-NEXT: [[DEF1:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF
+ ; GFX11-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY6]], [[DEF1]], implicit $exec
+ ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX11-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY7]], [[V_SET_INACTIVE_B32_]], 353, 15, 15, 0, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_SET_INACTIVE_B32_]], 0, [[V_MOV_B32_dpp]], 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX11-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[V_ADD_F32_e64_]], 354, 15, 15, 0, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[V_MOV_B32_dpp1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX11-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY9]], [[V_ADD_F32_e64_1]], 356, 15, 15, 0, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_1]], 0, [[V_MOV_B32_dpp2]], 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX11-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY10]], [[V_ADD_F32_e64_2]], 360, 15, 15, 0, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_F32_e64_3:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_2]], 0, [[V_MOV_B32_dpp3]], 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+ ; GFX11-NEXT: [[V_PERMLANEX16_B32_e64_:%[0-9]+]]:vgpr_32 = V_PERMLANEX16_B32_e64 0, [[V_ADD_F32_e64_3]], 0, [[S_MOV_B32_]], 0, [[S_MOV_B32_]], [[COPY11]], 0, implicit $exec
+ ; GFX11-NEXT: [[V_ADD_F32_e64_4:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_3]], 0, [[V_PERMLANEX16_B32_e64_]], 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: early-clobber %24:vgpr_32 = STRICT_WWM [[V_ADD_F32_e64_4]], implicit $exec
+ ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY12]], implicit $exec
+ ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.3
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.3 (%ir-block.13):
; GFX11-NEXT: successors: %bb.4(0x80000000)
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], [[COPY6]], [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX11-NEXT: GLOBAL_ATOMIC_ADD_F32_SADDR [[V_MOV_B32_e32_]], %24, [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.4.Flow:
; GFX11-NEXT: successors: %bb.5(0x80000000)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
index 2b216e27a56d39..31cbb9bf732ade 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
@@ -63,44 +63,42 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec
- ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX90A-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX90A-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub1
; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX90A-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
- ; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX90A-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
+ ; GFX90A-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
+ ; GFX90A-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX90A-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
+ ; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
+ ; GFX90A-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY6]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
; GFX90A-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; GFX90A-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; GFX90A-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY10]], [[DEF1]], implicit $exec
- ; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY7]], [[DEF1]], implicit $exec
+ ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
; GFX90A-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_SET_INACTIVE_B32_]], 0, [[V_MOV_B32_dpp]], 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY9]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
; GFX90A-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[V_MOV_B32_dpp1]], 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY10]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
; GFX90A-NEXT: [[V_ADD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_1]], 0, [[V_MOV_B32_dpp2]], 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY14]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
; GFX90A-NEXT: [[V_ADD_F32_e64_3:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_2]], 0, [[V_MOV_B32_dpp3]], 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY15]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
; GFX90A-NEXT: [[V_ADD_F32_e64_4:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_3]], 0, [[V_MOV_B32_dpp4]], 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY16]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
; GFX90A-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_4]], 0, [[V_MOV_B32_dpp5]], 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX90A-NEXT: [[V_MOV_B32_dpp6:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY17]], [[V_ADD_F32_e64_5]], 312, 15, 15, 0, implicit $exec
+ ; GFX90A-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX90A-NEXT: [[V_MOV_B32_dpp6:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY14]], [[V_ADD_F32_e64_5]], 312, 15, 15, 0, implicit $exec
; GFX90A-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 63
; GFX90A-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_ADD_F32_e64_5]], [[S_MOV_B32_2]]
- ; GFX90A-NEXT: early-clobber %34:sreg_32 = STRICT_WWM [[V_READLANE_B32_]], implicit $exec
- ; GFX90A-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY18]], implicit $exec
+ ; GFX90A-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[V_READLANE_B32_]]
+ ; GFX90A-NEXT: early-clobber %34:vgpr_32 = STRICT_WWM [[COPY15]], implicit $exec
+ ; GFX90A-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY16]], implicit $exec
; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
@@ -109,7 +107,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY %34
; GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX90A-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN [[V_MOV_B32_e32_]], [[COPY19]], [[REG_SEQUENCE]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX90A-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN [[V_MOV_B32_e32_]], %34, [[REG_SEQUENCE]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX90A-NEXT: S_BRANCH %bb.5
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.4.Flow:
@@ -126,10 +124,10 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
; GFX90A-NEXT: early-clobber %41:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
- ; GFX90A-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX90A-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY20]], 0, %41, 0, 0, implicit $mode, implicit $exec
- ; GFX90A-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX90A-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_6]], 0, [[COPY21]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; GFX90A-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY17]], 0, %41, 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX90A-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_6]], 0, [[COPY18]], [[V_CMP_EQ_U32_e64_]], implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.4
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.6 (%ir-block.41):
@@ -154,44 +152,42 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX942-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec
- ; GFX942-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX942-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub0
- ; GFX942-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[COPY3]].sub1
; GFX942-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GFX942-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GFX942-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX942-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY7]], [[COPY8]], implicit $exec
- ; GFX942-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX942-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY9]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
+ ; GFX942-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub0
+ ; GFX942-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX942-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY4]], [[COPY5]], implicit $exec
+ ; GFX942-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY3]].sub1
+ ; GFX942-NEXT: [[V_MBCNT_HI_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_HI_U32_B32_e64 [[COPY6]], [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX942-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; GFX942-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
- ; GFX942-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY10]], [[DEF1]], implicit $exec
- ; GFX942-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[V_SET_INACTIVE_B32_:%[0-9]+]]:vgpr_32 = V_SET_INACTIVE_B32 0, [[COPY2]], 0, [[COPY7]], [[DEF1]], implicit $exec
+ ; GFX942-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY8]], [[V_SET_INACTIVE_B32_]], 273, 15, 15, 0, implicit $exec
; GFX942-NEXT: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_SET_INACTIVE_B32_]], 0, [[V_MOV_B32_dpp]], 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY9]], [[V_ADD_F32_e64_]], 274, 15, 15, 0, implicit $exec
; GFX942-NEXT: [[V_ADD_F32_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_]], 0, [[V_MOV_B32_dpp1]], 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp2:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY10]], [[V_ADD_F32_e64_1]], 276, 15, 15, 0, implicit $exec
; GFX942-NEXT: [[V_ADD_F32_e64_2:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_1]], 0, [[V_MOV_B32_dpp2]], 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY14]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp3:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY11]], [[V_ADD_F32_e64_2]], 280, 15, 15, 0, implicit $exec
; GFX942-NEXT: [[V_ADD_F32_e64_3:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_2]], 0, [[V_MOV_B32_dpp3]], 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY15]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp4:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY12]], [[V_ADD_F32_e64_3]], 322, 10, 15, 0, implicit $exec
; GFX942-NEXT: [[V_ADD_F32_e64_4:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_3]], 0, [[V_MOV_B32_dpp4]], 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY16]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp5:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY13]], [[V_ADD_F32_e64_4]], 323, 12, 15, 0, implicit $exec
; GFX942-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_ADD_F32_e64_4]], 0, [[V_MOV_B32_dpp5]], 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
- ; GFX942-NEXT: [[V_MOV_B32_dpp6:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY17]], [[V_ADD_F32_e64_5]], 312, 15, 15, 0, implicit $exec
+ ; GFX942-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
+ ; GFX942-NEXT: [[V_MOV_B32_dpp6:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY14]], [[V_ADD_F32_e64_5]], 312, 15, 15, 0, implicit $exec
; GFX942-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 63
; GFX942-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_ADD_F32_e64_5]], [[S_MOV_B32_2]]
- ; GFX942-NEXT: early-clobber %33:sreg_32 = STRICT_WWM [[V_READLANE_B32_]], implicit $exec
- ; GFX942-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY18]], implicit $exec
+ ; GFX942-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[V_READLANE_B32_]]
+ ; GFX942-NEXT: early-clobber %33:vgpr_32 = STRICT_WWM [[COPY15]], implicit $exec
+ ; GFX942-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX942-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_HI_U32_B32_e64_]], [[COPY16]], implicit $exec
; GFX942-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX942-NEXT: S_BRANCH %bb.3
; GFX942-NEXT: {{ $}}
@@ -200,7 +196,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY %33
; GFX942-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX942-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN [[V_MOV_B32_e32_]], [[COPY19]], [[REG_SEQUENCE]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX942-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN [[V_MOV_B32_e32_]], %33, [[REG_SEQUENCE]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX942-NEXT: S_BRANCH %bb.5
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.4.Flow:
@@ -217,10 +213,10 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX942-NEXT: SI_END_CF [[SI_IF1]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX942-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
; GFX942-NEXT: early-clobber %40:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
- ; GFX942-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX942-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY20]], 0, %40, 0, 0, implicit $mode, implicit $exec
- ; GFX942-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX942-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_6]], 0, [[COPY21]], [[V_CMP_EQ_U32_e64_]], implicit $exec
+ ; GFX942-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX942-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY17]], 0, %40, 0, 0, implicit $mode, implicit $exec
+ ; GFX942-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX942-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_6]], 0, [[COPY18]], [[V_CMP_EQ_U32_e64_]], implicit $exec
; GFX942-NEXT: S_BRANCH %bb.4
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: bb.6 (%ir-block.41):
@@ -279,9 +275,10 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 [[V_READLANE_B32_]], [[S_MOV_B32_4]], [[V_MOV_B32_dpp5]]
; GFX11-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 31
; GFX11-NEXT: [[V_READLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[V_ADD_F32_e64_4]], [[S_MOV_B32_5]]
- ; GFX11-NEXT: early-clobber %33:sreg_32 = STRICT_WWM [[V_READLANE_B32_1]], implicit $exec
- ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
- ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY14]], implicit $exec
+ ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[V_READLANE_B32_1]]
+ ; GFX11-NEXT: early-clobber %33:vgpr_32 = STRICT_WWM [[COPY14]], implicit $exec
+ ; GFX11-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
+ ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_MBCNT_LO_U32_B32_e64_]], [[COPY15]], implicit $exec
; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.3
; GFX11-NEXT: {{ $}}
@@ -290,7 +287,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY %33
; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN [[V_MOV_B32_e32_]], [[COPY15]], [[REG_SEQUENCE]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (f32) on %ir.ptr, addrspace 1)
+ ; GFX11-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN [[V_MOV_B32_e32_]], %33, [[REG_SEQUENCE]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX11-NEXT: S_BRANCH %bb.5
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.4.Flow:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
index 5f40922651b17f..49007f8259a236 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
@@ -509,8 +509,7 @@ body: |
; PREGFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; PREGFX11-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; PREGFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; PREGFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
- ; PREGFX11-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; PREGFX11-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]]
;
; GFX11-TRUE16-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; GFX11-TRUE16: liveins: $vgpr0, $sgpr0
@@ -523,8 +522,7 @@ body: |
; GFX11-TRUE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; GFX11-TRUE16-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GFX11-TRUE16-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U16_t16_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[COPY2]]
+ ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]]
;
; GFX11-FAKE16-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; GFX11-FAKE16: liveins: $vgpr0, $sgpr0
@@ -536,8 +534,7 @@ body: |
; GFX11-FAKE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; GFX11-FAKE16-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GFX11-FAKE16-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_1]]
%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
index 6dca3753d5a0bd..5d1067e01c4faa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
@@ -121,9 +121,9 @@ body: |
; GFX11-TRUE16: liveins: $vgpr0
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[DEF]], %subreg.sub1
+ ; GFX11-TRUE16-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].lo16
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
@@ -290,9 +290,8 @@ body: |
; GFX11-TRUE16: liveins: $vgpr0
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].lo16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]]
;
; GFX11-FAKE16-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
; GFX11-FAKE16: liveins: $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
index 88c2d23840b4e8..0b189bb3056f52 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
@@ -106,9 +106,8 @@ body: |
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
- ; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
- ; WAVE32-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY3]]
- ; WAVE32-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY4]], implicit $exec
+ ; WAVE32-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
+ ; WAVE32-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY3]], implicit $exec
; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY3]], implicit-def dead $scc
; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; WAVE32-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
@@ -263,9 +262,8 @@ body: |
; WAVE32-LABEL: name: copy_s1_vcc_to_vcc
; WAVE32: liveins: $sgpr0_sgpr1
; WAVE32-NEXT: {{ $}}
- ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY]]
- ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $sgpr0
+ ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:vcc(s1) = G_TRUNC %0
%2:vcc(s1) = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
index 52d7b77708a2b1..d60f2708e40443 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
@@ -509,8 +509,10 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; VI-LABEL: name: fabs_s64_ss
@@ -520,8 +522,10 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX9-LABEL: name: fabs_s64_ss
@@ -531,8 +535,10 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX10-LABEL: name: fabs_s64_ss
@@ -542,8 +548,10 @@ body: |
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX11-LABEL: name: fabs_s64_ss
@@ -553,8 +561,10 @@ body: |
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; GFX11-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_FABS %0
@@ -722,8 +732,10 @@ body: |
; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
- ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
+ ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
+ ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; VI-LABEL: name: fabs_s64_ss_no_src_constraint
@@ -733,8 +745,10 @@ body: |
; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
- ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
+ ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
+ ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX9-LABEL: name: fabs_s64_ss_no_src_constraint
@@ -744,8 +758,10 @@ body: |
; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
+ ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
+ ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX10-LABEL: name: fabs_s64_ss_no_src_constraint
@@ -755,8 +771,10 @@ body: |
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
+ ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
+ ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX11-LABEL: name: fabs_s64_ss_no_src_constraint
@@ -766,8 +784,10 @@ body: |
; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
- ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
+ ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY [[DEF]].sub1
+ ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[DEF]].sub0
+ ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
; GFX11-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s64) = IMPLICIT_DEF
%1:sgpr(s64) = G_FABS %0:sgpr(s64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
index 07c8bf63488798..3cc029bd0fcb32 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
@@ -509,8 +509,10 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; SI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; VI-LABEL: name: fneg_s64_ss
@@ -520,8 +522,10 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; VI-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX9-LABEL: name: fneg_s64_ss
@@ -531,8 +535,10 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX9-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX10-LABEL: name: fneg_s64_ss
@@ -542,8 +548,10 @@ body: |
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX10-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX11-LABEL: name: fneg_s64_ss
@@ -553,8 +561,10 @@ body: |
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX11-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX11-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
; GFX11-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_FNEG %0
@@ -1217,8 +1227,10 @@ body: |
; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
+ ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; SI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; VI-LABEL: name: fneg_fabs_s64_ss
@@ -1228,8 +1240,10 @@ body: |
; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
+ ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; VI-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX9-LABEL: name: fneg_fabs_s64_ss
@@ -1239,8 +1253,10 @@ body: |
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
+ ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX9-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX10-LABEL: name: fneg_fabs_s64_ss
@@ -1250,8 +1266,10 @@ body: |
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
;
; GFX11-LABEL: name: fneg_fabs_s64_ss
@@ -1261,8 +1279,10 @@ body: |
; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
- ; GFX11-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def dead $scc
- ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
+ ; GFX11-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY [[COPY]].sub0
+ ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_OR_B32_]], %subreg.sub1
; GFX11-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_FABS %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
index dcf3f8ab52c9d2..a9b33eeef349c7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
@@ -17,7 +17,7 @@ body: |
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX10-NEXT: early-clobber %3:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[COPY]], 36, 0 :: (dereferenceable invariant load (<2 x s64>), align 4, addrspace 4)
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY %3.sub0_sub1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec_xnull = COPY %3.sub0_sub1
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY %3.sub2_sub3
; GFX10-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY2]], 0, 0 :: (load (s64), addrspace 1)
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775808
@@ -26,9 +26,8 @@ body: |
; GFX10-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[COPY3]], 1, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, [[V_ADD_F64_e64_]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_ADD_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[V_ADD_F64_e64_]], 1, [[V_FLOOR_F64_e64_]], 0, 0, implicit $mode, implicit $exec
- ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY1]]
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX10-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY5]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ ; GFX10-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY1]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
; GFX10-NEXT: S_ENDPGM 0
;
; GFX11-LABEL: name: fract_f64_neg
@@ -36,7 +35,7 @@ body: |
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX11-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 36, 0 :: (dereferenceable invariant load (<2 x s64>), align 4, addrspace 4)
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
; GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY2]], 0, 0 :: (load (s64), addrspace 1)
; GFX11-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775808
@@ -45,9 +44,8 @@ body: |
; GFX11-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[COPY3]], 1, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, [[V_ADD_F64_e64_]], 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: [[V_ADD_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[V_ADD_F64_e64_]], 1, [[V_FLOOR_F64_e64_]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY1]]
; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY5]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ ; GFX11-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY1]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
; GFX11-NEXT: S_ENDPGM 0
%2:sgpr(p4) = COPY $sgpr0_sgpr1
%7:sgpr(i64) = G_CONSTANT i64 36
@@ -85,7 +83,7 @@ body: |
; GFX10-NEXT: {{ $}}
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX10-NEXT: early-clobber %3:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[COPY]], 36, 0 :: (dereferenceable invariant load (<2 x s64>), align 4, addrspace 4)
- ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY %3.sub0_sub1
+ ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec_xnull = COPY %3.sub0_sub1
; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY %3.sub2_sub3
; GFX10-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY2]], 0, 0 :: (load (s64), addrspace 1)
; GFX10-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775808
@@ -94,9 +92,8 @@ body: |
; GFX10-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[COPY3]], 3, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, [[V_ADD_F64_e64_]], 0, 0, implicit $mode, implicit $exec
; GFX10-NEXT: [[V_ADD_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[V_ADD_F64_e64_]], 1, [[V_FLOOR_F64_e64_]], 0, 0, implicit $mode, implicit $exec
- ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY1]]
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX10-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY5]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ ; GFX10-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY1]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
; GFX10-NEXT: S_ENDPGM 0
;
; GFX11-LABEL: name: fract_f64_neg_abs
@@ -104,7 +101,7 @@ body: |
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GFX11-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 36, 0 :: (dereferenceable invariant load (<2 x s64>), align 4, addrspace 4)
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
+ ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[S_LOAD_DWORDX4_IMM]].sub0_sub1
; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX4_IMM]].sub2_sub3
; GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY2]], 0, 0 :: (load (s64), addrspace 1)
; GFX11-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775808
@@ -113,9 +110,8 @@ body: |
; GFX11-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[COPY3]], 3, [[COPY4]], 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, [[V_ADD_F64_e64_]], 0, 0, implicit $mode, implicit $exec
; GFX11-NEXT: [[V_ADD_F64_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_ADD_F64_e64 0, [[V_ADD_F64_e64_]], 1, [[V_FLOOR_F64_e64_]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_64_xexec_xnull = COPY [[COPY1]]
; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY5]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
+ ; GFX11-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[V_ADD_F64_e64_1]], [[COPY1]], 0, 0, implicit $exec :: (store (s64), addrspace 1)
; GFX11-NEXT: S_ENDPGM 0
%2:sgpr(p4) = COPY $sgpr0_sgpr1
%7:sgpr(i64) = G_CONSTANT i64 36
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
index 87ebb9fe98cd6f..d6c29176b504d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
@@ -30,9 +30,8 @@ body: |
; GFX11-TRUE16: liveins: $vgpr0
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].lo16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]]
;
; GFX11-FAKE16-LABEL: name: test_freeze_s1_vgpr_to_vgpr
; GFX11-FAKE16: liveins: $vgpr0
@@ -72,9 +71,8 @@ body: |
; GFX11-TRUE16: liveins: $vgpr0
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $agpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].lo16
+ ; GFX11-TRUE16-NEXT: $agpr0 = COPY [[COPY1]]
;
; GFX11-FAKE16-LABEL: name: test_freeze_s1_vgpr_to_agpr
; GFX11-FAKE16: liveins: $vgpr0
@@ -103,18 +101,16 @@ body: |
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX6-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
- ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX6-NEXT: S_ENDPGM 0, implicit [[COPY2]]
+ ; GFX6-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_U32_e64_]]
;
; GFX10Plus-LABEL: name: test_freeze_s1_vcc
; GFX10Plus: liveins: $vgpr0, $vgpr1
; GFX10Plus-NEXT: {{ $}}
; GFX10Plus-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10Plus-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX10Plus-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
- ; GFX10Plus-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX10Plus-NEXT: S_ENDPGM 0, implicit [[COPY2]]
+ ; GFX10Plus-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+ ; GFX10Plus-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_ICMP intpred(eq), %0(s32), %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
index 16d550d4e1364b..b223875c91b87d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
@@ -509,8 +509,7 @@ body: |
; PREGFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; PREGFX11-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; PREGFX11-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; PREGFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
- ; PREGFX11-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; PREGFX11-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
;
; GFX11-TRUE16-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; GFX11-TRUE16: liveins: $vgpr0, $sgpr0
@@ -523,8 +522,7 @@ body: |
; GFX11-TRUE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; GFX11-TRUE16-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GFX11-TRUE16-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U16_t16_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[COPY2]]
+ ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
;
; GFX11-FAKE16-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; GFX11-FAKE16: liveins: $vgpr0, $sgpr0
@@ -536,8 +534,7 @@ body: |
; GFX11-FAKE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; GFX11-FAKE16-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GFX11-FAKE16-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
index 4b01c9c41bcbbb..9520b9add42352 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pseudo-scalar-transcendental.mir
@@ -35,13 +35,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_EXP_F16_e64_]]
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
- %0:sgpr(i32) = COPY $sgpr0
- %1:sgpr(f16) = G_TRUNC %0(i32)
- %2:sgpr(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %1
- %3:sgpr(i32) = G_ANYEXT %2(f16)
- $vgpr0 = COPY %3(i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[V_S_EXP_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0(s32)
+ %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %1
+ %3:sgpr(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
...
---
@@ -78,13 +77,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_LOG_F16_e64_]]
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
- %0:sgpr(i32) = COPY $sgpr0
- %1:sgpr(f16) = G_TRUNC %0(i32)
- %2:sgpr(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), %1
- %3:sgpr(i32) = G_ANYEXT %2(f16)
- $vgpr0 = COPY %3(i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[V_S_LOG_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0(s32)
+ %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), %1
+ %3:sgpr(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
...
---
@@ -121,13 +119,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sreg_32_xexec = nnan ninf nsz arcp contract afn reassoc nofpexcept V_S_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_RCP_F16_e64_]]
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
- %0:sgpr(i32) = COPY $sgpr0
- %1:sgpr(f16) = G_TRUNC %0(i32)
- %2:sgpr(f16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1(f16)
- %3:sgpr(i32) = G_ANYEXT %2(f16)
- $vgpr0 = COPY %3(i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[V_S_RCP_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0(s32)
+ %2:sgpr(s16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1(s16)
+ %3:sgpr(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
...
---
@@ -164,13 +161,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_RSQ_F16_e64_]]
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
- %0:sgpr(i32) = COPY $sgpr0
- %1:sgpr(f16) = G_TRUNC %0(i32)
- %2:sgpr(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1(f16)
- %3:sgpr(i32) = G_ANYEXT %2(f16)
- $vgpr0 = COPY %3(i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[V_S_RSQ_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0(s32)
+ %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1(s16)
+ %3:sgpr(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
...
---
@@ -207,13 +203,12 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_SQRT_F16_e64_]]
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
- %0:sgpr(i32) = COPY $sgpr0
- %1:sgpr(f16) = G_TRUNC %0(i32)
- %2:sgpr(f16) = G_FSQRT %1
- %3:sgpr(i32) = G_ANYEXT %2(f16)
- $vgpr0 = COPY %3(i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[V_S_SQRT_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0(s32)
+ %2:sgpr(s16) = G_FSQRT %1
+ %3:sgpr(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
...
---
@@ -250,12 +245,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_SQRT_F16_e64_]]
- ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]
- %0:sgpr(i32) = COPY $sgpr0
- %1:sgpr(f16) = G_TRUNC %0(i32)
- %2:sgpr(f16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %1(f16)
- %3:sgpr(i32) = G_ANYEXT %2(f16)
- $vgpr0 = COPY %3(i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[V_S_SQRT_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0(s32)
+ %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %1(s16)
+ %3:sgpr(s32) = G_ANYEXT %2(s16)
+ $vgpr0 = COPY %3(s32)
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
index e9eae5dceb3d38..1e588b0f71115d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
@@ -103,10 +103,12 @@ body: |
; GCN: liveins: $sgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
- ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 31
+ ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[COPY]]
+ ; GCN-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sgpr_32 = S_ASHR_I32 [[S_SEXT_I32_I16_]], [[S_MOV_B32_]], implicit-def dead $scc
+ ; GCN-NEXT: [[S_SEXT_I32_I16_1:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = S_SEXT_I32_I16 [[COPY]]
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_SEXT_I32_I16_1]], %subreg.sub0, [[S_ASHR_I32_]], %subreg.sub1
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_SEXT %1
@@ -126,8 +128,8 @@ body: |
; GCN-LABEL: name: sext_sgpr_s32_to_sgpr_s64
; GCN: liveins: $sgpr0
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], 31, implicit-def dead $scc
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0
+ ; GCN-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[COPY]], 31, implicit-def dead $scc
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_ASHR_I32_]], %subreg.sub1
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
index 335308235c7484..d55bf460d6ad99 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
@@ -27,6 +27,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s32), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s32_to_4
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7-NEXT: {{ $}}
@@ -34,12 +35,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s32), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s32_to_4
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-NEXT: DS_WRITE_B32_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (s32), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s32_to_4
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -73,6 +76,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B16 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s16), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s32_to_2
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7-NEXT: {{ $}}
@@ -80,12 +84,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B16 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s16), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s32_to_2
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-NEXT: DS_WRITE_B16_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (s16), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s32_to_2
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -119,6 +125,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B8 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s32_to_1
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7-NEXT: {{ $}}
@@ -126,12 +133,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B8 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s32_to_1
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-NEXT: DS_WRITE_B8_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s32_to_1
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -165,6 +174,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (<2 x s16>), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_v2s16
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7-NEXT: {{ $}}
@@ -172,12 +182,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (<2 x s16>), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_v2s16
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-NEXT: DS_WRITE_B32_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (<2 x s16>), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_v2s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -211,6 +223,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (p3), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_p3
; GFX7: liveins: $vgpr0, $vgpr1
; GFX7-NEXT: {{ $}}
@@ -218,12 +231,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (p3), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_p3
; GFX9: liveins: $vgpr0, $vgpr1
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9-NEXT: DS_WRITE_B32_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (p3), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_p3
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
@@ -251,15 +266,18 @@ body: |
; GFX6-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s32_to_1_constant_4095
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
; GFX7-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s32_to_1_constant_4095
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
; GFX9-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX9-NEXT: DS_WRITE_B8_gfx9 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s32_to_1_constant_4095
; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
@@ -290,15 +308,18 @@ body: |
; GFX6-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s32_to_1_constant_4096
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX7-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s32_to_1_constant_4096
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX9-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX9-NEXT: DS_WRITE_B8_gfx9 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (store (s8), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s32_to_1_constant_4096
; GFX10: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
@@ -330,6 +351,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p3) :: (store (s64), align 4, addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s64_align4
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -339,6 +361,7 @@ body: |
; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX7-NEXT: DS_WRITE2_B32 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (s64), align 4, addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s64_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -347,6 +370,7 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX9-NEXT: DS_WRITE2_B32_gfx9 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $exec :: (store (s64), align 4, addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s64_align4
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -382,6 +406,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: G_STORE [[COPY]](p1), [[COPY1]](p3) :: (store (p1), align 4, addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_p1_align4
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -391,6 +416,7 @@ body: |
; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX7-NEXT: DS_WRITE2_B32 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (p1), align 4, addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_p1_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -399,6 +425,7 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX9-NEXT: DS_WRITE2_B32_gfx9 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $exec :: (store (p1), align 4, addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_p1_align4
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -434,6 +461,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: G_STORE [[COPY]](<2 x s32>), [[COPY1]](p3) :: (store (<2 x s32>), align 4, addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_v2s32_align4
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -443,6 +471,7 @@ body: |
; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX7-NEXT: DS_WRITE2_B32 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (<2 x s32>), align 4, addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_v2s32_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -451,6 +480,7 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX9-NEXT: DS_WRITE2_B32_gfx9 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $exec :: (store (<2 x s32>), align 4, addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_v2s32_align4
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -486,6 +516,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: G_STORE [[COPY]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), align 4, addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_v4s16_align4
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -495,6 +526,7 @@ body: |
; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX7-NEXT: DS_WRITE2_B32 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (<4 x s16>), align 4, addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_v4s16_align4
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -503,6 +535,7 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX9-NEXT: DS_WRITE2_B32_gfx9 [[COPY1]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $exec :: (store (<4 x s16>), align 4, addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_v4s16_align4
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -538,6 +571,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s64), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s64_align8
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -545,12 +579,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (s64), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s64_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-NEXT: DS_WRITE_B64_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (s64), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s64_align8
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -584,6 +620,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (p1), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_p1_align8
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -591,12 +628,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (p1), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_p1_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-NEXT: DS_WRITE_B64_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (p1), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_p1_align8
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -630,6 +669,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (<2 x s32>), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_v2s32_align8
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -637,12 +677,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (<2 x s32>), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_v2s32_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-NEXT: DS_WRITE_B64_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (<2 x s32>), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_v2s32_align8
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -676,6 +718,7 @@ body: |
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (<4 x s16>), addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_v4s16_align8
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -683,12 +726,14 @@ body: |
; GFX7-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX7-NEXT: $m0 = S_MOV_B32 -1
; GFX7-NEXT: DS_WRITE_B64 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store (<4 x s16>), addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_v4s16_align8
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9-NEXT: DS_WRITE_B64_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store (<4 x s16>), addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_v4s16_align8
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -724,6 +769,7 @@ body: |
; GFX6-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY1]], [[C]](s32)
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: G_STORE [[COPY]](s64), [[PTR_ADD]](p3) :: (store (s64), align 4, addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s64_align4_from_1_gep_1016
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -733,6 +779,7 @@ body: |
; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX7-NEXT: DS_WRITE2_B32 [[COPY1]], [[COPY3]], [[COPY2]], 254, 255, 0, implicit $m0, implicit $exec :: (store (s64), align 4, addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s64_align4_from_1_gep_1016
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -741,6 +788,7 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX9-NEXT: DS_WRITE2_B32_gfx9 [[COPY1]], [[COPY3]], [[COPY2]], 254, 255, 0, implicit $exec :: (store (s64), align 4, addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s64_align4_from_1_gep_1016
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -780,6 +828,7 @@ body: |
; GFX6-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY1]], [[C]](s32)
; GFX6-NEXT: $m0 = S_MOV_B32 -1
; GFX6-NEXT: G_STORE [[COPY]](s64), [[PTR_ADD]](p3) :: (store (s64), align 4, addrspace 3)
+ ;
; GFX7-LABEL: name: store_local_s64_align4_from_1_gep_1020
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2
; GFX7-NEXT: {{ $}}
@@ -791,6 +840,7 @@ body: |
; GFX7-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX7-NEXT: DS_WRITE2_B32 [[V_ADD_CO_U32_e64_]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $m0, implicit $exec :: (store (s64), align 4, addrspace 3)
+ ;
; GFX9-LABEL: name: store_local_s64_align4_from_1_gep_1020
; GFX9: liveins: $vgpr0_vgpr1, $vgpr2
; GFX9-NEXT: {{ $}}
@@ -801,6 +851,7 @@ body: |
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GFX9-NEXT: DS_WRITE2_B32_gfx9 [[V_ADD_U32_e64_]], [[COPY3]], [[COPY2]], 0, 1, 0, implicit $exec :: (store (s64), align 4, addrspace 3)
+ ;
; GFX10-LABEL: name: store_local_s64_align4_from_1_gep_1020
; GFX10: liveins: $vgpr0_vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
index 3f4f6ece113553..f951c41507801d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
@@ -294,11 +294,11 @@ body: |
; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:sgpr_384(<12 x s32>) = G_CONCAT_VECTORS [[COPY]](<3 x s32>), [[COPY1]](<3 x s32>), [[COPY2]](<3 x s32>), [[COPY3]](<3 x s32>)
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_96(<3 x s32>) = COPY [[CONCAT_VECTORS]].sub0_sub1_sub2(<12 x s32>)
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_96(<3 x s32>) = COPY [[CONCAT_VECTORS]].sub3_sub4_sub5(<12 x s32>)
- ; GCN-NEXT: [[UV:%[0-9]+]]:sgpr_96(<3 x s32>), [[UV1:%[0-9]+]]:sgpr_96(<3 x s32>), [[UV2:%[0-9]+]]:sgpr_96(<3 x s32>), [[UV3:%[0-9]+]]:sgpr_96(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>)
- ; GCN-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[UV]](<3 x s32>)
- ; GCN-NEXT: $sgpr4_sgpr5_sgpr6 = COPY [[UV1]](<3 x s32>)
- ; GCN-NEXT: $sgpr8_sgpr9_sgpr10 = COPY [[UV2]](<3 x s32>)
- ; GCN-NEXT: $sgpr12_sgpr13_sgpr14 = COPY [[UV3]](<3 x s32>)
+ ; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_96(<3 x s32>), [[COPY5:%[0-9]+]]:sgpr_96(<3 x s32>), [[UV:%[0-9]+]]:sgpr_96(<3 x s32>), [[UV1:%[0-9]+]]:sgpr_96(<3 x s32>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<12 x s32>)
+ ; GCN-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[COPY4]](<3 x s32>)
+ ; GCN-NEXT: $sgpr4_sgpr5_sgpr6 = COPY [[COPY5]](<3 x s32>)
+ ; GCN-NEXT: $sgpr8_sgpr9_sgpr10 = COPY [[UV]](<3 x s32>)
+ ; GCN-NEXT: $sgpr12_sgpr13_sgpr14 = COPY [[UV1]](<3 x s32>)
%0:sgpr(<3 x s32>) = COPY $sgpr0_sgpr1_sgpr2
%1:sgpr(<3 x s32>) = COPY $sgpr4_sgpr5_sgpr6
%2:sgpr(<3 x s32>) = COPY $sgpr8_sgpr9_sgpr10
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
index 005422a4d93796..18af22082d12d1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
@@ -510,8 +510,7 @@ body: |
; PREGFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; PREGFX11-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; PREGFX11-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; PREGFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
- ; PREGFX11-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; PREGFX11-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
;
; GFX11-TRUE16-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; GFX11-TRUE16: liveins: $vgpr0, $sgpr0
@@ -524,8 +523,7 @@ body: |
; GFX11-TRUE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; GFX11-TRUE16-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GFX11-TRUE16-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U16_t16_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[COPY2]]
+ ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
;
; GFX11-FAKE16-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
; GFX11-FAKE16: liveins: $vgpr0, $sgpr0
@@ -537,8 +535,7 @@ body: |
; GFX11-FAKE16-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
; GFX11-FAKE16-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
; GFX11-FAKE16-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[COPY1]]
+ ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%1:vgpr(s32) = COPY $vgpr0
%0:vgpr(s1) = G_TRUNC %1(s32)
%sgpr0:sgpr(s32) = COPY $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
index 1706beb5bb46e6..485ea7baa2ea70 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
@@ -103,10 +103,11 @@ body: |
; GCN: liveins: $sgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
- ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
- ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
+ ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
+ ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sgpr_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_AND_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
+ ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
index 04cdd48f8f78eb..408bde3943922b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
@@ -41,21 +41,17 @@ define amdgpu_ps ptr addrspace(8) @basic_raw_buffer(ptr inreg %p) {
; CHECK45-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 -536870912
; CHECK45-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[REG_SEQUENCE1]], [[S_MOV_B64_]], implicit-def dead $scc
- ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub0
- ; CHECK45-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub1
- ; CHECK45-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_1]].sub0
- ; CHECK45-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_1]].sub1
- ; CHECK45-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
; CHECK45-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK45-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
+ ; CHECK45-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
; CHECK45-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; CHECK45-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; CHECK45-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_1]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
; CHECK45-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; CHECK45-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; CHECK45-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_1]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; CHECK45-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
; CHECK45-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3
%rsrc = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p0.i64(ptr %p, i16 0, i64 1234, i32 5678)
@@ -395,21 +391,17 @@ define amdgpu_ps ptr addrspace(8) @basic_struct_buffer(ptr inreg %p) {
; CHECK45-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[REG_SEQUENCE1]], [[S_MOV_B64_]], implicit-def dead $scc
; CHECK45-NEXT: [[S_OR_B64_2:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_OR_B64_1]], [[REG_SEQUENCE2]], implicit-def dead $scc
- ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub0
- ; CHECK45-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub1
- ; CHECK45-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_2]].sub0
- ; CHECK45-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_2]].sub1
- ; CHECK45-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
+ ; CHECK45-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec
; CHECK45-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK45-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
+ ; CHECK45-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
; CHECK45-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; CHECK45-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; CHECK45-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_2]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
; CHECK45-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; CHECK45-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; CHECK45-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_2]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; CHECK45-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
; CHECK45-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3
%rsrc = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p0.i64(ptr %p, i16 4, i64 1234, i32 5678)
@@ -470,21 +462,17 @@ define amdgpu_ps ptr addrspace(8) @variable_top_half(ptr inreg %p, i64 inreg %nu
; CHECK45-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_LSHL_B32_1]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_LSHR_B64_]], [[REG_SEQUENCE3]], implicit-def dead $scc
; CHECK45-NEXT: [[S_OR_B64_2:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_OR_B64_1]], [[REG_SEQUENCE4]], implicit-def dead $scc
- ; CHECK45-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub0
- ; CHECK45-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub1
- ; CHECK45-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_2]].sub0
- ; CHECK45-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_2]].sub1
- ; CHECK45-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; CHECK45-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; CHECK45-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK45-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; CHECK45-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; CHECK45-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; CHECK45-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; CHECK45-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_2]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; CHECK45-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; CHECK45-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; CHECK45-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_2]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; CHECK45-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
; CHECK45-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3
%rsrc = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p0.i64(ptr %p, i16 4, i64 %numVals, i32 %flags)
@@ -549,21 +537,17 @@ define amdgpu_ps ptr addrspace(8) @general_case(ptr inreg %p, i16 inreg %stride,
; CHECK45-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_LSHL_B32_2]], %subreg.sub1
; CHECK45-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_LSHR_B64_]], [[REG_SEQUENCE3]], implicit-def dead $scc
; CHECK45-NEXT: [[S_OR_B64_2:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_OR_B64_1]], [[REG_SEQUENCE4]], implicit-def dead $scc
- ; CHECK45-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub0
- ; CHECK45-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_]].sub1
- ; CHECK45-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_2]].sub0
- ; CHECK45-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_OR_B64_2]].sub1
- ; CHECK45-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; CHECK45-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; CHECK45-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK45-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; CHECK45-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; CHECK45-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; CHECK45-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; CHECK45-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_2]].sub0
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; CHECK45-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; CHECK45-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; CHECK45-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_OR_B64_2]].sub1
+ ; CHECK45-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; CHECK45-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
; CHECK45-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3
%rsrc = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p0.i64(ptr %p, i16 %stride, i64 %numVals, i32 %flags)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
index 30d6fa4a679669..1f862d0745d582 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
@@ -556,13 +556,12 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr
; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0_sub1
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0
+ ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -584,13 +583,12 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr
; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1
- ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0
+ ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub1
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX1200-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1200-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -612,13 +610,12 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr
; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1
- ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0
+ ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub1
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
@@ -743,8 +740,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr
; GFX8-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY10]], %subreg.sub0_sub1, [[COPY11]], %subreg.sub2_sub3
- ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0_sub1
+ ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
; GFX8-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX8-NEXT: {{ $}}
@@ -754,11 +750,11 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: bb.5:
- ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub0
- ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub1
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0
+ ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -809,8 +805,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr
; GFX1200-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX1200-NEXT: {{ $}}
; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY10]], %subreg.sub0_sub1, [[COPY11]], %subreg.sub2_sub3
- ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1
+ ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
; GFX1200-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX1200-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX1200-NEXT: {{ $}}
@@ -820,11 +815,11 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr
; GFX1200-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
; GFX1200-NEXT: {{ $}}
; GFX1200-NEXT: bb.5:
- ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub0
- ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub1
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX1200-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0
+ ; GFX1200-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub1
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX1200-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX1200-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -875,8 +870,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr
; GFX1250-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY10]], %subreg.sub0_sub1, [[COPY11]], %subreg.sub2_sub3
- ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1
+ ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
; GFX1250-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX1250-NEXT: {{ $}}
@@ -886,11 +880,11 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr
; GFX1250-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.5:
- ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub0
- ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub1
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0
+ ; GFX1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub1
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.raw.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
@@ -1099,13 +1093,12 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr
; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0_sub1
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0
+ ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -1127,13 +1120,12 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr
; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1
- ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0
+ ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub1
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX1200-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1200-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -1158,13 +1150,12 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr
; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec
; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1
- ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0
+ ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub1
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%voffset = add i32 %voffset.base, 4095
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
index 0d0ab1388c0d64..26b1bcfee1a36c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
@@ -1123,15 +1123,13 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1
- ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub2_sub3
- ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[COPY12]]
+ ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3
- ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY14]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x i32>) into %ir.data_addr, align 16, addrspace 1)
+ ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1)
; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1
@@ -1365,16 +1363,16 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3
; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
- ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY12]], %subreg.sub0, [[COPY13]], %subreg.sub1
- ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3
- ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY14]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.data_addr, align 16, addrspace 1)
+ ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1)
; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
index a9ada36d4b2ffc..afd315391940fb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
@@ -245,9 +245,8 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
; GFX8-NEXT: successors: %bb.3(0x80000000)
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
- ; GFX8-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
- ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX8-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY7]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX8-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
+ ; GFX8-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: bb.3:
; GFX8-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
@@ -283,9 +282,8 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
; GFX12-NEXT: successors: %bb.3(0x80000000)
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
- ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[COPY7]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
+ ; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
index 38ebefab6eb909..750c580dd5ac1e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
@@ -216,13 +216,12 @@ define amdgpu_ps double @raw_ptr_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__
; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64) on %ir.rsrc, align 1, addrspace 8)
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0_sub1
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64) on %ir.rsrc, align 1, addrspace 8)
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub1
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
@@ -305,8 +304,7 @@ define amdgpu_ps double @raw_ptr_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY10]], %subreg.sub0_sub1, [[COPY11]], %subreg.sub2_sub3
- ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64) on %ir.rsrc, align 1, addrspace 8)
- ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0_sub1
+ ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE4]], [[COPY12]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64) on %ir.rsrc, align 1, addrspace 8)
; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; CHECK-NEXT: {{ $}}
@@ -316,11 +314,11 @@ define amdgpu_ps double @raw_ptr_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
- ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub0
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY17]].sub1
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0
+ ; CHECK-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub1
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
@@ -411,13 +409,12 @@ define amdgpu_ps double @raw_ptr_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__
; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64) on %ir.rsrc, align 1, addrspace 8)
- ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0_sub1
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub0
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY10]].sub1
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (s64) on %ir.rsrc, align 1, addrspace 8)
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub0
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN]].sub1
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%voffset = add i32 %voffset.base, 4095
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
index a150af1972ea58..a45e443a88d66c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
@@ -117,9 +117,8 @@ define amdgpu_ps void @raw_ptr_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
- ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
- ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_EQ_U32_e64_]]
- ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[COPY7]], implicit-def $exec, implicit-def $scc, implicit $exec
+ ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec
+ ; CHECK-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
index db25e1c0c3e34e..d62083ebc50a01 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
@@ -156,13 +156,11 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s64))
- ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
- ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
- ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
+ ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -177,13 +175,11 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s64))
- ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
- ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
- ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
+ ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -198,13 +194,11 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s64))
- ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
- ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
- ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
+ ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub0
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -219,13 +213,11 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s64))
- ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub0
- ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub1
- ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub0
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub1
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%val = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
@@ -244,18 +236,14 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s96), align 16)
- ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0
- ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1
- ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2
- ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3
- ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
;
@@ -270,18 +258,14 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s96), align 16)
- ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0
- ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1
- ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2
- ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3
- ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
;
@@ -296,18 +280,14 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX4_SGPR:%[0-9]+]]:sgpr_128 = S_BUFFER_LOAD_DWORDX4_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s96), align 16)
- ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0
- ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1
- ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2
- ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub3
- ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub0
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX4_SGPR]].sub2
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
;
@@ -322,17 +302,14 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM:%[0-9]+]]:sgpr_96 = S_BUFFER_LOAD_DWORDX3_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s96), align 16)
- ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub0
- ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub1
- ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub2
- ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub0
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub1
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub2
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2
%val = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
@@ -351,37 +328,29 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s256))
- ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
- ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
- ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
- ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
- ; GFX6-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
- ; GFX6-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
- ; GFX6-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
- ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
- ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
+ ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
+ ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
+ ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX6-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
+ ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX6-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX6-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX6-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX6-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
;
@@ -396,37 +365,29 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s256))
- ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
- ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
- ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
- ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
- ; GFX7-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
- ; GFX7-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
- ; GFX7-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
- ; GFX7-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
- ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
+ ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
+ ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
+ ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX7-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
+ ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX7-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX7-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX7-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX7-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
;
@@ -441,37 +402,29 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s256))
- ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
- ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
- ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
- ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
- ; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
- ; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
- ; GFX8-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
- ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub0
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
+ ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
+ ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub2
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
+ ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub3
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX8-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
+ ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub4
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX8-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub5
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX8-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub6
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX8-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR]].sub7
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX8-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
;
@@ -486,37 +439,29 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg
; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s256))
- ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub0
- ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub1
- ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub2
- ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub3
- ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub4
- ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub5
- ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub6
- ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub7
- ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub0
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub1
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub2
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub3
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX1200_1250-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub4
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX1200_1250-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub5
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX1200_1250-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub6
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1200_1250-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub7
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1200_1250-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7
%val = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
@@ -535,69 +480,53 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr
; GFX6-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX6-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s512))
- ; GFX6-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
- ; GFX6-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
- ; GFX6-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
- ; GFX6-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
- ; GFX6-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
- ; GFX6-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
- ; GFX6-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
- ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
- ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
- ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
- ; GFX6-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
- ; GFX6-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
- ; GFX6-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
- ; GFX6-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
- ; GFX6-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
- ; GFX6-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
- ; GFX6-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX6-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX6-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
+ ; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX6-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX6-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
+ ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX6-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX6-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
+ ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX6-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX6-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
+ ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX6-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX6-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
+ ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX6-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX6-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
+ ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX6-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX6-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
+ ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX6-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
- ; GFX6-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
+ ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
; GFX6-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
- ; GFX6-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
+ ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
; GFX6-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
- ; GFX6-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
+ ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
; GFX6-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
- ; GFX6-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
+ ; GFX6-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
; GFX6-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
- ; GFX6-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
+ ; GFX6-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX6-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
- ; GFX6-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
+ ; GFX6-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX6-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
- ; GFX6-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
+ ; GFX6-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX6-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
- ; GFX6-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
- ; GFX6-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
+ ; GFX6-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX6-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
; GFX6-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
;
@@ -612,69 +541,53 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr
; GFX7-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX7-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s512))
- ; GFX7-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
- ; GFX7-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
- ; GFX7-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
- ; GFX7-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
- ; GFX7-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
- ; GFX7-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
- ; GFX7-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
- ; GFX7-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
- ; GFX7-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
- ; GFX7-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
- ; GFX7-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
- ; GFX7-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
- ; GFX7-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
- ; GFX7-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
- ; GFX7-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
- ; GFX7-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
- ; GFX7-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX7-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX7-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
+ ; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX7-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX7-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
+ ; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX7-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX7-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
+ ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX7-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX7-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
+ ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX7-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX7-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
+ ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX7-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX7-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
+ ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX7-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX7-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
+ ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX7-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
- ; GFX7-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
+ ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
; GFX7-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
- ; GFX7-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
+ ; GFX7-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
; GFX7-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
- ; GFX7-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
+ ; GFX7-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
; GFX7-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
- ; GFX7-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
+ ; GFX7-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
; GFX7-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
- ; GFX7-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
+ ; GFX7-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX7-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
- ; GFX7-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
+ ; GFX7-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX7-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
- ; GFX7-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
+ ; GFX7-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX7-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
- ; GFX7-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
- ; GFX7-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
+ ; GFX7-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
+ ; GFX7-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX7-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
; GFX7-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
;
@@ -689,69 +602,53 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr
; GFX8-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR [[REG_SEQUENCE]], [[COPY4]], 0 :: (dereferenceable invariant load (s512))
- ; GFX8-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
- ; GFX8-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
- ; GFX8-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
- ; GFX8-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
- ; GFX8-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
- ; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
- ; GFX8-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
- ; GFX8-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
- ; GFX8-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
- ; GFX8-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
- ; GFX8-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
- ; GFX8-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
- ; GFX8-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
- ; GFX8-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
- ; GFX8-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
- ; GFX8-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub0
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
+ ; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX8-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
+ ; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub2
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX8-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX8-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
+ ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub3
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX8-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX8-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
+ ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub4
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX8-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX8-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
+ ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub5
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX8-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX8-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
+ ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub6
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX8-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX8-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
+ ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub7
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX8-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
- ; GFX8-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
+ ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub8
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
; GFX8-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
- ; GFX8-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
+ ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub9
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
; GFX8-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
- ; GFX8-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
+ ; GFX8-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub10
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
; GFX8-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
- ; GFX8-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
+ ; GFX8-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub11
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
; GFX8-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
- ; GFX8-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
+ ; GFX8-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub12
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX8-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
- ; GFX8-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
+ ; GFX8-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub13
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX8-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
- ; GFX8-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
+ ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub14
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX8-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
- ; GFX8-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
+ ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR]].sub15
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX8-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
;
@@ -766,69 +663,53 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr
; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s512))
- ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub0
- ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub1
- ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub2
- ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub3
- ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub4
- ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub5
- ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub6
- ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub7
- ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub8
- ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub9
- ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub10
- ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub11
- ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub12
- ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub13
- ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub14
- ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub15
- ; GFX1200_1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub0
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; GFX1200_1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200_1250-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY22]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub1
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
; GFX1200_1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX1200_1250-NEXT: [[COPY23:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY23]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub2
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX1200_1250-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GFX1200_1250-NEXT: [[COPY24:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY24]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub3
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX1200_1250-NEXT: $sgpr3 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GFX1200_1250-NEXT: [[COPY25:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY25]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub4
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX1200_1250-NEXT: $sgpr4 = COPY [[V_READFIRSTLANE_B32_4]]
- ; GFX1200_1250-NEXT: [[COPY26:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY26]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub5
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
; GFX1200_1250-NEXT: $sgpr5 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX1200_1250-NEXT: [[COPY27:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY27]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub6
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1200_1250-NEXT: $sgpr6 = COPY [[V_READFIRSTLANE_B32_6]]
- ; GFX1200_1250-NEXT: [[COPY28:%[0-9]+]]:vgpr_32 = COPY [[COPY12]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY28]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub7
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_7:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1200_1250-NEXT: $sgpr7 = COPY [[V_READFIRSTLANE_B32_7]]
- ; GFX1200_1250-NEXT: [[COPY29:%[0-9]+]]:vgpr_32 = COPY [[COPY13]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY29]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub8
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_8:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
; GFX1200_1250-NEXT: $sgpr8 = COPY [[V_READFIRSTLANE_B32_8]]
- ; GFX1200_1250-NEXT: [[COPY30:%[0-9]+]]:vgpr_32 = COPY [[COPY14]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY30]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub9
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_9:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
; GFX1200_1250-NEXT: $sgpr9 = COPY [[V_READFIRSTLANE_B32_9]]
- ; GFX1200_1250-NEXT: [[COPY31:%[0-9]+]]:vgpr_32 = COPY [[COPY15]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY31]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub10
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_10:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
; GFX1200_1250-NEXT: $sgpr10 = COPY [[V_READFIRSTLANE_B32_10]]
- ; GFX1200_1250-NEXT: [[COPY32:%[0-9]+]]:vgpr_32 = COPY [[COPY16]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY32]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub11
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_11:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
; GFX1200_1250-NEXT: $sgpr11 = COPY [[V_READFIRSTLANE_B32_11]]
- ; GFX1200_1250-NEXT: [[COPY33:%[0-9]+]]:vgpr_32 = COPY [[COPY17]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY33]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub12
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_12:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
; GFX1200_1250-NEXT: $sgpr12 = COPY [[V_READFIRSTLANE_B32_12]]
- ; GFX1200_1250-NEXT: [[COPY34:%[0-9]+]]:vgpr_32 = COPY [[COPY18]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY34]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub13
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_13:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
; GFX1200_1250-NEXT: $sgpr13 = COPY [[V_READFIRSTLANE_B32_13]]
- ; GFX1200_1250-NEXT: [[COPY35:%[0-9]+]]:vgpr_32 = COPY [[COPY19]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY35]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub14
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_14:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX1200_1250-NEXT: $sgpr14 = COPY [[V_READFIRSTLANE_B32_14]]
- ; GFX1200_1250-NEXT: [[COPY36:%[0-9]+]]:vgpr_32 = COPY [[COPY20]]
- ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY36]], implicit $exec
+ ; GFX1200_1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub15
+ ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_15:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX1200_1250-NEXT: $sgpr15 = COPY [[V_READFIRSTLANE_B32_15]]
; GFX1200_1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr4, implicit $sgpr5, implicit $sgpr6, implicit $sgpr7, implicit $sgpr8, implicit $sgpr9, implicit $sgpr10, implicit $sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15
%val = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %soffset, i32 0)
@@ -2262,7 +2143,6 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
- ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
; GFX6-NEXT: $vgpr0 = COPY [[COPY5]]
; GFX6-NEXT: $vgpr1 = COPY [[COPY6]]
; GFX6-NEXT: $vgpr2 = COPY [[COPY7]]
@@ -2283,7 +2163,6 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
- ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
; GFX7-NEXT: $vgpr0 = COPY [[COPY5]]
; GFX7-NEXT: $vgpr1 = COPY [[COPY6]]
; GFX7-NEXT: $vgpr2 = COPY [[COPY7]]
@@ -2304,7 +2183,6 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
- ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub3
; GFX8-NEXT: $vgpr0 = COPY [[COPY5]]
; GFX8-NEXT: $vgpr1 = COPY [[COPY6]]
; GFX8-NEXT: $vgpr2 = COPY [[COPY7]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
index 473b3ead9af839..272ae39681b586 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
@@ -593,13 +593,12 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s
; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0_sub1
- ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0
+ ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -623,13 +622,12 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s
; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0_sub1
- ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0
+ ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub1
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1200-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1200-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -653,13 +651,12 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s
; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; GFX1250-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0_sub1
- ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0
+ ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub1
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
@@ -793,8 +790,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY13]], %subreg.sub0, [[COPY14]], %subreg.sub1
; GFX8-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY11]], %subreg.sub0_sub1, [[COPY12]], %subreg.sub2_sub3
- ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0_sub1
+ ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
; GFX8-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX8-NEXT: {{ $}}
@@ -804,11 +800,11 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
; GFX8-NEXT: {{ $}}
; GFX8-NEXT: bb.5:
- ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub0
- ; GFX8-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub1
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX8-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0
+ ; GFX8-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -862,8 +858,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v
; GFX1200-NEXT: {{ $}}
; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY13]], %subreg.sub0, [[COPY14]], %subreg.sub1
; GFX1200-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY11]], %subreg.sub0_sub1, [[COPY12]], %subreg.sub2_sub3
- ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0_sub1
+ ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
; GFX1200-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX1200-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX1200-NEXT: {{ $}}
@@ -873,11 +868,11 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v
; GFX1200-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
; GFX1200-NEXT: {{ $}}
; GFX1200-NEXT: bb.5:
- ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub0
- ; GFX1200-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub1
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX1200-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0
+ ; GFX1200-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub1
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX1200-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX1200-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -931,8 +926,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY13]], %subreg.sub0, [[COPY14]], %subreg.sub1
; GFX1250-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY11]], %subreg.sub0_sub1, [[COPY12]], %subreg.sub2_sub3
- ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0_sub1
+ ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
; GFX1250-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX1250-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX1250-NEXT: {{ $}}
@@ -942,11 +936,11 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v
; GFX1250-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
; GFX1250-NEXT: {{ $}}
; GFX1250-NEXT: bb.5:
- ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub0
- ; GFX1250-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub1
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; GFX1250-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0
+ ; GFX1250-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub1
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; GFX1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; GFX1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.struct.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
@@ -1166,13 +1160,12 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s
; GFX8-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0_sub1
- ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX8-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0
+ ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub1
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX8-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX8-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX8-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -1196,13 +1189,12 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s
; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0_sub1
- ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0
+ ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub1
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX1200-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1200-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
;
@@ -1229,13 +1221,12 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s
; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY9]], [[COPY11]], 0, implicit $exec
; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[V_ADD_U32_e64_]], %subreg.sub1
; GFX1250-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8)
- ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0_sub1
- ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY12]].sub0
- ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY12]].sub1
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64), align 1, addrspace 8)
+ ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub0
+ ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN]].sub1
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX1250-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
+ ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
; GFX1250-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; GFX1250-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%voffset = add i32 %voffset.base, 4095
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
index 81a44835c2c1e2..f2f27bd0df4907 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
@@ -1178,15 +1178,13 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1
- ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub2_sub3
- ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vreg_64 = COPY [[COPY13]]
+ ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3
- ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY15]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x i32>) into %ir.data_addr, align 16, addrspace 1)
+ ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1)
; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1
@@ -1429,16 +1427,16 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr
; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3
; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec
- ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY13]], %subreg.sub0, [[COPY14]], %subreg.sub1
- ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]]
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
+ ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3
- ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY15]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x f32>) into %ir.data_addr, align 16, addrspace 1)
+ ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1)
; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0
; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440
; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
index b7676537812e75..9744bf72e5984b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
@@ -230,13 +230,12 @@ define amdgpu_ps double @struct_ptr_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cm
; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; CHECK-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64) on %ir.rsrc, align 1, addrspace 8)
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0_sub1
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64) on %ir.rsrc, align 1, addrspace 8)
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub1
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
@@ -324,8 +323,7 @@ define amdgpu_ps double @struct_ptr_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cm
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY13]], %subreg.sub0, [[COPY14]], %subreg.sub1
; CHECK-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY11]], %subreg.sub0_sub1, [[COPY12]], %subreg.sub2_sub3
- ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64) on %ir.rsrc, align 1, addrspace 8)
- ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0_sub1
+ ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE5]], [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 1, implicit $exec :: (volatile dereferenceable load store (s64) on %ir.rsrc, align 1, addrspace 8)
; CHECK-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; CHECK-NEXT: {{ $}}
@@ -335,11 +333,11 @@ define amdgpu_ps double @struct_ptr_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cm
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
- ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub0
- ; CHECK-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[COPY19]].sub1
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
+ ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0
+ ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub1
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_5:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_5]]
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY21]], implicit $exec
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_6:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_6]]
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%ret = call i64 @llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.i64(i64 %val, i64 %cmp, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
@@ -435,13 +433,12 @@ define amdgpu_ps double @struct_ptr_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cm
; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1
; CHECK-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
- ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64) on %ir.rsrc, align 1, addrspace 8)
- ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0_sub1
- ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub0
- ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY11]].sub1
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; CHECK-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (s64) on %ir.rsrc, align 1, addrspace 8)
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub0
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN]].sub1
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%voffset = add i32 %voffset.base, 4095
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
index 116719a6e3e7b9..b83b6366484a6d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/trunc-brc.ll
@@ -17,8 +17,11 @@ define amdgpu_ps void @s_trunc_i64_to_i32(ptr addrspace(1) inreg %src, ptr addrs
; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
- ; GFX-950-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (i64) from %ir.src, addrspace 1)
- ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0, debug-location !4
+ ; GFX-950-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (s64) from %ir.src, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD_SADDR [[V_MOV_B32_e32_]], [[COPY4]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (s32) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i64, ptr addrspace(1) %src
%trunc = trunc i64 %val to i32, !dbg !4
store i32 %trunc, ptr addrspace(1) %dst
@@ -62,7 +65,10 @@ define amdgpu_ps void @s_trunc_i96_to_i64(ptr addrspace(1) inreg %src, ptr addrs
; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[S_LOAD_DWORD_IMM]], %subreg.sub2
- ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub0_sub1, debug-location !4
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_]], [[COPY6]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (s64) into %ir.dst, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i96, ptr addrspace(1) %src
%trunc = trunc i96 %val to i64, !dbg !4
store i64 %trunc, ptr addrspace(1) %dst
@@ -101,8 +107,11 @@ define amdgpu_ps void @s_trunc_i128_to_i96(ptr addrspace(1) inreg %src, ptr addr
; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
- ; GFX-950-NEXT: early-clobber %9:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<4 x i32>) from %ir.src, align 8, addrspace 1)
- ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sgpr_96 = COPY %9.sub0_sub1_sub2, debug-location !4
+ ; GFX-950-NEXT: early-clobber %9:sgpr_128 = S_LOAD_DWORDX4_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<4 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_96_align2 = COPY %9.sub0_sub1_sub2
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[V_MOV_B32_e32_]], [[COPY4]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i128, ptr addrspace(1) %src
%trunc = trunc i128 %val to i96, !dbg !4
store i96 %trunc, ptr addrspace(1) %dst
@@ -148,7 +157,10 @@ define amdgpu_ps void @s_trunc_i160_to_i128(ptr addrspace(1) inreg %src, ptr add
; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY %10.sub2
; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY %10.sub3
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_160 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[S_LOAD_DWORD_IMM]], %subreg.sub4
- ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sgpr_128 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3, debug-location !4
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY8]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i160, ptr addrspace(1) %src
%trunc = trunc i160 %val to i128, !dbg !4
store i128 %trunc, ptr addrspace(1) %dst
@@ -202,7 +214,18 @@ define amdgpu_ps void @s_trunc_i192_to_i160(ptr addrspace(1) inreg %src, ptr add
; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub0
; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX2_IMM]].sub1
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_192 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[COPY8]], %subreg.sub4, [[COPY9]], %subreg.sub5
- ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sgpr_160 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4, debug-location !4
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE2]].sub0
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE2]].sub1
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE2]].sub2
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE2]].sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY10]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY12]], %subreg.sub2, [[COPY13]], %subreg.sub3
+ ; GFX-950-NEXT: [[COPY14:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY14]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub4
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD_SADDR [[V_MOV_B32_e32_1]], [[COPY15]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (s32) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i192, ptr addrspace(1) %src
%trunc = trunc i192 %val to i160, !dbg !4
store i160 %trunc, ptr addrspace(1) %dst
@@ -229,7 +252,15 @@ define void @v_trunc_i192_to_i160(ptr addrspace(1) %src, ptr addrspace(1) %dst)
; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_192_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[COPY8]], %subreg.sub4, [[COPY9]], %subreg.sub5
- ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vreg_160_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4, debug-location !4
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub0
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub1
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub2
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub3
+ ; GFX-950-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub4
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY10]], %subreg.sub0, [[COPY11]], %subreg.sub1, [[COPY12]], %subreg.sub2, [[COPY13]], %subreg.sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE1]], [[COPY14]], 16, 0, implicit $exec :: (store (s32) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
%val = load i192, ptr addrspace(1) %src
%trunc = trunc i192 %val to i160, !dbg !4
store i160 %trunc, ptr addrspace(1) %dst
@@ -259,7 +290,16 @@ define amdgpu_ps void @s_trunc_i224_to_i192(ptr addrspace(1) inreg %src, ptr add
; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY %16.sub2
; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY %16.sub3
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_224 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1, [[COPY8]], %subreg.sub2, [[COPY9]], %subreg.sub3, [[COPY4]], %subreg.sub4, [[COPY5]], %subreg.sub5, [[S_LOAD_DWORD_IMM]], %subreg.sub6
- ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sgpr_192 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4_sub5, debug-location !4
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub2_sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY10]], %subreg.sub0_sub1, [[COPY11]], %subreg.sub2_sub3
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY12]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE2]].sub4_sub5
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2_SADDR [[V_MOV_B32_e32_1]], [[COPY13]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (<2 x s32>) into %ir.dst + 16, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i224, ptr addrspace(1) %src
%trunc = trunc i224 %val to i192, !dbg !4
store i192 %trunc, ptr addrspace(1) %dst
@@ -287,7 +327,13 @@ define void @v_trunc_i224_to_i192(ptr addrspace(1) %src, ptr addrspace(1) %dst)
; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub1
; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX3_]].sub2
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_224_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3, [[COPY8]], %subreg.sub4, [[COPY9]], %subreg.sub5, [[COPY10]], %subreg.sub6
- ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vreg_192_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4_sub5, debug-location !4
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE2]].sub2_sub3
+ ; GFX-950-NEXT: [[COPY13:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE2]].sub4_sub5
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY11]], %subreg.sub0_sub1, [[COPY12]], %subreg.sub2_sub3
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY13]], 16, 0, implicit $exec :: (store (<2 x s32>) into %ir.dst + 16, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
%val = load i224, ptr addrspace(1) %src
%trunc = trunc i224 %val to i192, !dbg !4
store i192 %trunc, ptr addrspace(1) %dst
@@ -307,8 +353,23 @@ define amdgpu_ps void @s_trunc_i256_to_i224(ptr addrspace(1) inreg %src, ptr add
; GFX-950-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX-950-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GFX-950-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
- ; GFX-950-NEXT: early-clobber %20:sgpr_256 = S_LOAD_DWORDX8_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<8 x i32>) from %ir.src, align 8, addrspace 1)
- ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sgpr_224 = COPY %20.lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16, debug-location !4
+ ; GFX-950-NEXT: early-clobber %20:sgpr_256 = S_LOAD_DWORDX8_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<8 x s32>) from %ir.src, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY %20.sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY %20.sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY %20.sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY %20.sub3
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY %20.sub4
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY %20.sub5
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY %20.sub6
+ ; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2
+ ; GFX-950-NEXT: [[COPY11:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY11]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY12:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE3]]
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3_SADDR [[V_MOV_B32_e32_1]], [[COPY12]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i256, ptr addrspace(1) %src
%trunc = trunc i256 %val to i224, !dbg !4
store i224 %trunc, ptr addrspace(1) %dst
@@ -329,7 +390,18 @@ define void @v_trunc_i256_to_i224(ptr addrspace(1) %src, ptr addrspace(1) %dst)
; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec :: (load (<4 x i32>) from %ir.src, align 8, addrspace 1)
; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_1:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 16, 0, implicit $exec :: (load (<4 x i32>) from %ir.src + 16, align 8, addrspace 1)
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_256_align2 = REG_SEQUENCE [[GLOBAL_LOAD_DWORDX4_]], %subreg.sub0_sub1_sub2_sub3, [[GLOBAL_LOAD_DWORDX4_1]], %subreg.sub4_sub5_sub6_sub7
- ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_224_align2 = COPY [[REG_SEQUENCE2]].lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16, debug-location !4
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub0
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub1
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub2
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub3
+ ; GFX-950-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub4
+ ; GFX-950-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub5
+ ; GFX-950-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE2]].sub6
+ ; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
+ ; GFX-950-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE4]], 16, 0, implicit $exec :: (store (<3 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
%val = load i256, ptr addrspace(1) %src
%trunc = trunc i256 %val to i224, !dbg !4
store i224 %trunc, ptr addrspace(1) %dst
@@ -352,7 +424,19 @@ define amdgpu_ps void @s_trunc_i1024_to_i512(ptr addrspace(1) inreg %src, ptr ad
; GFX-950-NEXT: early-clobber %20:sgpr_512 = S_LOAD_DWORDX16_IMM_ec [[REG_SEQUENCE]], 0, 0 :: ("amdgpu-noclobber" load (<16 x i32>) from %ir.src, align 8, addrspace 1)
; GFX-950-NEXT: early-clobber %23:sgpr_512 = S_LOAD_DWORDX16_IMM_ec [[REG_SEQUENCE]], 64, 0 :: ("amdgpu-noclobber" load (<16 x i32>) from %ir.src + 64, align 8, addrspace 1)
; GFX-950-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_1024 = REG_SEQUENCE %20, %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, %23, %subreg.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
- ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:sgpr_512 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, debug-location !4
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], [[COPY4]], [[REG_SEQUENCE1]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]].sub4_sub5_sub6_sub7
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_1]], [[COPY5]], [[REG_SEQUENCE1]], 16, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]].sub8_sub9_sub10_sub11
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_2]], [[COPY6]], [[REG_SEQUENCE1]], 32, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 32, align 8, addrspace 1)
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE2]].sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_3]], [[COPY7]], [[REG_SEQUENCE1]], 48, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 48, align 8, addrspace 1)
+ ; GFX-950-NEXT: S_ENDPGM 0
%val = load i1024, ptr addrspace(1) %src
%trunc = trunc i1024 %val to i512, !dbg !4
store i512 %trunc, ptr addrspace(1) %dst
@@ -381,7 +465,15 @@ define void @v_trunc_i1024_to_i512(ptr addrspace(1) %src, ptr addrspace(1) %dst)
; GFX-950-NEXT: [[GLOBAL_LOAD_DWORDX4_7:%[0-9]+]]:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 112, 0, implicit $exec :: (load (<4 x i32>) from %ir.src + 112, align 8, addrspace 1)
; GFX-950-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_512_align2 = REG_SEQUENCE [[GLOBAL_LOAD_DWORDX4_4]], %subreg.sub0_sub1_sub2_sub3, [[GLOBAL_LOAD_DWORDX4_5]], %subreg.sub4_sub5_sub6_sub7, [[GLOBAL_LOAD_DWORDX4_6]], %subreg.sub8_sub9_sub10_sub11, [[GLOBAL_LOAD_DWORDX4_7]], %subreg.sub12_sub13_sub14_sub15
; GFX-950-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_1024_align2 = REG_SEQUENCE [[REG_SEQUENCE2]], %subreg.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, [[REG_SEQUENCE3]], %subreg.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
- ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_512_align2 = COPY [[REG_SEQUENCE4]].sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15, debug-location !4
+ ; GFX-950-NEXT: [[COPY4:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE4]].sub0_sub1_sub2_sub3
+ ; GFX-950-NEXT: [[COPY5:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE4]].sub4_sub5_sub6_sub7
+ ; GFX-950-NEXT: [[COPY6:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE4]].sub8_sub9_sub10_sub11
+ ; GFX-950-NEXT: [[COPY7:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE4]].sub12_sub13_sub14_sub15
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY4]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY5]], 16, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 16, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY6]], 32, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 32, align 8, addrspace 1)
+ ; GFX-950-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY7]], 48, 0, implicit $exec :: (store (<4 x s32>) into %ir.dst + 48, align 8, addrspace 1)
+ ; GFX-950-NEXT: SI_RETURN
%val = load i1024, ptr addrspace(1) %src
%trunc = trunc i1024 %val to i512, !dbg !4
store i512 %trunc, ptr addrspace(1) %dst
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 5ff48c8c20c3e5..804c9785697d16 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -1387,49 +1387,45 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v6
-; GFX9-G-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v7
+; GFX9-G-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13_vgpr14_vgpr15 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v0
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, v0
; GFX9-G-O0-NEXT: s_mov_b64 s[8:9], 0
; GFX9-G-O0-NEXT: ; implicit-def: $vgpr31 : SGPR spill to VGPR lane
; GFX9-G-O0-NEXT: v_writelane_b32 v31, s8, 0
; GFX9-G-O0-NEXT: v_writelane_b32 v31, s9, 1
; GFX9-G-O0-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v7
+; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v11, v0, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v7
; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v11, v2, v7
-; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v9, v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v14
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v15
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v10, v2, v7
-; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
+; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v10, v0, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v15
+; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v8, v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v5
; GFX9-G-O0-NEXT: v_xor_b32_e64 v0, v11, v0
; GFX9-G-O0-NEXT: v_xor_b32_e64 v1, v11, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v7
; GFX9-G-O0-NEXT: v_xor_b32_e64 v3, v9, v3
; GFX9-G-O0-NEXT: v_xor_b32_e64 v2, v9, v2
; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v0, s[4:5], v0, v11
@@ -1440,16 +1436,12 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v2, s[4:5], v2, v9, s[4:5]
; GFX9-G-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v13
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v14
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, v15
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v12
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v13
; GFX9-G-O0-NEXT: v_xor_b32_e64 v7, v10, v5
; GFX9-G-O0-NEXT: v_xor_b32_e64 v5, v10, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v13
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v14
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v15
; GFX9-G-O0-NEXT: v_xor_b32_e64 v6, v8, v6
; GFX9-G-O0-NEXT: v_xor_b32_e64 v3, v8, v3
; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v7, s[4:5], v7, v10
@@ -1655,23 +1647,23 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_branch .LBB0_8
; GFX9-G-O0-NEXT: .LBB0_3: ; %udiv-loop-exit
-; GFX9-G-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(2)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v12
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v13
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v14
; GFX9-G-O0-NEXT: s_mov_b32 s4, 1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
-; GFX9-G-O0-NEXT: v_lshlrev_b64 v[9:10], v0, v[2:3]
+; GFX9-G-O0-NEXT: v_lshlrev_b64 v[11:12], v0, v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[4:5]
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
@@ -1680,20 +1672,16 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v5, v2, v3
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v11
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v13
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v14
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v9
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v10
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v6
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v1, v2
; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v7
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v10
; GFX9-G-O0-NEXT: v_or3_b32 v4, v4, v5, v6
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v2, v3
; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
@@ -1745,10 +1733,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-G-O0-NEXT: v_readlane_b32 s6, v31, 8
; GFX9-G-O0-NEXT: v_readlane_b32 s7, v31, 9
-; GFX9-G-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
@@ -1757,10 +1745,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
@@ -1789,43 +1777,40 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
; GFX9-G-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $vgpr4_vgpr5 killed $exec
; GFX9-G-O0-NEXT: v_or_b32_e64 v7, v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v24
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v25
-; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v30
+; GFX9-G-O0-NEXT: s_mov_b32 s11, 31
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s11
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v1, v0, v1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v3
; GFX9-G-O0-NEXT: v_or_b32_e64 v4, v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v22
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v23
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v24
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, v25
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s11
-; GFX9-G-O0-NEXT: v_lshlrev_b64 v[25:26], v0, v[2:3]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v27
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v28
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v29
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, v30
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-G-O0-NEXT: v_lshlrev_b64 v[27:28], v0, v[2:3]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[14:15]
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s10
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v15, v2, v3
; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(11)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v23
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(10)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v27
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v24
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v22, v27
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v28
-; GFX9-G-O0-NEXT: s_waitcnt vmcnt(8)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v23, v29
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v24, v30
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v22, v25
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v26
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v22
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v1, v2
; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v22, v23
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v24
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(9)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v22, v25
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(8)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v26
; GFX9-G-O0-NEXT: v_or3_b32 v14, v14, v15, v22
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v2, v3
; GFX9-G-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec
@@ -2181,18 +2166,16 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(3)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v8
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(2)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v9
-; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v11
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v9
; GFX9-G-O0-NEXT: v_xor_b32_e64 v0, v0, v7
; GFX9-G-O0-NEXT: v_xor_b32_e64 v1, v1, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v9
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(1)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v10
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v11
; GFX9-G-O0-NEXT: v_xor_b32_e64 v2, v2, v5
; GFX9-G-O0-NEXT: v_xor_b32_e64 v3, v3, v4
; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v0, s[4:5], v0, v7
@@ -3419,7 +3402,7 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0: ; %bb.0: ; %_udiv-special-cases
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-G-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GFX9-G-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v2
@@ -3433,157 +3416,156 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v4
-; GFX9-G-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9_vgpr10_vgpr11 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v7
-; GFX9-G-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v4
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v7
+; GFX9-G-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v0
+; GFX9-G-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_nop 0
-; GFX9-G-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 s[8:9], 0
-; GFX9-G-O0-NEXT: ; implicit-def: $vgpr32 : SGPR spill to VGPR lane
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s8, 0
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s9, 1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v9
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, v11
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v13
-; GFX9-G-O0-NEXT: v_or_b32_e64 v4, v4, v7
-; GFX9-G-O0-NEXT: v_or_b32_e64 v6, v5, v6
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s9
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[4:5], v[4:5], v[6:7]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v0
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v13
-; GFX9-G-O0-NEXT: v_or_b32_e64 v4, v4, v7
-; GFX9-G-O0-NEXT: v_or_b32_e64 v6, v5, v6
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s9
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[4:5], v[6:7]
+; GFX9-G-O0-NEXT: ; implicit-def: $vgpr30 : SGPR spill to VGPR lane
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s8, 0
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s9, 1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v3
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v4
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v5
+; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v11
+; GFX9-G-O0-NEXT: v_or_b32_e64 v10, v1, v10
+; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s8
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[4:5], v[0:1], v[10:11]
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(7)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v6
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(6)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v7
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(5)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v8
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(4)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v9
+; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v11
+; GFX9-G-O0-NEXT: v_or_b32_e64 v10, v1, v10
+; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s8
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[0:1], v[10:11]
; GFX9-G-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v11
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, s9
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[9:10], v[4:5]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v7
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v4, v4
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v5, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, 32
-; GFX9-G-O0-NEXT: v_add_u32_e64 v5, v5, v8
-; GFX9-G-O0-NEXT: v_min_u32_e64 v4, v4, v5
-; GFX9-G-O0-NEXT: s_mov_b32 s11, 64
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, s11
-; GFX9-G-O0-NEXT: v_add_u32_e64 v5, v4, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v9
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v10
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v4, v4
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v6, v6
-; GFX9-G-O0-NEXT: v_add_u32_e64 v6, v6, v8
-; GFX9-G-O0-NEXT: v_min_u32_e64 v4, v4, v6
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[6:7]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v4
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, s9
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[10:11], v[0:1]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v3
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v0, v0
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v1, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, 32
+; GFX9-G-O0-NEXT: v_add_u32_e64 v1, v1, v4
+; GFX9-G-O0-NEXT: v_min_u32_e64 v0, v0, v1
+; GFX9-G-O0-NEXT: s_mov_b32 s10, 64
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, s10
+; GFX9-G-O0-NEXT: v_add_u32_e64 v1, v0, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v11
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v0, v0
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v2, v2
+; GFX9-G-O0-NEXT: v_add_u32_e64 v2, v2, v4
+; GFX9-G-O0-NEXT: v_min_u32_e64 v0, v0, v2
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[6:7]
+; GFX9-G-O0-NEXT: s_mov_b32 s14, 0
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, s8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s9
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[10:11], v[1:2]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v7
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v1, v1
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v2, v2
+; GFX9-G-O0-NEXT: v_add_u32_e64 v2, v2, v4
+; GFX9-G-O0-NEXT: v_min_u32_e64 v1, v1, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s10
+; GFX9-G-O0-NEXT: v_add_u32_e64 v2, v1, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v11
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v1, v1
+; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v3, v3
+; GFX9-G-O0-NEXT: v_add_u32_e64 v3, v3, v4
+; GFX9-G-O0-NEXT: v_min_u32_e64 v1, v1, v3
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[6:7]
+; GFX9-G-O0-NEXT: s_mov_b32 s13, 0
+; GFX9-G-O0-NEXT: s_mov_b32 s11, 0
+; GFX9-G-O0-NEXT: s_mov_b32 s12, 0
; GFX9-G-O0-NEXT: s_mov_b32 s10, 0
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v0
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, s8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s9
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[9:10], v[5:6]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v11
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v12
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v5, v5
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v6, v6
-; GFX9-G-O0-NEXT: v_add_u32_e64 v6, v6, v8
-; GFX9-G-O0-NEXT: v_min_u32_e64 v5, v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s11
-; GFX9-G-O0-NEXT: v_add_u32_e64 v6, v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v9
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v10
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v5, v5
-; GFX9-G-O0-NEXT: v_ffbh_u32_e64 v7, v7
-; GFX9-G-O0-NEXT: v_add_u32_e64 v7, v7, v8
-; GFX9-G-O0-NEXT: v_min_u32_e64 v5, v5, v7
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[6:7]
-; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v4, s[6:7], v4, v5
-; GFX9-G-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, s10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s10
-; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v5, s[6:7], v5, v6, s[6:7]
-; GFX9-G-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s10
-; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v7, s[6:7], v6, v7, s[6:7]
-; GFX9-G-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v6, s[6:7], v6, v8, s[6:7]
-; GFX9-G-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v0, s[6:7], v0, v1
+; GFX9-G-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, s14
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s14
+; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v1, s[6:7], v1, v2, s[6:7]
+; GFX9-G-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s13
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, s12
+; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v3, s[6:7], v2, v3, s[6:7]
+; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s10
+; GFX9-G-O0-NEXT: v_subb_co_u32_e64 v2, s[6:7], v2, v4, s[6:7]
+; GFX9-G-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 s[6:7], 0x7f
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v7
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v0
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v3
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, s7
; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, s6
; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[14:15], v[10:11], v[12:13]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s9
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s8
-; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[12:13], v[8:9], v[10:11]
+; GFX9-G-O0-NEXT: v_cmp_gt_u64_e64 s[12:13], v[4:5], v[10:11]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s9
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s8
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[10:11], v[8:9], v[10:11]
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[10:11], v[4:5], v[10:11]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, 1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, 0
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v11, v9, v10, s[14:15]
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[12:13]
-; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v8, v8, v11, s[10:11]
-; GFX9-G-O0-NEXT: v_and_b32_e64 v8, v8, v10
-; GFX9-G-O0-NEXT: v_cmp_ne_u16_e64 s[10:11], v8, v9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v11, v5, v10, s[14:15]
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v4, v5, v10, s[12:13]
+; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v4, v4, v11, s[10:11]
+; GFX9-G-O0-NEXT: v_and_b32_e64 v4, v4, v10
+; GFX9-G-O0-NEXT: v_cmp_ne_u16_e64 s[10:11], v4, v5
; GFX9-G-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, s7
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, s6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v11
-; GFX9-G-O0-NEXT: v_xor_b32_e64 v4, v4, v9
-; GFX9-G-O0-NEXT: v_xor_b32_e64 v5, v5, v8
-; GFX9-G-O0-NEXT: v_or_b32_e64 v4, v4, v7
-; GFX9-G-O0-NEXT: v_or_b32_e64 v6, v5, v6
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, s8
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, s9
-; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[4:5], v[6:7]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v0
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v10
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v11
+; GFX9-G-O0-NEXT: v_xor_b32_e64 v0, v0, v5
+; GFX9-G-O0-NEXT: v_xor_b32_e64 v1, v1, v4
+; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v3
+; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v1, v2
+; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, s9
+; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[6:7], v[0:1], v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s8
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, s9
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v6
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v7
; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5]
; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]
; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
@@ -3592,8 +3574,8 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, s9
; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v2
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v9
; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[4:5]
; GFX9-G-O0-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
@@ -3610,10 +3592,10 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 s[4:5], exec
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s4, 2
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s5, 3
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s4, 2
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s5, 3
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[4:5]
@@ -3621,11 +3603,11 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_branch .LBB1_7
; GFX9-G-O0-NEXT: .LBB1_1: ; %Flow
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_readlane_b32 s4, v32, 4
-; GFX9-G-O0-NEXT: v_readlane_b32 s5, v32, 5
+; GFX9-G-O0-NEXT: v_readlane_b32 s4, v30, 4
+; GFX9-G-O0-NEXT: v_readlane_b32 s5, v30, 5
; GFX9-G-O0-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-G-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -3651,11 +3633,11 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_branch .LBB1_4
; GFX9-G-O0-NEXT: .LBB1_2: ; %Flow2
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_readlane_b32 s4, v32, 2
-; GFX9-G-O0-NEXT: v_readlane_b32 s5, v32, 3
+; GFX9-G-O0-NEXT: v_readlane_b32 s4, v30, 2
+; GFX9-G-O0-NEXT: v_readlane_b32 s5, v30, 3
; GFX9-G-O0-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-G-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
@@ -3671,23 +3653,23 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_branch .LBB1_8
; GFX9-G-O0-NEXT: .LBB1_3: ; %udiv-loop-exit
-; GFX9-G-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(2)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v4
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v12
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v6
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v13
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v14
; GFX9-G-O0-NEXT: s_mov_b32 s4, 1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
-; GFX9-G-O0-NEXT: v_lshlrev_b64 v[9:10], v0, v[2:3]
+; GFX9-G-O0-NEXT: v_lshlrev_b64 v[11:12], v0, v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[4:5]
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
@@ -3696,20 +3678,16 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v5, v2, v3
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v7
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v11
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v12
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v13
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v14
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v9
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v10
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v6
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v1, v2
; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v7
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v8
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v9
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v10
; GFX9-G-O0-NEXT: v_or3_b32 v4, v4, v5, v6
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v2, v3
; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec
@@ -3725,11 +3703,11 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_branch .LBB1_2
; GFX9-G-O0-NEXT: .LBB1_4: ; %Flow1
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_readlane_b32 s4, v32, 6
-; GFX9-G-O0-NEXT: v_readlane_b32 s5, v32, 7
+; GFX9-G-O0-NEXT: v_readlane_b32 s4, v30, 6
+; GFX9-G-O0-NEXT: v_readlane_b32 s5, v30, 7
; GFX9-G-O0-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-G-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
@@ -3756,11 +3734,11 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: .LBB1_5: ; %udiv-do-while
; GFX9-G-O0-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-G-O0-NEXT: v_readlane_b32 s6, v32, 8
-; GFX9-G-O0-NEXT: v_readlane_b32 s7, v32, 9
+; GFX9-G-O0-NEXT: v_readlane_b32 s6, v30, 8
+; GFX9-G-O0-NEXT: v_readlane_b32 s7, v30, 9
; GFX9-G-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -3773,14 +3751,14 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GFX9-G-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
@@ -3791,13 +3769,13 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v3
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(16)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v21, v5
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v20, v4
-; GFX9-G-O0-NEXT: s_mov_b32 s11, 1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v29, v5
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v28, v4
+; GFX9-G-O0-NEXT: s_mov_b32 s10, 1
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s10
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[2:3], v2, v[0:1]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s11
-; GFX9-G-O0-NEXT: v_lshlrev_b64 v[4:5], v4, v[20:21]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s10
+; GFX9-G-O0-NEXT: v_lshlrev_b64 v[4:5], v4, v[28:29]
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s10, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
@@ -3805,10 +3783,9 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
; GFX9-G-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $vgpr4_vgpr5 killed $exec
; GFX9-G-O0-NEXT: v_or_b32_e64 v7, v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v14
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v15
-; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-G-O0-NEXT: s_mov_b32 s11, 31
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s11
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v1, v0, v1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v3
@@ -3817,31 +3794,29 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v13
; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v14
; GFX9-G-O0-NEXT: v_mov_b32_e32 v13, v15
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s11
-; GFX9-G-O0-NEXT: v_lshlrev_b64 v[22:23], v0, v[2:3]
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s11
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-G-O0-NEXT: v_lshlrev_b64 v[28:29], v0, v[2:3]
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s10
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[12:13]
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s10
; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v13, v2, v3
; GFX9-G-O0-NEXT: v_mov_b32_e32 v12, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(11)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v24
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(10)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v28
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v25
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v28
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v29
-; GFX9-G-O0-NEXT: s_waitcnt vmcnt(8)
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v20, v30
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v21, v31
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v1
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v22
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v23
; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v14
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v1, v2
; GFX9-G-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v2
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v20
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v21
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(9)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, v26
+; GFX9-G-O0-NEXT: s_waitcnt vmcnt(8)
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v27
; GFX9-G-O0-NEXT: v_or3_b32 v12, v12, v13, v14
; GFX9-G-O0-NEXT: v_or_b32_e64 v2, v2, v3
; GFX9-G-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec
@@ -3880,16 +3855,12 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v22, v24
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v23, v25
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v20, v26
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v21, v27
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v22
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v23
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v20
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v21
; GFX9-G-O0-NEXT: v_and_b32_e64 v11, v8, v11
; GFX9-G-O0-NEXT: v_and_b32_e64 v10, v8, v10
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v20
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v20, v21
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v8, v22
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v20, v23
; GFX9-G-O0-NEXT: v_and_b32_e64 v8, v6, v8
; GFX9-G-O0-NEXT: v_and_b32_e64 v6, v6, v20
; GFX9-G-O0-NEXT: v_sub_co_u32_e64 v4, s[8:9], v4, v11
@@ -3925,13 +3896,13 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v18, s4
; GFX9-G-O0-NEXT: v_cmp_eq_u64_e64 s[4:5], v[16:17], v[18:19]
; GFX9-G-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s4, 4
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s5, 5
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s4, 4
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s5, 5
; GFX9-G-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s6, 8
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s7, 9
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s6, 8
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s7, 9
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_nop 0
@@ -3958,7 +3929,7 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_branch .LBB1_1
; GFX9-G-O0-NEXT: .LBB1_6: ; %udiv-preheader
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -4048,10 +4019,10 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 s[4:5], s[8:9]
; GFX9-G-O0-NEXT: s_mov_b64 s[6:7], s[8:9]
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s8, 8
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s9, 9
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s8, 8
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s9, 9
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, s7
; GFX9-G-O0-NEXT: v_mov_b32_e32 v14, s6
@@ -4080,7 +4051,7 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_branch .LBB1_5
; GFX9-G-O0-NEXT: .LBB1_7: ; %udiv-bb1
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
@@ -4193,10 +4164,10 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_mov_b64 s[6:7], exec
; GFX9-G-O0-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
; GFX9-G-O0-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s6, 6
-; GFX9-G-O0-NEXT: v_writelane_b32 v32, s7, 7
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s6, 6
+; GFX9-G-O0-NEXT: v_writelane_b32 v30, s7, 7
; GFX9-G-O0-NEXT: s_or_saveexec_b64 s[18:19], -1
-; GFX9-G-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
+; GFX9-G-O0-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[18:19]
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-G-O0-NEXT: s_cbranch_execz .LBB1_4
@@ -4215,7 +4186,7 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, v6
; GFX9-G-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GFX9-G-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; GFX9-G-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-G-O0-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-G-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4321,11 +4292,9 @@ define i128 @v_sdiv_i128_v_pow2k(i128 %lhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v3
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v10
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v11
-; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
-; GFX9-G-O0-NEXT: s_mov_b32 s5, 31
-; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
+; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v0, v0, v1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v0
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
index 3a2f21b7dc79fa..6b632b64a2a75b 100644
--- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -2132,9 +2132,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_cndmask_b32_e64 v32, v10, 0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v18, v8, 0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v19, v9, 0, s[4:5]
-; GISEL-NEXT: s_xor_b64 s[8:9], s[6:7], s[10:11]
-; GISEL-NEXT: v_cndmask_b32_e64 v33, v11, 0, s[4:5]
-; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
+; GISEL-NEXT: s_or_b64 s[6:7], s[4:5], vcc
+; GISEL-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
+; GISEL-NEXT: v_cndmask_b32_e64 v33, v17, 0, s[4:5]
+; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[6:7]
; GISEL-NEXT: s_cbranch_execz .LBB4_6
; GISEL-NEXT: ; %bb.1: ; %udiv-bb15
; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v0
@@ -2240,23 +2241,17 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: s_cbranch_execnz .LBB4_3
; GISEL-NEXT: ; %bb.4: ; %Flow13
; GISEL-NEXT: s_or_b64 exec, exec, s[8:9]
-; GISEL-NEXT: .LBB4_5: ; %Flow14
-; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
-; GISEL-NEXT: v_lshl_b64 v[2:3], v[19:20], 1
-; GISEL-NEXT: v_lshl_b64 v[18:19], v[21:22], 1
-; GISEL-NEXT: v_lshrrev_b32_e32 v20, 31, v20
+; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1
+; GISEL-NEXT: v_lshl_b64 v[18:19], v[18:19], 1
+; GISEL-NEXT: v_lshrrev_b32_e32 v20, 31, v21
; GISEL-NEXT: v_or_b32_e32 v18, v18, v20
-; GISEL-NEXT: v_or_b32_e32 v32, v0, v2
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
; GISEL-NEXT: v_or_b32_e32 v33, v1, v3
; GISEL-NEXT: .LBB4_6: ; %Flow16
-; GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GISEL-NEXT: v_ashrrev_i32_e32 v28, 31, v7
-; GISEL-NEXT: v_xor_b32_e32 v1, v4, v28
-; GISEL-NEXT: v_xor_b32_e32 v2, v5, v28
-; GISEL-NEXT: v_xor_b32_e32 v3, v6, v28
-; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v1, v28
-; GISEL-NEXT: v_xor_b32_e32 v5, v7, v28
-; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v2, v28, vcc
+; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
+; GISEL-NEXT: s_mov_b64 s[10:11], exec
+; GISEL-NEXT: s_mov_b64 s[8:9], 0
+; GISEL-NEXT: v_ashrrev_i32_e32 v32, 31, v7
; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v15
; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v3, v28, vcc
; GISEL-NEXT: v_xor_b32_e32 v12, v12, v0
@@ -2301,30 +2296,75 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_mov_b32_e32 v2, 0x7f
; GISEL-NEXT: v_mov_b32_e32 v3, 0
-; GISEL-NEXT: v_subb_u32_e64 v14, s[4:5], 0, 0, s[4:5]
-; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3]
-; GISEL-NEXT: v_subb_u32_e64 v15, s[4:5], 0, 0, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[14:15]
-; GISEL-NEXT: s_mov_b64 s[6:7], exec
-; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
-; GISEL-NEXT: s_mov_b64 s[8:9], 0
-; GISEL-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GISEL-NEXT: v_and_b32_e32 v2, 1, v2
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT: v_xor_b32_e32 v2, 0x7f, v0
-; GISEL-NEXT: v_or_b32_e32 v2, v2, v14
-; GISEL-NEXT: v_or_b32_e32 v3, v1, v15
-; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3]
-; GISEL-NEXT: s_or_b64 s[10:11], s[10:11], vcc
-; GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v20, v6, 0, s[10:11]
-; GISEL-NEXT: v_cndmask_b32_e64 v21, v7, 0, s[10:11]
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[10:11]
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, 0, s[10:11]
-; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
-; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
+; GISEL-NEXT: v_xor_b32_e32 v1, v4, v32
+; GISEL-NEXT: v_xor_b32_e32 v4, v5, v32
+; GISEL-NEXT: v_xor_b32_e32 v5, v6, v32
+; GISEL-NEXT: v_xor_b32_e32 v7, v7, v32
+; GISEL-NEXT: v_xor_b32_e32 v6, v12, v0
+; GISEL-NEXT: v_xor_b32_e32 v20, v13, v0
+; GISEL-NEXT: v_xor_b32_e32 v14, v14, v0
+; GISEL-NEXT: v_xor_b32_e32 v15, v15, v0
+; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v1, v32
+; GISEL-NEXT: v_subb_u32_e32 v13, vcc, v4, v32, vcc
+; GISEL-NEXT: v_sub_i32_e64 v35, s[4:5], v6, v0
+; GISEL-NEXT: v_subb_u32_e64 v34, s[4:5], v20, v0, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v5, v32, vcc
+; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v32, vcc
+; GISEL-NEXT: v_subb_u32_e64 v4, vcc, v14, v0, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v15, v0, vcc
+; GISEL-NEXT: v_ffbh_u32_e32 v20, v34
+; GISEL-NEXT: v_ffbh_u32_e32 v21, v35
+; GISEL-NEXT: v_ffbh_u32_e32 v22, v13
+; GISEL-NEXT: v_ffbh_u32_e32 v23, v12
+; GISEL-NEXT: v_or_b32_e32 v0, v35, v4
+; GISEL-NEXT: v_or_b32_e32 v1, v34, v5
+; GISEL-NEXT: v_or_b32_e32 v14, v12, v6
+; GISEL-NEXT: v_or_b32_e32 v15, v13, v7
+; GISEL-NEXT: v_add_i32_e32 v21, vcc, 32, v21
+; GISEL-NEXT: v_ffbh_u32_e32 v24, v5
+; GISEL-NEXT: v_ffbh_u32_e32 v25, v4
+; GISEL-NEXT: v_add_i32_e32 v23, vcc, 32, v23
+; GISEL-NEXT: v_ffbh_u32_e32 v26, v7
+; GISEL-NEXT: v_ffbh_u32_e32 v27, v6
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[14:15]
+; GISEL-NEXT: v_min_u32_e32 v0, v20, v21
+; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v25
+; GISEL-NEXT: v_min_u32_e32 v14, v22, v23
+; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], 32, v27
+; GISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v0
+; GISEL-NEXT: v_min_u32_e32 v1, v24, v1
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, 64, v14
+; GISEL-NEXT: v_min_u32_e32 v15, v26, v15
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v15, v14, vcc
+; GISEL-NEXT: v_sub_i32_e32 v14, vcc, v0, v1
+; GISEL-NEXT: v_subb_u32_e64 v15, s[4:5], 0, 0, vcc
+; GISEL-NEXT: v_subb_u32_e64 v0, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[14:15], v[2:3]
+; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
+; GISEL-NEXT: v_xor_b32_e32 v2, 0x7f, v14
+; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc
+; GISEL-NEXT: v_or_b32_e32 v2, v2, v0
+; GISEL-NEXT: v_or_b32_e32 v3, v15, v1
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GISEL-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc
+; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
+; GISEL-NEXT: v_and_b32_e32 v2, 1, v20
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v2
+; GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v20, v12, 0, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v21, v13, 0, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v7, 0, s[4:5]
+; GISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
+; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[10:11]
+; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5]
; GISEL-NEXT: s_cbranch_execz .LBB4_12
; GISEL-NEXT: ; %bb.7: ; %udiv-bb1
; GISEL-NEXT: v_add_i32_e32 v36, vcc, 1, v0
@@ -2439,55 +2479,55 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_or_b32_e32 v20, v0, v22
; GISEL-NEXT: v_or_b32_e32 v21, v1, v23
; GISEL-NEXT: .LBB4_12: ; %Flow12
-; GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v31, v18, 0
-; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v31, v32, 0
-; GISEL-NEXT: v_mul_lo_u32 v36, v30, v18
-; GISEL-NEXT: v_mul_lo_u32 v3, v35, v3
-; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v30, v33, v[0:1]
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v35, v2, 0
-; GISEL-NEXT: v_mul_lo_u32 v2, v34, v2
-; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v32, v[14:15]
-; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v35, v20, 0
-; GISEL-NEXT: v_mad_u64_u32 v[26:27], vcc, v31, v33, v[23:24]
-; GISEL-NEXT: v_mul_lo_u32 v23, v31, v19
-; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v34, v21, v[0:1]
-; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v30, v32, v[26:27]
-; GISEL-NEXT: v_addc_u32_e64 v23, s[4:5], v25, v23, s[4:5]
-; GISEL-NEXT: v_addc_u32_e32 v23, vcc, v23, v36, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v33, v[23:24]
-; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v10, v22
-; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v11, v0, vcc
-; GISEL-NEXT: v_xor_b32_e32 v22, v10, v29
-; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v17, v32, v[24:25]
-; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v12, v20, v[18:19]
-; GISEL-NEXT: v_xor_b32_e32 v23, v0, v29
-; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v8, v1, vcc
-; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v9, v10, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[8:9], vcc, v35, v21, v[15:16]
-; GISEL-NEXT: v_xor_b32_e32 v18, v0, v29
-; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v22, v29
-; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v34, v20, v[8:9]
-; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], v17, v3, s[6:7]
-; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v2, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v12, v21, v[2:3]
-; GISEL-NEXT: v_xor_b32_e32 v19, v1, v29
-; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v23, v29, s[4:5]
-; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v18, v29, s[4:5]
-; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v19, v29, vcc
-; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v13, v20, v[8:9]
-; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v14
-; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v10, vcc
-; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v4, v11, vcc
-; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v15, vcc
-; GISEL-NEXT: v_xor_b32_e32 v6, v6, v28
-; GISEL-NEXT: v_xor_b32_e32 v7, v7, v28
-; GISEL-NEXT: v_xor_b32_e32 v8, v4, v28
-; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v6, v28
-; GISEL-NEXT: v_xor_b32_e32 v9, v5, v28
-; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v7, v28, vcc
-; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v8, v28, vcc
-; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v9, v28, vcc
+; GISEL-NEXT: s_or_b64 exec, exec, s[12:13]
+; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v30, v31, 0
+; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v30, v18, 0
+; GISEL-NEXT: v_mul_lo_u32 v26, v30, v19
+; GISEL-NEXT: v_mul_lo_u32 v27, v29, v18
+; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v35, v20, 0
+; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v35, v2, 0
+; GISEL-NEXT: v_mul_lo_u32 v36, v35, v3
+; GISEL-NEXT: v_mul_lo_u32 v37, v34, v2
+; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v29, v33, v[14:15]
+; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v34, v21, v[18:19]
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v10, v31, v[24:25]
+; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v4, v20, v[14:15]
+; GISEL-NEXT: v_mad_u64_u32 v[14:15], vcc, v30, v33, v[1:2]
+; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v35, v21, v[23:24]
+; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[6:7], v29, v31, v[14:15]
+; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], v3, v26, s[6:7]
+; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[6:7], v34, v20, v[1:2]
+; GISEL-NEXT: v_addc_u32_e64 v2, s[6:7], v25, v36, s[6:7]
+; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v3, v27, vcc
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v16, v0
+; GISEL-NEXT: v_subb_u32_e32 v16, vcc, v17, v18, vcc
+; GISEL-NEXT: v_xor_b32_e32 v18, v0, v28
+; GISEL-NEXT: v_addc_u32_e64 v0, s[4:5], v2, v37, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v12, v22
+; GISEL-NEXT: v_subb_u32_e64 v14, s[4:5], v13, v14, s[4:5]
+; GISEL-NEXT: v_xor_b32_e32 v22, v2, v32
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v10, v33, v[1:2]
+; GISEL-NEXT: v_xor_b32_e32 v1, v16, v28
+; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v4, v21, v[0:1]
+; GISEL-NEXT: v_xor_b32_e32 v10, v14, v32
+; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[6:7], v11, v31, v[2:3]
+; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], v18, v28
+; GISEL-NEXT: v_subb_u32_e64 v1, s[6:7], v1, v28, s[6:7]
+; GISEL-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v5, v20, v[12:13]
+; GISEL-NEXT: v_sub_i32_e64 v4, s[8:9], v22, v32
+; GISEL-NEXT: v_subb_u32_e64 v5, s[8:9], v10, v32, s[8:9]
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v8, v19, vcc
+; GISEL-NEXT: v_subb_u32_e32 v8, vcc, v9, v16, vcc
+; GISEL-NEXT: v_xor_b32_e32 v3, v3, v28
+; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v15, s[4:5]
+; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v7, v2, vcc
+; GISEL-NEXT: v_xor_b32_e32 v6, v6, v32
+; GISEL-NEXT: v_xor_b32_e32 v7, v8, v28
+; GISEL-NEXT: v_xor_b32_e32 v8, v2, v32
+; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v3, v28, s[6:7]
+; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v7, v28, vcc
+; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v32, s[8:9]
+; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v8, v32, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31]
%shl = srem <2 x i128> %lhs, %rhs
ret <2 x i128> %shl
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
index 04b69cc223ca96..32ab05bf072aaa 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll
@@ -34,9 +34,8 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: chain_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -66,9 +65,8 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: chain_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -160,9 +158,8 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: cs_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -192,9 +189,8 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: cs_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -286,9 +282,8 @@ define amdgpu_es void @es_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: es_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -318,9 +313,8 @@ define amdgpu_es void @es_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: es_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -412,9 +406,8 @@ define amdgpu_gs void @gs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: gs_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -444,9 +437,8 @@ define amdgpu_gs void @gs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: gs_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -538,9 +530,8 @@ define amdgpu_hs void @hs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: hs_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -570,9 +561,8 @@ define amdgpu_hs void @hs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: hs_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -664,9 +654,8 @@ define amdgpu_ls void @ls_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: ls_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -696,9 +685,8 @@ define amdgpu_ls void @ls_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: ls_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -790,9 +778,8 @@ define amdgpu_vs void @vs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: vs_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -822,9 +809,8 @@ define amdgpu_vs void @vs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: vs_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -916,9 +902,8 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: chain_to_chain_preserve
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -948,9 +933,8 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: chain_to_chain_preserve
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -1042,9 +1026,8 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: cs_to_chain_preserve
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -1074,9 +1057,8 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: cs_to_chain_preserve
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -1402,9 +1384,8 @@ define amdgpu_cs_chain void @non_imm_exec(i32 inreg %exec, <3 x i32> inreg %sgpr
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY7]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: non_imm_exec
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -1435,9 +1416,8 @@ define amdgpu_cs_chain void @non_imm_exec(i32 inreg %exec, <3 x i32> inreg %sgpr
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY11]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY12]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: non_imm_exec
; DAGISEL-GFX11: bb.0 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
index 66c5d7b7552696..f4288063d9f2c9 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll
@@ -34,9 +34,8 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: chain_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -66,9 +65,8 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: chain_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -160,9 +158,8 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: cs_to_chain
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -192,9 +189,8 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: cs_to_chain
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -286,9 +282,8 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: chain_to_chain_preserve
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -318,9 +313,8 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: chain_to_chain_preserve
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -412,9 +406,8 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY6]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: cs_to_chain_preserve
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -444,9 +437,8 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: cs_to_chain_preserve
; DAGISEL-GFX11: bb.0 (%ir-block.0):
@@ -773,9 +765,8 @@ define amdgpu_cs_chain void @non_imm_exec(i64 inreg %exec, <3 x i32> inreg %sgpr
; GISEL-GFX11-NEXT: $vgpr11 = COPY [[COPY8]]
; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX11-NEXT: [[COPY12:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE1]]
- ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY12]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE1]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; GISEL-GFX10-LABEL: name: non_imm_exec
; GISEL-GFX10: bb.1 (%ir-block.0):
@@ -808,9 +799,8 @@ define amdgpu_cs_chain void @non_imm_exec(i64 inreg %exec, <3 x i32> inreg %sgpr
; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY12]]
; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX10-NEXT: [[COPY13:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE1]]
- ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY13]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
+ ; GISEL-GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE1]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51
;
; DAGISEL-GFX11-LABEL: name: non_imm_exec
; DAGISEL-GFX11: bb.0 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
index d6a0fef927d24f..861767ba79c01b 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-intrinsic-dyn-vgpr-w32.ll
@@ -36,11 +36,13 @@ define amdgpu_cs_chain void @direct_callee_direct_fallback(<3 x i32> inreg %sgpr
; GISEL-GFX12-NEXT: $vgpr9 = COPY [[COPY4]]
; GISEL-GFX12-NEXT: $vgpr10 = COPY [[COPY5]]
; GISEL-GFX12-NEXT: $vgpr11 = COPY [[COPY6]]
- ; GISEL-GFX12-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
- ; GISEL-GFX12-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1
- ; GISEL-GFX12-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE1]]
- ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[COPY11]], 0, 0, 15, 64, -1, [[COPY7]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
+ ; GISEL-GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX12-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @retry_vgpr_alloc
+ ; GISEL-GFX12-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @retry_vgpr_alloc
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1
+ ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[REG_SEQUENCE]], 0, 0, 15, 64, -1, [[REG_SEQUENCE1]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; DAGISEL-GFX12-LABEL: name: direct_callee_direct_fallback
; DAGISEL-GFX12: bb.0 (%ir-block.0):
@@ -85,6 +87,7 @@ define amdgpu_cs_chain void @indirect_callee_direct_fallback(i32 inreg %exec, pt
; GISEL-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GISEL-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GISEL-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
; GISEL-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GISEL-GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GISEL-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
@@ -93,30 +96,23 @@ define amdgpu_cs_chain void @indirect_callee_direct_fallback(i32 inreg %exec, pt
; GISEL-GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr10
; GISEL-GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr11
; GISEL-GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GISEL-GFX12-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
+ ; GISEL-GFX12-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
- ; GISEL-GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
+ ; GISEL-GFX12-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GISEL-GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
- ; GISEL-GFX12-NEXT: [[COPY13:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @retry_vgpr_alloc
- ; GISEL-GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @retry_vgpr_alloc
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX12-NEXT: [[COPY14:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE1]]
- ; GISEL-GFX12-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
- ; GISEL-GFX12-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GISEL-GFX12-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
- ; GISEL-GFX12-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GISEL-GFX12-NEXT: [[COPY17:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY17]], implicit $exec
- ; GISEL-GFX12-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_4]]
+ ; GISEL-GFX12-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
+ ; GISEL-GFX12-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
+ ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GISEL-GFX12-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GISEL-GFX12-NEXT: $vgpr8 = COPY [[COPY6]]
; GISEL-GFX12-NEXT: $vgpr9 = COPY [[COPY7]]
; GISEL-GFX12-NEXT: $vgpr10 = COPY [[COPY8]]
; GISEL-GFX12-NEXT: $vgpr11 = COPY [[COPY9]]
- ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[COPY13]], 0, 0, [[COPY]], [[COPY10]], -1, [[COPY14]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @retry_vgpr_alloc
+ ; GISEL-GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @retry_vgpr_alloc
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[REG_SEQUENCE]], 0, 0, [[COPY]], [[COPY10]], -1, [[REG_SEQUENCE1]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; DAGISEL-GFX12-LABEL: name: indirect_callee_direct_fallback
; DAGISEL-GFX12: bb.0 (%ir-block.0):
@@ -170,7 +166,7 @@ define amdgpu_cs_chain void @direct_callee_indirect_fallback(i32 inreg %exec, pt
; GISEL-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GISEL-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GISEL-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1
; GISEL-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GISEL-GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GISEL-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
@@ -179,15 +175,14 @@ define amdgpu_cs_chain void @direct_callee_indirect_fallback(i32 inreg %exec, pt
; GISEL-GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr10
; GISEL-GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr11
; GISEL-GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GISEL-GFX12-NEXT: [[COPY11:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
+ ; GISEL-GFX12-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
+ ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec
; GISEL-GFX12-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
- ; GISEL-GFX12-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
+ ; GISEL-GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
+ ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec
; GISEL-GFX12-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
- ; GISEL-GFX12-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
+ ; GISEL-GFX12-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
+ ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec
; GISEL-GFX12-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GISEL-GFX12-NEXT: $vgpr8 = COPY [[COPY6]]
; GISEL-GFX12-NEXT: $vgpr9 = COPY [[COPY7]]
@@ -195,9 +190,8 @@ define amdgpu_cs_chain void @direct_callee_indirect_fallback(i32 inreg %exec, pt
; GISEL-GFX12-NEXT: $vgpr11 = COPY [[COPY9]]
; GISEL-GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee
; GISEL-GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
- ; GISEL-GFX12-NEXT: [[COPY15:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE1]]
- ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[COPY15]], 0, 0, [[COPY]], [[COPY10]], -1, [[COPY11]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
+ ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[REG_SEQUENCE1]], 0, 0, [[COPY]], [[COPY10]], -1, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; DAGISEL-GFX12-LABEL: name: direct_callee_indirect_fallback
; DAGISEL-GFX12: bb.0 (%ir-block.0):
@@ -246,9 +240,10 @@ define amdgpu_cs_chain void @indirect_callee_indirect_fallback(i32 inreg %exec,
; GISEL-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GISEL-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GISEL-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1
; GISEL-GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GISEL-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
+ ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; GISEL-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GISEL-GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr7
; GISEL-GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr8
@@ -257,27 +252,20 @@ define amdgpu_cs_chain void @indirect_callee_indirect_fallback(i32 inreg %exec,
; GISEL-GFX12-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY $vgpr10
; GISEL-GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY $vgpr11
; GISEL-GFX12-NEXT: [[COPY13:%[0-9]+]]:sreg_32 = COPY $sgpr9
- ; GISEL-GFX12-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
+ ; GISEL-GFX12-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY14]], implicit $exec
- ; GISEL-GFX12-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY3]]
+ ; GISEL-GFX12-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GISEL-GFX12-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY15]], implicit $exec
- ; GISEL-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
- ; GISEL-GFX12-NEXT: [[COPY16:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE1]]
- ; GISEL-GFX12-NEXT: [[COPY17:%[0-9]+]]:sgpr_64 = COPY [[REG_SEQUENCE]]
- ; GISEL-GFX12-NEXT: [[COPY18:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY18]], implicit $exec
- ; GISEL-GFX12-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_2]]
- ; GISEL-GFX12-NEXT: [[COPY19:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY19]], implicit $exec
- ; GISEL-GFX12-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_3]]
- ; GISEL-GFX12-NEXT: [[COPY20:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
- ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY20]], implicit $exec
- ; GISEL-GFX12-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_4]]
+ ; GISEL-GFX12-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
+ ; GISEL-GFX12-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[COPY8]]
+ ; GISEL-GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY16]], implicit $exec
+ ; GISEL-GFX12-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]]
; GISEL-GFX12-NEXT: $vgpr8 = COPY [[COPY9]]
; GISEL-GFX12-NEXT: $vgpr9 = COPY [[COPY10]]
; GISEL-GFX12-NEXT: $vgpr10 = COPY [[COPY11]]
; GISEL-GFX12-NEXT: $vgpr11 = COPY [[COPY12]]
- ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[COPY16]], 0, 0, [[COPY]], [[COPY13]], [[COPY1]], [[COPY17]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
+ ; GISEL-GFX12-NEXT: SI_CS_CHAIN_TC_W32_DVGPR [[REG_SEQUENCE]], 0, 0, [[COPY]], [[COPY13]], [[COPY1]], [[REG_SEQUENCE1]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11
;
; DAGISEL-GFX12-LABEL: name: indirect_callee_indirect_fallback
; DAGISEL-GFX12: bb.0 (%ir-block.0):
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
index cc942e6b802bb6..ac3c4738445976 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.wave32.ll
@@ -12,11 +12,17 @@ declare i64 @llvm.ctpop.i64(i64)
; Test ballot(0)
define amdgpu_cs i64 @constant_false() {
-; CHECK-LABEL: constant_false:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: s_mov_b32 s1, 0
-; CHECK-NEXT: ; return to shader part epilog
+; DAGISEL-LABEL: constant_false:
+; DAGISEL: ; %bb.0:
+; DAGISEL-NEXT: s_mov_b32 s0, 0
+; DAGISEL-NEXT: s_mov_b32 s1, 0
+; DAGISEL-NEXT: ; return to shader part epilog
+;
+; GISEL-LABEL: constant_false:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s0, 0
+; GISEL-NEXT: s_mov_b32 s1, s0
+; GISEL-NEXT: ; return to shader part epilog
%ballot = call i64 @llvm.amdgcn.ballot.i64(i1 0)
ret i64 %ballot
}
diff --git a/llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll b/llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
index ea1fedb18d42b7..d3cd0b6cb83cb2 100644
--- a/llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
+++ b/llvm/test/CodeGen/AMDGPU/overlapping-tuple-copy-implicit-op-failure.ll
@@ -8,75 +8,59 @@ define amdgpu_kernel void @test_long_add4(<4 x i64> %arg) #0 {
; CHECK-NEXT: s_mov_b64 s[6:7], 0
; CHECK-NEXT: v_mov_b32_e32 v0, s6
; CHECK-NEXT: v_mov_b32_e32 v1, s7
-; CHECK-NEXT: global_load_dwordx4 v[10:13], v[0:1], off
+; CHECK-NEXT: global_load_dwordx4 v[2:5], v[0:1], off
; CHECK-NEXT: s_mov_b64 s[4:5], 16
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
-; CHECK-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; CHECK-NEXT: ; kill: def $vgpr10_vgpr11_vgpr12_vgpr13 killed $vgpr10_vgpr11_vgpr12_vgpr13 def $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 killed $exec
+; CHECK-NEXT: global_load_dwordx4 v[10:13], v[0:1], off
+; CHECK-NEXT: ; kill: def $vgpr2_vgpr3_vgpr4_vgpr5 killed $vgpr2_vgpr3_vgpr4_vgpr5 def $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 killed $exec
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v17, v3
-; CHECK-NEXT: v_mov_b32_e32 v16, v2
-; CHECK-NEXT: v_mov_b32_e32 v15, v1
-; CHECK-NEXT: v_mov_b32_e32 v14, v0
-; CHECK-NEXT: v_mov_b32_e32 v8, v10
-; CHECK-NEXT: v_mov_b32_e32 v9, v11
-; CHECK-NEXT: v_mov_b32_e32 v6, v12
-; CHECK-NEXT: v_mov_b32_e32 v7, v13
-; CHECK-NEXT: v_mov_b32_e32 v4, v14
-; CHECK-NEXT: v_mov_b32_e32 v5, v15
-; CHECK-NEXT: v_mov_b32_e32 v2, v16
-; CHECK-NEXT: v_mov_b32_e32 v3, v17
-; CHECK-NEXT: v_mov_b32_e32 v1, v8
-; CHECK-NEXT: v_mov_b32_e32 v0, v9
+; CHECK-NEXT: v_mov_b32_e32 v6, v10
+; CHECK-NEXT: v_mov_b32_e32 v7, v11
+; CHECK-NEXT: v_mov_b32_e32 v8, v12
+; CHECK-NEXT: v_mov_b32_e32 v9, v13
+; CHECK-NEXT: v_mov_b32_e32 v1, v2
+; CHECK-NEXT: v_mov_b32_e32 v0, v3
; CHECK-NEXT: v_readfirstlane_b32 s12, v1
; CHECK-NEXT: v_readfirstlane_b32 s13, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, v6
-; CHECK-NEXT: v_mov_b32_e32 v0, v7
-; CHECK-NEXT: v_readfirstlane_b32 s10, v1
-; CHECK-NEXT: v_readfirstlane_b32 s11, v0
; CHECK-NEXT: v_mov_b32_e32 v1, v4
; CHECK-NEXT: v_mov_b32_e32 v0, v5
+; CHECK-NEXT: v_readfirstlane_b32 s10, v1
+; CHECK-NEXT: v_readfirstlane_b32 s11, v0
+; CHECK-NEXT: v_mov_b32_e32 v1, v6
+; CHECK-NEXT: v_mov_b32_e32 v0, v7
; CHECK-NEXT: v_readfirstlane_b32 s8, v1
; CHECK-NEXT: v_readfirstlane_b32 s9, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, v2
-; CHECK-NEXT: v_mov_b32_e32 v0, v3
+; CHECK-NEXT: v_mov_b32_e32 v1, v8
+; CHECK-NEXT: v_mov_b32_e32 v0, v9
; CHECK-NEXT: v_readfirstlane_b32 s16, v1
; CHECK-NEXT: v_readfirstlane_b32 s14, v0
; CHECK-NEXT: v_mov_b32_e32 v0, s6
; CHECK-NEXT: v_mov_b32_e32 v1, s7
-; CHECK-NEXT: global_load_dwordx4 v[10:13], v[0:1], off
+; CHECK-NEXT: global_load_dwordx4 v[2:5], v[0:1], off
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v1, s5
-; CHECK-NEXT: global_load_dwordx4 v[0:3], v[0:1], off
-; CHECK-NEXT: ; kill: def $vgpr10_vgpr11_vgpr12_vgpr13 killed $vgpr10_vgpr11_vgpr12_vgpr13 def $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 killed $exec
+; CHECK-NEXT: global_load_dwordx4 v[10:13], v[0:1], off
+; CHECK-NEXT: ; kill: def $vgpr2_vgpr3_vgpr4_vgpr5 killed $vgpr2_vgpr3_vgpr4_vgpr5 def $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 killed $exec
; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v17, v3
-; CHECK-NEXT: v_mov_b32_e32 v16, v2
-; CHECK-NEXT: v_mov_b32_e32 v15, v1
-; CHECK-NEXT: v_mov_b32_e32 v14, v0
-; CHECK-NEXT: v_mov_b32_e32 v8, v10
-; CHECK-NEXT: v_mov_b32_e32 v9, v11
-; CHECK-NEXT: v_mov_b32_e32 v6, v12
-; CHECK-NEXT: v_mov_b32_e32 v7, v13
-; CHECK-NEXT: v_mov_b32_e32 v4, v14
-; CHECK-NEXT: v_mov_b32_e32 v5, v15
-; CHECK-NEXT: v_mov_b32_e32 v2, v16
-; CHECK-NEXT: v_mov_b32_e32 v3, v17
-; CHECK-NEXT: v_mov_b32_e32 v1, v8
-; CHECK-NEXT: v_mov_b32_e32 v0, v9
+; CHECK-NEXT: v_mov_b32_e32 v6, v10
+; CHECK-NEXT: v_mov_b32_e32 v7, v11
+; CHECK-NEXT: v_mov_b32_e32 v8, v12
+; CHECK-NEXT: v_mov_b32_e32 v9, v13
+; CHECK-NEXT: v_mov_b32_e32 v1, v2
+; CHECK-NEXT: v_mov_b32_e32 v0, v3
; CHECK-NEXT: v_readfirstlane_b32 s23, v1
; CHECK-NEXT: v_readfirstlane_b32 s22, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, v6
-; CHECK-NEXT: v_mov_b32_e32 v0, v7
-; CHECK-NEXT: v_readfirstlane_b32 s21, v1
-; CHECK-NEXT: v_readfirstlane_b32 s20, v0
; CHECK-NEXT: v_mov_b32_e32 v1, v4
; CHECK-NEXT: v_mov_b32_e32 v0, v5
+; CHECK-NEXT: v_readfirstlane_b32 s21, v1
+; CHECK-NEXT: v_readfirstlane_b32 s20, v0
+; CHECK-NEXT: v_mov_b32_e32 v1, v6
+; CHECK-NEXT: v_mov_b32_e32 v0, v7
; CHECK-NEXT: v_readfirstlane_b32 s19, v1
; CHECK-NEXT: v_readfirstlane_b32 s18, v0
-; CHECK-NEXT: v_mov_b32_e32 v1, v2
-; CHECK-NEXT: v_mov_b32_e32 v0, v3
+; CHECK-NEXT: v_mov_b32_e32 v1, v8
+; CHECK-NEXT: v_mov_b32_e32 v0, v9
; CHECK-NEXT: v_readfirstlane_b32 s17, v1
; CHECK-NEXT: v_readfirstlane_b32 s15, v0
; CHECK-NEXT: s_add_u32 s12, s12, s23
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 935bbd34651f46..c64ad3feb872f1 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -80,10 +80,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[ANDri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
@@ -108,11 +110,13 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[RSBri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[RSBri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
@@ -137,11 +141,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY [[COPY]]
- ; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[SXTB]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-NEXT: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[SXTB]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -166,11 +171,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY [[COPY]]
- ; CHECK: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[UXTH]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-NEXT: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[UXTH]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -195,9 +201,11 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -222,9 +230,11 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -252,11 +262,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: STRH [[ANDri]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: STRH [[ANDri]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -286,12 +297,13 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: STRH [[RSBri]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: STRH [[RSBri]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -321,10 +333,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -354,12 +367,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
- ; CHECK: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
- ; CHECK: STRH [[UXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: STRH [[UXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -389,12 +402,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
- ; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
- ; CHECK: STRH [[SXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: STRH [[SXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -424,10 +437,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -457,11 +471,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[ANDri:%[0-9]+]]:gprnopc = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: STRBi12 [[ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ANDri:%[0-9]+]]:gprnopc = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: STRBi12 [[ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -491,12 +506,13 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[RSBri:%[0-9]+]]:gprnopc = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: STRBi12 [[RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[RSBri:%[0-9]+]]:gprnopc = RSBri [[ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: STRBi12 [[RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -526,11 +542,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
- ; CHECK: STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: STRBi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -557,11 +573,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_add_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[ADDrr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[ADDrr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -586,10 +604,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_add_fold_imm_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 255, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[ADDri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[ADDri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 255
@@ -613,11 +633,13 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_add_no_fold_imm_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[MOVi16_:%[0-9]+]]:gpr = MOVi16 65535, 14 /* CC::al */, $noreg
- ; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[MOVi16_]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[ADDrr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[MOVi16_:%[0-9]+]]:gpr = MOVi16 65535, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[MOVi16_]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[ADDrr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 65535
@@ -642,11 +664,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_sub_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[SUBrr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[SUBrr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -671,10 +695,12 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_sub_imm_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[SUBri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[SUBri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 17
@@ -698,10 +724,12 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_sub_rev_imm_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[RSBri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 17, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[RSBri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 17
@@ -725,11 +753,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_mul_s32
- ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
- ; CHECK: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MUL]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MUL]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -754,11 +784,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_mulv5_s32
- ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
- ; CHECK: early-clobber %2:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY %2
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: early-clobber %2:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY %2
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -783,11 +815,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_sdiv_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[SDIV]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[SDIV]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -812,11 +846,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_udiv_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[UDIV]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[UDIV]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -841,11 +877,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_lshr_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MOVsr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVsr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -870,11 +908,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_ashr_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MOVsr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVsr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -899,11 +939,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_shl_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MOVsr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[MOVsr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -934,14 +976,15 @@ body: |
liveins: $r0, $r1, $r2, $r3
; CHECK-LABEL: name: test_load_from_stack
- ; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[ADDri]], 0, 14 /* CC::al */, $noreg :: (load (s32))
- ; CHECK: $r0 = COPY [[LDRi12_]]
- ; CHECK: [[ADDri1:%[0-9]+]]:gpr = ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[LDRBi12_:%[0-9]+]]:gprnopc = LDRBi12 [[ADDri1]], 0, 14 /* CC::al */, $noreg :: (load (s8))
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[LDRBi12_]]
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[ADDri:%[0-9]+]]:gpr = ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[ADDri]], 0, 14 /* CC::al */, $noreg :: (load (s32))
+ ; CHECK-NEXT: $r0 = COPY [[LDRi12_]]
+ ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[LDRBi12_:%[0-9]+]]:gprnopc = LDRBi12 [[ADDri1]], 0, 14 /* CC::al */, $noreg :: (load (s8))
+ ; CHECK-NEXT: $r0 = COPY [[LDRBi12_]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0) :: (load (s32))
@@ -974,13 +1017,14 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_stores
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]]
- ; CHECK: STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK-NEXT: STRBi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: STRi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%3(s32) = COPY $r1
@@ -1011,11 +1055,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_gep
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[ADDrr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[ADDrr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -1036,8 +1082,8 @@ body: |
bb.0:
; CHECK-LABEL: name: test_MOVi32imm
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr = MOVi32imm 65537
- ; CHECK: $r0 = COPY [[MOVi32imm]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: $r0 = COPY [[MOVi32imm]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 65537
$r0 = COPY %0(s32)
@@ -1054,8 +1100,8 @@ body: |
bb.0:
; CHECK-LABEL: name: test_constant_imm
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MOVi]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: $r0 = COPY [[MOVi]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 42
$r0 = COPY %0(s32)
@@ -1074,8 +1120,8 @@ body: |
; We still want to see the same thing in the output though.
; CHECK-LABEL: name: test_constant_cimm
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MOVi]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: $r0 = COPY [[MOVi]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = G_CONSTANT i32 42
$r0 = COPY %0(s32)
@@ -1092,8 +1138,8 @@ body: |
bb.0:
; CHECK-LABEL: name: test_pointer_constant_unconstrained
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[MOVi]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: $r0 = COPY [[MOVi]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = G_CONSTANT i32 0
; This leaves %0 unconstrained before the G_CONSTANT is selected.
@@ -1111,7 +1157,7 @@ body: |
bb.0:
; CHECK-LABEL: name: test_pointer_constant_constrained
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: STRi12 [[MOVi]], [[MOVi]], 0, 14 /* CC::al */, $noreg :: (store (p0))
+ ; CHECK-NEXT: STRi12 [[MOVi]], [[MOVi]], 0, 14 /* CC::al */, $noreg :: (store (p0))
%0(p0) = G_CONSTANT i32 0
; This constrains %0 before the G_CONSTANT is selected.
@@ -1130,9 +1176,11 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_inttoptr_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
@@ -1153,9 +1201,11 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_ptrtoint_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
@@ -1178,12 +1228,14 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_select_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
- ; CHECK: $r0 = COPY [[MOVCCr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: $r0 = COPY [[MOVCCr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -1212,13 +1264,15 @@ body: |
liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_select_ptr
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
- ; CHECK: TSTri [[COPY2]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
- ; CHECK: $r0 = COPY [[MOVCCr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r2
+ ; CHECK-NEXT: TSTri [[COPY2]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: $r0 = COPY [[MOVCCr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
%1(p0) = COPY $r1
@@ -1244,16 +1298,21 @@ registers:
body: |
; CHECK-LABEL: name: test_br
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: Bcc %bb.1, 1 /* CC::ne */, $cpsr
- ; CHECK: B %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: B %bb.2
- ; CHECK: bb.2:
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: Bcc %bb.1, 1 /* CC::ne */, $cpsr
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0
@@ -1288,21 +1347,25 @@ registers:
body: |
; CHECK-LABEL: name: test_phi_s32
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $r0, $r1, $r2
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
- ; CHECK: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: Bcc %bb.1, 1 /* CC::ne */, $cpsr
- ; CHECK: B %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: B %bb.2
- ; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, [[COPY2]], %bb.1
- ; CHECK: $r0 = COPY [[PHI]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r2
+ ; CHECK-NEXT: TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: Bcc %bb.1, 1 /* CC::ne */, $cpsr
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: B %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, [[COPY2]], %bb.1
+ ; CHECK-NEXT: $r0 = COPY [[PHI]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
index 7e473fb1529db2..584db5ff2c75f5 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
@@ -14,17 +14,21 @@ registers:
body: |
; CHECK-LABEL: name: test_br
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: t2TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: t2Bcc %bb.1, 1 /* CC::ne */, $cpsr
- ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
- ; CHECK: bb.2:
- ; CHECK: tBX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: t2TSTri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: t2Bcc %bb.1, 1 /* CC::ne */, $cpsr
+ ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
index f626e56b9c68b2..47c46d5b98dcb9 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
@@ -41,11 +41,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[t2ANDri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2ANDri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
@@ -72,12 +72,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[t2RSBri]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2RSBri]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
@@ -104,9 +104,10 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
@@ -133,11 +134,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[t2UXTB]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2UXTB]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -164,11 +165,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[t2SXTB]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2SXTB]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -195,9 +196,10 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -224,11 +226,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[t2UXTH]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[COPY]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2UXTH]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -255,11 +257,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]]
- ; CHECK: [[t2SXTH:%[0-9]+]]:rgpr = t2SXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
- ; CHECK: $r0 = COPY [[t2SXTH]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[t2SXTH:%[0-9]+]]:rgpr = t2SXTH [[COPY]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2SXTH]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -286,9 +288,10 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32
; CHECK: liveins: $r0
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: $r0 = COPY [[COPY]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -316,12 +319,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STRHi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STRHi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -351,13 +354,13 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STRHi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STRHi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -387,11 +390,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: t2STRHi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -421,12 +424,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
- ; CHECK: t2STRHi12 [[t2UXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRHi12 [[t2UXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -456,12 +459,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
- ; CHECK: t2STRHi12 [[t2SXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: t2STRHi12 [[t2SXTB]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -491,11 +494,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: t2STRHi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -525,12 +528,12 @@ body: |
; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -560,13 +563,13 @@ body: |
; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: t2STRBi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: t2STRBi12 [[t2RSBri]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -596,11 +599,11 @@ body: |
; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8
; CHECK: liveins: $r0, $r1
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]]
- ; CHECK: t2STRBi12 [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: t2STRBi12 [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $r1
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
index ff97632736ecc7..98edc1ed87e857 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
@@ -22,10 +22,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_s8
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s8))
- ; CHECK: t2STRBi12 [[t2LDRBi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s8))
+ ; CHECK-NEXT: t2STRBi12 [[t2LDRBi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load (s8))
@@ -47,10 +49,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_s16
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s16))
- ; CHECK: t2STRHi12 [[t2LDRHi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s16))
+ ; CHECK-NEXT: t2STRHi12 [[t2LDRHi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0(p0) :: (load (s16))
@@ -72,10 +76,12 @@ body: |
liveins: $r0
; CHECK-LABEL: name: test_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
- ; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))
- ; CHECK: t2STRi12 [[t2LDRi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK: liveins: $r0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK-NEXT: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))
+ ; CHECK-NEXT: t2STRi12 [[t2LDRi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load (s32))
@@ -98,11 +104,13 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_gep
- ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
- ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
- ; CHECK: $r0 = COPY [[t2ADDrr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: $r0 = COPY [[t2ADDrr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
%1(s32) = COPY $r1
@@ -133,14 +141,15 @@ body: |
liveins: $r0, $r1, $r2, $r3
; CHECK-LABEL: name: test_load_from_stack
- ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[t2ADDri]], 0, 14 /* CC::al */, $noreg :: (load (s32))
- ; CHECK: $r0 = COPY [[t2LDRi12_]]
- ; CHECK: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
- ; CHECK: [[t2LDRBi12_:%[0-9]+]]:gprnopc = t2LDRBi12 [[t2ADDri1]], 0, 14 /* CC::al */, $noreg :: (load (s8))
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[t2LDRBi12_]]
- ; CHECK: $r0 = COPY [[COPY]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg
+ ; CHECK: liveins: $r0, $r1, $r2, $r3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[t2ADDri]], 0, 14 /* CC::al */, $noreg :: (load (s32))
+ ; CHECK-NEXT: $r0 = COPY [[t2LDRi12_]]
+ ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK-NEXT: [[t2LDRBi12_:%[0-9]+]]:gprnopc = t2LDRBi12 [[t2ADDri1]], 0, 14 /* CC::al */, $noreg :: (load (s8))
+ ; CHECK-NEXT: $r0 = COPY [[t2LDRBi12_]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0) :: (load (s32))
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
index f8f7c594b2aa19..104896d52bbca6 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
@@ -19,12 +19,14 @@ body: |
liveins: $r0, $r1
; CHECK-LABEL: name: test_select_s32
- ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
- ; CHECK: t2TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
- ; CHECK: $r0 = COPY [[t2MOVCCr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: t2TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: $r0 = COPY [[t2MOVCCr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $r0
%1(s32) = COPY $r1
@@ -53,14 +55,15 @@ body: |
liveins: $r0, $r1, $r2
; CHECK-LABEL: name: test_select_ptr
- ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
- ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
- ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2
- ; CHECK: [[COPY3:%[0-9]+]]:rgpr = COPY [[COPY2]]
- ; CHECK: t2TSTri [[COPY3]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
- ; CHECK: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
- ; CHECK: $r0 = COPY [[t2MOVCCr]]
- ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r2
+ ; CHECK-NEXT: t2TSTri [[COPY2]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 /* CC::eq */, $cpsr
+ ; CHECK-NEXT: $r0 = COPY [[t2MOVCCr]]
+ ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(p0) = COPY $r0
%1(p0) = COPY $r1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir b/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
index 0c98fc1c437e11..282678ccaad466 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/isel-fp64-to-sint-x86.mir
@@ -122,10 +122,9 @@ body: |
; GISEL-X86-LABEL: name: test_double_to_int8
; GISEL-X86: [[DEF:%[0-9]+]]:rfp64 = IMPLICIT_DEF
; GISEL-X86-NEXT: FP64_TO_INT16_IN_MEM %stack.0, 1, $noreg, 0, $noreg, [[DEF]], implicit-def dead $eflags :: (store (s16) into %stack.0)
- ; GISEL-X86-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %stack.0, 1, $noreg, 0, $noreg :: (load (s16) from %stack.0)
- ; GISEL-X86-NEXT: [[COPY:%[0-9]+]]:gr16_abcd = COPY [[MOV16rm]]
- ; GISEL-X86-NEXT: [[COPY1:%[0-9]+]]:gr8_abcd_l = COPY [[COPY]].sub_8bit
- ; GISEL-X86-NEXT: $al = COPY [[COPY1]]
+ ; GISEL-X86-NEXT: [[MOV16rm:%[0-9]+]]:gr16_abcd = MOV16rm %stack.0, 1, $noreg, 0, $noreg :: (load (s16) from %stack.0)
+ ; GISEL-X86-NEXT: [[COPY:%[0-9]+]]:gr8_abcd_l = COPY [[MOV16rm]].sub_8bit
+ ; GISEL-X86-NEXT: $al = COPY [[COPY]]
; GISEL-X86-NEXT: RET 0, implicit $al
%0:_(s64) = IMPLICIT_DEF
%4:_(p0) = G_FRAME_INDEX %stack.0
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
index 5c059a4e0539d3..4d043615c90860 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
@@ -95,10 +95,9 @@ body: |
; X86-LABEL: name: test_copy3
; X86: liveins: $eax
; X86-NEXT: {{ $}}
- ; X86-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax
- ; X86-NEXT: [[COPY1:%[0-9]+]]:gr16_abcd = COPY [[COPY]]
- ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
- ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr16_abcd = COPY $ax
+ ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8_abcd_l = COPY [[COPY]].sub_8bit
+ ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
; X86-NEXT: RET 0, implicit $eax
;
@@ -161,10 +160,9 @@ body: |
; X86-LABEL: name: test_copy5
; X86: liveins: $eax, $edx
; X86-NEXT: {{ $}}
- ; X86-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
- ; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
- ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
- ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edx
+ ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8_abcd_l = COPY [[COPY]].sub_8bit
+ ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
; X86-NEXT: RET 0, implicit $eax
;
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
index d204e09dd9ef12..e3dc7f3fe60562 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
@@ -37,12 +37,14 @@ body: |
liveins: $edi
; ALL-LABEL: name: test_zext_i1
- ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
- ; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
- ; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_8bit
- ; ALL: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def $eflags
- ; ALL: $rax = COPY [[AND64ri32_]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+ ; ALL-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+ ; ALL-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_8bit
+ ; ALL-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def $eflags
+ ; ALL-NEXT: $rax = COPY [[AND64ri32_]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s1) = G_TRUNC %0(s8)
%2(s64) = G_ZEXT %1(s1)
@@ -63,10 +65,12 @@ body: |
liveins: $edi
; ALL-LABEL: name: test_sext_i8
- ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
- ; ALL: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]]
- ; ALL: $rax = COPY [[MOVSX64rr8_]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+ ; ALL-NEXT: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]]
+ ; ALL-NEXT: $rax = COPY [[MOVSX64rr8_]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s8) = COPY $dil
%1(s64) = G_SEXT %0(s8)
$rax = COPY %1(s64)
@@ -86,10 +90,12 @@ body: |
liveins: $edi
; ALL-LABEL: name: test_sext_i16
- ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY $di
- ; ALL: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]]
- ; ALL: $rax = COPY [[MOVSX64rr16_]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
+ ; ALL-NEXT: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]]
+ ; ALL-NEXT: $rax = COPY [[MOVSX64rr16_]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s16) = COPY $di
%1(s64) = G_SEXT %0(s16)
$rax = COPY %1(s64)
@@ -110,11 +116,13 @@ body: |
liveins: $edi
; ALL-LABEL: name: anyext_s64_from_s1
- ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
- ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit
- ; ALL: $rax = COPY [[SUBREG_TO_REG]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; ALL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit
+ ; ALL-NEXT: $rax = COPY [[SUBREG_TO_REG]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s1) = G_TRUNC %0(s64)
%2(s64) = G_ANYEXT %1(s1)
@@ -135,12 +143,14 @@ body: |
liveins: $edi
; ALL-LABEL: name: anyext_s64_from_s8
- ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
- ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; ALL: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr8_]], %subreg.sub_32bit
- ; ALL: $rax = COPY [[SUBREG_TO_REG]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; ALL-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
+ ; ALL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr8_]], %subreg.sub_32bit
+ ; ALL-NEXT: $rax = COPY [[SUBREG_TO_REG]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s8) = G_TRUNC %0(s64)
%2(s64) = G_ANYEXT %1(s8)
@@ -161,12 +171,14 @@ body: |
liveins: $edi
; ALL-LABEL: name: anyext_s64_from_s16
- ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; ALL: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
- ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr16_]], %subreg.sub_32bit
- ; ALL: $rax = COPY [[SUBREG_TO_REG]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; ALL-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
+ ; ALL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr16_]], %subreg.sub_32bit
+ ; ALL-NEXT: $rax = COPY [[SUBREG_TO_REG]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s16) = G_TRUNC %0(s64)
%2(s64) = G_ANYEXT %1(s16)
@@ -187,12 +199,14 @@ body: |
liveins: $edi
; ALL-LABEL: name: anyext_s64_from_s32
- ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
- ; ALL: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
- ; ALL: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32bit
- ; ALL: $rax = COPY [[INSERT_SUBREG]]
- ; ALL: RET 0, implicit $rax
+ ; ALL: liveins: $edi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
+ ; ALL-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
+ ; ALL-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32bit
+ ; ALL-NEXT: $rax = COPY [[INSERT_SUBREG]]
+ ; ALL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s32) = G_TRUNC %0(s64)
%2(s64) = G_ANYEXT %1(s32)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
index 0805a486a76a82..23c5e83ec9916d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
@@ -61,13 +61,18 @@ body: |
liveins: $edi
; X86-LABEL: name: test_zext_i1toi8
- ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X86-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
; X86-NEXT: $al = COPY [[AND8ri]]
; X86-NEXT: RET 0, implicit $al
+ ;
; X64-LABEL: name: test_zext_i1toi8
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
; X64-NEXT: $al = COPY [[AND8ri]]
@@ -94,20 +99,25 @@ body: |
liveins: $edi
; X86-LABEL: name: test_zext_i1toi16
- ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X86-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
; X86-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr16 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
- ; X86-NEXT: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[INSERT_SUBREG]], 1, implicit-def $eflags
- ; X86-NEXT: $ax = COPY [[AND16ri_]]
+ ; X86-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[INSERT_SUBREG]], 1, implicit-def $eflags
+ ; X86-NEXT: $ax = COPY [[AND16ri]]
; X86-NEXT: RET 0, implicit $ax
+ ;
; X64-LABEL: name: test_zext_i1toi16
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
; X64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr16 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
- ; X64-NEXT: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[INSERT_SUBREG]], 1, implicit-def $eflags
- ; X64-NEXT: $ax = COPY [[AND16ri_]]
+ ; X64-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[INSERT_SUBREG]], 1, implicit-def $eflags
+ ; X64-NEXT: $ax = COPY [[AND16ri]]
; X64-NEXT: RET 0, implicit $ax
%0(s32) = COPY $edi
%1(s1) = G_TRUNC %0(s32)
@@ -131,20 +141,25 @@ body: |
liveins: $edi
; X86-LABEL: name: test_zext_i1
- ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X86-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X86-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
- ; X86-NEXT: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[INSERT_SUBREG]], 1, implicit-def $eflags
- ; X86-NEXT: $eax = COPY [[AND32ri_]]
+ ; X86-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[INSERT_SUBREG]], 1, implicit-def $eflags
+ ; X86-NEXT: $eax = COPY [[AND32ri]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_zext_i1
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
; X64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
- ; X64-NEXT: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[INSERT_SUBREG]], 1, implicit-def $eflags
- ; X64-NEXT: $eax = COPY [[AND32ri_]]
+ ; X64-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[INSERT_SUBREG]], 1, implicit-def $eflags
+ ; X64-NEXT: $eax = COPY [[AND32ri]]
; X64-NEXT: RET 0, implicit $eax
%0(s32) = COPY $edi
%1(s1) = G_TRUNC %0(s32)
@@ -167,12 +182,17 @@ body: |
liveins: $edi
; X86-LABEL: name: test_zext_i8
- ; X86: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_zext_i8
- ; X64: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
; X64-NEXT: RET 0, implicit $eax
@@ -196,12 +216,17 @@ body: |
liveins: $edi
; X86-LABEL: name: test_zext_i16
- ; X86: [[COPY:%[0-9]+]]:gr16 = COPY $di
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
; X86-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY]]
; X86-NEXT: $eax = COPY [[MOVZX32rr16_]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_zext_i16
- ; X64: [[COPY:%[0-9]+]]:gr16 = COPY $di
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
; X64-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY]]
; X64-NEXT: $eax = COPY [[MOVZX32rr16_]]
; X64-NEXT: RET 0, implicit $eax
@@ -225,12 +250,17 @@ body: |
liveins: $edi
; X86-LABEL: name: test_sext_i8
- ; X86: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
; X86-NEXT: [[MOVSX32rr8_:%[0-9]+]]:gr32 = MOVSX32rr8 [[COPY]]
; X86-NEXT: $eax = COPY [[MOVSX32rr8_]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_sext_i8
- ; X64: [[COPY:%[0-9]+]]:gr8 = COPY $dil
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $dil
; X64-NEXT: [[MOVSX32rr8_:%[0-9]+]]:gr32 = MOVSX32rr8 [[COPY]]
; X64-NEXT: $eax = COPY [[MOVSX32rr8_]]
; X64-NEXT: RET 0, implicit $eax
@@ -254,12 +284,17 @@ body: |
liveins: $edi
; X86-LABEL: name: test_sext_i16
- ; X86: [[COPY:%[0-9]+]]:gr16 = COPY $di
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
; X86-NEXT: [[MOVSX32rr16_:%[0-9]+]]:gr32 = MOVSX32rr16 [[COPY]]
; X86-NEXT: $eax = COPY [[MOVSX32rr16_]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_sext_i16
- ; X64: [[COPY:%[0-9]+]]:gr16 = COPY $di
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
; X64-NEXT: [[MOVSX32rr16_:%[0-9]+]]:gr32 = MOVSX32rr16 [[COPY]]
; X64-NEXT: $eax = COPY [[MOVSX32rr16_]]
; X64-NEXT: RET 0, implicit $eax
@@ -284,12 +319,17 @@ body: |
liveins: $edi
; X86-LABEL: name: test_anyext_i1toi8
- ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X86-NEXT: $al = COPY [[COPY1]]
; X86-NEXT: RET 0, implicit $al
+ ;
; X64-LABEL: name: test_anyext_i1toi8
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: $al = COPY [[COPY1]]
; X64-NEXT: RET 0, implicit $al
@@ -314,13 +354,18 @@ body: |
liveins: $edi
; X86-LABEL: name: test_anyext_i1toi16
- ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit
; X86-NEXT: $ax = COPY [[SUBREG_TO_REG]]
; X86-NEXT: RET 0, implicit $ax
+ ;
; X64-LABEL: name: test_anyext_i1toi16
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit
; X64-NEXT: $ax = COPY [[SUBREG_TO_REG]]
@@ -346,13 +391,18 @@ body: |
liveins: $edi
; X86-LABEL: name: test_anyext_i1toi32
- ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit
; X86-NEXT: $eax = COPY [[SUBREG_TO_REG]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_anyext_i1toi32
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit
; X64-NEXT: $eax = COPY [[SUBREG_TO_REG]]
@@ -378,15 +428,19 @@ body: |
liveins: $edi
; X86-LABEL: name: test_anyext_i8toi16
- ; X86: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
- ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
- ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
- ; X86-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
- ; X86-NEXT: $ax = COPY [[COPY3]]
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8_abcd_l = COPY [[COPY]].sub_8bit
+ ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
+ ; X86-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
+ ; X86-NEXT: $ax = COPY [[COPY2]]
; X86-NEXT: RET 0, implicit $ax
+ ;
; X64-LABEL: name: test_anyext_i8toi16
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; X64-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
@@ -413,14 +467,18 @@ body: |
liveins: $edi
; X86-LABEL: name: test_anyext_i8toi32
- ; X86: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
- ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
- ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
+ ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8_abcd_l = COPY [[COPY]].sub_8bit
+ ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_anyext_i8toi32
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
@@ -446,14 +504,19 @@ body: |
liveins: $edi
; X86-LABEL: name: test_anyext_i16toi32
- ; X86: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X86: liveins: $edi
+ ; X86-NEXT: {{ $}}
+ ; X86-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X86-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; X86-NEXT: [[DEF:%[0-9]+]]:low32_addr_access_rbp = IMPLICIT_DEF
; X86-NEXT: [[INSERT_SUBREG:%[0-9]+]]:low32_addr_access_rbp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_16bit
; X86-NEXT: $eax = COPY [[INSERT_SUBREG]]
; X86-NEXT: RET 0, implicit $eax
+ ;
; X64-LABEL: name: test_anyext_i16toi32
- ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; X64: liveins: $edi
+ ; X64-NEXT: {{ $}}
+ ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; X64-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; X64-NEXT: [[DEF:%[0-9]+]]:low32_addr_access_rbp = IMPLICIT_DEF
; X64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:low32_addr_access_rbp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_16bit
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
index c0b73536460d7b..9f804da59510ca 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
@@ -40,41 +40,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fadd_float
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; SSE: %4:fr32 = nofpexcept ADDSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[ADDSSrr:%[0-9]+]]:vr128 = nofpexcept ADDSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[ADDSSrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fadd_float
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; AVX: %4:fr32 = nofpexcept VADDSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VADDSSrr:%[0-9]+]]:vr128 = nofpexcept VADDSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VADDSSrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fadd_float
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512F: %4:fr32x = nofpexcept VADDSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VADDSSZrr:%[0-9]+]]:vr128x = nofpexcept VADDSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VADDSSZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fadd_float
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512VL: %4:fr32x = nofpexcept VADDSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VADDSSZrr:%[0-9]+]]:vr128x = nofpexcept VADDSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VADDSSZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -109,41 +108,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fadd_double
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; SSE: %4:fr64 = nofpexcept ADDSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[ADDSDrr:%[0-9]+]]:vr128 = nofpexcept ADDSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[ADDSDrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fadd_double
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; AVX: %4:fr64 = nofpexcept VADDSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VADDSDrr:%[0-9]+]]:vr128 = nofpexcept VADDSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VADDSDrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fadd_double
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512F: %4:fr64x = nofpexcept VADDSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VADDSDZrr:%[0-9]+]]:vr128x = nofpexcept VADDSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VADDSDZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fadd_double
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512VL: %4:fr64x = nofpexcept VADDSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VADDSDZrr:%[0-9]+]]:vr128x = nofpexcept VADDSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VADDSDZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
index 2f0e60d53b9b0c..1d4a03f5ad74bd 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fcmp.mir
@@ -165,16 +165,15 @@ body: |
; CHECK-LABEL: name: fcmp_float_oeq
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
- ; CHECK: $al = COPY [[AND8rr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+ ; CHECK-NEXT: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK-NEXT: $al = COPY [[AND8rr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -205,14 +204,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ogt
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -243,14 +241,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_oge
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -281,14 +278,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_olt
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -319,14 +315,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ole
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -357,14 +352,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_one
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -395,14 +389,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ord
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -433,14 +426,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_uno
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -471,14 +463,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ueq
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -509,14 +500,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ugt
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -547,14 +537,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_uge
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -585,14 +574,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ult
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -623,14 +611,13 @@ body: |
; CHECK-LABEL: name: fcmp_float_ule
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -661,16 +648,15 @@ body: |
; CHECK-LABEL: name: fcmp_float_une
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; CHECK: UCOMISSrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
- ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
- ; CHECK: $al = COPY [[OR8rr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISSrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+ ; CHECK-NEXT: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK-NEXT: $al = COPY [[OR8rr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -701,16 +687,15 @@ body: |
; CHECK-LABEL: name: fcmp_double_oeq
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; CHECK: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
- ; CHECK: $al = COPY [[AND8rr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+ ; CHECK-NEXT: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK-NEXT: $al = COPY [[AND8rr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -741,14 +726,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ogt
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -779,14 +763,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_oge
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -817,14 +800,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_olt
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -855,14 +837,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ole
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -893,14 +874,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_one
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -931,14 +911,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ord
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 11, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -969,14 +948,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_uno
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -1007,14 +985,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ueq
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -1045,14 +1022,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ugt
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -1083,14 +1059,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_uge
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY3]], [[COPY1]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY1]], [[COPY]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -1121,14 +1096,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ult
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -1159,14 +1133,13 @@ body: |
; CHECK-LABEL: name: fcmp_double_ule
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
- ; CHECK: $al = COPY [[SETCCr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
+ ; CHECK-NEXT: $al = COPY [[SETCCr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -1197,16 +1170,15 @@ body: |
; CHECK-LABEL: name: fcmp_double_une
; CHECK: liveins: $xmm0, $xmm1
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; CHECK: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; CHECK: UCOMISDrr [[COPY1]], [[COPY3]], implicit-def $eflags
- ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
- ; CHECK: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
- ; CHECK: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
- ; CHECK: $al = COPY [[OR8rr]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; CHECK-NEXT: UCOMISDrr [[COPY]], [[COPY1]], implicit-def $eflags, implicit $mxcsr
+ ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
+ ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 10, implicit $eflags
+ ; CHECK-NEXT: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[SETCCr]], [[SETCCr1]], implicit-def $eflags
+ ; CHECK-NEXT: $al = COPY [[OR8rr]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir
index 10f9cbdce73f2b..74b2948a9c3f16 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir
@@ -29,30 +29,29 @@ registers:
body: |
bb.1.entry:
; CHECK_NOPIC64-LABEL: name: test_float
- ; CHECK_NOPIC64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_NOPIC64-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
- ; CHECK_NOPIC64-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_NOPIC64: [[MOVSSrm_alt:%[0-9]+]]:vr128 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_NOPIC64-NEXT: $xmm0 = COPY [[MOVSSrm_alt]]
; CHECK_NOPIC64-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_LARGE64-LABEL: name: test_float
; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
- ; CHECK_LARGE64-NEXT: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load (p0) from constant-pool, align 4)
- ; CHECK_LARGE64-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
- ; CHECK_LARGE64-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_LARGE64-NEXT: [[MOVSSrm_alt:%[0-9]+]]:vr128 = MOVSSrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load (p0) from constant-pool, align 4)
+ ; CHECK_LARGE64-NEXT: $xmm0 = COPY [[MOVSSrm_alt]]
; CHECK_LARGE64-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_SMALL32-LABEL: name: test_float
- ; CHECK_SMALL32: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_SMALL32-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
- ; CHECK_SMALL32-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_SMALL32: [[MOVSSrm_alt:%[0-9]+]]:vr128 = MOVSSrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_SMALL32-NEXT: $xmm0 = COPY [[MOVSSrm_alt]]
; CHECK_SMALL32-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_LARGE32-LABEL: name: test_float
- ; CHECK_LARGE32: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_LARGE32-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
- ; CHECK_LARGE32-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_LARGE32: [[MOVSSrm_alt:%[0-9]+]]:vr128 = MOVSSrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_LARGE32-NEXT: $xmm0 = COPY [[MOVSSrm_alt]]
; CHECK_LARGE32-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_PIC64-LABEL: name: test_float
- ; CHECK_PIC64: [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_PIC64-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSSrm_alt]]
- ; CHECK_PIC64-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_PIC64: [[MOVSSrm_alt:%[0-9]+]]:vr128 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_PIC64-NEXT: $xmm0 = COPY [[MOVSSrm_alt]]
; CHECK_PIC64-NEXT: RET 0, implicit $xmm0
%0:vecr(s32) = G_FCONSTANT float 5.500000e+00
%1:vecr(s128) = G_ANYEXT %0(s32)
@@ -76,30 +75,29 @@ registers:
body: |
bb.1.entry:
; CHECK_NOPIC64-LABEL: name: test_double
- ; CHECK_NOPIC64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_NOPIC64-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
- ; CHECK_NOPIC64-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_NOPIC64: [[MOVSDrm_alt:%[0-9]+]]:vr128 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_NOPIC64-NEXT: $xmm0 = COPY [[MOVSDrm_alt]]
; CHECK_NOPIC64-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_LARGE64-LABEL: name: test_double
; CHECK_LARGE64: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri %const.0
- ; CHECK_LARGE64-NEXT: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load (p0) from constant-pool)
- ; CHECK_LARGE64-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
- ; CHECK_LARGE64-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_LARGE64-NEXT: [[MOVSDrm_alt:%[0-9]+]]:vr128 = MOVSDrm_alt [[MOV64ri]], 1, $noreg, 0, $noreg :: (load (p0) from constant-pool)
+ ; CHECK_LARGE64-NEXT: $xmm0 = COPY [[MOVSDrm_alt]]
; CHECK_LARGE64-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_SMALL32-LABEL: name: test_double
- ; CHECK_SMALL32: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_SMALL32-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
- ; CHECK_SMALL32-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_SMALL32: [[MOVSDrm_alt:%[0-9]+]]:vr128 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_SMALL32-NEXT: $xmm0 = COPY [[MOVSDrm_alt]]
; CHECK_SMALL32-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_LARGE32-LABEL: name: test_double
- ; CHECK_LARGE32: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg
- ; CHECK_LARGE32-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
- ; CHECK_LARGE32-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_LARGE32: [[MOVSDrm_alt:%[0-9]+]]:vr128 = MOVSDrm_alt $noreg, 1, $noreg, %const.0, $noreg
+ ; CHECK_LARGE32-NEXT: $xmm0 = COPY [[MOVSDrm_alt]]
; CHECK_LARGE32-NEXT: RET 0, implicit $xmm0
+ ;
; CHECK_PIC64-LABEL: name: test_double
- ; CHECK_PIC64: [[MOVSDrm_alt:%[0-9]+]]:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg
- ; CHECK_PIC64-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY [[MOVSDrm_alt]]
- ; CHECK_PIC64-NEXT: $xmm0 = COPY [[COPY]]
+ ; CHECK_PIC64: [[MOVSDrm_alt:%[0-9]+]]:vr128 = MOVSDrm_alt $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK_PIC64-NEXT: $xmm0 = COPY [[MOVSDrm_alt]]
; CHECK_PIC64-NEXT: RET 0, implicit $xmm0
%0:vecr(s64) = G_FCONSTANT double 5.500000e+00
%1:vecr(s128) = G_ANYEXT %0(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
index 31db338ac35040..bf3583b212e13d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
@@ -40,41 +40,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fdiv_float
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; SSE: %4:fr32 = nofpexcept DIVSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[DIVSSrr:%[0-9]+]]:vr128 = nofpexcept DIVSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[DIVSSrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fdiv_float
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; AVX: %4:fr32 = nofpexcept VDIVSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VDIVSSrr:%[0-9]+]]:vr128 = nofpexcept VDIVSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VDIVSSrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fdiv_float
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512F: %4:fr32x = nofpexcept VDIVSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VDIVSSZrr:%[0-9]+]]:vr128x = nofpexcept VDIVSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VDIVSSZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fdiv_float
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512VL: %4:fr32x = nofpexcept VDIVSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VDIVSSZrr:%[0-9]+]]:vr128x = nofpexcept VDIVSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VDIVSSZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -109,41 +108,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fdiv_double
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; SSE: %4:fr64 = nofpexcept DIVSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[DIVSDrr:%[0-9]+]]:vr128 = nofpexcept DIVSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[DIVSDrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fdiv_double
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; AVX: %4:fr64 = nofpexcept VDIVSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VDIVSDrr:%[0-9]+]]:vr128 = nofpexcept VDIVSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VDIVSDrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fdiv_double
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512F: %4:fr64x = nofpexcept VDIVSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VDIVSDZrr:%[0-9]+]]:vr128x = nofpexcept VDIVSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VDIVSDZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fdiv_double
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512VL: %4:fr64x = nofpexcept VDIVSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VDIVSDZrr:%[0-9]+]]:vr128x = nofpexcept VDIVSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VDIVSDZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
index 9c8e3a76a70cff..930956849fe1b2 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
@@ -40,41 +40,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fmul_float
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; SSE: %4:fr32 = nofpexcept MULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[MULSSrr:%[0-9]+]]:vr128 = nofpexcept MULSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[MULSSrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fmul_float
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; AVX: %4:fr32 = nofpexcept VMULSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VMULSSrr:%[0-9]+]]:vr128 = nofpexcept VMULSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VMULSSrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fmul_float
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512F: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VMULSSZrr:%[0-9]+]]:vr128x = nofpexcept VMULSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VMULSSZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fmul_float
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512VL: %4:fr32x = nofpexcept VMULSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VMULSSZrr:%[0-9]+]]:vr128x = nofpexcept VMULSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VMULSSZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -109,41 +108,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fmul_double
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; SSE: %4:fr64 = nofpexcept MULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[MULSDrr:%[0-9]+]]:vr128 = nofpexcept MULSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[MULSDrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fmul_double
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; AVX: %4:fr64 = nofpexcept VMULSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VMULSDrr:%[0-9]+]]:vr128 = nofpexcept VMULSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VMULSDrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fmul_double
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512F: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VMULSDZrr:%[0-9]+]]:vr128x = nofpexcept VMULSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VMULSDZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fmul_double
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512VL: %4:fr64x = nofpexcept VMULSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VMULSDZrr:%[0-9]+]]:vr128x = nofpexcept VMULSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VMULSDZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
index 05ade0e2c6c99c..f297bc1ff0183d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
@@ -28,12 +28,12 @@ body: |
liveins: $xmm0
; ALL-LABEL: name: test
- ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; ALL: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; ALL: %2:fr64 = nofpexcept CVTSS2SDrr [[COPY1]], implicit $mxcsr
- ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY %2
- ; ALL: $xmm0 = COPY [[COPY2]]
- ; ALL: RET 0, implicit $xmm0
+ ; ALL: liveins: $xmm0
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; ALL-NEXT: [[CVTSS2SDrr:%[0-9]+]]:vr128 = nofpexcept CVTSS2SDrr [[COPY]], implicit $mxcsr
+ ; ALL-NEXT: $xmm0 = COPY [[CVTSS2SDrr]]
+ ; ALL-NEXT: RET 0, implicit $xmm0
%1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128)
%2:vecr(s64) = G_FPEXT %0(s32)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir
index 9ad08072ae5375..ffa82610e093a7 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir
@@ -25,12 +25,11 @@ body: |
; ALL-LABEL: name: test_fptrunc
; ALL: liveins: $xmm0
- ; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; ALL: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; ALL: %2:fr32 = nofpexcept CVTSD2SSrr [[COPY1]], implicit $mxcsr
- ; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY %2
- ; ALL: $xmm0 = COPY [[COPY2]]
- ; ALL: RET 0, implicit $xmm0
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; ALL-NEXT: [[CVTSD2SSrr:%[0-9]+]]:vr128 = nofpexcept CVTSD2SSrr [[COPY]], implicit $mxcsr
+ ; ALL-NEXT: $xmm0 = COPY [[CVTSD2SSrr]]
+ ; ALL-NEXT: RET 0, implicit $xmm0
%1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128)
%2:vecr(s32) = G_FPTRUNC %0(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
index 5a8f01a914250b..d3faa881bc2777 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
@@ -40,41 +40,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fsub_float
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; SSE: %4:fr32 = nofpexcept SUBSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[SUBSSrr:%[0-9]+]]:vr128 = nofpexcept SUBSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[SUBSSrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fsub_float
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr32 = COPY [[COPY2]]
- ; AVX: %4:fr32 = nofpexcept VSUBSSrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VSUBSSrr:%[0-9]+]]:vr128 = nofpexcept VSUBSSrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VSUBSSrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fsub_float
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512F: %4:fr32x = nofpexcept VSUBSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VSUBSSZrr:%[0-9]+]]:vr128x = nofpexcept VSUBSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VSUBSSZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fsub_float
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr32x = COPY [[COPY2]]
- ; AVX512VL: %4:fr32x = nofpexcept VSUBSSZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VSUBSSZrr:%[0-9]+]]:vr128x = nofpexcept VSUBSSZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VSUBSSZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
@@ -109,41 +108,40 @@ body: |
liveins: $xmm0, $xmm1
; SSE-LABEL: name: test_fsub_double
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; SSE: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; SSE: %4:fr64 = nofpexcept SUBSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; SSE: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; SSE: $xmm0 = COPY [[COPY4]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $xmm0, $xmm1
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; SSE-NEXT: [[SUBSDrr:%[0-9]+]]:vr128 = nofpexcept SUBSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; SSE-NEXT: $xmm0 = COPY [[SUBSDrr]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_fsub_double
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
- ; AVX: [[COPY3:%[0-9]+]]:fr64 = COPY [[COPY2]]
- ; AVX: %4:fr64 = nofpexcept VSUBSDrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX: [[COPY4:%[0-9]+]]:vr128 = COPY %4
- ; AVX: $xmm0 = COPY [[COPY4]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $xmm0, $xmm1
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
+ ; AVX-NEXT: [[VSUBSDrr:%[0-9]+]]:vr128 = nofpexcept VSUBSDrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX-NEXT: $xmm0 = COPY [[VSUBSDrr]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_fsub_double
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512F: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512F: %4:fr64x = nofpexcept VSUBSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512F: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512F: $xmm0 = COPY [[COPY4]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $xmm0, $xmm1
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512F-NEXT: [[VSUBSDZrr:%[0-9]+]]:vr128x = nofpexcept VSUBSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512F-NEXT: $xmm0 = COPY [[VSUBSDZrr]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_fsub_double
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY $xmm1
- ; AVX512VL: [[COPY3:%[0-9]+]]:fr64x = COPY [[COPY2]]
- ; AVX512VL: %4:fr64x = nofpexcept VSUBSDZrr [[COPY1]], [[COPY3]], implicit $mxcsr
- ; AVX512VL: [[COPY4:%[0-9]+]]:vr128x = COPY %4
- ; AVX512VL: $xmm0 = COPY [[COPY4]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $xmm0, $xmm1
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
+ ; AVX512VL-NEXT: [[VSUBSDZrr:%[0-9]+]]:vr128x = nofpexcept VSUBSDZrr [[COPY]], [[COPY1]], implicit $mxcsr
+ ; AVX512VL-NEXT: $xmm0 = COPY [[VSUBSDZrr]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%3:vecr(s128) = COPY $xmm1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir
index e173557791202b..3cef86e37b5187 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir
@@ -112,25 +112,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i8
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
- ; SSE: $al = COPY [[MOV8rm]]
- ; SSE: RET 0, implicit $al
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
+ ; SSE-NEXT: $al = COPY [[MOV8rm]]
+ ; SSE-NEXT: RET 0, implicit $al
+ ;
; AVX-LABEL: name: test_load_i8
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
- ; AVX: $al = COPY [[MOV8rm]]
- ; AVX: RET 0, implicit $al
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
+ ; AVX-NEXT: $al = COPY [[MOV8rm]]
+ ; AVX-NEXT: RET 0, implicit $al
+ ;
; AVX512F-LABEL: name: test_load_i8
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
- ; AVX512F: $al = COPY [[MOV8rm]]
- ; AVX512F: RET 0, implicit $al
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
+ ; AVX512F-NEXT: $al = COPY [[MOV8rm]]
+ ; AVX512F-NEXT: RET 0, implicit $al
+ ;
; AVX512VL-LABEL: name: test_load_i8
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
- ; AVX512VL: $al = COPY [[MOV8rm]]
- ; AVX512VL: RET 0, implicit $al
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s8) from %ir.p1)
+ ; AVX512VL-NEXT: $al = COPY [[MOV8rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $al
%0(p0) = COPY $rdi
%1(s8) = G_LOAD %0(p0) :: (load unordered (s8) from %ir.p1)
$al = COPY %1(s8)
@@ -150,25 +161,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i16
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
- ; SSE: $ax = COPY [[MOV16rm]]
- ; SSE: RET 0, implicit $ax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
+ ; SSE-NEXT: $ax = COPY [[MOV16rm]]
+ ; SSE-NEXT: RET 0, implicit $ax
+ ;
; AVX-LABEL: name: test_load_i16
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
- ; AVX: $ax = COPY [[MOV16rm]]
- ; AVX: RET 0, implicit $ax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
+ ; AVX-NEXT: $ax = COPY [[MOV16rm]]
+ ; AVX-NEXT: RET 0, implicit $ax
+ ;
; AVX512F-LABEL: name: test_load_i16
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
- ; AVX512F: $ax = COPY [[MOV16rm]]
- ; AVX512F: RET 0, implicit $ax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
+ ; AVX512F-NEXT: $ax = COPY [[MOV16rm]]
+ ; AVX512F-NEXT: RET 0, implicit $ax
+ ;
; AVX512VL-LABEL: name: test_load_i16
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
- ; AVX512VL: $ax = COPY [[MOV16rm]]
- ; AVX512VL: RET 0, implicit $ax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s16) from %ir.p1)
+ ; AVX512VL-NEXT: $ax = COPY [[MOV16rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $ax
%0(p0) = COPY $rdi
%1(s16) = G_LOAD %0(p0) :: (load unordered (s16) from %ir.p1)
$ax = COPY %1(s16)
@@ -188,25 +210,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i32
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; SSE: $eax = COPY [[MOV32rm]]
- ; SSE: RET 0, implicit $eax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; SSE-NEXT: $eax = COPY [[MOV32rm]]
+ ; SSE-NEXT: RET 0, implicit $eax
+ ;
; AVX-LABEL: name: test_load_i32
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX: $eax = COPY [[MOV32rm]]
- ; AVX: RET 0, implicit $eax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX-NEXT: RET 0, implicit $eax
+ ;
; AVX512F-LABEL: name: test_load_i32
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX512F: $eax = COPY [[MOV32rm]]
- ; AVX512F: RET 0, implicit $eax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX512F-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: RET 0, implicit $eax
+ ;
; AVX512VL-LABEL: name: test_load_i32
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX512VL: $eax = COPY [[MOV32rm]]
- ; AVX512VL: RET 0, implicit $eax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX512VL-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = G_LOAD %0(p0) :: (load unordered (s32) from %ir.p1)
$eax = COPY %1(s32)
@@ -226,25 +259,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i64
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; SSE: $rax = COPY [[MOV64rm]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[MOV64rm]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_load_i64
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX: $rax = COPY [[MOV64rm]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_load_i64
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX512F: $rax = COPY [[MOV64rm]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_load_i64
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX512VL: $rax = COPY [[MOV64rm]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(p0) = COPY $rdi
%1(s64) = G_LOAD %0(p0) :: (load unordered (s64) from %ir.p1)
$rax = COPY %1(s64)
@@ -266,33 +310,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_float
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_float
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_float
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_float
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s32) = G_LOAD %0(p0) :: (load unordered (s32) from %ir.p1)
%3:vecr(s32) = COPY %1(s32)
@@ -316,33 +367,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_float_vecreg
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_float_vecreg
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_float_vecreg
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_float_vecreg
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s32) = G_LOAD %0(p0) :: (load unordered (s32) from %ir.p1)
%3:vecr(s32) = COPY %1(s32)
@@ -366,33 +424,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_double
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_double
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_double
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_double
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s64) = G_LOAD %0(p0) :: (load unordered (s64) from %ir.p1)
%3:vecr(s64) = COPY %1(s64)
@@ -416,33 +481,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_double_vecreg
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_double_vecreg
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_double_vecreg
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_double_vecreg
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (s64) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s64) = G_LOAD %0(p0) :: (load unordered (s64) from %ir.p1)
%3:vecr(s64) = COPY %1(s64)
@@ -464,29 +536,40 @@ body: |
liveins: $edi, $rsi
; SSE-LABEL: name: test_store_i32
- ; SSE: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; SSE: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
- ; SSE: $rax = COPY [[COPY1]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $edi, $rsi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; SSE-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_i32
- ; AVX: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
- ; AVX: $rax = COPY [[COPY1]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $edi, $rsi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_i32
- ; AVX512F: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512F: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY1]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $edi, $rsi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512F-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_i32
- ; AVX512VL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512VL: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY1]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $edi, $rsi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512VL-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s32) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(s32) = COPY $edi
%1(p0) = COPY $rsi
G_STORE %0(s32), %1(p0) :: (store unordered (s32) into %ir.p1)
@@ -507,29 +590,40 @@ body: |
liveins: $rdi, $rsi
; SSE-LABEL: name: test_store_i64
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; SSE: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
- ; SSE: $rax = COPY [[COPY1]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $rsi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; SSE-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_i64
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
- ; AVX: $rax = COPY [[COPY1]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $rsi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_i64
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512F: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY1]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $rsi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512F-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_i64
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512VL: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY1]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $rsi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512VL-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store unordered (s64) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(p0) = COPY $rsi
G_STORE %0(s64), %1(p0) :: (store unordered (s64) into %ir.p1)
@@ -552,37 +646,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_float
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; SSE: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; SSE-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_float
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_float
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512F: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_float
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512VL: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -607,37 +708,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_float_vec
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; SSE: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; SSE-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_float_vec
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_float_vec
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512F: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_float_vec
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512VL: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s32) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s32) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -663,37 +771,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_double
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; SSE: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; SSE-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_double
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_double
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512F: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_double
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512VL: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -718,37 +833,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_double_vec
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; SSE: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; SSE-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_double_vec
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_double_vec
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512F: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_double_vec
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512VL: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store unordered (s64) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store unordered (s64) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -772,25 +894,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_ptr
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
- ; SSE: $rax = COPY [[MOV64rm]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
+ ; SSE-NEXT: $rax = COPY [[MOV64rm]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_load_ptr
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
- ; AVX: $rax = COPY [[MOV64rm]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
+ ; AVX-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_load_ptr
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
- ; AVX512F: $rax = COPY [[MOV64rm]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
+ ; AVX512F-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_load_ptr
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
- ; AVX512VL: $rax = COPY [[MOV64rm]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load unordered (p0) from %ir.ptr1)
+ ; AVX512VL-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(p0) = COPY $rdi
%1(p0) = G_LOAD %0(p0) :: (load unordered (p0) from %ir.ptr1)
$rax = COPY %1(p0)
@@ -811,25 +944,36 @@ body: |
liveins: $rdi, $rsi
; SSE-LABEL: name: test_store_ptr
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; SSE: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
- ; SSE: RET 0
+ ; SSE: liveins: $rdi, $rsi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; SSE-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
+ ; SSE-NEXT: RET 0
+ ;
; AVX-LABEL: name: test_store_ptr
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
- ; AVX: RET 0
+ ; AVX: liveins: $rdi, $rsi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
+ ; AVX-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_store_ptr
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512F: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
- ; AVX512F: RET 0
+ ; AVX512F: liveins: $rdi, $rsi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512F-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
+ ; AVX512F-NEXT: RET 0
+ ;
; AVX512VL-LABEL: name: test_store_ptr
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512VL: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
- ; AVX512VL: RET 0
+ ; AVX512VL: liveins: $rdi, $rsi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512VL-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (p0) into %ir.ptr1)
+ ; AVX512VL-NEXT: RET 0
%0(p0) = COPY $rdi
%1(p0) = COPY $rsi
G_STORE %1(p0), %0(p0) :: (store unordered (p0) into %ir.ptr1)
@@ -852,33 +996,44 @@ body: |
liveins: $esi, $rdi
; SSE-LABEL: name: test_gep_folding
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; SSE: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; SSE: $eax = COPY [[MOV32rm]]
- ; SSE: RET 0, implicit $eax
+ ; SSE: liveins: $esi, $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; SSE-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; SSE-NEXT: $eax = COPY [[MOV32rm]]
+ ; SSE-NEXT: RET 0, implicit $eax
+ ;
; AVX-LABEL: name: test_gep_folding
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; AVX: $eax = COPY [[MOV32rm]]
- ; AVX: RET 0, implicit $eax
+ ; AVX: liveins: $esi, $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; AVX-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX-NEXT: RET 0, implicit $eax
+ ;
; AVX512F-LABEL: name: test_gep_folding
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512F: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; AVX512F: $eax = COPY [[MOV32rm]]
- ; AVX512F: RET 0, implicit $eax
+ ; AVX512F: liveins: $esi, $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512F-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; AVX512F-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: RET 0, implicit $eax
+ ;
; AVX512VL-LABEL: name: test_gep_folding
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512VL: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; AVX512VL: $eax = COPY [[MOV32rm]]
- ; AVX512VL: RET 0, implicit $eax
+ ; AVX512VL: liveins: $esi, $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512VL-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; AVX512VL-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = COPY $esi
%2(s64) = G_CONSTANT i64 20
@@ -905,41 +1060,52 @@ body: |
liveins: $esi, $rdi
; SSE-LABEL: name: test_gep_folding_largeGepIndex
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; SSE: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; SSE: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; SSE: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; SSE: $eax = COPY [[MOV32rm]]
- ; SSE: RET 0, implicit $eax
+ ; SSE: liveins: $esi, $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; SSE-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; SSE-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; SSE-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; SSE-NEXT: $eax = COPY [[MOV32rm]]
+ ; SSE-NEXT: RET 0, implicit $eax
+ ;
; AVX-LABEL: name: test_gep_folding_largeGepIndex
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; AVX: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; AVX: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; AVX: $eax = COPY [[MOV32rm]]
- ; AVX: RET 0, implicit $eax
+ ; AVX: liveins: $esi, $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; AVX-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; AVX-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; AVX-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX-NEXT: RET 0, implicit $eax
+ ;
; AVX512F-LABEL: name: test_gep_folding_largeGepIndex
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512F: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; AVX512F: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; AVX512F: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; AVX512F: $eax = COPY [[MOV32rm]]
- ; AVX512F: RET 0, implicit $eax
+ ; AVX512F: liveins: $esi, $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512F-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; AVX512F-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; AVX512F-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; AVX512F-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: RET 0, implicit $eax
+ ;
; AVX512VL-LABEL: name: test_gep_folding_largeGepIndex
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512VL: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; AVX512VL: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; AVX512VL: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
- ; AVX512VL: $eax = COPY [[MOV32rm]]
- ; AVX512VL: RET 0, implicit $eax
+ ; AVX512VL: liveins: $esi, $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512VL-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; AVX512VL-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; AVX512VL-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store unordered (s32) into %ir.arrayidx)
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load unordered (s32) from %ir.arrayidx)
+ ; AVX512VL-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = COPY $esi
%2(s64) = G_CONSTANT i64 228719476720
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
index e2c778b702f4d3..5d30b41a0ed93a 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
@@ -112,25 +112,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i8
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
- ; SSE: $al = COPY [[MOV8rm]]
- ; SSE: RET 0, implicit $al
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
+ ; SSE-NEXT: $al = COPY [[MOV8rm]]
+ ; SSE-NEXT: RET 0, implicit $al
+ ;
; AVX-LABEL: name: test_load_i8
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
- ; AVX: $al = COPY [[MOV8rm]]
- ; AVX: RET 0, implicit $al
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
+ ; AVX-NEXT: $al = COPY [[MOV8rm]]
+ ; AVX-NEXT: RET 0, implicit $al
+ ;
; AVX512F-LABEL: name: test_load_i8
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
- ; AVX512F: $al = COPY [[MOV8rm]]
- ; AVX512F: RET 0, implicit $al
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
+ ; AVX512F-NEXT: $al = COPY [[MOV8rm]]
+ ; AVX512F-NEXT: RET 0, implicit $al
+ ;
; AVX512VL-LABEL: name: test_load_i8
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
- ; AVX512VL: $al = COPY [[MOV8rm]]
- ; AVX512VL: RET 0, implicit $al
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.p1)
+ ; AVX512VL-NEXT: $al = COPY [[MOV8rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $al
%0(p0) = COPY $rdi
%1(s8) = G_LOAD %0(p0) :: (load (s8) from %ir.p1)
$al = COPY %1(s8)
@@ -150,25 +161,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i16
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
- ; SSE: $ax = COPY [[MOV16rm]]
- ; SSE: RET 0, implicit $ax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
+ ; SSE-NEXT: $ax = COPY [[MOV16rm]]
+ ; SSE-NEXT: RET 0, implicit $ax
+ ;
; AVX-LABEL: name: test_load_i16
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
- ; AVX: $ax = COPY [[MOV16rm]]
- ; AVX: RET 0, implicit $ax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
+ ; AVX-NEXT: $ax = COPY [[MOV16rm]]
+ ; AVX-NEXT: RET 0, implicit $ax
+ ;
; AVX512F-LABEL: name: test_load_i16
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
- ; AVX512F: $ax = COPY [[MOV16rm]]
- ; AVX512F: RET 0, implicit $ax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
+ ; AVX512F-NEXT: $ax = COPY [[MOV16rm]]
+ ; AVX512F-NEXT: RET 0, implicit $ax
+ ;
; AVX512VL-LABEL: name: test_load_i16
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
- ; AVX512VL: $ax = COPY [[MOV16rm]]
- ; AVX512VL: RET 0, implicit $ax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s16) from %ir.p1)
+ ; AVX512VL-NEXT: $ax = COPY [[MOV16rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $ax
%0(p0) = COPY $rdi
%1(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.p1)
$ax = COPY %1(s16)
@@ -188,25 +210,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i32
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; SSE: $eax = COPY [[MOV32rm]]
- ; SSE: RET 0, implicit $eax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; SSE-NEXT: $eax = COPY [[MOV32rm]]
+ ; SSE-NEXT: RET 0, implicit $eax
+ ;
; AVX-LABEL: name: test_load_i32
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX: $eax = COPY [[MOV32rm]]
- ; AVX: RET 0, implicit $eax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX-NEXT: RET 0, implicit $eax
+ ;
; AVX512F-LABEL: name: test_load_i32
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX512F: $eax = COPY [[MOV32rm]]
- ; AVX512F: RET 0, implicit $eax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX512F-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: RET 0, implicit $eax
+ ;
; AVX512VL-LABEL: name: test_load_i32
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX512VL: $eax = COPY [[MOV32rm]]
- ; AVX512VL: RET 0, implicit $eax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX512VL-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p1)
$eax = COPY %1(s32)
@@ -226,25 +259,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_i64
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; SSE: $rax = COPY [[MOV64rm]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[MOV64rm]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_load_i64
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX: $rax = COPY [[MOV64rm]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_load_i64
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX512F: $rax = COPY [[MOV64rm]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_load_i64
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX512VL: $rax = COPY [[MOV64rm]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(p0) = COPY $rdi
%1(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.p1)
$rax = COPY %1(s64)
@@ -266,33 +310,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_float
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_float
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_float
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_float
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p1)
%3:vecr(s32) = COPY %1(s32)
@@ -316,33 +367,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_float_vecreg
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_float_vecreg
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[MOV32rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV32rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_float_vecreg
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_float_vecreg
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[MOV32rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.p1)
%3:vecr(s32) = COPY %1(s32)
@@ -366,33 +424,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_double
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_double
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_double
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_double
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.p1)
%3:vecr(s64) = COPY %1(s64)
@@ -416,33 +481,40 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_double_vecreg
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; SSE: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; SSE: $xmm0 = COPY [[COPY2]]
- ; SSE: RET 0, implicit $xmm0
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; SSE-NEXT: $xmm0 = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $xmm0
+ ;
; AVX-LABEL: name: test_load_double_vecreg
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[MOV64rm]]
- ; AVX: [[COPY2:%[0-9]+]]:vr128 = COPY [[COPY1]]
- ; AVX: $xmm0 = COPY [[COPY2]]
- ; AVX: RET 0, implicit $xmm0
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[MOV64rm]]
+ ; AVX-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512F-LABEL: name: test_load_double_vecreg
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512F: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512F: $xmm0 = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $xmm0
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $xmm0
+ ;
; AVX512VL-LABEL: name: test_load_double_vecreg
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[MOV64rm]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:vr128x = COPY [[COPY1]]
- ; AVX512VL: $xmm0 = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $xmm0
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.p1)
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: $xmm0 = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $xmm0
%0:gpr(p0) = COPY $rdi
%1:gpr(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.p1)
%3:vecr(s64) = COPY %1(s64)
@@ -464,29 +536,40 @@ body: |
liveins: $edi, $rsi
; SSE-LABEL: name: test_store_i32
- ; SSE: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; SSE: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
- ; SSE: $rax = COPY [[COPY1]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $edi, $rsi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; SSE-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_i32
- ; AVX: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
- ; AVX: $rax = COPY [[COPY1]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $edi, $rsi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_i32
- ; AVX512F: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512F: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY1]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $edi, $rsi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512F-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_i32
- ; AVX512VL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512VL: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY1]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $edi, $rsi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512VL-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s32) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(s32) = COPY $edi
%1(p0) = COPY $rsi
G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.p1)
@@ -507,29 +590,40 @@ body: |
liveins: $rdi, $rsi
; SSE-LABEL: name: test_store_i64
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; SSE: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
- ; SSE: $rax = COPY [[COPY1]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $rsi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; SSE-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_i64
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
- ; AVX: $rax = COPY [[COPY1]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $rsi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_i64
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512F: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY1]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $rsi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512F-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_i64
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512VL: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY1]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $rsi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512VL-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (s64) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(p0) = COPY $rsi
G_STORE %0(s64), %1(p0) :: (store (s64) into %ir.p1)
@@ -552,37 +646,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_float
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; SSE: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; SSE-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_float
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_float
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512F: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_float
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512VL: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -607,37 +708,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_float_vec
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; SSE: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; SSE-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_float_vec
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_float_vec
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512F: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_float_vec
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY1]]
- ; AVX512VL: MOV32mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s32) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV32mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s32) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -663,37 +771,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_double
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; SSE: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; SSE-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_double
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_double
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512F: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_double
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512VL: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -718,37 +833,44 @@ body: |
liveins: $rdi, $xmm0
; SSE-LABEL: name: test_store_double_vec
- ; SSE: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; SSE: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; SSE: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; SSE: $rax = COPY [[COPY2]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi, $xmm0
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; SSE-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; SSE-NEXT: $rax = COPY [[COPY1]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_store_double_vec
- ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; AVX: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; AVX: $rax = COPY [[COPY2]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi, $xmm0
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; AVX-NEXT: $rax = COPY [[COPY1]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_store_double_vec
- ; AVX512F: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512F: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512F: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; AVX512F: $rax = COPY [[COPY2]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi, $xmm0
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512F-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; AVX512F-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_store_double_vec
- ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
- ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY [[COPY]]
- ; AVX512VL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY1]]
- ; AVX512VL: MOV64mr [[COPY2]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s64) into %ir.p1)
- ; AVX512VL: $rax = COPY [[COPY2]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi, $xmm0
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY]]
+ ; AVX512VL-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY2]] :: (store (s64) into %ir.p1)
+ ; AVX512VL-NEXT: $rax = COPY [[COPY1]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%2:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %2(s128)
%1:gpr(p0) = COPY $rdi
@@ -772,25 +894,36 @@ body: |
liveins: $rdi
; SSE-LABEL: name: test_load_ptr
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
- ; SSE: $rax = COPY [[MOV64rm]]
- ; SSE: RET 0, implicit $rax
+ ; SSE: liveins: $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
+ ; SSE-NEXT: $rax = COPY [[MOV64rm]]
+ ; SSE-NEXT: RET 0, implicit $rax
+ ;
; AVX-LABEL: name: test_load_ptr
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
- ; AVX: $rax = COPY [[MOV64rm]]
- ; AVX: RET 0, implicit $rax
+ ; AVX: liveins: $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
+ ; AVX-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX-NEXT: RET 0, implicit $rax
+ ;
; AVX512F-LABEL: name: test_load_ptr
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
- ; AVX512F: $rax = COPY [[MOV64rm]]
- ; AVX512F: RET 0, implicit $rax
+ ; AVX512F: liveins: $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
+ ; AVX512F-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512F-NEXT: RET 0, implicit $rax
+ ;
; AVX512VL-LABEL: name: test_load_ptr
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
- ; AVX512VL: $rax = COPY [[MOV64rm]]
- ; AVX512VL: RET 0, implicit $rax
+ ; AVX512VL: liveins: $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (p0) from %ir.ptr1)
+ ; AVX512VL-NEXT: $rax = COPY [[MOV64rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $rax
%0(p0) = COPY $rdi
%1(p0) = G_LOAD %0(p0) :: (load (p0) from %ir.ptr1)
$rax = COPY %1(p0)
@@ -811,25 +944,36 @@ body: |
liveins: $rdi, $rsi
; SSE-LABEL: name: test_store_ptr
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; SSE: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
- ; SSE: RET 0
+ ; SSE: liveins: $rdi, $rsi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; SSE-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
+ ; SSE-NEXT: RET 0
+ ;
; AVX-LABEL: name: test_store_ptr
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
- ; AVX: RET 0
+ ; AVX: liveins: $rdi, $rsi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
+ ; AVX-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_store_ptr
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512F: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
- ; AVX512F: RET 0
+ ; AVX512F: liveins: $rdi, $rsi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512F-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
+ ; AVX512F-NEXT: RET 0
+ ;
; AVX512VL-LABEL: name: test_store_ptr
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; AVX512VL: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
- ; AVX512VL: RET 0
+ ; AVX512VL: liveins: $rdi, $rsi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; AVX512VL-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (p0) into %ir.ptr1)
+ ; AVX512VL-NEXT: RET 0
%0(p0) = COPY $rdi
%1(p0) = COPY $rsi
G_STORE %1(p0), %0(p0) :: (store (p0) into %ir.ptr1)
@@ -852,33 +996,44 @@ body: |
liveins: $esi, $rdi
; SSE-LABEL: name: test_gep_folding
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; SSE: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
- ; SSE: $eax = COPY [[MOV32rm]]
- ; SSE: RET 0, implicit $eax
+ ; SSE: liveins: $esi, $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; SSE-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
+ ; SSE-NEXT: $eax = COPY [[MOV32rm]]
+ ; SSE-NEXT: RET 0, implicit $eax
+ ;
; AVX-LABEL: name: test_gep_folding
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
- ; AVX: $eax = COPY [[MOV32rm]]
- ; AVX: RET 0, implicit $eax
+ ; AVX: liveins: $esi, $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
+ ; AVX-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX-NEXT: RET 0, implicit $eax
+ ;
; AVX512F-LABEL: name: test_gep_folding
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512F: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
- ; AVX512F: $eax = COPY [[MOV32rm]]
- ; AVX512F: RET 0, implicit $eax
+ ; AVX512F: liveins: $esi, $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512F-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
+ ; AVX512F-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: RET 0, implicit $eax
+ ;
; AVX512VL-LABEL: name: test_gep_folding
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512VL: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
- ; AVX512VL: $eax = COPY [[MOV32rm]]
- ; AVX512VL: RET 0, implicit $eax
+ ; AVX512VL: liveins: $esi, $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512VL-NEXT: MOV32mr [[COPY]], 1, $noreg, 20, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 20, $noreg :: (load (s32) from %ir.arrayidx)
+ ; AVX512VL-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = COPY $esi
%2(s64) = G_CONSTANT i64 20
@@ -905,41 +1060,52 @@ body: |
liveins: $esi, $rdi
; SSE-LABEL: name: test_gep_folding_largeGepIndex
- ; SSE: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; SSE: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; SSE: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; SSE: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; SSE: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; SSE: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
- ; SSE: $eax = COPY [[MOV32rm]]
- ; SSE: RET 0, implicit $eax
+ ; SSE: liveins: $esi, $rdi
+ ; SSE-NEXT: {{ $}}
+ ; SSE-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; SSE-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; SSE-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; SSE-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; SSE-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; SSE-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
+ ; SSE-NEXT: $eax = COPY [[MOV32rm]]
+ ; SSE-NEXT: RET 0, implicit $eax
+ ;
; AVX-LABEL: name: test_gep_folding_largeGepIndex
- ; AVX: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; AVX: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; AVX: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; AVX: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
- ; AVX: $eax = COPY [[MOV32rm]]
- ; AVX: RET 0, implicit $eax
+ ; AVX: liveins: $esi, $rdi
+ ; AVX-NEXT: {{ $}}
+ ; AVX-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; AVX-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; AVX-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; AVX-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
+ ; AVX-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX-NEXT: RET 0, implicit $eax
+ ;
; AVX512F-LABEL: name: test_gep_folding_largeGepIndex
- ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512F: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512F: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; AVX512F: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; AVX512F: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; AVX512F: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
- ; AVX512F: $eax = COPY [[MOV32rm]]
- ; AVX512F: RET 0, implicit $eax
+ ; AVX512F: liveins: $esi, $rdi
+ ; AVX512F-NEXT: {{ $}}
+ ; AVX512F-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512F-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512F-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; AVX512F-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; AVX512F-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; AVX512F-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
+ ; AVX512F-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512F-NEXT: RET 0, implicit $eax
+ ;
; AVX512VL-LABEL: name: test_gep_folding_largeGepIndex
- ; AVX512VL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; AVX512VL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; AVX512VL: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
- ; AVX512VL: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
- ; AVX512VL: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
- ; AVX512VL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
- ; AVX512VL: $eax = COPY [[MOV32rm]]
- ; AVX512VL: RET 0, implicit $eax
+ ; AVX512VL: liveins: $esi, $rdi
+ ; AVX512VL-NEXT: {{ $}}
+ ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; AVX512VL-NEXT: [[MOV64ri:%[0-9]+]]:gr64_nosp = MOV64ri 228719476720
+ ; AVX512VL-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri]], 0, $noreg
+ ; AVX512VL-NEXT: MOV32mr [[LEA64r]], 1, $noreg, 0, $noreg, [[COPY1]] :: (store (s32) into %ir.arrayidx)
+ ; AVX512VL-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[LEA64r]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.arrayidx)
+ ; AVX512VL-NEXT: $eax = COPY [[MOV32rm]]
+ ; AVX512VL-NEXT: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = COPY $esi
%2(s64) = G_CONSTANT i64 228719476720
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
index 6626131661b220..b830fbf94e9ddc 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
@@ -394,9 +394,7 @@ body: |
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
- ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
- ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
- ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
@@ -407,9 +405,8 @@ body: |
; ALL-NEXT: successors: %bb.2(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.end:
- ; ALL-NEXT: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
- ; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
- ; ALL-NEXT: $xmm0 = COPY [[COPY5]]
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:vr128 = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
+ ; ALL-NEXT: $xmm0 = COPY [[PHI]]
; ALL-NEXT: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
@@ -459,9 +456,7 @@ body: |
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
- ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
- ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
- ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:vr128 = COPY $xmm1
; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
@@ -472,9 +467,8 @@ body: |
; ALL-NEXT: successors: %bb.2(0x80000000)
; ALL-NEXT: {{ $}}
; ALL-NEXT: bb.2.cond.end:
- ; ALL-NEXT: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
- ; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
- ; ALL-NEXT: $xmm0 = COPY [[COPY5]]
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:vr128 = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
+ ; ALL-NEXT: $xmm0 = COPY [[PHI]]
; ALL-NEXT: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir
index 089431724871d7..4e188467f81448 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir
@@ -46,10 +46,12 @@ body: |
liveins: $edi
; CHECK-LABEL: name: trunc_i32toi1
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: $al = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK: liveins: $edi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%0(s32) = COPY $edi
%1(s1) = G_TRUNC %0(s32)
%2(s8) = G_ANYEXT %1(s1)
@@ -70,10 +72,12 @@ body: |
liveins: $edi
; CHECK-LABEL: name: trunc_i32toi8
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: $al = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK: liveins: $edi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%0(s32) = COPY $edi
%1(s8) = G_TRUNC %0(s32)
$al = COPY %1(s8)
@@ -93,10 +97,12 @@ body: |
liveins: $edi
; CHECK-LABEL: name: trunc_i32toi16
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK: $ax = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK: liveins: $edi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%0(s32) = COPY $edi
%1(s16) = G_TRUNC %0(s32)
$ax = COPY %1(s16)
@@ -116,10 +122,12 @@ body: |
liveins: $rdi
; CHECK-LABEL: name: trunc_i64toi8
- ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: $al = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK: liveins: $rdi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%0(s64) = COPY $rdi
%1(s8) = G_TRUNC %0(s64)
$al = COPY %1(s8)
@@ -139,10 +147,12 @@ body: |
liveins: $rdi
; CHECK-LABEL: name: trunc_i64toi16
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK: $ax = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK: liveins: $rdi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%0(s64) = COPY $rdi
%1(s16) = G_TRUNC %0(s64)
$ax = COPY %1(s16)
@@ -162,10 +172,12 @@ body: |
liveins: $rdi
; CHECK-LABEL: name: trunc_i64toi32
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
- ; CHECK: $eax = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $eax
+ ; CHECK: liveins: $rdi
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
+ ; CHECK-NEXT: $eax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%0(s64) = COPY $rdi
%1(s32) = G_TRUNC %0(s64)
$eax = COPY %1(s32)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
index 785cf79ca1db90..ac4d4a9326aa7c 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
@@ -26,12 +26,12 @@ body: |
; ALL-LABEL: name: test_unmerge_v128
; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
- ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
- ; ALL: [[VEXTRACTF32X4Zrri:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 1
- ; ALL: [[VEXTRACTF32X4Zrri1:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 2
- ; ALL: [[VEXTRACTF32X4Zrri2:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 3
- ; ALL: $xmm0 = COPY [[COPY]]
- ; ALL: RET 0, implicit $xmm0
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
+ ; ALL-NEXT: [[VEXTRACTF32X4Zrri:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 1
+ ; ALL-NEXT: [[VEXTRACTF32X4Zrri1:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 2
+ ; ALL-NEXT: [[VEXTRACTF32X4Zrri2:%[0-9]+]]:vr128x = VEXTRACTF32X4Zrri [[DEF]], 3
+ ; ALL-NEXT: $xmm0 = COPY [[COPY]]
+ ; ALL-NEXT: RET 0, implicit $xmm0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
$xmm0 = COPY %1(<4 x s32>)
@@ -52,10 +52,10 @@ body: |
; ALL-LABEL: name: test_unmerge_v256
; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
- ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm
- ; ALL: [[VEXTRACTF64X4Zrri:%[0-9]+]]:vr256x = VEXTRACTF64X4Zrri [[DEF]], 1
- ; ALL: $ymm0 = COPY [[COPY]]
- ; ALL: RET 0, implicit $ymm0
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm
+ ; ALL-NEXT: [[VEXTRACTF64X4Zrri:%[0-9]+]]:vr256x = VEXTRACTF64X4Zrri [[DEF]], 1
+ ; ALL-NEXT: $ymm0 = COPY [[COPY]]
+ ; ALL-NEXT: RET 0, implicit $ymm0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
$ymm0 = COPY %1(<8 x s32>)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
index 768120b2739d64..a3c7de8d9b2a53 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir
@@ -47,9 +47,9 @@ body: |
bb.1.entry:
; CHECK-LABEL: name: ptrtoint_s1_p0
; CHECK: [[MOV32rm:%[0-9]+]]:gr32_abcd = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load (p0) from %fixed-stack.0, align 16)
- ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit
- ; CHECK: $al = COPY [[COPY]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $al
%1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
%0:gpr(p0) = G_LOAD %1(p0) :: (invariant load (p0) from %fixed-stack.0, align 16)
%2:gpr(s1) = G_PTRTOINT %0(p0)
@@ -76,9 +76,9 @@ body: |
bb.1.entry:
; CHECK-LABEL: name: ptrtoint_s8_p0
; CHECK: [[MOV32rm:%[0-9]+]]:gr32_abcd = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load (p0) from %fixed-stack.0, align 16)
- ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit
- ; CHECK: $al = COPY [[COPY]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32rm]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $al
%1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
%0:gpr(p0) = G_LOAD %1(p0) :: (invariant load (p0) from %fixed-stack.0, align 16)
%2:gpr(s8) = G_PTRTOINT %0(p0)
@@ -104,9 +104,9 @@ body: |
bb.1.entry:
; CHECK-LABEL: name: ptrtoint_s16_p0
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load (p0) from %fixed-stack.0, align 16)
- ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY [[MOV32rm]].sub_16bit
- ; CHECK: $ax = COPY [[COPY]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY [[MOV32rm]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
%0:gpr(p0) = G_LOAD %1(p0) :: (invariant load (p0) from %fixed-stack.0, align 16)
%2:gpr(s16) = G_PTRTOINT %0(p0)
@@ -132,8 +132,8 @@ body: |
bb.1.entry:
; CHECK-LABEL: name: ptrtoint_s32_p0
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load (p0) from %fixed-stack.0, align 16)
- ; CHECK: $eax = COPY [[MOV32rm]]
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: $eax = COPY [[MOV32rm]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%1:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
%0:gpr(p0) = G_LOAD %1(p0) :: (invariant load (p0) from %fixed-stack.0, align 16)
%2:gpr(s32) = G_PTRTOINT %0(p0)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir
index e957859161ee6c..c5ed067c25d8b0 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir
@@ -69,12 +69,12 @@ body: |
; CHECK-LABEL: name: float_to_int8
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
- ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit
- ; CHECK: $al = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = nofpexcept CVTTSS2SIrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[CVTTSS2SIrr]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s32)
@@ -100,12 +100,12 @@ body: |
; CHECK-LABEL: name: float_to_int16
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
- ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit
- ; CHECK: $ax = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = nofpexcept CVTTSS2SIrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[CVTTSS2SIrr]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s32)
@@ -130,11 +130,11 @@ body: |
; CHECK-LABEL: name: float_to_int32
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: %2:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr
- ; CHECK: $eax = COPY %2
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = nofpexcept CVTTSS2SIrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $eax = COPY [[CVTTSS2SIrr]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128)
%2:gpr(s32) = G_FPTOSI %0(s32)
@@ -158,11 +158,11 @@ body: |
; CHECK-LABEL: name: float_to_int64
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
- ; CHECK: %2:gr64 = nofpexcept CVTTSS2SI64rr [[COPY1]], implicit $mxcsr
- ; CHECK: $rax = COPY %2
- ; CHECK: RET 0, implicit $rax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSS2SI64rr:%[0-9]+]]:gr64 = nofpexcept CVTTSS2SI64rr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $rax = COPY [[CVTTSS2SI64rr]]
+ ; CHECK-NEXT: RET 0, implicit $rax
%1:vecr(s128) = COPY $xmm0
%0:vecr(s32) = G_TRUNC %1(s128)
%2:gpr(s64) = G_FPTOSI %0(s32)
@@ -187,12 +187,12 @@ body: |
; CHECK-LABEL: name: double_to_int8
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
- ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit
- ; CHECK: $al = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = nofpexcept CVTTSD2SIrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[CVTTSD2SIrr]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s64)
@@ -218,12 +218,12 @@ body: |
; CHECK-LABEL: name: double_to_int16
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
- ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit
- ; CHECK: $ax = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = nofpexcept CVTTSD2SIrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrr]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128)
%3:gpr(s32) = G_FPTOSI %0(s64)
@@ -248,11 +248,11 @@ body: |
; CHECK-LABEL: name: double_to_int32
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: %2:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr
- ; CHECK: $eax = COPY %2
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = nofpexcept CVTTSD2SIrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $eax = COPY [[CVTTSD2SIrr]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128)
%2:gpr(s32) = G_FPTOSI %0(s64)
@@ -276,11 +276,11 @@ body: |
; CHECK-LABEL: name: double_to_int64
; CHECK: liveins: $xmm0
- ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
- ; CHECK: %2:gr64 = nofpexcept CVTTSD2SI64rr [[COPY1]], implicit $mxcsr
- ; CHECK: $rax = COPY %2
- ; CHECK: RET 0, implicit $rax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
+ ; CHECK-NEXT: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = nofpexcept CVTTSD2SI64rr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $rax = COPY [[CVTTSD2SI64rr]]
+ ; CHECK-NEXT: RET 0, implicit $rax
%1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128)
%2:gpr(s64) = G_FPTOSI %0(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir
index 328cf718b2353b..24f455ca0a951c 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir
@@ -50,10 +50,11 @@ body: |
; CHECK-LABEL: name: ptrtoint_s1_p0
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: $al = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%0:gpr(p0) = COPY $rdi
%1:gpr(s1) = G_PTRTOINT %0(p0)
%2:gpr(s8) = G_ANYEXT %1(s1)
@@ -76,10 +77,11 @@ body: |
; CHECK-LABEL: name: ptrtoint_s8_p0
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: $al = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: $al = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $al
%0:gpr(p0) = COPY $rdi
%1:gpr(s8) = G_PTRTOINT %0(p0)
$al = COPY %1(s8)
@@ -101,10 +103,11 @@ body: |
; CHECK-LABEL: name: ptrtoint_s16_p0
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK: $ax = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%0:gpr(p0) = COPY $rdi
%1:gpr(s16) = G_PTRTOINT %0(p0)
$ax = COPY %1(s16)
@@ -126,10 +129,11 @@ body: |
; CHECK-LABEL: name: ptrtoint_s32_p0
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
- ; CHECK: $eax = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
+ ; CHECK-NEXT: $eax = COPY [[COPY1]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%0:gpr(p0) = COPY $rdi
%1:gpr(s32) = G_PTRTOINT %0(p0)
$eax = COPY %1(s32)
@@ -151,9 +155,10 @@ body: |
; CHECK-LABEL: name: ptrtoint_s64_p0
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: $rax = COPY [[COPY]]
- ; CHECK: RET 0, implicit $rax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: $rax = COPY [[COPY]]
+ ; CHECK-NEXT: RET 0, implicit $rax
%0:gpr(p0) = COPY $rdi
%1:gpr(s64) = G_PTRTOINT %0(p0)
$rax = COPY %1(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir
index 8f76ad500491c0..5fe1cf81646927 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir
@@ -60,11 +60,11 @@ body: |
; CHECK-LABEL: name: int32_to_float
; CHECK: liveins: $edi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: %1:fr32 = nofpexcept CVTSI2SSrr [[COPY]], implicit $mxcsr
- ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1
- ; CHECK: $xmm0 = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $xmm0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[CVTSI2SSrr:%[0-9]+]]:vr128 = nofpexcept CVTSI2SSrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $xmm0 = COPY [[CVTSI2SSrr]]
+ ; CHECK-NEXT: RET 0, implicit $xmm0
%0:gpr(s32) = COPY $edi
%1:vecr(s32) = G_SITOFP %0(s32)
%2:vecr(s128) = G_ANYEXT %1(s32)
@@ -88,11 +88,11 @@ body: |
; CHECK-LABEL: name: int64_to_float
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: %1:fr32 = nofpexcept CVTSI642SSrr [[COPY]], implicit $mxcsr
- ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1
- ; CHECK: $xmm0 = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $xmm0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[CVTSI642SSrr:%[0-9]+]]:vr128 = nofpexcept CVTSI642SSrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $xmm0 = COPY [[CVTSI642SSrr]]
+ ; CHECK-NEXT: RET 0, implicit $xmm0
%0:gpr(s64) = COPY $rdi
%1:vecr(s32) = G_SITOFP %0(s64)
%2:vecr(s128) = G_ANYEXT %1(s32)
@@ -116,11 +116,11 @@ body: |
; CHECK-LABEL: name: int32_to_double
; CHECK: liveins: $edi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
- ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]]
- ; CHECK: $xmm0 = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $xmm0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[CVTSI2SDrr:%[0-9]+]]:vr128 = CVTSI2SDrr [[COPY]]
+ ; CHECK-NEXT: $xmm0 = COPY [[CVTSI2SDrr]]
+ ; CHECK-NEXT: RET 0, implicit $xmm0
%0:gpr(s32) = COPY $edi
%1:vecr(s64) = G_SITOFP %0(s32)
%2:vecr(s128) = G_ANYEXT %1(s64)
@@ -144,11 +144,11 @@ body: |
; CHECK-LABEL: name: int64_to_double
; CHECK: liveins: $rdi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: %1:fr64 = nofpexcept CVTSI642SDrr [[COPY]], implicit $mxcsr
- ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1
- ; CHECK: $xmm0 = COPY [[COPY1]]
- ; CHECK: RET 0, implicit $xmm0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[CVTSI642SDrr:%[0-9]+]]:vr128 = nofpexcept CVTSI642SDrr [[COPY]], implicit $mxcsr
+ ; CHECK-NEXT: $xmm0 = COPY [[CVTSI642SDrr]]
+ ; CHECK-NEXT: RET 0, implicit $xmm0
%0:gpr(s64) = COPY $rdi
%1:vecr(s64) = G_SITOFP %0(s64)
%2:vecr(s128) = G_ANYEXT %1(s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
index a685b417a9b52b..96f1c8b01ff7e9 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
@@ -202,11 +202,10 @@ body: |
; CHECK: liveins: $edi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
- ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
- ; CHECK-NEXT: $ax = COPY [[COPY3]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY2]]
; CHECK-NEXT: RET 0, implicit $ax
%1:gpr(s32) = COPY $edi
%3:gpr(s16) = G_CONSTANT i16 255
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