[clang] [llvm] [Clang][RISCV] Add packed widening shift intrinsics (PR #224790)

[Craig Topper via llvm-commits]

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@@ -13089,6 +13089,26 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getNode(getRVPShiftOpcode(IntNo), DL, Op.getValueType(),
                        Op.getOperand(1), ShAmt);
   }
+  case Intrinsic::riscv_pwsll:
+  case Intrinsic::riscv_pwsla: {
+    MVT VT = Op.getSimpleValueType();
+    SDValue Src = Op.getOperand(1);
+    MVT SrcVT = Src.getSimpleValueType();
+    if (!((VT == MVT::v4i16 && SrcVT == MVT::v4i8) ||
+          (VT == MVT::v2i32 && SrcVT == MVT::v2i16)))
+      reportFatalUsageError("unsupported packed widening shift intrinsic");
+
+    SDValue ShAmt = DAG.getAnyExtOrTrunc(Op.getOperand(2), DL, XLenVT);
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topperc wrote:

Will this ever trunc? Can we use DAG.getNode(ISD::ANY_EXTEND?

https://github.com/llvm/llvm-project/pull/224790