[llvm] [ARM] Add combine for vector_interleave operation (PR #225818)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/ARM/ARMISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 93e68bf7c..5d5ee7af7 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -16978,9 +16978,9 @@ static SDValue PerformExtractFpToIntStores(StoreSDNode *St, SelectionDAG &DAG) {
 }
 
 // Combine stores of all VECTOR_INTERLEAVE results into a structured store
-// (vstN) when they access consecutive memory. Running this after type legalization
-// let wider vector types to be splitted into legal types, so each split can form
-// structured store.
+// (vstN) when they access consecutive memory. Running this after type
+// legalization let wider vector types to be splitted into legal types, so each
+// split can form structured store.
 static SDValue PerformLegalizedInterleavedStoreCombine(
     StoreSDNode *ST, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) {
   if (DCI.getDAGCombineLevel() < AfterLegalizeTypes)
@@ -17027,8 +17027,7 @@ static SDValue PerformLegalizedInterleavedStoreCombine(
       DAG.getTargetConstant(NEONStores[NumParts - 2], DL, MVT::i64),
       BaseStore->getBasePtr()};
   Ops.append(Interleave->op_begin(), Interleave->op_end());
-  Ops.push_back(
-      DAG.getConstant(BaseStore->getAlign().value(), DL, MVT::i32));
+  Ops.push_back(DAG.getConstant(BaseStore->getAlign().value(), DL, MVT::i32));
 
   EVT MemVT =
       EVT::getVectorVT(*DAG.getContext(), SubVecTy.getVectorElementType(),
@@ -17075,8 +17074,7 @@ static SDValue PerformInterleavedStoreCombine(
   if (!DCI.isBeforeLegalize())
     return SDValue();
 
-  if (!ISD::isNormalStore(ST) || !ST->isSimple() ||
-      !ST->getOffset().isUndef())
+  if (!ISD::isNormalStore(ST) || !ST->isSimple() || !ST->getOffset().isUndef())
     return SDValue();
 
   SDValue WideValue = ST->getValue();
@@ -17111,12 +17109,11 @@ static SDValue PerformInterleavedStoreCombine(
   Ops.append(ValueInterleaveOps);
   Ops.push_back(DAG.getConstant(ST->getAlign().value(), DL, MVT::i32));
 
-  return DAG.getMemIntrinsicNode(
-      ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops,
-      ST->getMemoryVT(), ST->getMemOperand());
+  return DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, DL,
+                                 DAG.getVTList(MVT::Other), Ops,
+                                 ST->getMemoryVT(), ST->getMemOperand());
 }
 
-
 /// PerformSTORECombine - Target-specific dag combine xforms for
 /// ISD::STORE.
 static SDValue PerformSTORECombine(SDNode *N,

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https://github.com/llvm/llvm-project/pull/225818