[llvm] 0e718a8 - [AMDGPU] Add BarrierLatency mutations to CoexecSched (#200954)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 07:51:02 PDT 2026
Author: Jeffrey Byrnes
Date: 2026-09-23T07:50:53-07:00
New Revision: 0e718a81c3a564de6c4c7193c1bd748f7f96eb29
URL: https://github.com/llvm/llvm-project/commit/0e718a81c3a564de6c4c7193c1bd748f7f96eb29
DIFF: https://github.com/llvm/llvm-project/commit/0e718a81c3a564de6c4c7193c1bd748f7f96eb29.diff
LOG: [AMDGPU] Add BarrierLatency mutations to CoexecSched (#200954)
Change-Id: Id86bbdb427b23f68d39ceee196e4232e91974186
Added:
llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
Modified:
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index 50d444068e01d..8316342be6c89 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "AMDGPUCoExecSchedStrategy.h"
+#include "AMDGPUBarrierLatency.h"
#include "AMDGPUIGroupLP.h"
#include "GCNHazardRecognizer.h"
#include "llvm/Support/Debug.h"
@@ -1349,6 +1350,7 @@ llvm::createGCNCoExecMachineScheduler(MachineSchedContext *C) {
ScheduleDAGMILive *DAG = new GCNScheduleDAGMILive(
C, std::make_unique<AMDGPUCoExecSchedStrategy>(C));
DAG->addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::Initial));
+ DAG->addMutation(createAMDGPUBarrierLatencyDAGMutation(C->MF));
return DAG;
}
diff --git a/llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir b/llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
new file mode 100644
index 0000000000000..e5694cf2d9bd2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
@@ -0,0 +1,177 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=COEXEC %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched --amdgpu-barrier-signal-wait-latency=0 %s -o - | FileCheck -check-prefix=COEXEC-LAT-0 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched --amdgpu-barrier-signal-wait-latency=30 %s -o - | FileCheck -check-prefix=COEXEC-LAT-30 %s
+
+--- |
+ define void @test-sched-signal-wait() #0 { ret void }
+
+ attributes #0 = { "amdgpu-waves-per-eu"="1,1" }
+...
+
+# The coexec-scheduler includes BarrierLatency mutations, thus users have access to the amdgpu-barrier-signal-wait-latency control.
+# The coexec-scheduler gives strong preference to instructions with no outstanding dependent latency, and slightly less strong
+# priority to instructions which participate in memory pipelining. The consequence is that it should prioritize respecting the
+# requested amdgpu-barrier-signal-wait-latency, and schedule the S_BARRIER_WAIT shortly after it is ready. This test should
+# demonstrate how this S_BARRIER_SIGNAL/WAIT scheduling behav
+
+---
+name: test-sched-signal-wait
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+
+ ; COEXEC-LABEL: name: test-sched-signal-wait
+ ; COEXEC: liveins: $sgpr0, $sgpr1
+ ; COEXEC-NEXT: {{ $}}
+ ; COEXEC-NEXT: S_BARRIER_SIGNAL_IMM -1
+ ; COEXEC-NEXT: dead [[S_ADD_I32_:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_1:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_2:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_3:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_4:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_5:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_6:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_7:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_8:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_9:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_10:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_11:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: [[S_ADD_I32_12:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: [[S_ADD_I32_13:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: [[S_ADD_I32_14:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: S_BARRIER_WAIT -1
+ ; COEXEC-NEXT: dead [[S_ADD_I32_15:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_16:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_17:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_18:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_19:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_20:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_21:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_22:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_23:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_24:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_25:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_26:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_27:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_28:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_29:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_30:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: dead [[S_ADD_I32_31:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_12]], implicit [[S_ADD_I32_13]], implicit [[S_ADD_I32_14]]
+ ;
+ ; COEXEC-LAT-0-LABEL: name: test-sched-signal-wait
+ ; COEXEC-LAT-0: liveins: $sgpr0, $sgpr1
+ ; COEXEC-LAT-0-NEXT: {{ $}}
+ ; COEXEC-LAT-0-NEXT: S_BARRIER_SIGNAL_IMM -1
+ ; COEXEC-LAT-0-NEXT: S_BARRIER_WAIT -1
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_1:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_2:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_3:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_4:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_5:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_6:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_7:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_8:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_9:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_10:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_11:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: [[S_ADD_I32_12:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: [[S_ADD_I32_13:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: [[S_ADD_I32_14:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_15:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_16:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_17:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_18:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_19:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_20:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_21:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_22:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_23:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_24:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_25:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_26:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_27:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_28:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_29:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_30:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: dead [[S_ADD_I32_31:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-0-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_12]], implicit [[S_ADD_I32_13]], implicit [[S_ADD_I32_14]]
+ ;
+ ; COEXEC-LAT-30-LABEL: name: test-sched-signal-wait
+ ; COEXEC-LAT-30: liveins: $sgpr0, $sgpr1
+ ; COEXEC-LAT-30-NEXT: {{ $}}
+ ; COEXEC-LAT-30-NEXT: S_BARRIER_SIGNAL_IMM -1
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_1:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_2:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_3:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_4:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_5:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_6:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_7:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_8:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_9:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_10:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_11:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: [[S_ADD_I32_12:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: [[S_ADD_I32_13:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: [[S_ADD_I32_14:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_15:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_16:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_17:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_18:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_19:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_20:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_21:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_22:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_23:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_24:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_25:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_26:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_27:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_28:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: S_BARRIER_WAIT -1
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_29:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_30:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: dead [[S_ADD_I32_31:%[0-9]+]]:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ ; COEXEC-LAT-30-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_12]], implicit [[S_ADD_I32_13]], implicit [[S_ADD_I32_14]]
+ %0:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %1:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %2:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %3:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %4:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %5:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %6:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %7:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %8:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %9:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %10:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %11:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %12:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %13:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %14:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %15:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %16:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %17:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %18:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %19:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %20:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %21:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %22:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %23:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %24:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %25:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %26:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %27:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %28:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %29:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %30:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ %31:sgpr_32 = S_ADD_I32 $sgpr0, $sgpr1, implicit-def dead $scc
+ S_BARRIER_SIGNAL_IMM -1
+ S_BARRIER_WAIT -1
+ S_ENDPGM 0, implicit %12, implicit %13, implicit %14
+...
+
diff --git a/llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir b/llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
index e2c0e4567391a..c1ab2cb7a1526 100644
--- a/llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
+++ b/llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
@@ -176,6 +176,7 @@ body: |
; DEFAULT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
+ ; DEFAULT-NEXT: S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
@@ -184,7 +185,6 @@ body: |
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
- ; DEFAULT-NEXT: S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
; DEFAULT-NEXT: S_ENDPGM 0
;
; MAXOCC-LABEL: name: tensor_load_tensor_wait
@@ -275,6 +275,7 @@ body: |
; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
+ ; DEFAULT-NEXT: S_WAIT_TENSORCNT 1, implicit-def dead $tensorcnt, implicit $tensorcnt
; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
@@ -283,7 +284,6 @@ body: |
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
- ; DEFAULT-NEXT: S_WAIT_TENSORCNT 1, implicit-def dead $tensorcnt, implicit $tensorcnt
; DEFAULT-NEXT: S_ENDPGM 0
;
; MAXOCC-LABEL: name: tensor_load_tensor_wait2
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