[llvm] [DAG][X86] Bitfield insertion can combine into SHL + SHRD (PR #220182)

[Simon Pilgrim via llvm-commits]

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@@ -32352,8 +32352,49 @@ static SDValue LowerFunnelShift(SDValue Op, const X86Subtarget &Subtarget,
     return DAG.getZExtOrTrunc(Res, DL, VT);
   }
 
-  if (VT == MVT::i8 || ExpandFunnel)
-    return SDValue();
+  // Following fold is done in DAGCombiner:
+  //
+  // (or (and X, Mask), (shl Y, MaskBitNum)) -> (fshr X, (shl Y,
+  // (MaxWideNumBits - MaskBitNum)))
+  //
+  // Reverse this fold if funnel shifts is slow and if we are not optimizing
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RKSimon wrote:

I'm still kind of surprised we still have to do this - I'd expect folds after the expansion would clean it up?

https://github.com/llvm/llvm-project/pull/220182