[llvm] [AMDGPU][NFC] Explicitly narrow conversions in frame and register handling (PR #215203)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 06:49:24 PDT 2026
https://github.com/gretay-amd updated https://github.com/llvm/llvm-project/pull/215203
>From 6906e18b6d540767a027c4db6dc9bf822674f986 Mon Sep 17 00:00:00 2001
From: Greta Y <Greta.Yorsh at amd.com>
Date: Thu, 6 Aug 2026 16:15:16 +0100
Subject: [PATCH] [AMDGPU][NFC] Explicitly narrow conversions in frame and
register handling
This patch handles the following cases:
Frame offsets and object sizes are int64_t or uint64_t (MachineFrameInfo) and
are assigned to 32-bit locals or passed to 32-bit parameters. Add a static_cast
to make the existing narrowing conversion explicit. These are scratch offsets
within one function's frame, which the scratch instruction encodings already
limit to well under 2^32.
Register values are stored into MCPhysReg (uint16_t): the register-allocation
hint list in SIRegisterInfo::getRegAllocationHints, the MCPhysReg locals of
SIRegisterInfo::get32BitRegister and SIFrameLowering, and the callee-saved and
user-SGPR queries in SIMachineFunctionInfo. Add a static_cast. Each of these
values is physical -- the hint sites take a subreg or superreg of a register
already established as physical (Paired.isPhysical() or VRM->getPhys(Paired) on
the lines above), get32BitRegister both takes and returns MCPhysReg, and the
others are scratch or ABI registers.
Container size() returns size_t and is assigned to unsigned or int locals
holding spill-slot and register-tuple counts. Add a static_cast to make the
existing narrowing conversion explicit.
Bit-field and fixed-width members of SIMachineFunctionInfo and the register-info
tables are declared uint8_t, uint16_t or uint32_t and assigned from wider
values. Add a static_cast; the field widths are pre-existing and deliberate.
This fixes 85 instances of MSVC warning C4244 and 7 of C4267 ("possible loss of
data") across 9 files in llvm/lib/Target/AMDGPU.
Assisted-by: Claude <noreply at anthropic.com>
---
.../AMDGPU/AMDGPUMachineFunctionInfo.cpp | 21 +--
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 4 +-
.../AMDGPU/GCNRewritePartialRegUses.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 131 +++++++++++-------
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 4 +-
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 12 +-
.../Target/AMDGPU/SIMachineFunctionInfo.cpp | 26 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 65 +++++----
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 7 +-
9 files changed, 158 insertions(+), 116 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
index 22e9d8ae06b4f9..8f864d07ebb81c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
@@ -121,7 +121,8 @@ unsigned AMDGPUMachineFunctionInfo::allocateLDSGlobal(const DataLayout &DL,
// section, and not within some other non-absolute-address object
// allocated here, but the extra error detection is minimal and we would
// have to pass the Function around or cache the attribute value.
- uint32_t ObjectEnd = ObjectStart + GV.getGlobalSize(DL);
+ uint32_t ObjectEnd =
+ static_cast<uint32_t>(ObjectStart + GV.getGlobalSize(DL));
if (ObjectEnd > StaticLDSSize) {
report_fatal_error(
"Absolute address LDS variable outside of static frame");
@@ -135,18 +136,20 @@ unsigned AMDGPUMachineFunctionInfo::allocateLDSGlobal(const DataLayout &DL,
/// TODO: We should sort these to minimize wasted space due to alignment
/// padding. Currently the padding is decided by the first encountered use
/// during lowering.
- Offset = StaticLDSSize = alignTo(StaticLDSSize, Alignment);
+ Offset = StaticLDSSize =
+ static_cast<uint32_t>(alignTo(StaticLDSSize, Alignment));
- StaticLDSSize += GV.getGlobalSize(DL);
+ StaticLDSSize += static_cast<uint32_t>(GV.getGlobalSize(DL));
// Align LDS size to trailing, e.g. for aligning dynamic shared memory
- LDSSize = alignTo(StaticLDSSize, Trailing);
+ LDSSize = static_cast<uint32_t>(alignTo(StaticLDSSize, Trailing));
} else {
assert(GV.getAddressSpace() == AMDGPUAS::REGION_ADDRESS &&
"expected region address space");
- Offset = StaticGDSSize = alignTo(StaticGDSSize, Alignment);
- StaticGDSSize += GV.getGlobalSize(DL);
+ Offset = StaticGDSSize =
+ static_cast<uint32_t>(alignTo(StaticGDSSize, Alignment));
+ StaticGDSSize += static_cast<uint32_t>(GV.getGlobalSize(DL));
// FIXME: Apply alignment of dynamic GDS
GDSSize = StaticGDSSize;
@@ -186,7 +189,7 @@ AMDGPUMachineFunctionInfo::getLDSKernelIdMetadata(const Function &F) {
mdconst::extract<ConstantInt>(MD->getOperand(0))) {
uint64_t ZExt = KnownSize->getZExtValue();
if (ZExt <= UINT32_MAX) {
- return ZExt;
+ return static_cast<unsigned>(ZExt);
}
}
}
@@ -206,7 +209,7 @@ AMDGPUMachineFunctionInfo::get32BitAbsoluteAddress(const GlobalValue &GV,
if (const APInt *V = AbsSymRange->getSingleElement()) {
std::optional<uint64_t> ZExt = V->tryZExtValue();
if (ZExt && (*ZExt <= UINT32_MAX)) {
- return *ZExt;
+ return static_cast<unsigned>(*ZExt);
}
}
@@ -224,7 +227,7 @@ void AMDGPUMachineFunctionInfo::setDynLDSAlign(const Function &F,
if (Alignment <= DynLDSAlign)
return;
- LDSSize = alignTo(StaticLDSSize, Alignment);
+ LDSSize = static_cast<uint32_t>(alignTo(StaticLDSSize, Alignment));
DynLDSAlign = Alignment;
// If there is a dynamic LDS variable associated with this function F, every
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
index 5529808e632cfc..e4b06c7a1205c4 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
@@ -112,7 +112,7 @@ char &llvm::GCNNSAReassignID = GCNNSAReassignLegacy::ID;
bool GCNNSAReassignImpl::tryAssignRegisters(
SmallVectorImpl<LiveInterval *> &Intervals, unsigned StartReg) const {
- unsigned NumRegs = Intervals.size();
+ unsigned NumRegs = static_cast<unsigned>(Intervals.size());
for (unsigned N = 0; N < NumRegs; ++N)
if (VRM->hasPhys(Intervals[N]->reg()))
@@ -145,7 +145,7 @@ bool GCNNSAReassignImpl::canAssign(unsigned StartReg, unsigned NumRegs) const {
bool GCNNSAReassignImpl::scavengeRegs(
SmallVectorImpl<LiveInterval *> &Intervals) const {
- unsigned NumRegs = Intervals.size();
+ unsigned NumRegs = static_cast<unsigned>(Intervals.size());
if (NumRegs > MaxNumVGPRs)
return false;
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
index 94f82f2915cef9..fe1089824f9856 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
@@ -257,7 +257,7 @@ GCNRewritePartialRegUsesImpl::getRegClassWithShiftedSubregs(
unsigned MinNumBits = std::numeric_limits<unsigned>::max();
for (unsigned ClassID : ClassMask.set_bits()) {
auto *RC = TRI->getRegClass(ClassID);
- unsigned NumBits = TRI->getRegSizeInBits(*RC);
+ unsigned NumBits = static_cast<unsigned>(TRI->getRegSizeInBits(*RC));
if (NumBits < MinNumBits) {
MinNumBits = NumBits;
MinRC = RC;
@@ -438,7 +438,7 @@ bool GCNRewritePartialRegUsesImpl::run(MachineFunction &MF) {
TII = MF.getSubtarget().getInstrInfo();
bool Changed = false;
for (size_t I = 0, E = MRI->getNumVirtRegs(); I < E; ++I) {
- Changed |= rewriteReg(Register::index2VirtReg(I));
+ Changed |= rewriteReg(Register::index2VirtReg(static_cast<unsigned>(I)));
}
return Changed;
}
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 92fb77b1e6436d..dfbb3ddc859e60 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -76,7 +76,7 @@ static MCCFIInstruction createScaledCFAInPrivateWave(const GCNSubtarget &ST,
SmallString<20> Block;
raw_svector_ostream OSBlock(Block);
- encodeDwarfRegisterLocation(DwarfStackPtrReg, OSBlock);
+ encodeDwarfRegisterLocation(static_cast<int>(DwarfStackPtrReg), OSBlock);
OSBlock << uint8_t(dwarf::DW_OP_deref_size) << uint8_t(SGPRByteSize)
<< uint8_t(dwarf::DW_OP_lit0 + WavefrontSizeLog2)
<< uint8_t(dwarf::DW_OP_shl)
@@ -103,16 +103,17 @@ void SIFrameLowering::emitDefCFA(MachineBasicBlock &MBB,
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo *TRI = ST.getRegisterInfo();
- int64_t DwarfStackPtrReg = TRI->getDwarfRegNum(StackPtrReg, false);
+ int64_t DwarfStackPtrReg =
+ static_cast<unsigned>(TRI->getDwarfRegNum(StackPtrReg, false));
MCCFIInstruction CFIInst =
ST.hasFlatScratchEnabled()
? createScaledCFAInPrivateWave(ST, DwarfStackPtrReg)
: (AspaceAlreadyDefined
? MCCFIInstruction::createLLVMDefAspaceCfa(
- nullptr, DwarfStackPtrReg, 0,
+ nullptr, static_cast<unsigned>(DwarfStackPtrReg), 0,
dwarf::DW_ASPACE_LLVM_AMDGPU_private_wave, SMLoc())
- : MCCFIInstruction::createDefCfaRegister(nullptr,
- DwarfStackPtrReg));
+ : MCCFIInstruction::createDefCfaRegister(
+ nullptr, static_cast<unsigned>(DwarfStackPtrReg)));
buildCFI(MBB, MBBI, DL, CFIInst, Flags);
}
@@ -346,15 +347,16 @@ class PrologEpilogSGPRSpillBuilder {
initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ true);
- MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister(
- MRI, LiveUnits, AMDGPU::VGPR_32RegClass);
+ MCPhysReg TmpVGPR = static_cast<MCPhysReg>(findScratchNonCalleeSaveRegister(
+ MRI, LiveUnits, AMDGPU::VGPR_32RegClass));
if (!TmpVGPR)
report_fatal_error("failed to find free scratch register");
auto BuildCFI = [&](Register Reg) {
TFI->buildCFI(MBB, MI, DL,
MCCFIInstruction::createOffset(
- nullptr, MCRI->getDwarfRegNum(Reg, false),
+ nullptr,
+ static_cast<unsigned>(MCRI->getDwarfRegNum(Reg, false)),
MFI.getObjectOffset(FI) * ST.getWavefrontSize()));
};
MCRegister CFISuperReg = getCFISuperReg();
@@ -417,7 +419,8 @@ class PrologEpilogSGPRSpillBuilder {
if (DwarfCFISuperReg >= 0 && DwarfDstSuperReg >= 0) {
TFI->buildCFI(MBB, MI, DL,
MCCFIInstruction::createRegister(
- nullptr, DwarfCFISuperReg, DwarfDstSuperReg));
+ nullptr, static_cast<unsigned>(DwarfCFISuperReg),
+ static_cast<unsigned>(DwarfDstSuperReg)));
} else if (isExec(CFISuperReg)) {
assert(NumSubRegs == 2 && "EXEC larger than 64-bit");
TFI->buildCFIForRegToSGPRPairSpill(MBB, MI, DL, CFISuperReg, DstReg);
@@ -425,10 +428,13 @@ class PrologEpilogSGPRSpillBuilder {
for (unsigned I = 0; I < NumSubRegs; ++I) {
MCRegister SrcSubReg = TRI.getSubReg(SuperReg, SplitParts[I]);
MCRegister DstSubReg = TRI.getSubReg(DstReg, DstSplitParts[I]);
- TFI->buildCFI(MBB, MI, DL,
- MCCFIInstruction::createRegister(
- nullptr, MCRI->getDwarfRegNum(SrcSubReg, false),
- MCRI->getDwarfRegNum(DstSubReg, false)));
+ TFI->buildCFI(
+ MBB, MI, DL,
+ MCCFIInstruction::createRegister(
+ nullptr,
+ static_cast<unsigned>(MCRI->getDwarfRegNum(SrcSubReg, false)),
+ static_cast<unsigned>(
+ MCRI->getDwarfRegNum(DstSubReg, false))));
}
}
}
@@ -439,8 +445,8 @@ class PrologEpilogSGPRSpillBuilder {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ false);
- MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister(
- MRI, LiveUnits, AMDGPU::VGPR_32RegClass);
+ MCPhysReg TmpVGPR = static_cast<MCPhysReg>(findScratchNonCalleeSaveRegister(
+ MRI, LiveUnits, AMDGPU::VGPR_32RegClass));
if (!TmpVGPR)
report_fatal_error("failed to find free scratch register");
@@ -499,7 +505,8 @@ class PrologEpilogSGPRSpillBuilder {
NeedsFrameMoves(MF.needsFrameMoves()) {
const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);
SplitParts = TRI.getRegSplitParts(RC, EltSize);
- NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size();
+ NumSubRegs =
+ static_cast<unsigned>(SplitParts.empty() ? 1 : SplitParts.size());
assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
}
@@ -591,7 +598,8 @@ void SIFrameLowering::emitEntryFunctionFlatScratchInit(
unsigned Offset =
MF.getFunction().getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0;
const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
- unsigned EncodedOffset = AMDGPU::convertSMRDOffsetUnits(Subtarget, Offset);
+ unsigned EncodedOffset = static_cast<unsigned>(
+ AMDGPU::convertSMRDOffsetUnits(Subtarget, Offset));
BuildMI(MBB, I, DL, LoadDwordX2, FlatScrInit)
.addReg(FlatScrInit)
.addImm(EncodedOffset) // offset
@@ -792,7 +800,8 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
// Unwinding halts when the return address (PC) is undefined.
buildCFI(MBB, I, DL,
MCCFIInstruction::createUndefined(
- nullptr, TRI->getDwarfRegNum(AMDGPU::PC_REG, false)));
+ nullptr, static_cast<unsigned>(
+ TRI->getDwarfRegNum(AMDGPU::PC_REG, false))));
}
Register PreloadedScratchWaveOffsetReg = MFI->getPreloadedReg(
@@ -864,7 +873,8 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
}
assert(ScratchWaveOffsetReg || !PreloadedScratchWaveOffsetReg);
- unsigned Offset = FrameInfo.getStackSize() * getScratchScaleFactor(ST);
+ unsigned Offset = static_cast<unsigned>(FrameInfo.getStackSize() *
+ getScratchScaleFactor(ST));
if (!mayReserveScratchForCWSR(MF)) {
if (hasFP(MF)) {
Register FPReg = MFI->getFrameOffsetReg();
@@ -887,12 +897,12 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
assert(hasFP(MF));
Register FPReg = MFI->getFrameOffsetReg();
assert(FPReg != AMDGPU::FP_REG);
- unsigned VGPRSize = llvm::alignTo(
+ unsigned VGPRSize = static_cast<unsigned>(llvm::alignTo(
(ST.getAddressableNumVGPRs(MFI->getDynamicVGPRBlockSize()) -
AMDGPU::IsaInfo::getVGPRAllocGranule(ST,
MFI->getDynamicVGPRBlockSize())) *
4,
- FrameInfo.getMaxAlign());
+ FrameInfo.getMaxAlign()));
MFI->setScratchReservedForDynamicVGPRs(VGPRSize);
BuildMI(MBB, I, DL, TII->get(AMDGPU::GET_STACK_BASE), FPReg);
@@ -969,7 +979,8 @@ void SIFrameLowering::emitEntryFunctionScratchRsrcRegSetup(
16, Align(4));
unsigned Offset = Fn.getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0;
const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
- unsigned EncodedOffset = AMDGPU::convertSMRDOffsetUnits(Subtarget, Offset);
+ unsigned EncodedOffset = static_cast<unsigned>(
+ AMDGPU::convertSMRDOffsetUnits(Subtarget, Offset));
BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
.addReg(Rsrc01)
.addImm(EncodedOffset) // offset
@@ -1125,7 +1136,7 @@ void SIFrameLowering::emitPrologueEntryCFI(MachineBasicBlock &MBB,
return;
if (IsCalleeSaved.test(Reg) || !MRI.isPhysRegModified(Reg))
return;
- unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, false);
+ unsigned DwarfReg = static_cast<unsigned>(MCRI->getDwarfRegNum(Reg, false));
buildCFI(MBB, MBBI, DL,
MCCFIInstruction::createUndefined(nullptr, DwarfReg));
};
@@ -1224,10 +1235,12 @@ void SIFrameLowering::emitCSRSpillStores(
VGPR, FI, FrameReg);
if (NeedsFrameMoves) {
// We spill the entire VGPR, so we can get away with just cfi_offset
- buildCFI(MBB, MBBI, DL,
- MCCFIInstruction::createOffset(
- nullptr, MCRI->getDwarfRegNum(VGPR, false),
- MFI.getObjectOffset(FI) * ST.getWavefrontSize()));
+ buildCFI(
+ MBB, MBBI, DL,
+ MCCFIInstruction::createOffset(
+ nullptr,
+ static_cast<unsigned>(MCRI->getDwarfRegNum(VGPR, false)),
+ MFI.getObjectOffset(FI) * ST.getWavefrontSize()));
}
}
};
@@ -1294,13 +1307,13 @@ void SIFrameLowering::emitCSRSpillStores(
FuncInfo->getAllScratchSGPRCopyDstRegs(ScratchSGPRs);
if (!ScratchSGPRs.empty()) {
for (MachineBasicBlock &MBB : MF) {
- for (MCPhysReg Reg : ScratchSGPRs)
+ for (Register Reg : ScratchSGPRs)
MBB.addLiveIn(Reg);
MBB.sortUniqueLiveIns();
}
if (!LiveUnits.empty()) {
- for (MCPhysReg Reg : ScratchSGPRs)
+ for (Register Reg : ScratchSGPRs)
LiveUnits.addReg(Reg);
}
}
@@ -1443,7 +1456,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
bool HasFP = false;
bool HasBP = false;
- uint32_t NumBytes = MFI.getStackSize();
+ uint32_t NumBytes = static_cast<uint32_t>(MFI.getStackSize());
uint32_t RoundedSize = NumBytes;
// Functions that never return don't need to save and restore the FP or BP.
@@ -1496,7 +1509,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
}
if (HasFP) {
- const unsigned Alignment = MFI.getMaxAlign().value();
+ const unsigned Alignment = static_cast<unsigned>(MFI.getMaxAlign().value());
RoundedSize += Alignment;
if (LiveUnits.empty()) {
@@ -1604,10 +1617,11 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
MBBI = MBB.getFirstTerminator();
}
- uint32_t NumBytes = MFI.getStackSize();
- uint32_t RoundedSize = FuncInfo->isStackRealigned()
- ? NumBytes + MFI.getMaxAlign().value()
- : NumBytes;
+ uint32_t NumBytes = static_cast<uint32_t>(MFI.getStackSize());
+ uint32_t RoundedSize =
+ FuncInfo->isStackRealigned()
+ ? static_cast<uint32_t>(NumBytes + MFI.getMaxAlign().value())
+ : NumBytes;
const Register StackPtrReg = FuncInfo->getStackPtrOffsetReg();
Register FramePtrReg = FuncInfo->getFrameOffsetReg();
bool FPSaved = FuncInfo->hasPrologEpilogSGPRSpillEntry(FramePtrReg);
@@ -2231,7 +2245,7 @@ bool SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
AMDGPU::FlatAddrSpace::FlatScratch))
return false;
} else {
- if (TII->isLegalMUBUFImmOffset(MaxOffset))
+ if (TII->isLegalMUBUFImmOffset(static_cast<unsigned>(MaxOffset)))
return false;
}
@@ -2535,12 +2549,12 @@ MachineInstr *SIFrameLowering::buildCFIForVRegToVRegSpill(
const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- unsigned MaskReg = MCRI.getDwarfRegNum(
- ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false);
+ unsigned MaskReg = static_cast<unsigned>(MCRI.getDwarfRegNum(
+ ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false));
auto CFIInst = MCCFIInstruction::createLLVMVectorRegisterMask(
- nullptr, MCRI.getDwarfRegNum(Reg, false),
- MCRI.getDwarfRegNum(RegCopy, false), VGPRLaneBitSize, MaskReg,
- ST.getWavefrontSize());
+ nullptr, static_cast<unsigned>(MCRI.getDwarfRegNum(Reg, false)),
+ static_cast<unsigned>(MCRI.getDwarfRegNum(RegCopy, false)),
+ VGPRLaneBitSize, MaskReg, ST.getWavefrontSize());
return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
}
@@ -2551,8 +2565,10 @@ MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill(
const MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
- int DwarfSGPR = MCRI.getDwarfRegNum(SGPR, false);
- int DwarfVGPR = MCRI.getDwarfRegNum(VGPR, false);
+ int DwarfSGPR =
+ static_cast<int>(static_cast<unsigned>(MCRI.getDwarfRegNum(SGPR, false)));
+ int DwarfVGPR =
+ static_cast<int>(static_cast<unsigned>(MCRI.getDwarfRegNum(VGPR, false)));
assert(DwarfSGPR != -1 && DwarfVGPR != -1);
assert(Lane != -1 && "Expected a lane to be present");
@@ -2575,7 +2591,8 @@ MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill(
const MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
- int DwarfSGPR = MCRI.getDwarfRegNum(SGPR, false);
+ int DwarfSGPR =
+ static_cast<int>(static_cast<unsigned>(MCRI.getDwarfRegNum(SGPR, false)));
assert(DwarfSGPR != -1);
// Build a CFI instruction that represents a SGPR spilled to multiple lanes of
@@ -2583,7 +2600,8 @@ MachineInstr *SIFrameLowering::buildCFIForSGPRToVGPRSpill(
SmallVector<MCCFIInstruction::VectorRegisterWithLane> VGPRs;
for (SIRegisterInfo::SpilledReg Spill : VGPRSpills) {
- int DwarfVGPR = MCRI.getDwarfRegNum(Spill.VGPR, false);
+ int DwarfVGPR = static_cast<int>(
+ static_cast<unsigned>(MCRI.getDwarfRegNum(Spill.VGPR, false)));
assert(DwarfVGPR != -1);
assert(Spill.hasLane() && "Expected a lane to be present");
VGPRs.push_back(
@@ -2602,7 +2620,9 @@ MachineInstr *SIFrameLowering::buildCFIForSGPRToVMEMSpill(
const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
return buildCFI(MBB, MBBI, DL,
llvm::MCCFIInstruction::createOffset(
- nullptr, MCRI.getDwarfRegNum(SGPR, false), Offset));
+ nullptr,
+ static_cast<unsigned>(MCRI.getDwarfRegNum(SGPR, false)),
+ Offset));
}
MachineInstr *SIFrameLowering::buildCFIForVGPRToVMEMSpill(
@@ -2612,11 +2632,12 @@ MachineInstr *SIFrameLowering::buildCFIForVGPRToVMEMSpill(
const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- int DwarfVGPR = MCRI.getDwarfRegNum(VGPR, false);
+ int DwarfVGPR =
+ static_cast<int>(static_cast<unsigned>(MCRI.getDwarfRegNum(VGPR, false)));
assert(DwarfVGPR != -1);
- unsigned MaskReg = MCRI.getDwarfRegNum(
- ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false);
+ unsigned MaskReg = static_cast<unsigned>(MCRI.getDwarfRegNum(
+ ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC, false));
auto CFIInst = MCCFIInstruction::createLLVMVectorOffset(
nullptr, DwarfVGPR, VGPRLaneBitSize, MaskReg, ST.getWavefrontSize(),
Offset);
@@ -2633,9 +2654,12 @@ MachineInstr *SIFrameLowering::buildCFIForRegToSGPRPairSpill(
MCRegister SGPR0 = TRI.getSubReg(SGPRPair, AMDGPU::sub0);
MCRegister SGPR1 = TRI.getSubReg(SGPRPair, AMDGPU::sub1);
- int DwarfReg = TRI.getDwarfRegNum(Reg, false);
- int DwarfSGPR0 = TRI.getDwarfRegNum(SGPR0, false);
- int DwarfSGPR1 = TRI.getDwarfRegNum(SGPR1, false);
+ int DwarfReg =
+ static_cast<int>(static_cast<unsigned>(TRI.getDwarfRegNum(Reg, false)));
+ int DwarfSGPR0 =
+ static_cast<int>(static_cast<unsigned>(TRI.getDwarfRegNum(SGPR0, false)));
+ int DwarfSGPR1 =
+ static_cast<int>(static_cast<unsigned>(TRI.getDwarfRegNum(SGPR1, false)));
assert(DwarfReg != -1 && DwarfSGPR0 != -1 && DwarfSGPR1 != -1);
auto CFIInst = MCCFIInstruction::createLLVMRegisterPair(
@@ -2648,7 +2672,8 @@ MachineInstr *SIFrameLowering::buildCFIForSameValue(
const DebugLoc &DL, MCRegister Reg) const {
const MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo &MCRI = *MF.getContext().getRegisterInfo();
- int DwarfReg = MCRI.getDwarfRegNum(Reg, /*isEH=*/false);
+ int DwarfReg = static_cast<int>(
+ static_cast<unsigned>(MCRI.getDwarfRegNum(Reg, /*isEH=*/false)));
auto CFIInst = MCCFIInstruction::createSameValue(nullptr, DwarfReg);
return buildCFI(MBB, MBBI, DL, std::move(CFIInst));
}
diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
index c49270e34bf557..dbed59317a2626 100644
--- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -346,7 +346,7 @@ class LoopFinder {
}
}
- unsigned Level = CommonDominators.size();
+ unsigned Level = static_cast<unsigned>(CommonDominators.size());
while (!Stack.empty()) {
MachineBasicBlock *MBB = Stack.pop_back_val();
if (!PDT.dominates(VisitedPostDom, MBB))
@@ -401,7 +401,7 @@ insertUndefLaneMask(MachineBasicBlock *MBB, MachineRegisterInfo *MRI,
static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
const MachineRegisterInfo &MRI,
Register Reg) {
- unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
+ unsigned Size = static_cast<unsigned>(TRI.getRegSizeInBits(Reg, MRI));
return Size == 1 || Size == 32;
}
#endif
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index d0a57e163d29a0..678c8c55f6a6e8 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -266,9 +266,9 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
}
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
- int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC),
- TRI->getSpillAlign(*RC), true,
- nullptr, TRI->getSpillStackID(*RC));
+ int JunkFI = MFI.CreateStackObject(
+ TRI->getSpillSize(*RC), TRI->getSpillAlign(*RC), true, nullptr,
+ static_cast<uint8_t>(TRI->getSpillStackID(*RC)));
CSI.emplace_back(Reg, JunkFI);
CalleeSavedFIs.push_back(JunkFI);
@@ -280,9 +280,9 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(
// can be emitted appropriately.
if (SpillRetAddrReg) {
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(RetAddrReg);
- int JunkFI =
- MFI.CreateStackObject(TRI->getSpillSize(*RC), TRI->getSpillAlign(*RC),
- true, nullptr, TRI->getSpillStackID(*RC));
+ int JunkFI = MFI.CreateStackObject(
+ TRI->getSpillSize(*RC), TRI->getSpillAlign(*RC), true, nullptr,
+ static_cast<uint8_t>(TRI->getSpillStackID(*RC)));
CSI.push_back(CalleeSavedInfo(RetAddrReg, JunkFI));
CalleeSavedFIs.push_back(JunkFI);
}
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index d1df50d26a8327..bae938ef9a5965 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -173,8 +173,9 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
if (!S.empty())
S.consumeInteger(0, HighBitsOf32BitAddress);
- MaxMemoryClusterDWords = F.getFnAttributeAsParsedInteger(
- "amdgpu-max-memory-cluster-dwords", DefaultMemoryClusterDWordsLimit);
+ MaxMemoryClusterDWords =
+ static_cast<unsigned>(F.getFnAttributeAsParsedInteger(
+ "amdgpu-max-memory-cluster-dwords", DefaultMemoryClusterDWordsLimit));
// On GFX908, in order to guarantee copying between AGPRs, we need a scratch
// VGPR available at all times. For now, reserve highest available VGPR. After
@@ -326,7 +327,7 @@ void SIMachineFunctionInfo::splitWWMSpillRegisters(
SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const {
const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
for (auto &Reg : WWMSpills) {
- if (isCalleeSavedReg(CSRegs, Reg.first))
+ if (isCalleeSavedReg(CSRegs, static_cast<MCPhysReg>(Reg.first)))
CalleeSavedRegs.push_back(Reg);
else
ScratchRegs.push_back(Reg);
@@ -348,7 +349,7 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
BitVector &SavedVGPRs) {
const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
- for (unsigned I = 0, E = WWMVGPRs.size(); I < E; ++I) {
+ for (unsigned I = 0, E = static_cast<unsigned>(WWMVGPRs.size()); I < E; ++I) {
Register Reg = WWMVGPRs[I];
Register NewReg =
TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
@@ -367,7 +368,8 @@ void SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange(
// lanes while spilling special SGPRs like FP, BP, etc. during PEI.
auto *RegItr = llvm::find(SpillPhysVGPRs, Reg);
if (RegItr != SpillPhysVGPRs.end()) {
- unsigned Idx = std::distance(SpillPhysVGPRs.begin(), RegItr);
+ unsigned Idx =
+ static_cast<unsigned>(std::distance(SpillPhysVGPRs.begin(), RegItr));
SpillPhysVGPRs[Idx] = NewReg;
// For replacing registers used in the CFI instructions.
@@ -453,7 +455,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane(
MachineFrameInfo &FrameInfo = MF.getFrameInfo();
unsigned WaveSize = ST.getWavefrontSize();
- unsigned Size = FrameInfo.getObjectSize(FI);
+ unsigned Size = static_cast<unsigned>(FrameInfo.getObjectSize(FI));
unsigned NumLanes = Size / 4;
if (NumLanes > WaveSize)
@@ -500,7 +502,7 @@ bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
if (!Spill.Lanes.empty())
return Spill.FullyAllocated;
- unsigned Size = FrameInfo.getObjectSize(FI);
+ unsigned Size = static_cast<unsigned>(FrameInfo.getObjectSize(FI));
unsigned NumLanes = Size / 4;
Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
@@ -607,11 +609,11 @@ int SIMachineFunctionInfo::getScavengeFI(MachineFrameInfo &MFI,
MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
- return AMDGPU::SGPR0 + NumUserSGPRs;
+ return static_cast<MCPhysReg>(AMDGPU::SGPR0 + NumUserSGPRs);
}
MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
- return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
+ return static_cast<MCPhysReg>(AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs);
}
void SIMachineFunctionInfo::MRI_NoteNewVirtualRegister(Register Reg) {
@@ -733,8 +735,10 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
HasNoWWMPoolSGPRSpillFallback(MFI.hasNoWWMPoolSGPRSpillFallback()),
- NumWaveDispatchSGPRs(MFI.getNumWaveDispatchSGPRs()),
- NumWaveDispatchVGPRs(MFI.getNumWaveDispatchVGPRs()),
+ NumWaveDispatchSGPRs(
+ static_cast<uint16_t>(MFI.getNumWaveDispatchSGPRs())),
+ NumWaveDispatchVGPRs(
+ static_cast<uint16_t>(MFI.getNumWaveDispatchVGPRs())),
HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
Occupancy(MFI.getOccupancy()),
ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 7cad384c98a8d8..fc1725e7634168 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -144,7 +144,8 @@ struct SGPRSpillBuilder {
IsWave32(IsWave32) {
const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);
SplitParts = TRI.getRegSplitParts(RC, EltSize);
- NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size();
+ NumSubRegs =
+ static_cast<unsigned>(SplitParts.empty() ? 1 : SplitParts.size());
if (IsWave32) {
ExecReg = AMDGPU::EXEC_LO;
@@ -379,7 +380,7 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
unsigned MaxNumParts = 1024 / Size; // Maximum register is 1024 bits.
Vec.resize(MaxNumParts);
}
- Vec[Pos] = Idx;
+ Vec[Pos] = static_cast<int16_t>(Idx);
}
};
@@ -398,7 +399,7 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
unsigned TableIdx = Width - 1;
assert(TableIdx < SubRegFromChannelTable.size());
assert(Offset < SubRegFromChannelTable[TableIdx].size());
- SubRegFromChannelTable[TableIdx][Offset] = Idx;
+ SubRegFromChannelTable[TableIdx][Offset] = static_cast<uint16_t>(Idx);
}
};
@@ -658,7 +659,8 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
for (const TargetRegisterClass &RC : regclasses()) {
if (RC.isBaseClass() && isSGPRClass(&RC)) {
- unsigned NumRegs = divideCeil(getRegSizeInBits(RC), 32);
+ unsigned NumRegs =
+ static_cast<unsigned>(divideCeil(getRegSizeInBits(RC), 32));
for (MCPhysReg Reg : RC) {
unsigned Index = getHWRegIndex(Reg);
if (Index + NumRegs > MaxNumSGPRs && Index < TotalNumSGPRs &&
@@ -720,7 +722,8 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
for (const TargetRegisterClass &RC : regclasses()) {
if (RC.isBaseClass() && isVGPRClass(&RC)) {
- unsigned NumRegs = divideCeil(getRegSizeInBits(RC), 32);
+ unsigned NumRegs =
+ static_cast<unsigned>(divideCeil(getRegSizeInBits(RC), 32));
for (MCPhysReg Reg : RC) {
unsigned Index = getHWRegIndex(Reg);
if (Index + NumRegs > MaxNumVGPRs)
@@ -734,7 +737,8 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
MaxNumAGPRs = 0;
for (const TargetRegisterClass &RC : regclasses()) {
if (RC.isBaseClass() && isAGPRClass(&RC)) {
- unsigned NumRegs = divideCeil(getRegSizeInBits(RC), 32);
+ unsigned NumRegs =
+ static_cast<unsigned>(divideCeil(getRegSizeInBits(RC), 32));
for (MCPhysReg Reg : RC) {
unsigned Index = getHWRegIndex(Reg);
if (Index + NumRegs > MaxNumAGPRs)
@@ -925,7 +929,7 @@ bool SIRegisterInfo::needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
const SIInstrInfo *TII = ST.getInstrInfo();
if (SIInstrInfo::isMUBUF(*MI))
- return !TII->isLegalMUBUFImmOffset(FullOffset);
+ return !TII->isLegalMUBUFImmOffset(static_cast<unsigned>(FullOffset));
return !TII->isLegalFLATOffset(FullOffset, AMDGPUAS::PRIVATE_ADDRESS,
AMDGPU::FlatAddrSpace::FlatScratch);
@@ -1106,7 +1110,8 @@ void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
assert(SOffset->isImm() && SOffset->getImm() == 0);
#endif
- assert(TII->isLegalMUBUFImmOffset(NewOffset) && "offset should be legal");
+ assert(TII->isLegalMUBUFImmOffset(static_cast<unsigned>(NewOffset)) &&
+ "offset should be legal");
FIOp->ChangeToRegister(BaseReg, false);
OffsetOp->setImm(NewOffset);
@@ -1134,7 +1139,7 @@ bool SIRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
const SIInstrInfo *TII = ST.getInstrInfo();
if (SIInstrInfo::isMUBUF(*MI))
- return TII->isLegalMUBUFImmOffset(NewOffset);
+ return TII->isLegalMUBUFImmOffset(static_cast<unsigned>(NewOffset));
return TII->isLegalFLATOffset(NewOffset, AMDGPUAS::PRIVATE_ADDRESS,
AMDGPU::FlatAddrSpace::FlatScratch);
@@ -1705,7 +1710,7 @@ void SIRegisterInfo::buildSpillLoadStore(
bool IsOffsetLegal =
IsFlat ? TII->isLegalFLATOffset(MaxOffset, AMDGPUAS::PRIVATE_ADDRESS,
AMDGPU::FlatAddrSpace::FlatScratch)
- : TII->isLegalMUBUFImmOffset(MaxOffset);
+ : TII->isLegalMUBUFImmOffset(static_cast<unsigned>(MaxOffset));
if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) {
SOffset = MCRegister();
@@ -3503,7 +3508,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
// TODO: Fold if use instruction is another add of a constant.
if (IsVOP2 ||
- AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) {
+ AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Offset),
+ ST.hasInv2PiInlineImm())) {
// FIXME: This can fail
MIB.addImm(Offset);
MIB.addReg(ScaledReg, RegState::Kill);
@@ -3572,8 +3578,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
// to wavespace. We can right shift after the computation to
// get back to the desired per-lane value. We are using the
// mad_u32_u24 primarily as an add with no carry out clobber.
- bool IsInlinableLiteral =
- AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm());
+ bool IsInlinableLiteral = AMDGPU::isInlinableLiteral32(
+ static_cast<int32_t>(Offset), ST.hasInv2PiInlineImm());
if (!IsInlinableLiteral) {
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32),
TmpResultReg)
@@ -3688,7 +3694,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm();
int64_t NewOffset = OldImm + Offset;
- if (TII->isLegalMUBUFImmOffset(NewOffset) &&
+ if (TII->isLegalMUBUFImmOffset(static_cast<unsigned>(NewOffset)) &&
buildMUBUFOffsetLoadStore(ST, FrameInfo, MI, Index, NewOffset)) {
MI->eraseFromParent();
return true;
@@ -4041,7 +4047,7 @@ bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
const TargetRegisterClass *
SIRegisterInfo::getEquivalentVGPRClass(const TargetRegisterClass *SRC) const {
- unsigned Size = getRegSizeInBits(*SRC);
+ unsigned Size = static_cast<unsigned>(getRegSizeInBits(*SRC));
switch (SRC->getID()) {
default:
@@ -4063,7 +4069,7 @@ SIRegisterInfo::getEquivalentVGPRClass(const TargetRegisterClass *SRC) const {
const TargetRegisterClass *
SIRegisterInfo::getEquivalentAGPRClass(const TargetRegisterClass *SRC) const {
- unsigned Size = getRegSizeInBits(*SRC);
+ unsigned Size = static_cast<unsigned>(getRegSizeInBits(*SRC));
const TargetRegisterClass *ARC = getAGPRClassForBitWidth(Size);
assert(ARC && "Invalid register class size");
return ARC;
@@ -4071,7 +4077,7 @@ SIRegisterInfo::getEquivalentAGPRClass(const TargetRegisterClass *SRC) const {
const TargetRegisterClass *
SIRegisterInfo::getEquivalentAVClass(const TargetRegisterClass *SRC) const {
- unsigned Size = getRegSizeInBits(*SRC);
+ unsigned Size = static_cast<unsigned>(getRegSizeInBits(*SRC));
const TargetRegisterClass *ARC = getVectorSuperClassForBitWidth(Size);
assert(ARC && "Invalid register class size");
return ARC;
@@ -4079,7 +4085,7 @@ SIRegisterInfo::getEquivalentAVClass(const TargetRegisterClass *SRC) const {
const TargetRegisterClass *
SIRegisterInfo::getEquivalentSGPRClass(const TargetRegisterClass *VRC) const {
- unsigned Size = getRegSizeInBits(*VRC);
+ unsigned Size = static_cast<unsigned>(getRegSizeInBits(*VRC));
if (Size == 32)
return &AMDGPU::SGPR_32RegClass;
const TargetRegisterClass *SRC = getSGPRClassForBitWidth(Size);
@@ -4260,7 +4266,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
if (PairedPhys)
// isLo(Paired) is implicitly true here from the API of
// getMatchingSuperReg.
- Hints.push_back(PairedPhys);
+ Hints.push_back(static_cast<unsigned short>(PairedPhys));
return false;
}
case AMDGPURI::Size16: {
@@ -4275,7 +4281,7 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
// First prefer the paired physreg.
if (PairedPhys)
- Hints.push_back(PairedPhys);
+ Hints.push_back(static_cast<unsigned short>(PairedPhys));
else {
// Add all the lo16 physregs.
// When the Paired operand has not yet been assigned a physreg it is
@@ -4408,12 +4414,13 @@ MCPhysReg SIRegisterInfo::get32BitRegister(MCPhysReg Reg) const {
for (const TargetRegisterClass *RC :
{&AMDGPU::VGPR_32RegClass, &AMDGPU::SReg_32RegClass,
&AMDGPU::AGPR_32RegClass}) {
- if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, RC))
+ if (MCPhysReg Super =
+ static_cast<MCPhysReg>(getMatchingSuperReg(Reg, AMDGPU::lo16, RC)))
return Super;
}
- if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,
- &AMDGPU::VGPR_32RegClass)) {
- return Super;
+ if (MCPhysReg Super = static_cast<MCPhysReg>(
+ getMatchingSuperReg(Reg, AMDGPU::hi16, &AMDGPU::VGPR_32RegClass))) {
+ return Super;
}
return AMDGPU::NoRegister;
@@ -4424,12 +4431,14 @@ bool SIRegisterInfo::isProperlyAlignedRC(const TargetRegisterClass &RC) const {
return true;
if (isVGPRClass(&RC))
- return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC)));
+ return RC.hasSuperClassEq(
+ getVGPRClassForBitWidth(static_cast<unsigned>(getRegSizeInBits(RC))));
if (isAGPRClass(&RC))
- return RC.hasSuperClassEq(getAGPRClassForBitWidth(getRegSizeInBits(RC)));
- if (isVectorSuperClass(&RC))
return RC.hasSuperClassEq(
- getVectorSuperClassForBitWidth(getRegSizeInBits(RC)));
+ getAGPRClassForBitWidth(static_cast<unsigned>(getRegSizeInBits(RC))));
+ if (isVectorSuperClass(&RC))
+ return RC.hasSuperClassEq(getVectorSuperClassForBitWidth(
+ static_cast<unsigned>(getRegSizeInBits(RC))));
assert(&RC != &AMDGPU::VS_64RegClass);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 1eb9a88b819ed7..62aedff665a282 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -378,7 +378,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
const TargetRegisterClass *
getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const {
- return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank);
+ return getRegClassForSizeOnBank(static_cast<unsigned>(Ty.getSizeInBits()),
+ Bank);
}
const TargetRegisterClass *
@@ -508,8 +509,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
return AMDGPUGenRegisterInfo::getSpillWeightScaleFactor(RC) *
((RC == &AMDGPU::VGPR_32_Lo256RegClass ||
RC == &AMDGPU::VReg_64_Lo256_Align2RegClass)
- ? 2.0
- : 1.0);
+ ? 2.0f
+ : 1.0f);
}
};
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