[llvm] [AMDGPU][NFC] Change disassembler callback parameters from unsigned to uint64_t (PR #215190)
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Wed Sep 23 06:49:08 PDT 2026
https://github.com/gretay-amd updated https://github.com/llvm/llvm-project/pull/215190
>From 6babacc44c0ec2867ded0f79fd52eaad93da0817 Mon Sep 17 00:00:00 2001
From: Greta Y <Greta.Yorsh at amd.com>
Date: Thu, 6 Aug 2026 16:14:24 +0100
Subject: [PATCH] [AMDGPU][NFC] Change disassembler callback parameters from
unsigned to uint64_t
Every call from the TableGen-generated disassembler to a decoder callback in the
AMDGPU backend narrows implicitly: the caller passes a uint64_t and the callback
declares its operand parameter as unsigned. There are around 5900 such call
sites in AMDGPUGenDisassemblerTables.inc.
This patch changes the parameter type of the callbacks from unsigned to
uint64_t so that it matches the caller, and adds a static_cast where the value
is forwarded on to an interface that takes unsigned.
The call sites are generated by the TableGen disassembler backend
(llvm-tblgen -gen-disassembler, DecoderEmitter.cpp), in the decodeToMCInst
function it emits. decodeToMCInst declares the temporary it passes to the
callbacks as TmpType:
using TmpType =
std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
Changing the TableGen disassembler backend to emit an explicit conversion would
change the generated .inc file of every target. This patch addresses AMDGPU
only.
AMDGPU instantiates decodeToMCInst with four InsnTypes: uint32_t and uint64_t
for the 32- and 64-bit encodings, and std::bitset<96> and std::bitset<128> for
the wider ones. TmpType is uint64_t for three of them: directly for uint64_t,
and through the fallback for the two bitsets, which are not integral types.
Only the uint32_t tables get TmpType == uint32_t.
Most callbacks are shared between the uint32_t tables and the wider ones (20 of
the 23 reached from the uint32_t tables), so those call sites now implicitly
widen uint32_t to uint64_t where they used to match the parameter exactly.
Widening to a wider unsigned type is value-preserving, and where the callback
narrows back to unsigned the original value is recovered exactly. So this is
NFC.
This fixes 5899 instances of MSVC warning C4244 ("'argument': conversion from
'TmpType' to 'unsigned int', possible loss of data"). They are all reported in
the generated AMDGPUGenDisassemblerTables.inc, not in hand-written sources.
Assisted-by: Claude <noreply at anthropic.com>
---
.../Disassembler/AMDGPUDisassembler.cpp | 107 ++++++++++--------
1 file changed, 60 insertions(+), 47 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 3b200d412eb0d..1427c7aa49381 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -164,7 +164,7 @@ static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
return OpIdx;
}
-static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, uint64_t Imm,
uint64_t Addr,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
@@ -177,7 +177,7 @@ static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
return addOperand(Inst, MCOperand::createImm(Imm));
}
-static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
+static DecodeStatus decodeSMEMOffset(MCInst &Inst, uint64_t Imm, uint64_t Addr,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
int64_t Offset;
@@ -191,60 +191,65 @@ static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
return addOperand(Inst, MCOperand::createImm(Offset));
}
-static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr,
+static DecodeStatus decodeBoolReg(MCInst &Inst, uint64_t Val, uint64_t Addr,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeBoolReg(Inst, Val));
+ return addOperand(Inst,
+ DAsm->decodeBoolReg(Inst, static_cast<unsigned>(Val)));
}
-static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val,
+static DecodeStatus decodeSplitBarrier(MCInst &Inst, uint64_t Val,
uint64_t Addr,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeSplitBarrier(Inst, Val));
+ return addOperand(Inst,
+ DAsm->decodeSplitBarrier(Inst, static_cast<unsigned>(Val)));
}
-static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr,
+static DecodeStatus decodeDpp8FI(MCInst &Inst, uint64_t Val, uint64_t Addr,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeDpp8FI(Val));
+ return addOperand(Inst, DAsm->decodeDpp8FI(static_cast<unsigned>(Val)));
}
#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
- static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
+ static DecodeStatus StaticDecoderName(MCInst &Inst, uint64_t Imm, \
uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
- return addOperand(Inst, DAsm->DecoderName(Imm)); \
+ return addOperand(Inst, DAsm->DecoderName(static_cast<unsigned>(Imm))); \
}
// Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
// number of register. Used by VGPR only and AGPR only operands.
#define DECODE_OPERAND_REG_8(RegClass) \
static DecodeStatus Decode##RegClass##RegisterClass( \
- MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
+ MCInst &Inst, uint64_t Imm, uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
assert(Imm < (1 << 8) && "8-bit encoding"); \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
- return addOperand( \
- Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
+ return addOperand(Inst, \
+ DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, \
+ static_cast<unsigned>(Imm))); \
}
#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm) \
- static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
+ static DecodeStatus Name(MCInst &Inst, uint64_t Imm, uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
if (!isUInt<EncSize>(Imm)) \
return MCDisassembler::Fail; \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
- return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm)); \
+ return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, \
+ static_cast<unsigned>(EncImm))); \
}
static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
- unsigned OpWidth, unsigned Imm, unsigned EncImm,
+ unsigned OpWidth, uint64_t Imm, uint64_t EncImm,
const MCDisassembler *Decoder) {
assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!");
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm));
+ return addOperand(
+ Inst, DAsm->decodeSrcOp(Inst, OpWidth, static_cast<unsigned>(EncImm)));
}
// Decode an indexed-resource (rsrcidx) 9-bit srsrc field into a 32-bit index
@@ -295,7 +300,7 @@ static DecodeStatus decodeRsrcReg256(MCInst &Inst, unsigned Imm,
// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
// Used by AV_ register classes (AGPR or VGPR only register operands).
template <unsigned OpWidth>
-static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
+static DecodeStatus decodeAV10(MCInst &Inst, uint64_t Imm, uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,
Decoder);
@@ -303,7 +308,7 @@ static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
// Decoder for Src(9-bit encoding) registers only.
template <unsigned OpWidth>
-static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeSrcReg9(MCInst &Inst, uint64_t Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, Decoder);
@@ -313,7 +318,7 @@ static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
// Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
// only.
template <unsigned OpWidth>
-static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
+static DecodeStatus decodeSrcA9(MCInst &Inst, uint64_t Imm, uint64_t /* Addr */,
const MCDisassembler *Decoder) {
// A clear Imm{8} names an SGPR or an inline constant, which this
// register-only operand cannot hold.
@@ -325,7 +330,7 @@ static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
// Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
// Imm{9} is acc, registers only.
template <unsigned OpWidth>
-static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeSrcAV10(MCInst &Inst, uint64_t Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
// A clear Imm{8} names an SGPR or an inline constant, which this
@@ -341,7 +346,7 @@ static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
// decoded into constant matching the OperandType (important for floating point
// types).
template <unsigned OpWidth>
-static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, uint64_t Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, Decoder);
@@ -350,7 +355,7 @@ static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,
// Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
// and decode using 'enum10' from decodeSrcOp.
template <unsigned OpWidth>
-static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, uint64_t Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
@@ -400,31 +405,31 @@ DECODE_OPERAND_REG_8(AReg_256)
DECODE_OPERAND_REG_8(AReg_512)
DECODE_OPERAND_REG_8(AReg_1024)
-static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
+static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, uint64_t Imm,
uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
assert(isUInt<10>(Imm) && "10-bit encoding expected");
assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
bool IsHi = Imm & (1 << 9);
- unsigned RegIdx = Imm & 0xff;
+ unsigned RegIdx = static_cast<unsigned>(Imm & 0xff);
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
}
static DecodeStatus
-DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
+DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, uint64_t Imm, uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
assert(isUInt<8>(Imm) && "8-bit encoding expected");
bool IsHi = Imm & (1 << 7);
- unsigned RegIdx = Imm & 0x7f;
+ unsigned RegIdx = static_cast<unsigned>(Imm & 0x7f);
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
}
template <unsigned OpWidth>
-static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, uint64_t Imm,
uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
assert(isUInt<9>(Imm) && "9-bit encoding expected");
@@ -432,14 +437,16 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
if (Imm & AMDGPU::EncValues::IS_VGPR) {
bool IsHi = Imm & (1 << 7);
- unsigned RegIdx = Imm & 0x7f;
+ unsigned RegIdx = static_cast<unsigned>(Imm & 0x7f);
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
}
- return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(Inst, OpWidth, Imm & 0xFF));
+ return addOperand(
+ Inst, DAsm->decodeNonVGPRSrcOp(Inst, OpWidth,
+ static_cast<unsigned>(Imm & 0xFF)));
}
template <unsigned OpWidth>
-static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, uint64_t Imm,
uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
assert(isUInt<10>(Imm) && "10-bit encoding expected");
@@ -447,13 +454,15 @@ static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
if (Imm & AMDGPU::EncValues::IS_VGPR) {
bool IsHi = Imm & (1 << 9);
- unsigned RegIdx = Imm & 0xff;
+ unsigned RegIdx = static_cast<unsigned>(Imm & 0xff);
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
}
- return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(Inst, OpWidth, Imm & 0xFF));
+ return addOperand(
+ Inst, DAsm->decodeNonVGPRSrcOp(Inst, OpWidth,
+ static_cast<unsigned>(Imm & 0xFF)));
}
-static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, uint64_t Imm,
uint64_t /*Addr*/,
const MCDisassembler *Decoder) {
assert(isUInt<10>(Imm) && "10-bit encoding expected");
@@ -463,15 +472,16 @@ static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm,
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
bool IsHi = Imm & (1 << 9);
- unsigned RegIdx = Imm & 0xff;
+ unsigned RegIdx = static_cast<unsigned>(Imm & 0xff);
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
}
-static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, uint64_t Imm,
uint64_t Addr,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
+ return addOperand(
+ Inst, DAsm->decodeMandatoryLiteralConstant(static_cast<unsigned>(Imm)));
}
static DecodeStatus decodeOperand_KImmFP64(MCInst &Inst, uint64_t Imm,
@@ -481,31 +491,34 @@ static DecodeStatus decodeOperand_KImmFP64(MCInst &Inst, uint64_t Imm,
return addOperand(Inst, DAsm->decodeMandatoryLiteral64Constant(Imm));
}
-static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val,
+static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, uint64_t Val,
uint64_t Addr, const void *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
+ return addOperand(Inst,
+ DAsm->decodeVOPDDstYOp(Inst, static_cast<unsigned>(Val)));
}
-static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, unsigned Opw,
+static DecodeStatus decodeAVLdSt(MCInst &Inst, uint64_t Imm, unsigned Opw,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeSrcOp(Inst, Opw, Imm | 256));
+ return addOperand(
+ Inst, DAsm->decodeSrcOp(Inst, Opw, static_cast<unsigned>(Imm | 256)));
}
template <unsigned Opw>
-static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeAVLdSt(MCInst &Inst, uint64_t Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
return decodeAVLdSt(Inst, Imm, Opw, Decoder);
}
-static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, uint64_t Imm,
uint64_t Addr,
const MCDisassembler *Decoder) {
assert(Imm < (1 << 9) && "9-bit encoding");
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeSrcOp(Inst, 64, Imm));
+ return addOperand(Inst,
+ DAsm->decodeSrcOp(Inst, 64, static_cast<unsigned>(Imm)));
}
#define DECODE_SDWA(DecName) \
@@ -516,7 +529,7 @@ DECODE_SDWA(Src16)
DECODE_SDWA(VopcDst)
#define DECODE_SDWA_IMM_FIELD(Name, MaxImm) \
- static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, \
+ static DecodeStatus Name(MCInst &Inst, uint64_t Imm, uint64_t /* Addr */, \
const MCDisassembler * /* Decoder */) { \
if (Imm > (MaxImm)) \
return MCDisassembler::Fail; \
@@ -531,11 +544,11 @@ DECODE_SDWA_IMM_FIELD(decodeSDWADstUnused,
AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE)
#undef DECODE_SDWA_IMM_FIELD
-static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeVersionImm(MCInst &Inst, uint64_t Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
- return addOperand(Inst, DAsm->decodeVersionImm(Imm));
+ return addOperand(Inst, DAsm->decodeVersionImm(static_cast<unsigned>(Imm)));
}
#include "AMDGPUGenDisassemblerTables.inc"
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