[llvm] a8af62d - [RISCV] Use switches for opcode checks in RISCVInstrPredicates.td. NFC (#225695)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 06:00:45 PDT 2026
Author: Luke Lau
Date: 2026-09-23T13:00:37Z
New Revision: a8af62d00b82c9226cca3b4abdf376158f6bde53
URL: https://github.com/llvm/llvm-project/commit/a8af62d00b82c9226cca3b4abdf376158f6bde53
DIFF: https://github.com/llvm/llvm-project/commit/a8af62d00b82c9226cca3b4abdf376158f6bde53.diff
LOG: [RISCV] Use switches for opcode checks in RISCVInstrPredicates.td. NFC (#225695)
CheckOpcode expands out to a linear search which is slow when there's
lots of opcodes in the list. Using a switch statement allows a jump
table to be emitted which improves compile time, since these predicates
are hammered quite frequently.
Measured to reduce geomean -1.15% instructions retired on CTMark w/ a
stage2 rva23u64 -O3 Clang build.
Assisted-By: Opus 5.5
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrPredicates.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 619e592366353..cb8fae29e207d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -27,6 +27,14 @@ def SingleElementVecFP64SchedPred : FeatureSchedPredicate<TuneHasSingleElementVe
// is not enabled).
def RV32SchedPred : NotSchedPred<FeatureSchedPredicate<Feature64Bit>>;
+// Generates a switch statement over a list of opcodes. More efficient
+// than CheckOpcode with longer opcode lists.
+class OpcodeSwitchPredicate<string Name, list<Instruction> Opcodes>
+ : TIIPredicate<Name,
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<Opcodes, MCReturnStatement<TruePred>>],
+ MCReturnStatement<FalsePred>>>;
+
// Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
def isSEXT_W
: TIIPredicate<"isSEXT_W",
@@ -55,40 +63,38 @@ def isZEXT_B
]>>>;
def isSelectPseudo
- : TIIPredicate<"isSelectPseudo",
- MCReturnStatement<
- CheckOpcode<[
- Select_GPR_Using_CC_GPR,
- Select_GPR_Using_CC_Imm5_Zibi,
- Select_GPR_Using_CC_SImm5_CV,
- Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
- Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
- Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
- Select_GPRNoX0_Using_CC_UImm16NonZero_QC,
- Select_GPR_Using_CC_UImmLog2XLen_NDS,
- Select_GPR_Using_CC_UImm7_NDS,
- Select_FPR16_Using_CC_GPR,
- Select_FPR16INX_Using_CC_GPR,
- Select_FPR32_Using_CC_GPR,
- Select_FPR32INX_Using_CC_GPR,
- Select_FPR64_Using_CC_GPR,
- Select_FPR64INX_Using_CC_GPR,
- Select_FPR64IN32X_Using_CC_GPR
- ]>>>;
+ : OpcodeSwitchPredicate<"isSelectPseudo",
+ [
+ Select_GPR_Using_CC_GPR,
+ Select_GPR_Using_CC_Imm5_Zibi,
+ Select_GPR_Using_CC_SImm5_CV,
+ Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
+ Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
+ Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
+ Select_GPRNoX0_Using_CC_UImm16NonZero_QC,
+ Select_GPR_Using_CC_UImmLog2XLen_NDS,
+ Select_GPR_Using_CC_UImm7_NDS,
+ Select_FPR16_Using_CC_GPR,
+ Select_FPR16INX_Using_CC_GPR,
+ Select_FPR32_Using_CC_GPR,
+ Select_FPR32INX_Using_CC_GPR,
+ Select_FPR64_Using_CC_GPR,
+ Select_FPR64INX_Using_CC_GPR,
+ Select_FPR64IN32X_Using_CC_GPR
+ ]>;
// Returns true if this is a vector configuration instruction.
def isVectorConfigInstr
- : TIIPredicate<"isVectorConfigInstr",
- MCReturnStatement<
- CheckOpcode<[
- PseudoVSETVLI,
- PseudoVSETVLIX0,
- PseudoVSETVLIX0X0,
- PseudoVSETIVLI,
- PseudoSF_VSETTNT,
- PseudoSF_VSETTNTX0,
- PseudoSF_VSETTNTX0X0
- ]>>>;
+ : OpcodeSwitchPredicate<"isVectorConfigInstr",
+ [
+ PseudoVSETVLI,
+ PseudoVSETVLIX0,
+ PseudoVSETVLIX0X0,
+ PseudoVSETIVLI,
+ PseudoSF_VSETTNT,
+ PseudoSF_VSETTNTX0,
+ PseudoSF_VSETTNTX0X0
+ ]>;
// Returns true if this is a PseudoSF_VSETTNT* instructions.
def isXSfmmVectorConfigTNInstr
@@ -111,15 +117,14 @@ def isXSfmmVectorConfigTMTKInstr
// Returns true if this is a XSfmm vector configuration instruction.
def isXSfmmVectorConfigInstr
- : TIIPredicate<"isXSfmmVectorConfigInstr",
- MCReturnStatement<
- CheckOpcode<[
- PseudoSF_VSETTNT,
- PseudoSF_VSETTNTX0,
- PseudoSF_VSETTNTX0X0,
- PseudoSF_VSETTM,
- PseudoSF_VSETTK
- ]>>>;
+ : OpcodeSwitchPredicate<"isXSfmmVectorConfigInstr",
+ [
+ PseudoSF_VSETTNT,
+ PseudoSF_VSETTNTX0,
+ PseudoSF_VSETTNTX0X0,
+ PseudoSF_VSETTM,
+ PseudoSF_VSETTK
+ ]>;
// Return true if this is 'vsetvli x0, x0, vtype' which preserves
// VL and only sets VTYPE.
@@ -128,65 +133,57 @@ def isVLPreservingConfig
MCReturnStatement<CheckOpcode<[PseudoVSETVLIX0X0]>>>;
def isFloatScalarMoveOrScalarSplatInstr
- : TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr",
- MCReturnStatement<
- CheckOpcode<!listflatten([
- !instances<Pseudo>("^PseudoVFMV_S_F.*"),
- !instances<Pseudo>("^PseudoVFMV_V_F.*")
- ])>>>;
+ : OpcodeSwitchPredicate<"isFloatScalarMoveOrScalarSplatInstr",
+ !listflatten([
+ !instances<Pseudo>("^PseudoVFMV_S_F.*"),
+ !instances<Pseudo>("^PseudoVFMV_V_F.*")
+ ])>;
def isScalarExtractInstr
- : TIIPredicate<"isScalarExtractInstr",
- MCReturnStatement<
- CheckOpcode<!listflatten([
- !instances<Pseudo>("^PseudoVMV_X_S.*"),
- !instances<Pseudo>("^PseudoVFMV_F.*_S.*")
- ])>>>;
+ : OpcodeSwitchPredicate<"isScalarExtractInstr",
+ !listflatten([
+ !instances<Pseudo>("^PseudoVMV_X_S.*"),
+ !instances<Pseudo>("^PseudoVFMV_F.*_S.*")
+ ])>;
def isScalarInsertInstr
- : TIIPredicate<"isScalarInsertInstr",
- MCReturnStatement<
- CheckOpcode<!listflatten([
- !instances<Pseudo>("^PseudoVMV_S_X.*"),
- !instances<Pseudo>("^PseudoVFMV_S_F.*")
- ])>>>;
+ : OpcodeSwitchPredicate<"isScalarInsertInstr",
+ !listflatten([
+ !instances<Pseudo>("^PseudoVMV_S_X.*"),
+ !instances<Pseudo>("^PseudoVFMV_S_F.*")
+ ])>;
def isScalarSplatInstr
- : TIIPredicate<"isScalarSplatInstr",
- MCReturnStatement<
- CheckOpcode<!listflatten([
- !instances<Pseudo>("^PseudoVMV_V_I.*"),
- !instances<Pseudo>("^PseudoVMV_V_X.*"),
- !instances<Pseudo>("^PseudoVFMV_V_F.*")
- ])>>>;
+ : OpcodeSwitchPredicate<"isScalarSplatInstr",
+ !listflatten([
+ !instances<Pseudo>("^PseudoVMV_V_I.*"),
+ !instances<Pseudo>("^PseudoVMV_V_X.*"),
+ !instances<Pseudo>("^PseudoVFMV_V_F.*")
+ ])>;
def isVSlideInstr
- : TIIPredicate<"isVSlideInstr",
- MCReturnStatement<
- CheckOpcode<!listflatten([
- !instances<Pseudo>("^PseudoVSLIDEDOWN_VX.*"),
- !instances<Pseudo>("^PseudoVSLIDEDOWN_VI.*"),
- !instances<Pseudo>("^PseudoVSLIDEUP_VX.*"),
- !instances<Pseudo>("^PseudoVSLIDEUP_VI.*")
- ])>>>;
+ : OpcodeSwitchPredicate<"isVSlideInstr",
+ !listflatten([
+ !instances<Pseudo>("^PseudoVSLIDEDOWN_VX.*"),
+ !instances<Pseudo>("^PseudoVSLIDEDOWN_VI.*"),
+ !instances<Pseudo>("^PseudoVSLIDEUP_VX.*"),
+ !instances<Pseudo>("^PseudoVSLIDEUP_VI.*")
+ ])>;
// Returns true if this is an integer or floating-point vector comparison.
def isRVVCompare
- : TIIPredicate<"isRVVCompare",
- MCReturnStatement<
- CheckOpcode<!listflatten([
- !instances<Pseudo>(
- "^PseudoVMS(EQ|NE|LTU?|LEU?|GTU?)_.*"),
- !instances<Pseudo>(
- "^PseudoVMF(EQ|NE|LT|LE|GT|GE)(_ALT)?_.*")
- ])>>>;
+ : OpcodeSwitchPredicate<"isRVVCompare",
+ !listflatten([
+ !instances<Pseudo>(
+ "^PseudoVMS(EQ|NE|LTU?|LEU?|GTU?)_.*"),
+ !instances<Pseudo>(
+ "^PseudoVMF(EQ|NE|LT|LE|GT|GE)(_ALT)?_.*")
+ ])>;
def isFaultOnlyFirstLoad
- : TIIPredicate<"isFaultOnlyFirstLoad",
- MCReturnStatement<
- CheckOpcode<
- !instances<Pseudo>(
- "^PseudoVL(SEG[2-8])?E(8|16|32|64)FF_V.*")>>>;
+ : OpcodeSwitchPredicate<"isFaultOnlyFirstLoad",
+ !instances<Pseudo>(
+ "^PseudoVL(SEG[2-8])?E(8|16|32|64)FF_V.*")>;
def isLoadImmediate
: TIIPredicate<"isLoadImmediate",
@@ -225,47 +222,43 @@ def ignoresVXRM
// RVI Base Loads, only those using simm12(reg) for addressing
def isBaseLoad
- : TIIPredicate<"isBaseLoad",
- MCReturnStatement<
- CheckOpcode<[
- LD,
- LW,
- LWU,
- LH,
- LHU,
- LB,
- LBU
- ]>>>;
+ : OpcodeSwitchPredicate<"isBaseLoad",
+ [
+ LD,
+ LW,
+ LWU,
+ LH,
+ LHU,
+ LB,
+ LBU
+ ]>;
// RVI Base Stores, only those using simm12(reg) for addressing
def isBaseStore
- : TIIPredicate<"isBaseStore",
- MCReturnStatement<
- CheckOpcode<[
- SD,
- SW,
- SH,
- SB,
- ]>>>;
+ : OpcodeSwitchPredicate<"isBaseStore",
+ [
+ SD,
+ SW,
+ SH,
+ SB,
+ ]>;
// Xqcilo 26-bit offset Loads (qc.e.lb, qc.e.lbu, qc.e.lh, qc.e.lhu, qc.e.lw)
def isBaseQCLoad
- : TIIPredicate<"isBaseQCLoad",
- MCReturnStatement<
- CheckOpcode<[
- QC_E_LB,
- QC_E_LBU,
- QC_E_LH,
- QC_E_LHU,
- QC_E_LW
- ]>>>;
+ : OpcodeSwitchPredicate<"isBaseQCLoad",
+ [
+ QC_E_LB,
+ QC_E_LBU,
+ QC_E_LH,
+ QC_E_LHU,
+ QC_E_LW
+ ]>;
// Xqcilo 26-bit offset Stores (qc.e.sb, qc.e.sh, qc.e.sw)
def isBaseQCStore
- : TIIPredicate<"isBaseQCStore",
- MCReturnStatement<
- CheckOpcode<[
- QC_E_SB,
- QC_E_SH,
- QC_E_SW
- ]>>>;
+ : OpcodeSwitchPredicate<"isBaseQCStore",
+ [
+ QC_E_SB,
+ QC_E_SH,
+ QC_E_SW
+ ]>;
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