[llvm] [RISCV] Model interleave2 and deinterleave2 costs with Zvzip (PR #225752)
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Wed Sep 23 05:56:21 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-analysis
Author: renndong
<details>
<summary>Changes</summary>
This PR extends the RISC-V TTI cost model to recognize
`llvm.vector.interleave2` and `llvm.vector.deinterleave2` when the Zvzip
extension is available.
The cost is computed based on the operand that holds the interleaved
data: the destination operand of `vzip.vv`, and the source operand of
`unzipe.v` or `unzipo.v`.
This is the first PR split out from #<!-- -->224991.
Assisted-By: Trae CLI (GPT-5)
---
Patch is 73.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225752.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+95)
- (modified) llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll (+917-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 7f65e3dd4456a..7102bfe724a72 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -733,6 +733,54 @@ InstructionCost RISCVTTIImpl::getSlideCost(FixedVectorType *Tp,
return FirstSlideCost + SecondSlideCost + MaskCost;
}
+/// Return the type used to cost vzip.vv, whose LMUL represents the
+/// interleaved destination EMUL. Return std::nullopt if illegal.
+static std::optional<MVT> getZvzipVZIPCostVT(MVT InterleavedVT,
+ const RISCVSubtarget &ST,
+ const RISCVTargetLowering &TLI) {
+ if (!InterleavedVT.getVectorElementCount().isKnownEven())
+ return std::nullopt;
+
+ MVT CostVT = InterleavedVT;
+ if (InterleavedVT.isFixedLengthVector()) {
+ MVT SourceVT = InterleavedVT.getHalfNumVectorElementsVT();
+ CostVT = TLI.getContainerForFixedLengthVector(SourceVT)
+ .getDoubleNumVectorElementsVT();
+ }
+
+ unsigned EltBits = CostVT.getScalarSizeInBits();
+ unsigned MinSize = CostVT.getSizeInBits().getKnownMinValue();
+ unsigned LMULOctuple = MinSize / (RISCV::RVVBitsPerBlock / 8);
+ // Perform the 2 * SEW <= LMUL * min(ELEN, VLEN) check.
+ if (EltBits * 16 > LMULOctuple * std::min(ST.getELen(), ST.getRealMinVLen()))
+ return std::nullopt;
+ return CostVT;
+}
+
+/// Return the type used to cost vunzipe.v/vunzipo.v, whose LMUL represents
+/// the interleaved source EMUL. Return std::nullopt if illegal.
+static std::optional<MVT> getZvzipVUNZIPCostVT(MVT InterleavedVT,
+ const RISCVTargetLowering &TLI) {
+ if (!InterleavedVT.getVectorElementCount().isKnownEven())
+ return std::nullopt;
+
+ MVT CostVT = InterleavedVT;
+ // lowerZvzipVUNZIP widens the source container if halving it would produce
+ // an illegal result type. Apply the same rule here so the cost uses the
+ // source LMUL selected by ISel.
+ if (InterleavedVT.isFixedLengthVector()) {
+ CostVT = TLI.getContainerForFixedLengthVector(InterleavedVT);
+ if (CostVT.getVectorMinNumElements() == 1 ||
+ !TLI.isTypeLegal(CostVT.getHalfNumVectorElementsVT()))
+ CostVT = CostVT.getDoubleNumVectorElementsVT();
+ }
+
+ MVT DeinterleavedVT = CostVT.getHalfNumVectorElementsVT();
+ if (RISCVTargetLowering::getLMUL(DeinterleavedVT) == RISCVVType::LMUL_8)
+ return std::nullopt;
+ return CostVT;
+}
+
InstructionCost RISCVTTIImpl::getShuffleCost(
TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
TTI::TargetCostKind CostKind, ArrayRef<int> Mask, int Index,
@@ -1898,6 +1946,53 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
ValLT.second, CostKind);
return Cost;
}
+ case Intrinsic::vector_interleave2:
+ case Intrinsic::vector_deinterleave2: {
+ if (!ST->hasStdExtZvzip())
+ break;
+
+ bool IsInterleave = ICA.getID() == Intrinsic::vector_interleave2;
+ Type *InterleavedTy = IsInterleave ? RetTy : ICA.getArgTypes().front();
+ // ISel does not select vzip.vv if either interleave2 input is undef.
+ if (IsInterleave && !ICA.isTypeBasedOnly() &&
+ any_of(ICA.getArgs(),
+ [](const Value *Arg) { return isa<UndefValue>(Arg); }))
+ break;
+ if (InterleavedTy->getScalarSizeInBits() == 1)
+ break;
+
+ if (auto *FVT = dyn_cast<FixedVectorType>(InterleavedTy)) {
+ if (IsInterleave) {
+ unsigned VF = FVT->getNumElements() / 2;
+ auto *HalfFVT = FixedVectorType::getHalfElementsVectorType(FVT);
+ return getShuffleCost(TTI::SK_PermuteTwoSrc, FVT, HalfFVT, CostKind,
+ createInterleaveMask(VF, 2), 0, nullptr);
+ }
+
+ auto *HalfFVT = FixedVectorType::getHalfElementsVectorType(FVT);
+ unsigned VF = HalfFVT->getNumElements();
+ InstructionCost Cost = 0;
+ for (unsigned Start = 0; Start != 2; ++Start)
+ Cost += getShuffleCost(TTI::SK_PermuteSingleSrc, HalfFVT, FVT, CostKind,
+ createStrideMask(Start, 2, VF), 0, nullptr);
+ return Cost;
+ }
+
+ std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(InterleavedTy);
+ if (!LT.second.isScalableVector())
+ break;
+ if (IsInterleave) {
+ if (std::optional<MVT> CostVT = getZvzipVZIPCostVT(LT.second, *ST, *TLI))
+ return LT.first *
+ getRISCVInstructionCost(RISCV::VZIP_VV, *CostVT, CostKind);
+ } else if (std::optional<MVT> CostVT =
+ getZvzipVUNZIPCostVT(LT.second, *TLI)) {
+ return LT.first *
+ getRISCVInstructionCost({RISCV::VUNZIPE_V, RISCV::VUNZIPO_V},
+ *CostVT, CostKind);
+ }
+ break;
+ }
}
if (ST->hasVInstructions() && RetTy->isVectorTy()) {
diff --git a/llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll b/llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll
index 27c33dca5048a..9cf20debf3ef7 100644
--- a/llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/shuffle-interleave.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v | FileCheck --check-prefixes=CHECK,RV32 %s
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v | FileCheck --check-prefixes=CHECK,RV64 %s
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvzip | FileCheck --check-prefixes=CHECK,ZVZIP %s
+; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64 -mattr=+zve32f,+zvfh,+zvl128b,+experimental-zvzip | FileCheck --check-prefixes=CHECK,ZVE32 %s
; The mask here interleaves (%v1, %v0), not (%v0, %v1): it should still be cheap.
define <4 x i8> @interleave2_v2i8(<2 x i8> %v0, <2 x i8> %v1) {
@@ -26,10 +28,25 @@ define <8 x i8> @interleave2_v8i8(<4 x i8> %v0, <4 x i8> %v1) {
}
define <8 x i32> @interleave2_v8i32(<4 x i32> %v0, <4 x i32> %v1) {
-; CHECK-LABEL: 'interleave2_v8i32'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %concat = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = shufflevector <8 x i32> %concat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %res
+; RV32-LABEL: 'interleave2_v8i32'
+; RV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %concat = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; RV32-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = shufflevector <8 x i32> %concat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %res
+;
+; RV64-LABEL: 'interleave2_v8i32'
+; RV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %concat = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; RV64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = shufflevector <8 x i32> %concat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %res
+;
+; ZVZIP-LABEL: 'interleave2_v8i32'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %concat = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %res = shufflevector <8 x i32> %concat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %res
+;
+; ZVE32-LABEL: 'interleave2_v8i32'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %concat = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = shufflevector <8 x i32> %concat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %res
;
%concat = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%res = shufflevector <8 x i32> %concat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
@@ -47,6 +64,16 @@ define <8 x i64> @interleave2_v8i64(<4 x i64> %v0, <4 x i64> %v1) {
; RV64-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %concat = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; RV64-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %res = shufflevector <8 x i64> %concat, <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %res
+;
+; ZVZIP-LABEL: 'interleave2_v8i64'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %concat = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = shufflevector <8 x i64> %concat, <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %res
+;
+; ZVE32-LABEL: 'interleave2_v8i64'
+; ZVE32-NEXT: Cost Model: Invalid cost for instruction: %concat = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %res = shufflevector <8 x i64> %concat, <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %res
;
%concat = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%res = shufflevector <8 x i64> %concat, <8 x i64> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
@@ -98,3 +125,889 @@ define {<8 x i32>, <8 x i32>} @deinterleave_2_m2_dest(<16 x i32> %v) {
%res1 = insertvalue {<8 x i32>, <8 x i32>} %res0, <8 x i32> %v1, 1
ret {<8 x i32>, <8 x i32>} %res1
}
+
+; Fixed-length interleave2 intrinsics.
+; TODO: we not support the cost calculation of Zvzip in getShuffleCost yet, so
+; the cost of fixed vector may seems weird.
+
+define <2 x i32> @interleave2_intrinsic_v2i32(<1 x i32> %a, <1 x i32> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v2i32'
+; RV32-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x i32> @llvm.vector.interleave2.v2i32(<1 x i32> %a, <1 x i32> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+; RV64-LABEL: 'interleave2_intrinsic_v2i32'
+; RV64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x i32> @llvm.vector.interleave2.v2i32(<1 x i32> %a, <1 x i32> %b)
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+; ZVZIP-LABEL: 'interleave2_intrinsic_v2i32'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <2 x i32> @llvm.vector.interleave2.v2i32(<1 x i32> %a, <1 x i32> %b)
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+; ZVE32-LABEL: 'interleave2_intrinsic_v2i32'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <2 x i32> @llvm.vector.interleave2.v2i32(<1 x i32> %a, <1 x i32> %b)
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+ %res = call <2 x i32> @llvm.vector.interleave2.v2i32(<1 x i32> %a, <1 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i64> @interleave2_intrinsic_v2i64(<1 x i64> %a, <1 x i64> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v2i64'
+; RV32-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <2 x i64> @llvm.vector.interleave2.v2i64(<1 x i64> %a, <1 x i64> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %res
+;
+; RV64-LABEL: 'interleave2_intrinsic_v2i64'
+; RV64-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x i64> @llvm.vector.interleave2.v2i64(<1 x i64> %a, <1 x i64> %b)
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %res
+;
+; ZVZIP-LABEL: 'interleave2_intrinsic_v2i64'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <2 x i64> @llvm.vector.interleave2.v2i64(<1 x i64> %a, <1 x i64> %b)
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %res
+;
+; ZVE32-LABEL: 'interleave2_intrinsic_v2i64'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %res = call <2 x i64> @llvm.vector.interleave2.v2i64(<1 x i64> %a, <1 x i64> %b)
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %res
+;
+ %res = call <2 x i64> @llvm.vector.interleave2.v2i64(<1 x i64> %a, <1 x i64> %b)
+ ret <2 x i64> %res
+}
+
+define <4 x i1> @interleave2_intrinsic_v4i1(<2 x i1> %a, <2 x i1> %b) {
+; CHECK-LABEL: 'interleave2_intrinsic_v4i1'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %res = call <4 x i1> @llvm.vector.interleave2.v4i1(<2 x i1> %a, <2 x i1> %b)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i1> %res
+;
+ %res = call <4 x i1> @llvm.vector.interleave2.v4i1(<2 x i1> %a, <2 x i1> %b)
+ ret <4 x i1> %res
+}
+
+define <4 x i8> @interleave2_intrinsic_v4i8(<2 x i8> %a, <2 x i8> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v4i8'
+; RV32-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i8> @llvm.vector.interleave2.v4i8(<2 x i8> %a, <2 x i8> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %res
+;
+; RV64-LABEL: 'interleave2_intrinsic_v4i8'
+; RV64-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i8> @llvm.vector.interleave2.v4i8(<2 x i8> %a, <2 x i8> %b)
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %res
+;
+; ZVZIP-LABEL: 'interleave2_intrinsic_v4i8'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x i8> @llvm.vector.interleave2.v4i8(<2 x i8> %a, <2 x i8> %b)
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %res
+;
+; ZVE32-LABEL: 'interleave2_intrinsic_v4i8'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x i8> @llvm.vector.interleave2.v4i8(<2 x i8> %a, <2 x i8> %b)
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %res
+;
+ %res = call <4 x i8> @llvm.vector.interleave2.v4i8(<2 x i8> %a, <2 x i8> %b)
+ ret <4 x i8> %res
+}
+
+define <4 x i32> @interleave2_intrinsic_v4i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v4i32'
+; RV32-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; RV64-LABEL: 'interleave2_intrinsic_v4i32'
+; RV64-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; ZVZIP-LABEL: 'interleave2_intrinsic_v4i32'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; ZVE32-LABEL: 'interleave2_intrinsic_v4i32'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+ %res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b)
+ ret <4 x i32> %res
+}
+
+define <4 x i64> @interleave2_intrinsic_v4i64(<2 x i64> %a, <2 x i64> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v4i64'
+; RV32-NEXT: Cost Model: Found an estimated cost of 57 for instruction: %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %res
+;
+; RV64-LABEL: 'interleave2_intrinsic_v4i64'
+; RV64-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %res
+;
+; ZVZIP-LABEL: 'interleave2_intrinsic_v4i64'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %res
+;
+; ZVE32-LABEL: 'interleave2_intrinsic_v4i64'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %res
+;
+ %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+ ret <4 x i64> %res
+}
+
+define <8 x i16> @interleave2_intrinsic_v8i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v8i16'
+; RV32-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %res = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %a, <4 x i16> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %res
+;
+; RV64-LABEL: 'interleave2_intrinsic_v8i16'
+; RV64-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %res = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %a, <4 x i16> %b)
+; RV64-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %res
+;
+; ZVZIP-LABEL: 'interleave2_intrinsic_v8i16'
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %a, <4 x i16> %b)
+; ZVZIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %res
+;
+; ZVE32-LABEL: 'interleave2_intrinsic_v8i16'
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %a, <4 x i16> %b)
+; ZVE32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %res
+;
+ %res = call <8 x i16> @llvm.vector.interleave2.v8i16(<4 x i16> %a, <4 x i16> %b)
+ ret <8 x i16> %res
+}
+
+define <8 x i32> @interleave2_intrinsic_v8i32(<4 x i32> %a, <4 x i32> %b) {
+; RV32-LABEL: 'interleave2_intrinsic_v8i32'
+; RV32-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
+; RV32-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %res
+;
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225752
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