[llvm] [IR][REVEC] Define llvm.vector.repeat intrinsic (PR #208212)

[Gaëtan Bossu via llvm-commits]

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@@ -17807,6 +17792,28 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
   return SDValue();
 }
 
+SDValue AArch64TargetLowering::LowerVECTOR_REPEAT(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+  assert(isUnpackedType(VT, DAG) && "Expected an unpacked vector type!");
+
+  // Broadcast into a packed container before extracting the low lanes, which
+  // places the result elements at the spacing required by the unpacked type.
+  EVT PackedVT = getPackedSVEVectorVT(VT.getVectorElementType());
+  SDValue Src = Op.getOperand(0);
+  EVT SrcVT = Src.getValueType();
+  unsigned NumConcat =
+      PackedVT.getVectorMinNumElements() / SrcVT.getVectorMinNumElements();
+  SmallVector<SDValue, 8> Ops(NumConcat, Src);
+  EVT PackedSrcVT = SrcVT.changeVectorElementCount(
+      *DAG.getContext(),
+      ElementCount::getFixed(PackedVT.getVectorMinNumElements()));
+  SDValue PackedSrc = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedSrcVT, Ops);
+  SDValue Broadcast = DAG.getNode(ISD::VECTOR_REPEAT, DL, PackedVT, PackedSrc);
----------------
gbossu wrote:

Is your fear that the `concat(Op)->repeat->extract_subvector` eventually gets combined back to a smaller width repeat? (Meaning we'd be back at square one, potentially looping indefinitely)

What I was planning in a follow-up was to combine that `concat(Op)->repeat` into:
```
reinterpret src as v1i64
extractelement 0
splat to nxv2i64
bitcast as requested type
```

Which is basically what you were suggesting with the reinterprets, but without introducing any AArch64ISD opcode. That sequence gets selected as `mov z.d, d` I think I could directly lower the unpacked cases to that instead of introducing concats.

I'm not too sure about the benefits of introducing DUPLANE128/DUPLANE64 early, but maybe I'm missing something.

https://github.com/llvm/llvm-project/pull/208212