[llvm] [LLVM][CodeGen][AArch64] Implement expansion for fixed-length get.active.lane.mask. (PR #225459)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 05:02:55 PDT 2026
================
@@ -0,0 +1,401 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define void @lane_mask_v32i1_i32(i32 %index, i32 %TC) {
+; CHECK-LABEL: lane_mask_v32i1_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI0_0
+; CHECK-NEXT: adrp x10, .LCPI0_5
+; CHECK-NEXT: dup v1.4s, w0
+; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT: adrp x8, .LCPI0_1
+; CHECK-NEXT: ldr q5, [x10, :lo12:.LCPI0_5]
+; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_1]
+; CHECK-NEXT: adrp x8, .LCPI0_4
+; CHECK-NEXT: adrp x10, .LCPI0_7
+; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI0_4]
+; CHECK-NEXT: adrp x8, .LCPI0_6
+; CHECK-NEXT: ldr q7, [x10, :lo12:.LCPI0_7]
+; CHECK-NEXT: ldr q6, [x8, :lo12:.LCPI0_6]
+; CHECK-NEXT: adrp x9, .LCPI0_2
+; CHECK-NEXT: adrp x8, .LCPI0_3
+; CHECK-NEXT: uqadd v4.4s, v1.4s, v4.4s
+; CHECK-NEXT: uqadd v5.4s, v1.4s, v5.4s
+; CHECK-NEXT: uqadd v7.4s, v1.4s, v7.4s
+; CHECK-NEXT: uqadd v6.4s, v1.4s, v6.4s
+; CHECK-NEXT: dup v2.4s, w1
+; CHECK-NEXT: ldr q16, [x9, :lo12:.LCPI0_2]
+; CHECK-NEXT: ldr q17, [x8, :lo12:.LCPI0_3]
+; CHECK-NEXT: uqadd v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: uqadd v3.4s, v1.4s, v3.4s
+; CHECK-NEXT: uqadd v16.4s, v1.4s, v16.4s
+; CHECK-NEXT: uqadd v1.4s, v1.4s, v17.4s
+; CHECK-NEXT: cmhi v4.4s, v2.4s, v4.4s
+; CHECK-NEXT: cmhi v5.4s, v2.4s, v5.4s
+; CHECK-NEXT: cmhi v6.4s, v2.4s, v6.4s
+; CHECK-NEXT: cmhi v7.4s, v2.4s, v7.4s
+; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
+; CHECK-NEXT: cmhi v3.4s, v2.4s, v3.4s
+; CHECK-NEXT: cmhi v16.4s, v2.4s, v16.4s
+; CHECK-NEXT: cmhi v1.4s, v2.4s, v1.4s
+; CHECK-NEXT: uzp1 v2.8h, v5.8h, v4.8h
+; CHECK-NEXT: uzp1 v4.8h, v7.8h, v6.8h
+; CHECK-NEXT: uzp1 v0.8h, v3.8h, v0.8h
+; CHECK-NEXT: uzp1 v1.8h, v1.8h, v16.8h
+; CHECK-NEXT: uzp1 v2.16b, v4.16b, v2.16b
+; CHECK-NEXT: uzp1 v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: // fake_use: $q2
+; CHECK-NEXT: // fake_use: $q0
+; CHECK-NEXT: ret
+ %active.lane.mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i32(i32 %index, i32 %TC)
+ call void (...) @llvm.fake.use(<32 x i1> %active.lane.mask)
+ ret void
+}
+
+define <16 x i1> @lane_mask_v16i1_i32(i32 %index, i32 %TC) {
+; CHECK-LABEL: lane_mask_v16i1_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs w9, w1, w0
+; CHECK-NEXT: mov w8, #255 // =0xff
+; CHECK-NEXT: csel w9, wzr, w9, lo
+; CHECK-NEXT: cmp w9, #255
+; CHECK-NEXT: csel w8, w9, w8, lo
+; CHECK-NEXT: dup v0.16b, w8
+; CHECK-NEXT: adrp x8, .LCPI1_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
+ ret <16 x i1> %active.lane.mask
+}
+
+define <8 x i1> @lane_mask_v8i1_i32(i32 %index, i32 %TC) {
+; CHECK-LABEL: lane_mask_v8i1_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs w9, w1, w0
+; CHECK-NEXT: mov w8, #255 // =0xff
+; CHECK-NEXT: csel w9, wzr, w9, lo
+; CHECK-NEXT: cmp w9, #255
+; CHECK-NEXT: csel w8, w9, w8, lo
+; CHECK-NEXT: dup v0.8b, w8
+; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI2_0]
+; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
+ ret <8 x i1> %active.lane.mask
+}
+
+define <4 x i1> @lane_mask_v4i1_i32(i32 %index, i32 %TC) {
+; CHECK-LABEL: lane_mask_v4i1_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI3_0
+; CHECK-NEXT: dup v0.4s, w0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
+; CHECK-NEXT: uqadd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w1
+; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
+ ret <4 x i1> %active.lane.mask
+}
+
+define <2 x i1> @lane_mask_v2i1_i32(i32 %index, i32 %TC) {
+; CHECK-LABEL: lane_mask_v2i1_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4294967296 // =0x100000000
+; CHECK-NEXT: dup v0.2s, w0
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: uqadd v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w1
+; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+ %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
+ ret <2 x i1> %active.lane.mask
+}
+
+define <1 x i1> @lane_mask_v1i1_i32(i32 %index, i32 %TC) {
+; CHECK-LABEL: lane_mask_v1i1_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %active.lane.mask = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i32(i32 %index, i32 %TC)
+ ret <1 x i1> %active.lane.mask
+}
+
+define void @lane_mask_v32i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_v32i1_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI6_0
+; CHECK-NEXT: adrp x9, .LCPI6_2
+; CHECK-NEXT: dup v1.2d, x0
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-NEXT: adrp x8, .LCPI6_1
+; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI6_2]
+; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI6_1]
+; CHECK-NEXT: adrp x8, .LCPI6_3
+; CHECK-NEXT: adrp x9, .LCPI6_6
+; CHECK-NEXT: ldr q5, [x8, :lo12:.LCPI6_3]
+; CHECK-NEXT: adrp x8, .LCPI6_4
+; CHECK-NEXT: ldr q16, [x9, :lo12:.LCPI6_6]
+; CHECK-NEXT: ldr q6, [x8, :lo12:.LCPI6_4]
+; CHECK-NEXT: adrp x8, .LCPI6_5
+; CHECK-NEXT: adrp x9, .LCPI6_9
+; CHECK-NEXT: ldr q7, [x8, :lo12:.LCPI6_5]
+; CHECK-NEXT: adrp x8, .LCPI6_7
+; CHECK-NEXT: ldr q19, [x9, :lo12:.LCPI6_9]
+; CHECK-NEXT: ldr q17, [x8, :lo12:.LCPI6_7]
+; CHECK-NEXT: adrp x8, .LCPI6_8
+; CHECK-NEXT: adrp x9, .LCPI6_12
+; CHECK-NEXT: ldr q18, [x8, :lo12:.LCPI6_8]
+; CHECK-NEXT: adrp x8, .LCPI6_10
+; CHECK-NEXT: ldr q22, [x9, :lo12:.LCPI6_12]
+; CHECK-NEXT: ldr q20, [x8, :lo12:.LCPI6_10]
+; CHECK-NEXT: adrp x8, .LCPI6_11
+; CHECK-NEXT: adrp x9, .LCPI6_15
+; CHECK-NEXT: ldr q21, [x8, :lo12:.LCPI6_11]
+; CHECK-NEXT: adrp x8, .LCPI6_13
+; CHECK-NEXT: ldr q25, [x9, :lo12:.LCPI6_15]
+; CHECK-NEXT: ldr q23, [x8, :lo12:.LCPI6_13]
+; CHECK-NEXT: adrp x8, .LCPI6_14
+; CHECK-NEXT: uqadd v2.2d, v1.2d, v2.2d
+; CHECK-NEXT: ldr q24, [x8, :lo12:.LCPI6_14]
+; CHECK-NEXT: uqadd v3.2d, v1.2d, v3.2d
+; CHECK-NEXT: uqadd v4.2d, v1.2d, v4.2d
+; CHECK-NEXT: uqadd v5.2d, v1.2d, v5.2d
+; CHECK-NEXT: uqadd v6.2d, v1.2d, v6.2d
+; CHECK-NEXT: uqadd v7.2d, v1.2d, v7.2d
+; CHECK-NEXT: uqadd v16.2d, v1.2d, v16.2d
+; CHECK-NEXT: uqadd v17.2d, v1.2d, v17.2d
+; CHECK-NEXT: uqadd v18.2d, v1.2d, v18.2d
+; CHECK-NEXT: uqadd v19.2d, v1.2d, v19.2d
+; CHECK-NEXT: uqadd v20.2d, v1.2d, v20.2d
+; CHECK-NEXT: uqadd v21.2d, v1.2d, v21.2d
+; CHECK-NEXT: uqadd v22.2d, v1.2d, v22.2d
+; CHECK-NEXT: uqadd v23.2d, v1.2d, v23.2d
+; CHECK-NEXT: uqadd v24.2d, v1.2d, v24.2d
+; CHECK-NEXT: uqadd v1.2d, v1.2d, v25.2d
+; CHECK-NEXT: dup v0.2d, x1
+; CHECK-NEXT: cmhi v2.2d, v0.2d, v2.2d
+; CHECK-NEXT: cmhi v3.2d, v0.2d, v3.2d
+; CHECK-NEXT: cmhi v18.2d, v0.2d, v18.2d
+; CHECK-NEXT: cmhi v19.2d, v0.2d, v19.2d
+; CHECK-NEXT: cmhi v20.2d, v0.2d, v20.2d
+; CHECK-NEXT: cmhi v21.2d, v0.2d, v21.2d
+; CHECK-NEXT: cmhi v22.2d, v0.2d, v22.2d
+; CHECK-NEXT: cmhi v23.2d, v0.2d, v23.2d
+; CHECK-NEXT: cmhi v24.2d, v0.2d, v24.2d
+; CHECK-NEXT: cmhi v1.2d, v0.2d, v1.2d
+; CHECK-NEXT: cmhi v4.2d, v0.2d, v4.2d
+; CHECK-NEXT: cmhi v5.2d, v0.2d, v5.2d
+; CHECK-NEXT: cmhi v6.2d, v0.2d, v6.2d
+; CHECK-NEXT: cmhi v7.2d, v0.2d, v7.2d
+; CHECK-NEXT: cmhi v16.2d, v0.2d, v16.2d
+; CHECK-NEXT: cmhi v0.2d, v0.2d, v17.2d
+; CHECK-NEXT: uzp1 v2.4s, v3.4s, v2.4s
+; CHECK-NEXT: uzp1 v3.4s, v19.4s, v18.4s
+; CHECK-NEXT: uzp1 v17.4s, v21.4s, v20.4s
+; CHECK-NEXT: uzp1 v18.4s, v23.4s, v22.4s
+; CHECK-NEXT: uzp1 v1.4s, v1.4s, v24.4s
+; CHECK-NEXT: uzp1 v4.4s, v5.4s, v4.4s
+; CHECK-NEXT: uzp1 v5.4s, v7.4s, v6.4s
+; CHECK-NEXT: uzp1 v0.4s, v0.4s, v16.4s
+; CHECK-NEXT: uzp1 v3.8h, v17.8h, v3.8h
+; CHECK-NEXT: uzp1 v1.8h, v1.8h, v18.8h
+; CHECK-NEXT: uzp1 v2.8h, v4.8h, v2.8h
+; CHECK-NEXT: uzp1 v0.8h, v0.8h, v5.8h
+; CHECK-NEXT: uzp1 v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: uzp1 v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: // fake_use: $q1
+; CHECK-NEXT: // fake_use: $q0
+; CHECK-NEXT: ret
+ %active.lane.mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %TC)
+ call void (...) @llvm.fake.use(<32 x i1> %active.lane.mask)
+ ret void
+}
+
+define <16 x i1> @lane_mask_v16i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_v16i1_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs x9, x1, x0
+; CHECK-NEXT: mov w8, #255 // =0xff
+; CHECK-NEXT: csel x9, xzr, x9, lo
+; CHECK-NEXT: cmp x9, #255
+; CHECK-NEXT: csel x8, x9, x8, lo
+; CHECK-NEXT: dup v0.16b, w8
+; CHECK-NEXT: adrp x8, .LCPI7_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
+; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 %index, i64 %TC)
+ ret <16 x i1> %active.lane.mask
+}
+
+define <8 x i1> @lane_mask_v8i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_v8i1_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs x9, x1, x0
+; CHECK-NEXT: mov w8, #255 // =0xff
+; CHECK-NEXT: csel x9, xzr, x9, lo
+; CHECK-NEXT: cmp x9, #255
+; CHECK-NEXT: csel x8, x9, x8, lo
+; CHECK-NEXT: dup v0.8b, w8
+; CHECK-NEXT: adrp x8, .LCPI8_0
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI8_0]
+; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %TC)
+ ret <8 x i1> %active.lane.mask
+}
+
+define <4 x i1> @lane_mask_v4i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_v4i1_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: subs x9, x1, x0
+; CHECK-NEXT: mov w8, #65535 // =0xffff
+; CHECK-NEXT: csel x9, xzr, x9, lo
+; CHECK-NEXT: cmp x9, x8
+; CHECK-NEXT: csel x8, x9, x8, lo
+; CHECK-NEXT: dup v0.4h, w8
+; CHECK-NEXT: adrp x8, .LCPI9_0
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI9_0]
+; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %index, i64 %TC)
+ ret <4 x i1> %active.lane.mask
+}
+
+define <2 x i1> @lane_mask_v2i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_v2i1_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI10_0
+; CHECK-NEXT: dup v0.2d, x0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI10_0]
+; CHECK-NEXT: uqadd v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x1
+; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
+ %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %TC)
+ ret <2 x i1> %active.lane.mask
+}
+
+define <1 x i1> @lane_mask_v1i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_v1i1_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp x0, x1
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %active.lane.mask = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i64(i64 %index, i64 %TC)
+ ret <1 x i1> %active.lane.mask
+}
+
+define void @lane_mask_v32i1_i8(i8 %index, i8 %TC) {
+; CHECK-LABEL: lane_mask_v32i1_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI12_1
+; CHECK-NEXT: dup v0.16b, w0
+; CHECK-NEXT: adrp x9, .LCPI12_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_1]
+; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI12_0]
+; CHECK-NEXT: uqadd v1.16b, v0.16b, v1.16b
+; CHECK-NEXT: uqadd v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: dup v2.16b, w1
+; CHECK-NEXT: cmhi v1.16b, v2.16b, v1.16b
+; CHECK-NEXT: cmhi v0.16b, v2.16b, v0.16b
+; CHECK-NEXT: // fake_use: $q1
+; CHECK-NEXT: // fake_use: $q0
+; CHECK-NEXT: ret
+ %active.lane.mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i8(i8 %index, i8 %TC)
+ call void (...) @llvm.fake.use(<32 x i1> %active.lane.mask)
+ ret void
+}
+
+define <16 x i1> @lane_mask_v16i1_i8(i8 %index, i8 %TC) {
+; CHECK-LABEL: lane_mask_v16i1_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI13_0
+; CHECK-NEXT: dup v0.16b, w0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0]
+; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: dup v1.16b, w1
+; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i8(i8 %index, i8 %TC)
+ ret <16 x i1> %active.lane.mask
+}
+
+define <8 x i1> @lane_mask_v8i1_i8(i8 %index, i8 %TC) {
+; CHECK-LABEL: lane_mask_v8i1_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.8b, w0
+; CHECK-NEXT: adrp x8, .LCPI14_0
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
+; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: dup v1.8b, w1
+; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i8(i8 %index, i8 %TC)
+ ret <8 x i1> %active.lane.mask
+}
+
+define <4 x i1> @lane_mask_v4i1_i8(i8 %index, i8 %TC) {
+; CHECK-LABEL: lane_mask_v4i1_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: dup v0.4h, w0
+; CHECK-NEXT: adrp x8, .LCPI15_0
+; CHECK-NEXT: movi d2, #0xff00ff00ff00ff
+; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI15_0]
+; CHECK-NEXT: dup v3.4h, w1
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: bic v3.4h, #255, lsl #8
+; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: umin v0.4h, v0.4h, v2.4h
+; CHECK-NEXT: cmhi v0.4h, v3.4h, v0.4h
+; CHECK-NEXT: ret
+ %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i8(i8 %index, i8 %TC)
+ ret <4 x i1> %active.lane.mask
+}
+
+define <2 x i1> @lane_mask_v2i1_i8(i8 %index, i8 %TC) {
+; CHECK-LABEL: lane_mask_v2i1_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d0, #0x0000ff000000ff
+; CHECK-NEXT: dup v1.2s, w0
+; CHECK-NEXT: mov x8, #4294967296 // =0x100000000
+; CHECK-NEXT: fmov d3, x8
+; CHECK-NEXT: dup v2.2s, w1
+; CHECK-NEXT: and v1.8b, v1.8b, v0.8b
+; CHECK-NEXT: and v2.8b, v2.8b, v0.8b
+; CHECK-NEXT: add v1.2s, v1.2s, v3.2s
+; CHECK-NEXT: umin v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: cmhi v0.2s, v2.2s, v0.2s
+; CHECK-NEXT: ret
+ %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i8(i8 %index, i8 %TC)
+ ret <2 x i1> %active.lane.mask
+}
+
+define <1 x i1> @lane_mask_v1i1_i8(i8 %index, i8 %TC) {
+; CHECK-LABEL: lane_mask_v1i1_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and w8, w0, #0xff
+; CHECK-NEXT: cmp w8, w1, uxtb
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %active.lane.mask = call <1 x i1> @llvm.get.active.lane.mask.v1i1.i8(i8 %index, i8 %TC)
+ ret <1 x i1> %active.lane.mask
+}
+
+define <8 x i1> @lane_mask_v8i1_imm3() {
+; CHECK-LABEL: lane_mask_v8i1_imm3:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi d0, #0x00000000ffffff
+; CHECK-NEXT: ret
+entry:
----------------
lukel97 wrote:
Nit
```suggestion
```
https://github.com/llvm/llvm-project/pull/225459
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