[llvm] AMDGPU: Preserve dead carry-out when shrinking adds in SIFoldOperands (PR #225687)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 04:06:29 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
The VOP3 form of add/sub with carry out are sometimes shrunk to the VOPC
form when the carry out is dead. Preserve this information by setting the
dead flag on the new instruction. This alleviates some implicit dependence
on LiveVariables' later recomputation of dead flags.
Co-authored-by: Claude (Opus 4.8) <noreply@<!-- -->anthropic.com>
---
Patch is 1.86 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/225687.diff
40 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+49-65)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+49-65)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll (+4564-4570)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll (+75-92)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll (+4-7)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll (+20-25)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll (+19-22)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll (+222-243)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll (+18-21)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll (+136-148)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll (+24-27)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll (+45-50)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll (+53-58)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll (+2-4)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll (+1651-1680)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll (+85-90)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll (+91-96)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll (+15-22)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll (+101-106)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll (+111-116)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll (+183-192)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll (+395-398)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll (+210-221)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll (+44-55)
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+56-79)
- (modified) llvm/test/CodeGen/AMDGPU/div_v2i128.ll (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll (+86)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll (+5-8)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+3-6)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll (+4-8)
- (modified) llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll (+66-82)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll (+49-59)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll (+49-59)
- (modified) llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll (+66-82)
- (modified) llvm/test/CodeGen/AMDGPU/scratch-simple.ll (+772-790)
- (modified) llvm/test/CodeGen/AMDGPU/trunc-store.ll (+3-4)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 23d9610f4295e1..9166ff0f1e5b17 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -681,6 +681,10 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::COPY),
Dst1.getReg())
.addReg(AMDGPU::VCC, RegState::Kill);
+ } else {
+ // We only reach here when the carry-out vcc is dead so propagate the dead
+ // flag.
+ Inst32->getOperand(3).setIsDead();
}
// Keep the old instruction around to avoid breaking iterators, but
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index 3850141f089a77..aee2cd8428427a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -311,11 +311,10 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_min_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v1, v6, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
@@ -591,13 +590,12 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v1, v10, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v8
@@ -607,7 +605,7 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v11, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v2, v8, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
@@ -616,7 +614,7 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v5
@@ -626,7 +624,7 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
@@ -1583,18 +1581,17 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_min_i32_e32 v8, 0, v0
+; GFX6-NEXT: v_min_i32_e32 v7, 0, v0
; GFX6-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x7fffffff, v6
-; GFX6-NEXT: v_max_i32_e32 v3, v8, v3
+; GFX6-NEXT: v_max_i32_e32 v3, v7, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_min_i32_e32 v6, 0, v1
-; GFX6-NEXT: v_bfrev_b32_e32 v7, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v7, v3
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v4, 0, v2
@@ -1610,18 +1607,17 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_i32_e32 v8, 0, v0
+; GFX8-NEXT: v_min_i32_e32 v7, 0, v0
; GFX8-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x80000000, v8
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 0x80000000, v7
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x7fffffff, v6
-; GFX8-NEXT: v_max_i32_e32 v3, v8, v3
+; GFX8-NEXT: v_max_i32_e32 v3, v7, v3
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_min_i32_e32 v6, 0, v1
-; GFX8-NEXT: v_bfrev_b32_e32 v7, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, 0, v1
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v7, v3
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 0x7fffffff, v3
; GFX8-NEXT: v_max_i32_e32 v4, v6, v4
; GFX8-NEXT: v_min_i32_e32 v3, v4, v3
; GFX8-NEXT: v_min_i32_e32 v4, 0, v2
@@ -1734,26 +1730,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
+; GFX6-NEXT: v_min_i32_e32 v9, 0, v0
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
-; GFX6-NEXT: v_max_i32_e32 v4, v10, v4
+; GFX6-NEXT: v_max_i32_e32 v4, v9, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
-; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v9, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v8, v5
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v9, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1769,26 +1763,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX8-NEXT: v_bfrev_b32_e32 v11, 1
+; GFX8-NEXT: v_min_i32_e32 v9, 0, v0
; GFX8-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v11, v10
+; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 0x80000000, v9
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x7fffffff, v8
-; GFX8-NEXT: v_max_i32_e32 v4, v10, v4
+; GFX8-NEXT: v_max_i32_e32 v4, v9, v4
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_min_i32_e32 v8, 0, v1
-; GFX8-NEXT: v_bfrev_b32_e32 v9, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v1
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x80000000, v8
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v9, v4
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v8, v5
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v2
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x80000000, v5
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v9, v4
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1922,33 +1914,31 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v13, 1
+; GFX6-NEXT: v_min_i32_e32 v11, 0, v0
; GFX6-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v13, v12
+; GFX6-NEXT: v_sub_i32_e32 v11, vcc, 0x80000000, v11
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x7fffffff, v10
-; GFX6-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX6-NEXT: v_max_i32_e32 v5, v11, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_min_i32_e32 v10, 0, v1
-; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v13, v10
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v10, v6
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v7
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v8
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v4
@@ -1964,33 +1954,31 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX8-NEXT: v_bfrev_b32_e32 v13, 1
+; GFX8-NEXT: v_min_i32_e32 v11, 0, v0
; GFX8-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v12, vcc, v13, v12
+; GFX8-NEXT: v_sub_u32_e32 v11, vcc, 0x80000000, v11
; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x7fffffff, v10
-; GFX8-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX8-NEXT: v_max_i32_e32 v5, v11, v5
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_min_i32_e32 v10, 0, v1
-; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v13, v10
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x80000000, v10
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v10, v6
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v2
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v7
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v3
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v8
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v4
@@ -3002,11 +2990,10 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v1, v6, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
@@ -3222,11 +3209,10 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v5, 1
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v4, s0, v4
; GFX6-NEXT: v_min_i32_e32 v2, v4, v2
@@ -3302,11 +3288,10 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v2, v10, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v8
@@ -3316,7 +3301,7 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6
; GFX6-NEXT: v_max_i32_e32 v6, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v11, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
@@ -3327,7 +3312,7 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v9, v4
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v4
@@ -3336,7 +3321,7 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
@@ -3570,11 +3555,10 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v14, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v15, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_max_i32_e32 v12, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v15, v14
+; GFX6-NEXT: v_sub_i32_e32 v14, vcc, 0x80000000, v14
; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 0x7fffffff, v12
; GFX6-NEXT: v_max_i32_e32 v3, v14, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v12
@@ -3584,7 +3568,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_bfrev_b32_e32 v13, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GFX6-NEXT: v_max_i32_e32 v9, 0, v3
-; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v15, v12
+; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 0x80000000, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v13, v9
; GFX6-NEXT: v_max_i32_e32 v6, v12, v6
@@ -3595,7 +3579,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_max_i32_e32 v6, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v15, v9
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v13, v6
; GFX6-NEXT: v_max_i32_e32 v4, v9, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
@@ -3604,7 +3588,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_min_i32_e32 v9, 0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10
; GFX6-NEXT: v_max_i32_e32 v7, 0, v4
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v15, v9
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v9, v6
@@ -3615,7 +3599,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_max_i32_e32 v6, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v15, v7
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v13, v6
; GFX6-NEXT: v_max_i32_e32 v5, v7, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
@@ -3625,7 +3609,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; GFX6-NEXT: v_max_i32_e32 v7, 0, v5
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v15, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index fb824fa0ee11bf..e23337d7ae9ec5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -315,8 +315,7 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
; GFX6-NEXT: v_min_i32_e32 v6, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v6
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -597,8 +596,7 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
-; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_max_i32_e32 v1, v8, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -608,7 +606,7 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v8
; GFX6-NEXT:...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/225687
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