[llvm] AMDGPU: Preserve dead carry-out when shrinking adds in SIFoldOperands (PR #225687)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 23 04:05:34 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/225687
The VOP3 form of add/sub with carry out are sometimes shrunk to the VOPC
form when the carry out is dead. Preserve this information by setting the
dead flag on the new instruction. This alleviates some implicit dependence
on LiveVariables' later recomputation of dead flags.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
>From f2043da652017a771b69200aef4aa86a851995a4 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 23 Sep 2026 12:50:08 +0200
Subject: [PATCH] AMDGPU: Preserve dead carry-out when shrinking adds in
SIFoldOperands
The VOP3 form of add/sub with carry out are sometimes shrunk to the VOPC
form when the carry out is dead. Preserve this information by setting the
dead flag on the new instruction. This alleviates some implicit dependence
on LiveVariables' later recomputation of dead flags.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 4 +
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 114 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 114 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 9134 ++++++++---------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 167 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll | 11 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll | 45 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll | 41 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 465 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll | 39 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 284 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll | 51 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll | 95 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll | 111 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll | 6 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 3331 +++---
.../CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll | 175 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll | 187 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 37 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll | 207 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll | 227 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 375 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll | 793 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 431 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 99 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 135 +-
llvm/test/CodeGen/AMDGPU/div_v2i128.ll | 24 +-
...ds-negative-offset-addressing-mode-loop.ll | 86 +
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 13 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 9 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll | 12 +-
.../CodeGen/AMDGPU/fold-fi-operand-shrink.mir | 14 +-
...ld-immediate-operand-shrink-with-carry.mir | 4 +-
.../AMDGPU/fold-immediate-operand-shrink.mir | 26 +-
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 148 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 108 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 108 +-
.../CodeGen/AMDGPU/local-atomicrmw-fsub.ll | 148 +-
llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 1562 ++-
llvm/test/CodeGen/AMDGPU/trunc-store.ll | 7 +-
40 files changed, 9359 insertions(+), 9588 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 23d9610f4295e1..9166ff0f1e5b17 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -681,6 +681,10 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::COPY),
Dst1.getReg())
.addReg(AMDGPU::VCC, RegState::Kill);
+ } else {
+ // We only reach here when the carry-out vcc is dead so propagate the dead
+ // flag.
+ Inst32->getOperand(3).setIsDead();
}
// Keep the old instruction around to avoid breaking iterators, but
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index 3850141f089a77..aee2cd8428427a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -311,11 +311,10 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_min_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v1, v6, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
@@ -591,13 +590,12 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v1, v10, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v8
@@ -607,7 +605,7 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v11, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v2, v8, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
@@ -616,7 +614,7 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v5
@@ -626,7 +624,7 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
@@ -1583,18 +1581,17 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_min_i32_e32 v8, 0, v0
+; GFX6-NEXT: v_min_i32_e32 v7, 0, v0
; GFX6-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x7fffffff, v6
-; GFX6-NEXT: v_max_i32_e32 v3, v8, v3
+; GFX6-NEXT: v_max_i32_e32 v3, v7, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_min_i32_e32 v6, 0, v1
-; GFX6-NEXT: v_bfrev_b32_e32 v7, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v7, v3
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v4, 0, v2
@@ -1610,18 +1607,17 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_i32_e32 v8, 0, v0
+; GFX8-NEXT: v_min_i32_e32 v7, 0, v0
; GFX8-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x80000000, v8
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 0x80000000, v7
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x7fffffff, v6
-; GFX8-NEXT: v_max_i32_e32 v3, v8, v3
+; GFX8-NEXT: v_max_i32_e32 v3, v7, v3
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_min_i32_e32 v6, 0, v1
-; GFX8-NEXT: v_bfrev_b32_e32 v7, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, 0, v1
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v7, v3
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 0x7fffffff, v3
; GFX8-NEXT: v_max_i32_e32 v4, v6, v4
; GFX8-NEXT: v_min_i32_e32 v3, v4, v3
; GFX8-NEXT: v_min_i32_e32 v4, 0, v2
@@ -1734,26 +1730,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
+; GFX6-NEXT: v_min_i32_e32 v9, 0, v0
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
-; GFX6-NEXT: v_max_i32_e32 v4, v10, v4
+; GFX6-NEXT: v_max_i32_e32 v4, v9, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
-; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v9, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v8, v5
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v9, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1769,26 +1763,24 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX8-NEXT: v_bfrev_b32_e32 v11, 1
+; GFX8-NEXT: v_min_i32_e32 v9, 0, v0
; GFX8-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v11, v10
+; GFX8-NEXT: v_sub_u32_e32 v9, vcc, 0x80000000, v9
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x7fffffff, v8
-; GFX8-NEXT: v_max_i32_e32 v4, v10, v4
+; GFX8-NEXT: v_max_i32_e32 v4, v9, v4
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_min_i32_e32 v8, 0, v1
-; GFX8-NEXT: v_bfrev_b32_e32 v9, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v1
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 0x80000000, v8
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v9, v4
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v8, v5
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, 0, v2
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x80000000, v5
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v9, v4
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v4, v5, v4
; GFX8-NEXT: v_min_i32_e32 v5, 0, v3
@@ -1922,33 +1914,31 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_saddsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v13, 1
+; GFX6-NEXT: v_min_i32_e32 v11, 0, v0
; GFX6-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v13, v12
+; GFX6-NEXT: v_sub_i32_e32 v11, vcc, 0x80000000, v11
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x7fffffff, v10
-; GFX6-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX6-NEXT: v_max_i32_e32 v5, v11, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_min_i32_e32 v10, 0, v1
-; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v13, v10
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v10, v6
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v7
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
-; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x7fffffff, v5
; GFX6-NEXT: v_max_i32_e32 v6, v6, v8
; GFX6-NEXT: v_min_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v6, 0, v4
@@ -1964,33 +1954,31 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_saddsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX8-NEXT: v_bfrev_b32_e32 v13, 1
+; GFX8-NEXT: v_min_i32_e32 v11, 0, v0
; GFX8-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX8-NEXT: v_sub_u32_e32 v12, vcc, v13, v12
+; GFX8-NEXT: v_sub_u32_e32 v11, vcc, 0x80000000, v11
; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x7fffffff, v10
-; GFX8-NEXT: v_max_i32_e32 v5, v12, v5
+; GFX8-NEXT: v_max_i32_e32 v5, v11, v5
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_min_i32_e32 v10, 0, v1
-; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v13, v10
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v10, vcc, 0x80000000, v10
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v10, v6
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v2
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v7
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, 0, v3
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 0x80000000, v6
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v11, v5
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 0x7fffffff, v5
; GFX8-NEXT: v_max_i32_e32 v6, v6, v8
; GFX8-NEXT: v_min_i32_e32 v5, v6, v5
; GFX8-NEXT: v_min_i32_e32 v6, 0, v4
@@ -3002,11 +2990,10 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v6, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_max_i32_e32 v1, v6, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
@@ -3222,11 +3209,10 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v4, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v5, 1
; GFX6-NEXT: s_lshr_b32 s1, s0, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v4, s0, v4
; GFX6-NEXT: v_min_i32_e32 v2, v4, v2
@@ -3302,11 +3288,10 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v11, v10
+; GFX6-NEXT: v_sub_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x7fffffff, v8
; GFX6-NEXT: v_max_i32_e32 v2, v10, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v8
@@ -3316,7 +3301,7 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6
; GFX6-NEXT: v_max_i32_e32 v6, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v11, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
@@ -3327,7 +3312,7 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v9, v4
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v4
@@ -3336,7 +3321,7 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3
-; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
+; GFX6-NEXT: v_sub_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
@@ -3570,11 +3555,10 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v14, 0, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v15, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_max_i32_e32 v12, 0, v0
-; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v15, v14
+; GFX6-NEXT: v_sub_i32_e32 v14, vcc, 0x80000000, v14
; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 0x7fffffff, v12
; GFX6-NEXT: v_max_i32_e32 v3, v14, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v12
@@ -3584,7 +3568,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_bfrev_b32_e32 v13, -2
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GFX6-NEXT: v_max_i32_e32 v9, 0, v3
-; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v15, v12
+; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 0x80000000, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v13, v9
; GFX6-NEXT: v_max_i32_e32 v6, v12, v6
@@ -3595,7 +3579,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_max_i32_e32 v6, 0, v1
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v15, v9
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v13, v6
; GFX6-NEXT: v_max_i32_e32 v4, v9, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
@@ -3604,7 +3588,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_min_i32_e32 v9, 0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10
; GFX6-NEXT: v_max_i32_e32 v7, 0, v4
-; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v15, v9
+; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v9, v6
@@ -3615,7 +3599,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_max_i32_e32 v6, 0, v2
-; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v15, v7
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v13, v6
; GFX6-NEXT: v_max_i32_e32 v5, v7, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
@@ -3625,7 +3609,7 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; GFX6-NEXT: v_max_i32_e32 v7, 0, v5
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v15, v8
+; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index fb824fa0ee11bf..e23337d7ae9ec5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -315,8 +315,7 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
; GFX6-NEXT: v_min_i32_e32 v6, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v6
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -597,8 +596,7 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
-; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_max_i32_e32 v1, v8, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -608,7 +606,7 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
@@ -617,7 +615,7 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v3, v5, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
@@ -628,7 +626,7 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2
@@ -1585,14 +1583,13 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_max_i32_e32 v6, -1, v0
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000001, v6
-; GFX6-NEXT: v_min_i32_e32 v8, -1, v0
-; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000000, v8
+; GFX6-NEXT: v_min_i32_e32 v7, -1, v0
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
-; GFX6-NEXT: v_min_i32_e32 v3, v3, v8
-; GFX6-NEXT: v_mov_b32_e32 v7, 0x80000001
+; GFX6-NEXT: v_min_i32_e32 v3, v3, v7
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000001, v3
; GFX6-NEXT: v_min_i32_e32 v6, -1, v1
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v3, v3, v4
@@ -1612,14 +1609,13 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_i32_e32 v6, -1, v0
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000001, v6
-; GFX8-NEXT: v_min_i32_e32 v8, -1, v0
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, 0x80000000, v8
+; GFX8-NEXT: v_min_i32_e32 v7, -1, v0
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x80000000, v7
; GFX8-NEXT: v_max_i32_e32 v3, v6, v3
-; GFX8-NEXT: v_min_i32_e32 v3, v3, v8
-; GFX8-NEXT: v_mov_b32_e32 v7, 0x80000001
+; GFX8-NEXT: v_min_i32_e32 v3, v3, v7
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000001, v3
; GFX8-NEXT: v_min_i32_e32 v6, -1, v1
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v3, v3, v4
@@ -1736,22 +1732,20 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v8
-; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
-; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GFX6-NEXT: v_min_i32_e32 v9, -1, v0
+; GFX6-NEXT: v_add_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
-; GFX6-NEXT: v_min_i32_e32 v4, v4, v10
-; GFX6-NEXT: v_mov_b32_e32 v9, 0x80000001
+; GFX6-NEXT: v_min_i32_e32 v4, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v9
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v4, v4, v5
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v9
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v4, v4, v6
@@ -1771,22 +1765,20 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_i32_e32 v8, -1, v0
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 0x80000001, v8
-; GFX8-NEXT: v_min_i32_e32 v10, -1, v0
-; GFX8-NEXT: v_bfrev_b32_e32 v11, 1
-; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v11
+; GFX8-NEXT: v_min_i32_e32 v9, -1, v0
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x80000000, v9
; GFX8-NEXT: v_max_i32_e32 v4, v8, v4
-; GFX8-NEXT: v_min_i32_e32 v4, v4, v10
-; GFX8-NEXT: v_mov_b32_e32 v9, 0x80000001
+; GFX8-NEXT: v_min_i32_e32 v4, v4, v9
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v9
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000001, v4
; GFX8-NEXT: v_min_i32_e32 v8, -1, v1
; GFX8-NEXT: v_add_u32_e32 v8, vcc, 0x80000000, v8
; GFX8-NEXT: v_max_i32_e32 v4, v4, v5
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v9
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000001, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v2
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000000, v5
; GFX8-NEXT: v_max_i32_e32 v4, v4, v6
@@ -1924,29 +1916,27 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_max_i32_e32 v10, -1, v0
; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0x80000001, v10
-; GFX6-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v13, 1
-; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v13
+; GFX6-NEXT: v_min_i32_e32 v11, -1, v0
+; GFX6-NEXT: v_add_i32_e32 v11, vcc, 0x80000000, v11
; GFX6-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX6-NEXT: v_min_i32_e32 v5, v5, v12
-; GFX6-NEXT: v_mov_b32_e32 v11, 0x80000001
+; GFX6-NEXT: v_min_i32_e32 v5, v5, v11
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v11
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000001, v5
; GFX6-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v11
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000001, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v7
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v11
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000001, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v8
@@ -1966,29 +1956,27 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_i32_e32 v10, -1, v0
; GFX8-NEXT: v_add_u32_e32 v10, vcc, 0x80000001, v10
-; GFX8-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX8-NEXT: v_bfrev_b32_e32 v13, 1
-; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v13
+; GFX8-NEXT: v_min_i32_e32 v11, -1, v0
+; GFX8-NEXT: v_add_u32_e32 v11, vcc, 0x80000000, v11
; GFX8-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX8-NEXT: v_min_i32_e32 v5, v5, v12
-; GFX8-NEXT: v_mov_b32_e32 v11, 0x80000001
+; GFX8-NEXT: v_min_i32_e32 v5, v5, v11
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v11
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000001, v5
; GFX8-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v13
+; GFX8-NEXT: v_add_u32_e32 v10, vcc, 0x80000000, v10
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v11
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000001, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v2
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v7
; GFX8-NEXT: v_min_i32_e32 v5, v5, v6
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v11
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000001, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v3
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000000, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v8
@@ -3006,8 +2994,7 @@ define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
; GFX6-NEXT: v_min_i32_e32 v6, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v6
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -3226,8 +3213,7 @@ define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v2
; GFX6-NEXT: v_min_i32_e32 v4, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v5, 1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000000, v4
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -3306,8 +3292,7 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
-; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v11
+; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0x80000000, v10
; GFX6-NEXT: v_max_i32_e32 v2, v8, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
@@ -3317,7 +3302,7 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_max_i32_e32 v6, -1, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; GFX6-NEXT: v_min_i32_e32 v8, -1, v2
-; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v11
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
@@ -3328,7 +3313,7 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GFX6-NEXT: v_min_i32_e32 v6, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v3, v4, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
@@ -3337,7 +3322,7 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v11
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v6
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
@@ -3574,8 +3559,7 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v12, vcc, 0x80000001, v12
; GFX6-NEXT: v_min_i32_e32 v14, -1, v0
-; GFX6-NEXT: v_bfrev_b32_e32 v15, 1
-; GFX6-NEXT: v_add_i32_e32 v14, vcc, v14, v15
+; GFX6-NEXT: v_add_i32_e32 v14, vcc, 0x80000000, v14
; GFX6-NEXT: v_max_i32_e32 v3, v12, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v14
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
@@ -3585,7 +3569,7 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_max_i32_e32 v9, -1, v3
; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; GFX6-NEXT: v_min_i32_e32 v12, -1, v3
-; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v15
+; GFX6-NEXT: v_add_i32_e32 v12, vcc, 0x80000000, v12
; GFX6-NEXT: v_max_i32_e32 v6, v9, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX6-NEXT: v_min_i32_e32 v6, v6, v12
@@ -3596,7 +3580,7 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v13
; GFX6-NEXT: v_min_i32_e32 v9, -1, v1
-; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v15
+; GFX6-NEXT: v_add_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
@@ -3605,7 +3589,7 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GFX6-NEXT: v_min_i32_e32 v9, -1, v4
-; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v15
+; GFX6-NEXT: v_add_i32_e32 v9, vcc, 0x80000000, v9
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX6-NEXT: v_min_i32_e32 v6, v6, v9
@@ -3616,7 +3600,7 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v13
; GFX6-NEXT: v_min_i32_e32 v7, -1, v2
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v15
+; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0x80000000, v7
; GFX6-NEXT: v_max_i32_e32 v5, v6, v5
; GFX6-NEXT: v_min_i32_e32 v5, v5, v7
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
@@ -3627,7 +3611,7 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GFX6-NEXT: v_min_i32_e32 v8, -1, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
-; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v15
+; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000000, v8
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 47468f3c7c4cf4..37436f1d94c962 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -11931,9 +11931,9 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
@@ -11960,12 +11960,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
+; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v41, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
@@ -12035,7 +12035,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -12141,7 +12141,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
@@ -12175,7 +12175,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -12290,36 +12290,36 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -12328,12 +12328,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
+; SI-NEXT: v_or_b32_e32 v0, v0, v42
+; SI-NEXT: v_or_b32_e32 v2, v2, v54
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_or_b32_e32 v3, v40, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -12346,22 +12346,23 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v32, v4
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr58
@@ -12370,14 +12371,14 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
+; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
@@ -12506,7 +12507,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -12618,7 +12619,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -12905,8 +12906,9 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
@@ -12915,9 +12917,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
@@ -12936,7 +12937,6 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -12945,14 +12945,14 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
+; SI-NEXT: v_or_b32_e32 v0, v42, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -12960,7 +12960,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -12983,16 +12983,16 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
+; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
@@ -13001,12 +13001,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
+; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
@@ -13015,7 +13015,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -13024,7 +13024,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -13033,7 +13033,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -13042,7 +13042,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -13069,9 +13069,9 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
@@ -13085,7 +13085,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
@@ -13098,7 +13098,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
@@ -13111,7 +13111,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
@@ -13124,7 +13124,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
@@ -13136,7 +13136,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -13153,13 +13153,13 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -13170,7 +13170,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -13187,7 +13187,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
@@ -13204,7 +13204,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
@@ -13221,7 +13221,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
@@ -13238,7 +13238,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
@@ -13255,7 +13255,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
@@ -13272,7 +13272,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
@@ -13289,7 +13289,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
@@ -13305,8 +13305,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
@@ -13323,7 +13323,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
@@ -13340,7 +13340,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x3000000, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
@@ -13357,7 +13357,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -13374,7 +13374,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
@@ -13391,7 +13391,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
@@ -24358,9 +24358,8 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
@@ -24370,7 +24369,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24378,7 +24377,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
@@ -24388,7 +24387,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24396,7 +24395,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
@@ -24406,7 +24405,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24414,7 +24413,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
@@ -24424,7 +24423,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24432,7 +24431,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
@@ -24442,7 +24441,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24450,7 +24449,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
@@ -24460,7 +24459,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24468,7 +24467,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
@@ -24478,7 +24477,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24486,7 +24485,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
@@ -24496,7 +24495,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24504,7 +24503,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
@@ -24514,7 +24513,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24522,7 +24521,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
@@ -24532,7 +24531,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24540,7 +24539,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
@@ -24550,7 +24549,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24558,7 +24557,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
@@ -24568,7 +24567,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24576,7 +24575,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
@@ -24586,7 +24585,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24594,7 +24593,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
@@ -24604,7 +24603,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24612,7 +24611,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
@@ -24622,7 +24621,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24630,7 +24629,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
@@ -24641,7 +24640,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24649,7 +24648,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
@@ -24659,7 +24658,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24667,7 +24666,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
@@ -24677,7 +24676,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24685,7 +24684,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
@@ -24695,7 +24694,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24703,7 +24702,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
@@ -24713,7 +24712,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24721,7 +24720,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
@@ -24731,7 +24730,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24739,7 +24738,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
@@ -24749,7 +24748,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24757,7 +24756,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
@@ -24767,7 +24766,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24775,7 +24774,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
@@ -24785,7 +24784,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24793,7 +24792,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
@@ -24803,7 +24802,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24811,7 +24810,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
@@ -24821,7 +24820,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24829,7 +24828,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
@@ -24839,7 +24838,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24847,7 +24846,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
@@ -24857,7 +24856,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24865,7 +24864,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
@@ -24875,7 +24874,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24883,7 +24882,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
@@ -24893,7 +24892,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -24901,7 +24900,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
@@ -24911,7 +24910,7 @@ define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -34804,9 +34803,9 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v24
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
@@ -34935,9 +34934,9 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v1, v42
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
+; SI-NEXT: v_or_b32_e32 v6, v6, v48
; SI-NEXT: v_or_b32_e32 v7, v7, v55
; SI-NEXT: v_or_b32_e32 v9, v9, v54
; SI-NEXT: v_or_b32_e32 v10, v10, v39
@@ -34957,9 +34956,9 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
@@ -35129,35 +35128,34 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v49, v0
; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
+; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
+; SI-NEXT: v_or_b32_e32 v6, v48, v6
; SI-NEXT: v_or_b32_e32 v7, v55, v7
; SI-NEXT: v_or_b32_e32 v9, v54, v9
; SI-NEXT: v_or_b32_e32 v10, v39, v10
; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -35166,19 +35164,19 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -35187,8 +35185,8 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -35197,8 +35195,8 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
@@ -35207,8 +35205,8 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -35217,8 +35215,8 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -35227,8 +35225,8 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
@@ -35237,8 +35235,8 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
@@ -35247,7 +35245,7 @@ define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -48047,9 +48045,9 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
@@ -48076,12 +48074,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
+; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v41, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
@@ -48151,7 +48149,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -48257,7 +48255,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
@@ -48291,7 +48289,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -48406,36 +48404,36 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -48444,12 +48442,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
+; SI-NEXT: v_or_b32_e32 v0, v0, v42
+; SI-NEXT: v_or_b32_e32 v2, v2, v54
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_or_b32_e32 v3, v40, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -48462,22 +48460,23 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v32, v4
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr58
@@ -48486,14 +48485,14 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
+; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
@@ -48622,7 +48621,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -48734,7 +48733,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -49021,8 +49020,9 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
@@ -49031,9 +49031,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
@@ -49052,7 +49051,6 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -49061,14 +49059,14 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
+; SI-NEXT: v_or_b32_e32 v0, v42, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -49076,7 +49074,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -49099,16 +49097,16 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
+; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
@@ -49117,12 +49115,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
+; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
@@ -49131,7 +49129,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -49140,7 +49138,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -49149,7 +49147,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -49158,7 +49156,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -49185,9 +49183,9 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
@@ -49201,7 +49199,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
@@ -49214,7 +49212,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
@@ -49227,7 +49225,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
@@ -49240,7 +49238,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
@@ -49252,7 +49250,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -49269,13 +49267,13 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -49286,7 +49284,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -49303,7 +49301,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
@@ -49320,7 +49318,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
@@ -49337,7 +49335,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
@@ -49354,7 +49352,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
@@ -49371,7 +49369,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
@@ -49388,7 +49386,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
@@ -49405,7 +49403,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
@@ -49421,8 +49419,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
@@ -49439,7 +49437,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
@@ -49456,7 +49454,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x3000000, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
@@ -49473,7 +49471,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -49490,7 +49488,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
@@ -49507,7 +49505,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
@@ -60613,9 +60611,8 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
@@ -60625,7 +60622,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60633,7 +60630,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
@@ -60643,7 +60640,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60651,7 +60648,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
@@ -60661,7 +60658,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60669,7 +60666,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
@@ -60679,7 +60676,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60687,7 +60684,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
@@ -60697,7 +60694,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60705,7 +60702,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
@@ -60715,7 +60712,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60723,7 +60720,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
@@ -60733,7 +60730,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60741,7 +60738,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
@@ -60751,7 +60748,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60759,7 +60756,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
@@ -60769,7 +60766,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60777,7 +60774,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
@@ -60787,7 +60784,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60795,7 +60792,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
@@ -60805,7 +60802,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60813,7 +60810,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
@@ -60823,7 +60820,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60831,7 +60828,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
@@ -60841,7 +60838,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60849,7 +60846,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
@@ -60859,7 +60856,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60867,7 +60864,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
@@ -60877,7 +60874,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60885,7 +60882,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
@@ -60896,7 +60893,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60904,7 +60901,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
@@ -60914,7 +60911,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60922,7 +60919,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
@@ -60932,7 +60929,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60940,7 +60937,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
@@ -60950,7 +60947,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60958,7 +60955,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
@@ -60968,7 +60965,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60976,7 +60973,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
@@ -60986,7 +60983,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -60994,7 +60991,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
@@ -61004,7 +61001,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61012,7 +61009,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
@@ -61022,7 +61019,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61030,7 +61027,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
@@ -61040,7 +61037,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61048,7 +61045,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
@@ -61058,7 +61055,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61066,7 +61063,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
@@ -61076,7 +61073,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61084,7 +61081,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
@@ -61094,7 +61091,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61102,7 +61099,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
@@ -61112,7 +61109,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61120,7 +61117,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
@@ -61130,7 +61127,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61138,7 +61135,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
@@ -61148,7 +61145,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -61156,7 +61153,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
@@ -61166,7 +61163,7 @@ define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -71365,9 +71362,9 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v24
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
@@ -71496,9 +71493,9 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v1, v42
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
+; SI-NEXT: v_or_b32_e32 v6, v6, v48
; SI-NEXT: v_or_b32_e32 v7, v7, v55
; SI-NEXT: v_or_b32_e32 v9, v9, v54
; SI-NEXT: v_or_b32_e32 v10, v10, v39
@@ -71518,9 +71515,9 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
@@ -71690,35 +71687,34 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v49, v0
; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
+; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
+; SI-NEXT: v_or_b32_e32 v6, v48, v6
; SI-NEXT: v_or_b32_e32 v7, v55, v7
; SI-NEXT: v_or_b32_e32 v9, v54, v9
; SI-NEXT: v_or_b32_e32 v10, v39, v10
; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -71727,19 +71723,19 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -71748,8 +71744,8 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -71758,8 +71754,8 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
@@ -71768,8 +71764,8 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -71778,8 +71774,8 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -71788,8 +71784,8 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
@@ -71798,8 +71794,8 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
@@ -71808,7 +71804,7 @@ define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -82382,9 +82378,9 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
@@ -82411,12 +82407,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
+; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v41, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
@@ -82486,7 +82482,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -82592,7 +82588,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
@@ -82626,7 +82622,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -82741,36 +82737,36 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -82779,12 +82775,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
+; SI-NEXT: v_or_b32_e32 v0, v0, v42
+; SI-NEXT: v_or_b32_e32 v2, v2, v54
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_or_b32_e32 v3, v40, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -82797,22 +82793,23 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v32, v4
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr58
@@ -82821,14 +82818,14 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
+; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
@@ -82957,7 +82954,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -83069,7 +83066,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -83356,8 +83353,9 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
@@ -83366,9 +83364,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
@@ -83387,7 +83384,6 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -83396,14 +83392,14 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
+; SI-NEXT: v_or_b32_e32 v0, v42, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -83411,7 +83407,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -83434,16 +83430,16 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
+; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
@@ -83452,12 +83448,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
+; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
@@ -83466,7 +83462,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -83475,7 +83471,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -83484,7 +83480,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -83493,7 +83489,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -83520,9 +83516,9 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
@@ -83536,7 +83532,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
@@ -83549,7 +83545,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
@@ -83562,7 +83558,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
@@ -83575,7 +83571,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
@@ -83587,7 +83583,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -83604,13 +83600,13 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -83621,7 +83617,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -83638,7 +83634,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
@@ -83655,7 +83651,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
@@ -83672,7 +83668,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
@@ -83689,7 +83685,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
@@ -83706,7 +83702,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
@@ -83723,7 +83719,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
@@ -83740,7 +83736,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
@@ -83756,8 +83752,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
@@ -83774,7 +83770,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
@@ -83791,7 +83787,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x3000000, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
@@ -83808,7 +83804,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -83825,7 +83821,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
@@ -83842,7 +83838,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
@@ -94817,9 +94813,8 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
@@ -94829,7 +94824,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94837,7 +94832,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
@@ -94847,7 +94842,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94855,7 +94850,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
@@ -94865,7 +94860,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94873,7 +94868,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
@@ -94883,7 +94878,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94891,7 +94886,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
@@ -94901,7 +94896,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94909,7 +94904,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
@@ -94919,7 +94914,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94927,7 +94922,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
@@ -94937,7 +94932,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94945,7 +94940,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
@@ -94955,7 +94950,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94963,7 +94958,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
@@ -94973,7 +94968,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94981,7 +94976,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
@@ -94991,7 +94986,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -94999,7 +94994,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
@@ -95009,7 +95004,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95017,7 +95012,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
@@ -95027,7 +95022,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95035,7 +95030,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
@@ -95045,7 +95040,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95053,7 +95048,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
@@ -95063,7 +95058,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95071,7 +95066,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
@@ -95081,7 +95076,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95089,7 +95084,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
@@ -95100,7 +95095,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95108,7 +95103,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
@@ -95118,7 +95113,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95126,7 +95121,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
@@ -95136,7 +95131,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95144,7 +95139,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
@@ -95154,7 +95149,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95162,7 +95157,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
@@ -95172,7 +95167,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95180,7 +95175,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
@@ -95190,7 +95185,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95198,7 +95193,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
@@ -95208,7 +95203,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95216,7 +95211,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
@@ -95226,7 +95221,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95234,7 +95229,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
@@ -95244,7 +95239,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95252,7 +95247,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
@@ -95262,7 +95257,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95270,7 +95265,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
@@ -95280,7 +95275,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95288,7 +95283,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
@@ -95298,7 +95293,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95306,7 +95301,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
@@ -95316,7 +95311,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95324,7 +95319,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
@@ -95334,7 +95329,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95342,7 +95337,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
@@ -95352,7 +95347,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -95360,7 +95355,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
@@ -95370,7 +95365,7 @@ define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -105369,9 +105364,9 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v24
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
@@ -105500,9 +105495,9 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v1, v42
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
+; SI-NEXT: v_or_b32_e32 v6, v6, v48
; SI-NEXT: v_or_b32_e32 v7, v7, v55
; SI-NEXT: v_or_b32_e32 v9, v9, v54
; SI-NEXT: v_or_b32_e32 v10, v10, v39
@@ -105522,9 +105517,9 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
@@ -105694,35 +105689,34 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v49, v0
; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
+; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
+; SI-NEXT: v_or_b32_e32 v6, v48, v6
; SI-NEXT: v_or_b32_e32 v7, v55, v7
; SI-NEXT: v_or_b32_e32 v9, v54, v9
; SI-NEXT: v_or_b32_e32 v10, v39, v10
; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -105731,19 +105725,19 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -105752,8 +105746,8 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -105762,8 +105756,8 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
@@ -105772,8 +105766,8 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -105782,8 +105776,8 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -105792,8 +105786,8 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
@@ -105802,8 +105796,8 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
@@ -105812,7 +105806,7 @@ define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -115617,9 +115611,9 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
@@ -115646,12 +115640,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:168
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:184
-; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v5
+; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v1
+; SI-NEXT: v_lshlrev_b32_e32 v41, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v7
-; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v53, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v17
@@ -115721,7 +115715,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -115827,7 +115821,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
@@ -115861,7 +115855,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -115976,36 +115970,36 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xff, v49
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -116014,12 +116008,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v54
-; SI-NEXT: v_or_b32_e32 v2, v2, v41
+; SI-NEXT: v_or_b32_e32 v0, v0, v42
+; SI-NEXT: v_or_b32_e32 v2, v2, v54
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_or_b32_e32 v3, v40, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -116032,22 +116026,23 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v32, v4
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v60, v5
-; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v58, v6
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr58
@@ -116056,14 +116051,14 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_or_b32_e32 v2, v2, v53
+; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
@@ -116192,7 +116187,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -116304,7 +116299,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -116591,8 +116586,9 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB74_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
@@ -116601,9 +116597,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v49
@@ -116622,7 +116617,6 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
@@ -116631,14 +116625,14 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v54, v0
+; SI-NEXT: v_or_b32_e32 v0, v42, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v41, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
@@ -116646,7 +116640,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v34, v3
+; SI-NEXT: v_or_b32_e32 v3, v53, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -116669,16 +116663,16 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v37, v7
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v41, v1
+; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
@@ -116687,12 +116681,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v53, v2
+; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
@@ -116701,7 +116695,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -116710,7 +116704,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -116719,7 +116713,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -116728,7 +116722,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -116755,9 +116749,9 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v63
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
@@ -116771,7 +116765,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v59
@@ -116784,7 +116778,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
@@ -116797,7 +116791,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v47
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v50
@@ -116810,7 +116804,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v45
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v36
@@ -116822,7 +116816,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -116839,13 +116833,13 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -116856,7 +116850,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
@@ -116873,7 +116867,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v17
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
@@ -116890,7 +116884,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
@@ -116907,7 +116901,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
@@ -116924,7 +116918,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v20
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xff, v21
@@ -116941,7 +116935,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
@@ -116958,7 +116952,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xff, v23
@@ -116975,7 +116969,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
@@ -116991,8 +116985,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v24
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v24
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xff, v25
@@ -117009,7 +117003,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xff, v26
@@ -117026,7 +117020,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x3000000, v26
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xff, v27
@@ -117043,7 +117037,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v27, v28, v27
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v27
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v27
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xff, v28
@@ -117060,7 +117054,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v28, v29, v28
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v28
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xff, v29
@@ -117077,7 +117071,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v29, v30, v29
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v29
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v29
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xff, v30
@@ -128052,9 +128046,8 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc
@@ -128064,7 +128057,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128072,7 +128065,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc
@@ -128082,7 +128075,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128090,7 +128083,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc
@@ -128100,7 +128093,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128108,7 +128101,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc
@@ -128118,7 +128111,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128126,7 +128119,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc
@@ -128136,7 +128129,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128144,7 +128137,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc
@@ -128154,7 +128147,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128162,7 +128155,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc
@@ -128172,7 +128165,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128180,7 +128173,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc
@@ -128190,7 +128183,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128198,7 +128191,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc
@@ -128208,7 +128201,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128216,7 +128209,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc
@@ -128226,7 +128219,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128234,7 +128227,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc
@@ -128244,7 +128237,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128252,7 +128245,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc
@@ -128262,7 +128255,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128270,7 +128263,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc
@@ -128280,7 +128273,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128288,7 +128281,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc
@@ -128298,7 +128291,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128306,7 +128299,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc
@@ -128316,7 +128309,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128324,7 +128317,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc
@@ -128335,7 +128328,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128343,7 +128336,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc
@@ -128353,7 +128346,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128361,7 +128354,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc
@@ -128371,7 +128364,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128379,7 +128372,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc
@@ -128389,7 +128382,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128397,7 +128390,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc
@@ -128407,7 +128400,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128415,7 +128408,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc
@@ -128425,7 +128418,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128433,7 +128426,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc
@@ -128443,7 +128436,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128451,7 +128444,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc
@@ -128461,7 +128454,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128469,7 +128462,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc
@@ -128479,7 +128472,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128487,7 +128480,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc
@@ -128497,7 +128490,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128505,7 +128498,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc
@@ -128515,7 +128508,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128523,7 +128516,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc
@@ -128533,7 +128526,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128541,7 +128534,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc
@@ -128551,7 +128544,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128559,7 +128552,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc
@@ -128569,7 +128562,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128577,7 +128570,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc
@@ -128587,7 +128580,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -128595,7 +128588,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc
@@ -128605,7 +128598,7 @@ define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
; VI-NEXT: v_bfe_u32 v33, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
@@ -138584,9 +138577,9 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v27
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v26
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v24
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v19
@@ -138715,9 +138708,9 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v1, v42
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v41
-; SI-NEXT: v_or_b32_e32 v4, v4, v48
+; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v40
-; SI-NEXT: v_or_b32_e32 v6, v6, v33
+; SI-NEXT: v_or_b32_e32 v6, v6, v48
; SI-NEXT: v_or_b32_e32 v7, v7, v55
; SI-NEXT: v_or_b32_e32 v9, v9, v54
; SI-NEXT: v_or_b32_e32 v10, v10, v39
@@ -138737,9 +138730,9 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr39
@@ -138909,35 +138902,34 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v49, v0
; SI-NEXT: v_or_b32_e32 v1, v42, v1
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v41, v3
-; SI-NEXT: v_or_b32_e32 v4, v48, v4
+; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v40, v5
-; SI-NEXT: v_or_b32_e32 v6, v33, v6
+; SI-NEXT: v_or_b32_e32 v6, v48, v6
; SI-NEXT: v_or_b32_e32 v7, v55, v7
; SI-NEXT: v_or_b32_e32 v9, v54, v9
; SI-NEXT: v_or_b32_e32 v10, v39, v10
; SI-NEXT: v_or_b32_e32 v11, v53, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -138946,19 +138938,19 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -138967,8 +138959,8 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v38, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -138977,8 +138969,8 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
@@ -138987,8 +138979,8 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v37, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -138997,8 +138989,8 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v15, v51, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -139007,8 +138999,8 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v36, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
@@ -139017,8 +139009,8 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v17, v50, v17
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v29, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
@@ -139027,7 +139019,7 @@ define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v35, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
@@ -140395,7 +140387,6 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; kill: killed $vgpr21
; SI-NEXT: ; implicit-def: $vgpr21
-; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; kill: killed $vgpr21
@@ -140405,15 +140396,14 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr37
@@ -140462,6 +140452,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -140510,12 +140502,6 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; kill: killed $vgpr22
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; kill: killed $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
@@ -140540,7 +140526,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v26
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v28
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
@@ -140558,7 +140544,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v1
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
@@ -140581,52 +140567,52 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v3
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v1
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:280
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v0
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v3
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v6
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:304
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:304
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:300
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:300
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:296
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:292
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:308
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -140634,34 +140620,34 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v0
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v5
+; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v9
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:336
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:344
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:316
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:332
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:344
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:324
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:340
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v11
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v13
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v14
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:352
+; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v15
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:352
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:376
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:364
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:360
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:356
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:372
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:384
+; SI-NEXT: v_lshlrev_b32_e32 v60, 24, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:384
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:380
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v61, 24, v13
@@ -140669,458 +140655,285 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; kill: killed $vgpr13
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v14
+; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v15
; SI-NEXT: ; kill: killed $vgpr13
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; kill: killed $vgpr13
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:36
+; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:36
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:28
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:12
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:92
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:116
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:84
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:76
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:68
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:60
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:52
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:44
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:40
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; kill: killed $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v31, v7, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v6
-; SI-NEXT: v_or_b32_e32 v32, v4, v2
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v11
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v29, v45, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: v_or_b32_e32 v33, v0, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_or_b32_e32 v31, v7, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v20
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v34, v47, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
-; SI-NEXT: v_or_b32_e32 v0, v0, v59
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v8
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v27, v54, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v9
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v2, v2, v43
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v42
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v35, v60, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v56
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v46
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v36, v5, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v44
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v37, v61, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v58
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v57
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v4, v4, v63
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v38, v62, v5
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v4
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v29, v45, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v53
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v12
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr42
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr44
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr45
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
+; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v12, v12, v13
+; SI-NEXT: v_or_b32_e32 v11, v11, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v13, v13, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v14, v15
+; SI-NEXT: v_or_b32_e32 v16, v15, v16
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
+; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
+; SI-NEXT: v_or_b32_e32 v15, v18, v15
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v21, v15, v19
+; SI-NEXT: v_or_b32_e32 v18, v15, v18
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v18
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v19, v15
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -141144,18 +140957,19 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v39, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v21, v15, v19
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
@@ -141164,7 +140978,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v15, v19, v15
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -141178,8 +140992,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v48, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v39, v15, v19
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -141205,23 +141019,22 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v49, v15, v19
+; SI-NEXT: v_or_b32_e32 v48, v15, v19
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v49
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
@@ -141231,7 +141044,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -141247,9 +141060,10 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v50, v15, v19
+; SI-NEXT: v_or_b32_e32 v49, v15, v19
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v49
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
@@ -141281,7 +141095,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v51, v15, v19
+; SI-NEXT: v_or_b32_e32 v50, v15, v19
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -141302,7 +141116,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
@@ -141315,12 +141129,9 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v15, v19
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v51, v15, v19
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v52
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
@@ -141352,16 +141163,17 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v53, v15, v19
+; SI-NEXT: v_or_b32_e32 v52, v15, v19
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v22, v19, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
@@ -141372,41 +141184,35 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v48
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v1
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v25, v3, v15
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v25, v2, v15
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v24, v17, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v3, v3, v18
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v3
-; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v2, v2, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
-; SI-NEXT: v_or_b32_e32 v30, v17, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v24, v17, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v28, v10, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v30, v15, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v39
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v50
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; kill: killed $vgpr2
; SI-NEXT: ; implicit-def: $vgpr2
@@ -141473,445 +141279,629 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; kill: killed $vgpr2
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; kill: killed $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v28, v5, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v10
+; SI-NEXT: v_or_b32_e32 v32, v4, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v9
+; SI-NEXT: v_or_b32_e32 v33, v4, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_or_b32_e32 v34, v47, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
+; SI-NEXT: v_or_b32_e32 v0, v0, v59
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v42
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v35, v60, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v56
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v46
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v36, v5, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v44
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v27, v55, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v8
+; SI-NEXT: v_or_b32_e32 v37, v61, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v58
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v57
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v3, v3, v43
+; SI-NEXT: v_or_b32_e32 v4, v4, v63
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_or_b32_e32 v38, v62, v5
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v4
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr6
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: .LBB88_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB88_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v4
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_or_b32_e32 v2, v7, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v7, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v8, v43, v8
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_or_b32_e32 v0, v45, v0
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: v_or_b32_e32 v8, v0, v8
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v20
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_or_b32_e32 v0, v10, v0
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_or_b32_e32 v5, v47, v5
+; SI-NEXT: v_or_b32_e32 v6, v55, v6
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v11
-; SI-NEXT: v_or_b32_e32 v5, v43, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_or_b32_e32 v9, v45, v9
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v5, v9, v5
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
-; SI-NEXT: v_or_b32_e32 v6, v6, v9
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_or_b32_e32 v8, v54, v8
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: v_or_b32_e32 v6, v8, v6
+; SI-NEXT: v_or_b32_e32 v6, v6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v3
+; SI-NEXT: v_or_b32_e32 v0, v12, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v1, v7, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v7, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v58
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
-; SI-NEXT: v_or_b32_e32 v12, v63, v12
+; SI-NEXT: v_or_b32_e32 v11, v63, v11
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, 0x300, v12
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x300, v11
; SI-NEXT: v_or_b32_e32 v13, v62, v13
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v13, v12
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v46
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v44
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v46
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v44
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_or_b32_e32 v14, v61, v14
+; SI-NEXT: v_or_b32_e32 v15, v61, v15
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v41
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v42
-; SI-NEXT: v_or_b32_e32 v14, v59, v14
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v15, v60, v15
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v4
-; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v42
+; SI-NEXT: v_or_b32_e32 v15, v59, v15
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_or_b32_e32 v16, v60, v16
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
+; SI-NEXT: v_or_b32_e32 v9, v9, v16
+; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_or_b32_e32 v14, v47, v14
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v14, v9
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v9
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v3
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v10, v2
-; SI-NEXT: v_or_b32_e32 v8, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v8
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_or_b32_e32 v1, v18, v1
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_or_b32_e32 v2, v17, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v9, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v9
-; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v1, v5, v1
+; SI-NEXT: v_or_b32_e32 v10, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v6
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v1, v17, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v12, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v8
+; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v4
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v10, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v10
-; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v11, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v11
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; SI-NEXT: v_or_b32_e32 v14, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v15, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v16, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v10
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
+; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v16, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v16
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v16
-; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v17, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v17
+; SI-NEXT: v_or_b32_e32 v17, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v17
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v18, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, s7, v18
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v18
+; SI-NEXT: v_or_b32_e32 v18, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v18
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v14
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v19, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v19
+; SI-NEXT: v_or_b32_e32 v19, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v19
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v21, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v22
+; SI-NEXT: v_or_b32_e32 v20, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v20
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v20
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v21, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v21
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v23, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v25, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v25
+; SI-NEXT: v_or_b32_e32 v23, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v23
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v26, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v26
+; SI-NEXT: v_or_b32_e32 v24, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v24
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v27, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v25, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_or_b32_e32 v28, v2, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s7, v28
-; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v3
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v3
+; SI-NEXT: v_or_b32_e32 v26, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_or_b32_e32 v27, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v29, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_or_b32_e32 v30, v2, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v27
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v29
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_or_b32_e32 v28, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v15
+; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v2
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v2
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v29, v1, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v29
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v30, v12
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v30, v1, v0
+; SI-NEXT: v_or_b32_e32 v15, v30, v15
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v27
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x3000000, v28
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v2
-; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v1
-; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v1
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v1
+; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v0
+; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v0
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v16, v19, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_or_b32_e32 v16, v19, v16
+; SI-NEXT: v_or_b32_e32 v15, v16, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
@@ -141927,7 +141917,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v23, v19
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
@@ -141945,7 +141935,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v23, v19
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -141963,7 +141953,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v29, v19
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -141980,7 +141970,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v30, v19
; SI-NEXT: v_or_b32_e32 v15, v19, v15
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -141998,7 +141988,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_or_b32_e32 v30, v31, v30
; SI-NEXT: v_or_b32_e32 v15, v30, v15
-; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -142017,7 +142007,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v15, v31, v15
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v31
; SI-NEXT: v_and_b32_e32 v31, 0xff, v31
@@ -142033,10 +142023,10 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_or_b32_e32 v32, v33, v32
; SI-NEXT: v_or_b32_e32 v31, v32, v31
-; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v31
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
@@ -142050,7 +142040,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v23
; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
@@ -142059,64 +142049,67 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v16
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
-; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v18
+; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v13
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v11
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v25
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v21
-; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v13
+; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v21
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v22
-; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v20
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
+; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v20
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
-; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
+; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v9
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v9
@@ -142127,12 +142120,11 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v5
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: .LBB88_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
@@ -142140,24 +142132,24 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v19
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v12
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v13
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v23
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v21
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v39
-; SI-NEXT: v_mul_f32_e32 v18, 1.0, v48
-; SI-NEXT: v_mul_f32_e32 v20, 1.0, v49
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v21
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v18
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v18, 1.0, v39
+; SI-NEXT: v_mul_f32_e32 v20, 1.0, v48
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v26
-; SI-NEXT: v_mul_f32_e32 v26, 1.0, v52
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v26, 1.0, v51
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
@@ -142176,11 +142168,11 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
; SI-NEXT: s_waitcnt vmcnt(2)
@@ -142191,7 +142183,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
@@ -142226,7 +142218,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v8
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
@@ -142235,22 +142227,22 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v10
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v10, v10, v12, 16
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
-; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v12, v12, v14, 16
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
+; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
@@ -142288,14 +142280,14 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_alignbit_b32 v20, v20, v21, 16
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v22
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
-; SI-NEXT: v_mul_f32_e32 v22, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v22, 1.0, v49
; SI-NEXT: v_alignbit_b32 v21, v21, v22, 16
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v25
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22
; SI-NEXT: v_alignbit_b32 v22, v22, v23, 16
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v24
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
-; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v24, 1.0, v50
; SI-NEXT: v_alignbit_b32 v23, v23, v24, 16
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v28
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
@@ -142327,7 +142319,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_alignbit_b32 v26, v26, v27, 16
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v29
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
-; SI-NEXT: v_mul_f32_e32 v28, 1.0, v53
+; SI-NEXT: v_mul_f32_e32 v28, 1.0, v52
; SI-NEXT: v_alignbit_b32 v27, v27, v28, 16
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
@@ -142335,7 +142327,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_alignbit_b32 v28, v28, v29, 16
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v35
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
-; SI-NEXT: v_mul_f32_e32 v30, 1.0, v55
+; SI-NEXT: v_mul_f32_e32 v30, 1.0, v54
; SI-NEXT: v_alignbit_b32 v29, v29, v30, 16
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v37
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30
@@ -153548,9 +153540,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v18, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v18
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v34, v35, vcc
@@ -153560,7 +153551,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153568,7 +153559,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: v_cndmask_b32_e32 v17, v34, v35, vcc
@@ -153578,7 +153569,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153586,7 +153577,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v20
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v34, v35, vcc
@@ -153596,7 +153587,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153604,7 +153595,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v19
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v34, v35, vcc
@@ -153614,7 +153605,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153622,7 +153613,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v22
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v34, v35, vcc
@@ -153632,7 +153623,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153640,7 +153631,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v21
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v34, v35, vcc
@@ -153650,7 +153641,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153658,7 +153649,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v24
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v34, v35, vcc
@@ -153668,7 +153659,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153676,7 +153667,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v23
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v34, v35, vcc
@@ -153686,7 +153677,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153694,7 +153685,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v26
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v34, v35, vcc
@@ -153704,7 +153695,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153712,7 +153703,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v25
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v34, v35, vcc
@@ -153722,7 +153713,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153730,7 +153721,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v28
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v34, v35, vcc
@@ -153740,7 +153731,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153748,7 +153739,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v27
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v34, v35, vcc
@@ -153758,7 +153749,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153766,7 +153757,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v30
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v34, v35, vcc
@@ -153776,7 +153767,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153784,7 +153775,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v29
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v34, v35, vcc
@@ -153794,7 +153785,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153802,7 +153793,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v32, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v32
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v32
; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32
; VI-NEXT: v_cndmask_b32_e32 v32, v34, v35, vcc
@@ -153812,7 +153803,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153820,7 +153811,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v31
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v34, v35, vcc
@@ -153830,7 +153821,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153838,7 +153829,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v2
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v34, v35, vcc
@@ -153848,7 +153839,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153856,7 +153847,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v1
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v34, v35, vcc
@@ -153866,7 +153857,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153874,7 +153865,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v4
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v34, v35, vcc
@@ -153884,7 +153875,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153892,7 +153883,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v3
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v34, v35, vcc
@@ -153902,7 +153893,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153910,7 +153901,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v6
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v34, v35, vcc
@@ -153920,7 +153911,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153928,7 +153919,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v5
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v34, v35, vcc
@@ -153938,7 +153929,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153946,7 +153937,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v8
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v34, v35, vcc
@@ -153956,7 +153947,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153964,7 +153955,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v7
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v34, v35, vcc
@@ -153974,7 +153965,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -153982,7 +153973,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v10
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v34, v35, vcc
@@ -153992,7 +153983,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154000,7 +153991,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v9
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v34, v35, vcc
@@ -154010,7 +154001,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154018,7 +154009,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v12
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v34, v35, vcc
@@ -154028,7 +154019,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154036,7 +154027,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v11
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v34, v35, vcc
@@ -154046,7 +154037,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154054,7 +154045,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v14
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v34, v35, vcc
@@ -154064,7 +154055,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154072,7 +154063,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v13
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v34, v35, vcc
@@ -154082,7 +154073,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154090,7 +154081,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v16
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
; VI-NEXT: v_cndmask_b32_e32 v16, v34, v35, vcc
@@ -154100,7 +154091,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -154108,7 +154099,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v15
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v34, v35, vcc
@@ -166935,27 +166926,28 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v59, v24
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v47, v16
-; SI-NEXT: v_mov_b32_e32 v61, v14
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v60, v6
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v60, v24
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v59, v16
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v41, v0
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
@@ -166969,1360 +166961,1357 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:144
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92
-; SI-NEXT: v_lshlrev_b32_e32 v40, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v21
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v19
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v29
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v27
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v43, v8
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v61, v6
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v8
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v10
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v4
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v14
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v12
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v20
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v18
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:76
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:108
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:100
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:136
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(5) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v28
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v30
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:168
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v32
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v33
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v33
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v34
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v5
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:240
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v4
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(6) expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v2
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v0
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:268
+; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v3
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v5
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:300
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:260
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:304
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:292
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v15
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:340
+; SI-NEXT: v_lshlrev_b32_e32 v45, 8, v3
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v14
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v16
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v4
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:376
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v0
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:332
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:328
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v3
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:380
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:364
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v18
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:368
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:364
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:360
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:356
+; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v16
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v14
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v18
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v20
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:100
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(3) expcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v7
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v10
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v51, 0xff, v47
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v48, 0xff, v43
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v41
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v58
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v6, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v60
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mov_b32_e32 v60, v32
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v9, v1, v9
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mov_b32_e32 v61, v32
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v6, v0, v6
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v11, v10, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v61
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v10, v1, v10
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v12, v0, v7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v12, v1, v12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v13, v7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v13, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v7, v0, v7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v14, v0, v10
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v15, v10, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v15, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v10, v0, v10
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v25, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v16, v0, v11
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v16, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v17, v11, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v19, v19, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v11, v0, v11
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v49, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v19, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v20, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v20, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v21, v21, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v25, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v50, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v21, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v22, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v22, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v23, v23, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v24, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v24, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v27, v27, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v49, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v53, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v27, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v28, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v28, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v29, v29, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v50, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v54, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v29, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v30, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v30, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v33, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v52, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v55, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v33, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v34, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v34, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v35, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v53, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v41, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v35, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v36, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v37, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v54, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v42, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v37, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v38, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v38, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v39, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v40, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v44, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v39, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v45, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v43, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v63, v31, v63
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v26, v26, v31
+; SI-NEXT: v_or_b32_e32 v42, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v7, v7, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v32, v31, v4
+; SI-NEXT: v_or_b32_e32 v44, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v63, v18, v63
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v46, v56, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v5, v5, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v31, v31, v40
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v59
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v31, v31, v9
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v48, v48, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v32, v26, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v51, v51, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v45, v18, v45
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v56, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v26, v47, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v47, v56, v18
+; SI-NEXT: v_or_b32_e32 v56, v2, v58
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v55
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v2, v57, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v3, v62, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v4, v4, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v12
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v31, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v59
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v51, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v60
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v57, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v57, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v58, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v58, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v62, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v62, v18, v0
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v18, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v1, v18, v1
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v18, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v6, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v40, v1
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v40, v40, v43
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v9, v18, v9
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v60, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v55, v18, v55
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v61
+; SI-NEXT: v_or_b32_e32 v60, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v47, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v46, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v61, v43, v59
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v61, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v43, v43, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v41, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v59, 0xff, v59
-; SI-NEXT: v_or_b32_e32 v59, v59, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v59, v18, v59
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v5
-; SI-NEXT: v_alignbit_b32 v9, v8, v9, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v11, v9, v10
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v48, v9, v12
-; SI-NEXT: v_alignbit_b32 v9, v11, v12, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v12, v9, v17
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v51
-; SI-NEXT: v_or_b32_e32 v9, v9, v14
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v9, v12, v14, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v51, v9, v25
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v56
-; SI-NEXT: v_or_b32_e32 v15, v9, v16
-; SI-NEXT: v_alignbit_b32 v9, v51, v16, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v9, v9, v49
+; SI-NEXT: v_or_b32_e32 v8, v8, v6
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v4, v8, v12, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v4, v4, v7
+; SI-NEXT: v_or_b32_e32 v12, v12, v14
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v12, v4, v14, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v10
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v51
+; SI-NEXT: v_or_b32_e32 v15, v13, v16
+; SI-NEXT: v_alignbit_b32 v13, v12, v16, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v17
+; SI-NEXT: v_or_b32_e32 v51, v13, v11
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v57
-; SI-NEXT: v_or_b32_e32 v16, v13, v20
-; SI-NEXT: v_alignbit_b32 v13, v9, v20, 16
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v17, v13, v19
+; SI-NEXT: v_alignbit_b32 v13, v51, v19, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v31, v13, v50
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v14, v13, v25
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v58
-; SI-NEXT: v_or_b32_e32 v13, v13, v22
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v13, v31, v22, 16
+; SI-NEXT: v_or_b32_e32 v16, v13, v21
+; SI-NEXT: v_alignbit_b32 v13, v14, v21, 16
; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v23
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v62
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: v_or_b32_e32 v14, v14, v24
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v14, v13, v24, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v24, v14, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v14, v28
-; SI-NEXT: v_alignbit_b32 v14, v24, v28, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v29
-; SI-NEXT: v_or_b32_e32 v21, v14, v54
-; SI-NEXT: v_or_b32_e32 v22, v6, v30
-; SI-NEXT: v_alignbit_b32 v6, v21, v30, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v19, v6, v55
-; SI-NEXT: v_or_b32_e32 v29, v1, v34
-; SI-NEXT: v_alignbit_b32 v1, v19, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v23, v1, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v20, v1, v36
-; SI-NEXT: v_alignbit_b32 v1, v23, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v30, v1, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
-; SI-NEXT: v_or_b32_e32 v27, v1, v38
-; SI-NEXT: v_alignbit_b32 v1, v30, v38, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
-; SI-NEXT: v_or_b32_e32 v28, v1, v44
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v47
-; SI-NEXT: v_or_b32_e32 v34, v1, v45
-; SI-NEXT: v_alignbit_b32 v1, v28, v45, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v63
-; SI-NEXT: v_or_b32_e32 v33, v1, v26
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v36, v1, v7
-; SI-NEXT: v_alignbit_b32 v1, v33, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v35, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v38, v1, v46
-; SI-NEXT: v_alignbit_b32 v1, v35, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v31, v13, v48
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v62
+; SI-NEXT: v_or_b32_e32 v57, v13, v23
+; SI-NEXT: v_alignbit_b32 v13, v31, v23, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v37, v1, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v59
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v0
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v13, v13, v49
+; SI-NEXT: v_alignbit_b32 v0, v13, v27, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v28
+; SI-NEXT: v_or_b32_e32 v24, v0, v50
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v29
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v24, v29, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v30
+; SI-NEXT: v_or_b32_e32 v21, v0, v52
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v22, v0, v33
+; SI-NEXT: v_alignbit_b32 v0, v21, v33, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v19, v0, v53
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55
+; SI-NEXT: v_or_b32_e32 v29, v0, v35
+; SI-NEXT: v_alignbit_b32 v0, v19, v35, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v23, v0, v54
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v60
+; SI-NEXT: v_or_b32_e32 v20, v0, v37
+; SI-NEXT: v_alignbit_b32 v0, v23, v37, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v38
+; SI-NEXT: v_or_b32_e32 v30, v0, v40
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v46
+; SI-NEXT: v_or_b32_e32 v27, v0, v39
+; SI-NEXT: v_alignbit_b32 v0, v30, v39, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v43
+; SI-NEXT: v_or_b32_e32 v28, v0, v42
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v61
+; SI-NEXT: v_or_b32_e32 v34, v0, v44
+; SI-NEXT: v_alignbit_b32 v0, v28, v44, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v63
+; SI-NEXT: v_or_b32_e32 v33, v0, v5
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v41
+; SI-NEXT: v_or_b32_e32 v36, v0, v32
+; SI-NEXT: v_alignbit_b32 v0, v33, v32, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v35, v0, v26
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
+; SI-NEXT: v_or_b32_e32 v38, v0, v47
+; SI-NEXT: v_alignbit_b32 v0, v35, v47, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v56
+; SI-NEXT: v_or_b32_e32 v37, v0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v39, v0, v3
+; SI-NEXT: v_alignbit_b32 v0, v37, v3, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v39, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v37, v3, 16
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_mov_b32_e32 v18, v57
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: .LBB92_2: ; %Flow
-; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
-; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB92_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_or_b32_e32 v2, v58, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
+; SI-NEXT: v_or_b32_e32 v3, v57, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v37
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v62, v4
+; SI-NEXT: v_mov_b32_e32 v20, v1
+; SI-NEXT: v_add_i32_e32 v37, vcc, 0x3000000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v37
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v6, v0, v6
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x300, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v4, v4, v6
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x3000000, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v3, v0, v3
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: v_or_b32_e32 v6, v56, v6
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 0x300, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v6, v45, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v47, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x3000000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v35
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v1, v0, v7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v56, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v35
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v26, v7
+; SI-NEXT: v_or_b32_e32 v1, v7, v1
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x3000000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_or_b32_e32 v7, v63, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v7, v5
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v63, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v5, v5, v8
+; SI-NEXT: v_or_b32_e32 v5, v5, v7
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x3000000, v5
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v0, v0, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v0, v7, v0
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v6
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x3000000, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -168337,10 +168326,10 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v7
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v28
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
@@ -168357,7 +168346,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v8
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
@@ -168371,12 +168360,12 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v9
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
@@ -168404,16 +168393,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v11
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168422,16 +168411,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v12
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v12
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168440,14 +168429,14 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168456,15 +168445,15 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168473,46 +168462,48 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v17
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v17
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v24
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168521,16 +168512,15 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v18
-; SI-NEXT: v_mov_b32_e32 v18, v5
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168539,15 +168529,15 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v25, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168556,10 +168546,10 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v26, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v26
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v26
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
@@ -168574,18 +168564,18 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v31, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v15
-; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v31
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v15
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v32, v20, v19
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -168595,19 +168585,19 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v48, v20, v19
; SI-NEXT: v_or_b32_e32 v0, v48, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v25
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v10
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v25
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168616,15 +168606,15 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168633,16 +168623,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168651,15 +168641,15 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v51, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v51, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v51
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168668,16 +168658,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168686,14 +168676,14 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -168702,51 +168692,52 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v40, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -168754,170 +168745,173 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v0, v11, v48, 16
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v0, v8, v7, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v12, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v4, v6, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v51, v15, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v12, v15, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v9, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v31, v3, 16
+; SI-NEXT: v_alignbit_b32 v0, v51, v17, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v14, v16, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v31, v18, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v13, v4, 16
+; SI-NEXT: v_alignbit_b32 v0, v13, v3, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v24, v5, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v21, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v19, v29, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v23, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v30, v27, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v28, v34, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v33, v36, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v35, v38, 16
-; SI-NEXT: v_alignbit_b32 v1, v8, v7, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v37, v39, 16
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: .LBB92_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v45
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v44
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v48
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
-; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v49
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v12, v12, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v29
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v55
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v54
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v18, v18, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v25
; SI-NEXT: v_or_b32_e32 v19, v19, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -168927,7 +168921,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v28
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v44
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v43
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
@@ -187664,27 +187658,28 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v59, v24
-; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v47, v16
-; SI-NEXT: v_mov_b32_e32 v61, v14
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v60, v6
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(6)
+; SI-NEXT: v_mov_b32_e32 v60, v24
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v59, v16
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v46, v8
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v41, v0
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:388
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:16
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48
@@ -187698,1360 +187693,1357 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:160
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:144
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:184
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92
-; SI-NEXT: v_lshlrev_b32_e32 v40, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:92
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v21
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v19
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v29
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v27
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; SI-NEXT: v_mov_b32_e32 v43, v8
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v17
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v25
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: v_mov_b32_e32 v61, v6
+; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr55
-; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v8
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v10
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v4
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v14
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v14
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v16
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v12
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v20
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v20
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v22
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v18
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v18
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v24
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v24
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:76
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:36
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:108
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:100
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:136
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(5) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v8
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v5
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v28
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v30
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v30
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:168
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v10
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:164
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:732 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v32
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v33
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v33
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v34
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:720 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:188
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:212
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:212
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:724 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:744 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:208
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:208
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:752 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v5
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:800 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:240
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:828 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v3
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v2
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:708 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:196
; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:276
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284
-; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:832 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v4
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(6) expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:756 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268
-; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v2
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v4
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:232
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:228
+; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:768 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:276
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v0
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:816 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:340
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:804 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:272
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:268
+; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v3
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304
+; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v5
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:808 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:300
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:264
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:260
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:920 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:728 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:304
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:292
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v15
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:340
+; SI-NEXT: v_lshlrev_b32_e32 v45, 8, v3
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v3
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v14
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr14
-; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v16
+; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v4
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:376
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v0
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:384
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:296
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:292
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:764 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:336
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:332
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v14
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:328
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:324
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:824 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v2
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:376
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v3
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:384
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:380
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:952 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:364
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:356
-; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v18
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:368
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:364
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:360
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:356
+; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v16
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: s_waitcnt vmcnt(7)
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v15
+; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v14
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v19
+; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v18
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v20
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:40
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:36
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:100
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(3) expcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v6
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:772 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v7
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:812 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:836 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v10
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:876 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v11
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:928 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v13
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:960 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v15
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v19
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr10
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v51, 0xff, v47
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v48, 0xff, v43
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v41
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v2, v58
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v5, v1
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v6, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v60
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_mov_b32_e32 v60, v32
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v9, v1, v9
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v61
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_mov_b32_e32 v61, v32
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v6, v0, v6
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v11, v10, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v61
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v10, v1, v10
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v12, v0, v7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v12, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v12, v1, v12
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v13, v7, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v13, v13, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v7, v0, v7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v14, v0, v10
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v1, v14
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v15, v10, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v15, v15, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v10, v0, v10
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v25, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v16, v0, v11
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v16, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v16, v1, v16
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v17, v11, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v19, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v19, v19, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v11, v0, v11
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v49, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v19, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v20, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v20, v1, v20
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v20, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v21, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v21, v21, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v25, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v50, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v21, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v22, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v22, v1, v22
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v22, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v23, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v23, v23, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v52, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v24, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v24, v1, v24
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v24, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v27, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v27, v27, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v49, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v53, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v27, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v28, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v28, v1, v28
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v28, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v29, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v29, v29, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v50, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v54, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v29, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v30, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v30, v1, v30
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v30, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v33, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v52, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v55, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v33, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v34, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v34, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v35, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v53, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v41, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v35, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v36, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v37, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v54, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v42, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v37, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v38, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v38, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v39, v31, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v40, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v44, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v39, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v45, v1, v31
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v43, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:816 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v63, v31, v63
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v26, v26, v31
+; SI-NEXT: v_or_b32_e32 v42, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v7, v7, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v32, v31, v4
+; SI-NEXT: v_or_b32_e32 v44, v0, v18
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v63, v18, v63
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: v_or_b32_e32 v46, v56, v31
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v5, v5, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v31, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v31, v31, v40
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v59
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
-; SI-NEXT: v_or_b32_e32 v31, v31, v9
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v48, v48, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v32, v26, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v51, v51, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v45, v18, v45
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v56, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v26, v47, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; SI-NEXT: v_or_b32_e32 v47, v56, v18
+; SI-NEXT: v_or_b32_e32 v56, v2, v58
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v55
+; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v46
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_or_b32_e32 v2, v57, v2
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_or_b32_e32 v3, v62, v3
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v4, v4, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v4, v4, v12
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v31, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v59
+; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v51, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v60
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v57, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v57, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v58, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v58, v18, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v62, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v62, v18, v0
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v1
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v18, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v0, v0, v27
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v1, v18, v1
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v18, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v6, v40, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v40, v1
-; SI-NEXT: v_and_b32_e32 v40, 0xff, v60
-; SI-NEXT: v_or_b32_e32 v40, v40, v43
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v9, v18, v9
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v60, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v55, v18, v55
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v61
+; SI-NEXT: v_or_b32_e32 v60, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v47, v43, v47
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v46, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v61, v43, v59
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v61, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v43, 0xff, v43
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v43, v43, v59
-; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v41, v18, v41
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v59, 0xff, v59
-; SI-NEXT: v_or_b32_e32 v59, v59, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v59, v18, v59
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_or_b32_e32 v18, v18, v8
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v8, v5
-; SI-NEXT: v_alignbit_b32 v9, v8, v9, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:968 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v11, v9, v10
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v48
-; SI-NEXT: v_or_b32_e32 v48, v9, v12
-; SI-NEXT: v_alignbit_b32 v9, v11, v12, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v13
-; SI-NEXT: v_or_b32_e32 v12, v9, v17
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v51
-; SI-NEXT: v_or_b32_e32 v9, v9, v14
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v9, v12, v14, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v51, v9, v25
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v56
-; SI-NEXT: v_or_b32_e32 v15, v9, v16
-; SI-NEXT: v_alignbit_b32 v9, v51, v16, 16
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v9, v9, v49
+; SI-NEXT: v_or_b32_e32 v8, v8, v6
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v4, v8, v12, 16
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v13
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v31
+; SI-NEXT: v_or_b32_e32 v4, v4, v7
+; SI-NEXT: v_or_b32_e32 v12, v12, v14
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v12, v4, v14, 16
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v12, v12, v10
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v51
+; SI-NEXT: v_or_b32_e32 v15, v13, v16
+; SI-NEXT: v_alignbit_b32 v13, v12, v16, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v17
+; SI-NEXT: v_or_b32_e32 v51, v13, v11
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v57
-; SI-NEXT: v_or_b32_e32 v16, v13, v20
-; SI-NEXT: v_alignbit_b32 v13, v9, v20, 16
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v17, v13, v19
+; SI-NEXT: v_alignbit_b32 v13, v51, v19, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v31, v13, v50
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v20
+; SI-NEXT: v_or_b32_e32 v14, v13, v25
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v58
-; SI-NEXT: v_or_b32_e32 v13, v13, v22
-; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v13, v31, v22, 16
+; SI-NEXT: v_or_b32_e32 v16, v13, v21
+; SI-NEXT: v_alignbit_b32 v13, v14, v21, 16
; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v23
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v62
-; SI-NEXT: v_or_b32_e32 v13, v13, v52
-; SI-NEXT: v_or_b32_e32 v14, v14, v24
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v14, v13, v24, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v24, v14, v53
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v18, v14, v28
-; SI-NEXT: v_alignbit_b32 v14, v24, v28, 16
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v29
-; SI-NEXT: v_or_b32_e32 v21, v14, v54
-; SI-NEXT: v_or_b32_e32 v22, v6, v30
-; SI-NEXT: v_alignbit_b32 v6, v21, v30, 16
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v33
-; SI-NEXT: v_or_b32_e32 v19, v6, v55
-; SI-NEXT: v_or_b32_e32 v29, v1, v34
-; SI-NEXT: v_alignbit_b32 v1, v19, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35
-; SI-NEXT: v_or_b32_e32 v23, v1, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v40
-; SI-NEXT: v_or_b32_e32 v20, v1, v36
-; SI-NEXT: v_alignbit_b32 v1, v23, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v30, v1, v42
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v60
-; SI-NEXT: v_or_b32_e32 v27, v1, v38
-; SI-NEXT: v_alignbit_b32 v1, v30, v38, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39
-; SI-NEXT: v_or_b32_e32 v28, v1, v44
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v47
-; SI-NEXT: v_or_b32_e32 v34, v1, v45
-; SI-NEXT: v_alignbit_b32 v1, v28, v45, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v63
-; SI-NEXT: v_or_b32_e32 v33, v1, v26
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
-; SI-NEXT: v_or_b32_e32 v36, v1, v7
-; SI-NEXT: v_alignbit_b32 v1, v33, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32
-; SI-NEXT: v_or_b32_e32 v35, v1, v4
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v43
-; SI-NEXT: v_or_b32_e32 v38, v1, v46
-; SI-NEXT: v_alignbit_b32 v1, v35, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v22
+; SI-NEXT: v_or_b32_e32 v31, v13, v48
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v62
+; SI-NEXT: v_or_b32_e32 v57, v13, v23
+; SI-NEXT: v_alignbit_b32 v13, v31, v23, 16
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v37, v1, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v59
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v0
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v24
+; SI-NEXT: v_or_b32_e32 v13, v13, v49
+; SI-NEXT: v_alignbit_b32 v0, v13, v27, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v28
+; SI-NEXT: v_or_b32_e32 v24, v0, v50
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v29
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v24, v29, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v30
+; SI-NEXT: v_or_b32_e32 v21, v0, v52
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v22, v0, v33
+; SI-NEXT: v_alignbit_b32 v0, v21, v33, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v34
+; SI-NEXT: v_or_b32_e32 v19, v0, v53
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55
+; SI-NEXT: v_or_b32_e32 v29, v0, v35
+; SI-NEXT: v_alignbit_b32 v0, v19, v35, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v36
+; SI-NEXT: v_or_b32_e32 v23, v0, v54
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v60
+; SI-NEXT: v_or_b32_e32 v20, v0, v37
+; SI-NEXT: v_alignbit_b32 v0, v23, v37, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v38
+; SI-NEXT: v_or_b32_e32 v30, v0, v40
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v46
+; SI-NEXT: v_or_b32_e32 v27, v0, v39
+; SI-NEXT: v_alignbit_b32 v0, v30, v39, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v43
+; SI-NEXT: v_or_b32_e32 v28, v0, v42
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v61
+; SI-NEXT: v_or_b32_e32 v34, v0, v44
+; SI-NEXT: v_alignbit_b32 v0, v28, v44, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v63
+; SI-NEXT: v_or_b32_e32 v33, v0, v5
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v41
+; SI-NEXT: v_or_b32_e32 v36, v0, v32
+; SI-NEXT: v_alignbit_b32 v0, v33, v32, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v45
+; SI-NEXT: v_or_b32_e32 v35, v0, v26
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v59
+; SI-NEXT: v_or_b32_e32 v38, v0, v47
+; SI-NEXT: v_alignbit_b32 v0, v35, v47, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v56
+; SI-NEXT: v_or_b32_e32 v37, v0, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
+; SI-NEXT: v_or_b32_e32 v39, v0, v3
+; SI-NEXT: v_alignbit_b32 v0, v37, v3, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: v_or_b32_e32 v39, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v37, v3, 16
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v17
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: v_mov_b32_e32 v18, v57
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v49
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v52
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v54
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v55
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v41
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v42
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v44
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v48
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v49
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v50
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v54
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v40
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v42
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: .LBB96_2: ; %Flow
-; SI-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
-; SI-NEXT: s_xor_b64 exec, exec, s[4:5]
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_or_b32_e32 v2, v58, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_or_b32_e32 v0, v57, v0
+; SI-NEXT: v_or_b32_e32 v3, v57, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v3, v62, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v37, vcc, s7, v0
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v37
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v3, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v55
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v62, v4
+; SI-NEXT: v_mov_b32_e32 v20, v1
+; SI-NEXT: v_add_i32_e32 v37, vcc, 0x3000000, v2
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v37
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:968 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v6, v0, v6
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x300, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v4, v4, v6
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x3000000, v4
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:964 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v3, v0, v3
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_or_b32_e32 v6, v26, v6
+; SI-NEXT: v_or_b32_e32 v6, v56, v6
+; SI-NEXT: v_or_b32_e32 v3, v6, v3
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v5, v1, v5
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, 0x300, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v39, vcc, s7, v3
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v6, v45, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v47, v7
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x3000000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v35
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:960 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v1, v0, v7
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v56, v2
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v38, vcc, s7, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_or_b32_e32 v4, v46, v4
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v35, vcc, s7, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v35
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v7, v26, v7
+; SI-NEXT: v_or_b32_e32 v1, v7, v1
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x3000000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_or_b32_e32 v7, v63, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_or_b32_e32 v5, v7, v5
-; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:952 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v36, vcc, s7, v4
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v5, v63, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v33, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v5, v5, v8
+; SI-NEXT: v_or_b32_e32 v5, v5, v7
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x3000000, v5
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v33
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:956 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v0, v0, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:808 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: v_or_b32_e32 v0, v7, v0
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v34, vcc, s7, v6
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x3000000, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -189066,10 +189058,10 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:920 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v7
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v28
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:928 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v7
+; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
@@ -189086,7 +189078,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v27, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x3000000, v8
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
@@ -189100,12 +189092,12 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:876 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_add_i32_e32 v30, vcc, s7, v9
-; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x3000000, v9
+; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
@@ -189133,16 +189125,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v11
-; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v11
+; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189151,16 +189143,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v12
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v12
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189169,14 +189161,14 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189185,15 +189177,15 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s7, v14
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189202,46 +189194,48 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v16
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v19, v17
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v17
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v17, v18, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v17
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v24
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189250,16 +189244,15 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_or_b32_e32 v18, v19, v18
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v18
-; SI-NEXT: v_mov_b32_e32 v18, v5
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189268,15 +189261,15 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v25, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189285,10 +189278,10 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v26, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:784 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v26
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x3000000, v26
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
@@ -189303,18 +189296,18 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: v_or_b32_e32 v31, v20, v19
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v15
-; SI-NEXT: v_add_i32_e32 v31, vcc, s7, v31
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v31
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v15
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x3000000, v31
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v21
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v32, v20, v19
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -189324,19 +189317,19 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v48, v20, v19
; SI-NEXT: v_or_b32_e32 v0, v48, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v13
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v25
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v10
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
-; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v25
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v10
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v31
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189345,15 +189338,15 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v60
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v14
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189362,16 +189355,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189380,15 +189373,15 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v51, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v51, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v59
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v51
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189397,16 +189390,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189415,14 +189408,14 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v43
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v46
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -189431,51 +189424,52 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v40, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:820 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v60
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v61
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
@@ -189483,170 +189477,173 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v0
-; SI-NEXT: v_alignbit_b32 v0, v11, v48, 16
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v0, v8, v7, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:840 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:780 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:796 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v12, v6, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:848 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v4, v6, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:844 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v51, v15, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:856 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v12, v15, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:852 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v0, v9, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:864 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v31, v3, 16
+; SI-NEXT: v_alignbit_b32 v0, v51, v17, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:860 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v14, v16, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:868 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v31, v18, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:872 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v13, v4, 16
+; SI-NEXT: v_alignbit_b32 v0, v13, v3, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:880 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v24, v5, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:884 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:888 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v21, v22, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:892 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:896 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v19, v29, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:900 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:904 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v23, v20, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:908 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v30, v27, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:912 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:916 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v28, v34, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:924 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v33, v36, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:932 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:936 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v35, v38, 16
-; SI-NEXT: v_alignbit_b32 v1, v8, v7, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:940 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v37, v39, 16
-; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v11
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:944 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v12
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:948 ; 4-byte Folded Spill
; SI-NEXT: .LBB96_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:856 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:840 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:852 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v45
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:848 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v44
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:844 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:860 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xffff, v48
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:872 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v11
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:864 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:868 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v15
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v15
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v12
+; SI-NEXT: v_or_b32_e32 v5, v5, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
-; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:884 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:896 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v49
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:892 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:888 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v8, v8, v9
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v14
+; SI-NEXT: v_or_b32_e32 v9, v9, v10
+; SI-NEXT: v_and_b32_e32 v10, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:880 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:948 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v12, v12, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:900 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:904 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v29
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v55
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:940 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:944 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v54
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v18, v18, v21
-; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v25
; SI-NEXT: v_or_b32_e32 v19, v19, v21
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:908 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:924 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v23
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:912 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:916 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:932 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:936 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: v_or_b32_e32 v22, v22, v23
@@ -189656,7 +189653,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v28
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v44
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v43
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
@@ -198515,7 +198512,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; kill: killed $vgpr39
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v27
-; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v2
@@ -198541,7 +198538,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: ; kill: killed $vgpr39
; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
@@ -198579,7 +198576,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; kill: killed $vgpr39
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v18
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v47
@@ -198607,7 +198604,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; kill: killed $vgpr39
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v26
-; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v43
@@ -198653,7 +198650,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v38
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v58
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
@@ -198944,7 +198941,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v62, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -198984,7 +198981,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v43, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v36, v55, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -198992,7 +198989,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v44, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v36, v55, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -199040,7 +199037,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v52, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v37, v50, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -199056,7 +199053,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v49, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v34, v35, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -199318,7 +199315,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v31, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
@@ -199326,7 +199323,6 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
@@ -199362,156 +199358,156 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v32, 0xffff, v32
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v32, v33, v32
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v31
-; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v32
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v32
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v29, v33, v29
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v29
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v30, v33, v30
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v30
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v30
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v27, v30, v27
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v51, vcc, 0x30000, v27
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v28
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v27, v28, v27
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v52, vcc, 0x30000, v27
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v25, v27, v25
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v53, vcc, 0x30000, v25
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v26
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v25, v26, v25
-; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v25
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v54, vcc, 0x30000, v25
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v23, v25, v23
-; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v40, vcc, 0x30000, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v23, v24, v23
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v41, vcc, 0x30000, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v21, v23, v21
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v43, vcc, 0x30000, v21
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v44, vcc, 0x30000, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v21, v19
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v46, vcc, 0x30000, v19
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v19, v17
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v57, vcc, 0x30000, v17
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v56, vcc, 0x30000, v17
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v17, v15
-; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v60, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v16
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v59, vcc, 0x30000, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v13, v15, v13
-; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v62, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v61, vcc, 0x30000, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v13, v11
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
-; SI-NEXT: v_add_i32_e32 v63, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v63, vcc, 0x30000, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v9, v11, v9
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v7, v9, v7
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x30000, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v5, v7, v5
-; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v50, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v37, vcc, 0x30000, v5
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v47, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x30000, v1
; SI-NEXT: v_alignbit_b32 v1, v36, v55, 24
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -209332,9 +209328,8 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
@@ -209342,7 +209337,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -209350,7 +209345,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
@@ -209359,7 +209354,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; VI-NEXT: v_bfe_u32 v35, v34, 16, 1
; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v34
-; VI-NEXT: v_add_u32_e32 v35, vcc, s6, v35
+; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; VI-NEXT: v_or_b32_e32 v36, 0x400000, v34
; VI-NEXT: v_cmp_u_f32_e32 vcc, v34, v34
@@ -209367,7 +209362,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc
; VI-NEXT: v_bfe_u32 v35, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v18
-; VI-NEXT: v_add_u32_e32 v35, vcc, s6, v35
+; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
; VI-NEXT: v_or_b32_e32 v36, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v35, v36, vcc
@@ -209375,7 +209370,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
; VI-NEXT: v_bfe_u32 v36, v35, 16, 1
; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v35
-; VI-NEXT: v_add_u32_e32 v36, vcc, s6, v36
+; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v37, 0x400000, v35
; VI-NEXT: v_cmp_u_f32_e32 vcc, v35, v35
@@ -209383,7 +209378,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc
; VI-NEXT: v_bfe_u32 v36, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v19
-; VI-NEXT: v_add_u32_e32 v36, vcc, s6, v36
+; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
; VI-NEXT: v_or_b32_e32 v37, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc
@@ -209391,7 +209386,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
; VI-NEXT: v_bfe_u32 v37, v36, 16, 1
; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v36
-; VI-NEXT: v_add_u32_e32 v37, vcc, s6, v37
+; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v38, 0x400000, v36
; VI-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
@@ -209399,7 +209394,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc
; VI-NEXT: v_bfe_u32 v37, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v20
-; VI-NEXT: v_add_u32_e32 v37, vcc, s6, v37
+; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
; VI-NEXT: v_or_b32_e32 v38, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc
@@ -209407,7 +209402,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v37, 0x40c00000, v37
; VI-NEXT: v_bfe_u32 v38, v37, 16, 1
; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v37
-; VI-NEXT: v_add_u32_e32 v38, vcc, s6, v38
+; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v39, 0x400000, v37
; VI-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
@@ -209415,7 +209410,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc
; VI-NEXT: v_bfe_u32 v38, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v21
-; VI-NEXT: v_add_u32_e32 v38, vcc, s6, v38
+; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
; VI-NEXT: v_or_b32_e32 v39, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc
@@ -209423,7 +209418,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
; VI-NEXT: v_bfe_u32 v39, v38, 16, 1
; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v38
-; VI-NEXT: v_add_u32_e32 v39, vcc, s6, v39
+; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v48, 0x400000, v38
; VI-NEXT: v_cmp_u_f32_e32 vcc, v38, v38
@@ -209431,7 +209426,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc
; VI-NEXT: v_bfe_u32 v39, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v22
-; VI-NEXT: v_add_u32_e32 v39, vcc, s6, v39
+; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
; VI-NEXT: v_or_b32_e32 v48, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc
@@ -209439,7 +209434,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v39, 0x40c00000, v39
; VI-NEXT: v_bfe_u32 v48, v39, 16, 1
; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v39
-; VI-NEXT: v_add_u32_e32 v48, vcc, s6, v48
+; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v49, 0x400000, v39
; VI-NEXT: v_cmp_u_f32_e32 vcc, v39, v39
@@ -209447,7 +209442,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc
; VI-NEXT: v_bfe_u32 v48, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v23
-; VI-NEXT: v_add_u32_e32 v48, vcc, s6, v48
+; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
; VI-NEXT: v_or_b32_e32 v49, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc
@@ -209455,7 +209450,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v48, 0x40c00000, v48
; VI-NEXT: v_bfe_u32 v49, v48, 16, 1
; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v48
-; VI-NEXT: v_add_u32_e32 v49, vcc, s6, v49
+; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v50, 0x400000, v48
; VI-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
@@ -209463,7 +209458,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc
; VI-NEXT: v_bfe_u32 v49, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v24
-; VI-NEXT: v_add_u32_e32 v49, vcc, s6, v49
+; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
; VI-NEXT: v_or_b32_e32 v50, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc
@@ -209471,7 +209466,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
; VI-NEXT: v_bfe_u32 v50, v49, 16, 1
; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v49
-; VI-NEXT: v_add_u32_e32 v50, vcc, s6, v50
+; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v51, 0x400000, v49
; VI-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
@@ -209479,7 +209474,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc
; VI-NEXT: v_bfe_u32 v50, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v25
-; VI-NEXT: v_add_u32_e32 v50, vcc, s6, v50
+; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
; VI-NEXT: v_or_b32_e32 v51, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc
@@ -209487,7 +209482,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
; VI-NEXT: v_bfe_u32 v51, v50, 16, 1
; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v50
-; VI-NEXT: v_add_u32_e32 v51, vcc, s6, v51
+; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v52, 0x400000, v50
; VI-NEXT: v_cmp_u_f32_e32 vcc, v50, v50
@@ -209495,7 +209490,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc
; VI-NEXT: v_bfe_u32 v51, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v26
-; VI-NEXT: v_add_u32_e32 v51, vcc, s6, v51
+; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc
@@ -209503,7 +209498,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v51, 0x40c00000, v51
; VI-NEXT: v_bfe_u32 v52, v51, 16, 1
; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v51
-; VI-NEXT: v_add_u32_e32 v52, vcc, s6, v52
+; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v53, 0x400000, v51
; VI-NEXT: v_cmp_u_f32_e32 vcc, v51, v51
@@ -209511,7 +209506,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc
; VI-NEXT: v_bfe_u32 v52, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v27
-; VI-NEXT: v_add_u32_e32 v52, vcc, s6, v52
+; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
; VI-NEXT: v_or_b32_e32 v53, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc
@@ -209519,7 +209514,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v52, 0x40c00000, v52
; VI-NEXT: v_bfe_u32 v53, v52, 16, 1
; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v52
-; VI-NEXT: v_add_u32_e32 v53, vcc, s6, v53
+; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v54, 0x400000, v52
; VI-NEXT: v_cmp_u_f32_e32 vcc, v52, v52
@@ -209527,7 +209522,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc
; VI-NEXT: v_bfe_u32 v53, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v28
-; VI-NEXT: v_add_u32_e32 v53, vcc, s6, v53
+; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc
@@ -209535,7 +209530,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v53, 0x40c00000, v53
; VI-NEXT: v_bfe_u32 v54, v53, 16, 1
; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v53
-; VI-NEXT: v_add_u32_e32 v54, vcc, s6, v54
+; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v55, 0x400000, v53
; VI-NEXT: v_cmp_u_f32_e32 vcc, v53, v53
@@ -209543,7 +209538,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc
; VI-NEXT: v_bfe_u32 v54, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v29
-; VI-NEXT: v_add_u32_e32 v54, vcc, s6, v54
+; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
; VI-NEXT: v_or_b32_e32 v55, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc
@@ -209551,7 +209546,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
; VI-NEXT: v_bfe_u32 v55, v54, 16, 1
; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54
-; VI-NEXT: v_add_u32_e32 v55, vcc, s6, v55
+; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54
; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54
@@ -209559,7 +209554,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc
; VI-NEXT: v_bfe_u32 v55, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v30
-; VI-NEXT: v_add_u32_e32 v55, vcc, s6, v55
+; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_or_b32_e32 v40, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc
@@ -209568,7 +209563,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55
; VI-NEXT: v_bfe_u32 v40, v55, 16, 1
; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v55
-; VI-NEXT: v_add_u32_e32 v40, vcc, s6, v40
+; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v41, 0x400000, v55
; VI-NEXT: v_cmp_u_f32_e32 vcc, v55, v55
@@ -209576,7 +209571,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc
; VI-NEXT: v_bfe_u32 v40, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v31
-; VI-NEXT: v_add_u32_e32 v40, vcc, s6, v40
+; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
; VI-NEXT: v_or_b32_e32 v41, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc
@@ -209584,7 +209579,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v40, 0x40c00000, v40
; VI-NEXT: v_bfe_u32 v41, v40, 16, 1
; VI-NEXT: v_add_u32_e32 v41, vcc, v41, v40
-; VI-NEXT: v_add_u32_e32 v41, vcc, s6, v41
+; VI-NEXT: v_add_u32_e32 v41, vcc, 0x7fff, v41
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v42, 0x400000, v40
; VI-NEXT: v_cmp_u_f32_e32 vcc, v40, v40
@@ -209592,7 +209587,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc
; VI-NEXT: v_bfe_u32 v41, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v41, vcc, v41, v0
-; VI-NEXT: v_add_u32_e32 v41, vcc, s6, v41
+; VI-NEXT: v_add_u32_e32 v41, vcc, 0x7fff, v41
; VI-NEXT: v_or_b32_e32 v42, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v17, v41, v42, vcc
@@ -209600,7 +209595,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v41, 0x40c00000, v41
; VI-NEXT: v_bfe_u32 v42, v41, 16, 1
; VI-NEXT: v_add_u32_e32 v42, vcc, v42, v41
-; VI-NEXT: v_add_u32_e32 v42, vcc, s6, v42
+; VI-NEXT: v_add_u32_e32 v42, vcc, 0x7fff, v42
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v43, 0x400000, v41
; VI-NEXT: v_cmp_u_f32_e32 vcc, v41, v41
@@ -209608,7 +209603,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc
; VI-NEXT: v_bfe_u32 v42, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v42, vcc, v42, v1
-; VI-NEXT: v_add_u32_e32 v42, vcc, s6, v42
+; VI-NEXT: v_add_u32_e32 v42, vcc, 0x7fff, v42
; VI-NEXT: v_or_b32_e32 v43, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
@@ -209617,7 +209612,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v42, 0x40c00000, v42
; VI-NEXT: v_bfe_u32 v43, v42, 16, 1
; VI-NEXT: v_add_u32_e32 v43, vcc, v43, v42
-; VI-NEXT: v_add_u32_e32 v43, vcc, s6, v43
+; VI-NEXT: v_add_u32_e32 v43, vcc, 0x7fff, v43
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v44, 0x400000, v42
; VI-NEXT: v_cmp_u_f32_e32 vcc, v42, v42
@@ -209625,7 +209620,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v42, v43, v44, vcc
; VI-NEXT: v_bfe_u32 v43, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v43, vcc, v43, v2
-; VI-NEXT: v_add_u32_e32 v43, vcc, s6, v43
+; VI-NEXT: v_add_u32_e32 v43, vcc, 0x7fff, v43
; VI-NEXT: v_or_b32_e32 v44, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v43, v44, vcc
@@ -209633,7 +209628,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v43, 0x40c00000, v43
; VI-NEXT: v_bfe_u32 v44, v43, 16, 1
; VI-NEXT: v_add_u32_e32 v44, vcc, v44, v43
-; VI-NEXT: v_add_u32_e32 v44, vcc, s6, v44
+; VI-NEXT: v_add_u32_e32 v44, vcc, 0x7fff, v44
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v45, 0x400000, v43
; VI-NEXT: v_cmp_u_f32_e32 vcc, v43, v43
@@ -209641,7 +209636,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v43, v44, v45, vcc
; VI-NEXT: v_bfe_u32 v44, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v44, vcc, v44, v3
-; VI-NEXT: v_add_u32_e32 v44, vcc, s6, v44
+; VI-NEXT: v_add_u32_e32 v44, vcc, 0x7fff, v44
; VI-NEXT: v_or_b32_e32 v45, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v44, v45, vcc
@@ -209649,7 +209644,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v44, 0x40c00000, v44
; VI-NEXT: v_bfe_u32 v45, v44, 16, 1
; VI-NEXT: v_add_u32_e32 v45, vcc, v45, v44
-; VI-NEXT: v_add_u32_e32 v45, vcc, s6, v45
+; VI-NEXT: v_add_u32_e32 v45, vcc, 0x7fff, v45
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v46, 0x400000, v44
; VI-NEXT: v_cmp_u_f32_e32 vcc, v44, v44
@@ -209657,7 +209652,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v44, v45, v46, vcc
; VI-NEXT: v_bfe_u32 v45, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v45, vcc, v45, v4
-; VI-NEXT: v_add_u32_e32 v45, vcc, s6, v45
+; VI-NEXT: v_add_u32_e32 v45, vcc, 0x7fff, v45
; VI-NEXT: v_or_b32_e32 v46, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v45, v46, vcc
@@ -209665,7 +209660,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v45, 0x40c00000, v45
; VI-NEXT: v_bfe_u32 v46, v45, 16, 1
; VI-NEXT: v_add_u32_e32 v46, vcc, v46, v45
-; VI-NEXT: v_add_u32_e32 v46, vcc, s6, v46
+; VI-NEXT: v_add_u32_e32 v46, vcc, 0x7fff, v46
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v47, 0x400000, v45
; VI-NEXT: v_cmp_u_f32_e32 vcc, v45, v45
@@ -209673,7 +209668,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v45, v46, v47, vcc
; VI-NEXT: v_bfe_u32 v46, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v46, vcc, v46, v5
-; VI-NEXT: v_add_u32_e32 v46, vcc, s6, v46
+; VI-NEXT: v_add_u32_e32 v46, vcc, 0x7fff, v46
; VI-NEXT: v_or_b32_e32 v47, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v46, v47, vcc
@@ -209681,7 +209676,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v46, 0x40c00000, v46
; VI-NEXT: v_bfe_u32 v47, v46, 16, 1
; VI-NEXT: v_add_u32_e32 v47, vcc, v47, v46
-; VI-NEXT: v_add_u32_e32 v47, vcc, s6, v47
+; VI-NEXT: v_add_u32_e32 v47, vcc, 0x7fff, v47
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v56, 0x400000, v46
; VI-NEXT: v_cmp_u_f32_e32 vcc, v46, v46
@@ -209689,7 +209684,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v46, v47, v56, vcc
; VI-NEXT: v_bfe_u32 v47, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v47, vcc, v47, v6
-; VI-NEXT: v_add_u32_e32 v47, vcc, s6, v47
+; VI-NEXT: v_add_u32_e32 v47, vcc, 0x7fff, v47
; VI-NEXT: v_or_b32_e32 v56, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v47, v56, vcc
@@ -209697,7 +209692,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v47, 0x40c00000, v47
; VI-NEXT: v_bfe_u32 v56, v47, 16, 1
; VI-NEXT: v_add_u32_e32 v56, vcc, v56, v47
-; VI-NEXT: v_add_u32_e32 v56, vcc, s6, v56
+; VI-NEXT: v_add_u32_e32 v56, vcc, 0x7fff, v56
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v57, 0x400000, v47
; VI-NEXT: v_cmp_u_f32_e32 vcc, v47, v47
@@ -209705,7 +209700,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v47, v56, v57, vcc
; VI-NEXT: v_bfe_u32 v56, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v56, vcc, v56, v7
-; VI-NEXT: v_add_u32_e32 v56, vcc, s6, v56
+; VI-NEXT: v_add_u32_e32 v56, vcc, 0x7fff, v56
; VI-NEXT: v_or_b32_e32 v57, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v56, v57, vcc
@@ -209713,7 +209708,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v56, 0x40c00000, v56
; VI-NEXT: v_bfe_u32 v57, v56, 16, 1
; VI-NEXT: v_add_u32_e32 v57, vcc, v57, v56
-; VI-NEXT: v_add_u32_e32 v57, vcc, s6, v57
+; VI-NEXT: v_add_u32_e32 v57, vcc, 0x7fff, v57
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v58, 0x400000, v56
; VI-NEXT: v_cmp_u_f32_e32 vcc, v56, v56
@@ -209721,7 +209716,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v56, v57, v58, vcc
; VI-NEXT: v_bfe_u32 v57, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v57, vcc, v57, v8
-; VI-NEXT: v_add_u32_e32 v57, vcc, s6, v57
+; VI-NEXT: v_add_u32_e32 v57, vcc, 0x7fff, v57
; VI-NEXT: v_or_b32_e32 v58, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v57, v58, vcc
@@ -209729,7 +209724,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v57, 0x40c00000, v57
; VI-NEXT: v_bfe_u32 v58, v57, 16, 1
; VI-NEXT: v_add_u32_e32 v58, vcc, v58, v57
-; VI-NEXT: v_add_u32_e32 v58, vcc, s6, v58
+; VI-NEXT: v_add_u32_e32 v58, vcc, 0x7fff, v58
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v59, 0x400000, v57
; VI-NEXT: v_cmp_u_f32_e32 vcc, v57, v57
@@ -209737,7 +209732,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v57, v58, v59, vcc
; VI-NEXT: v_bfe_u32 v58, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v58, vcc, v58, v9
-; VI-NEXT: v_add_u32_e32 v58, vcc, s6, v58
+; VI-NEXT: v_add_u32_e32 v58, vcc, 0x7fff, v58
; VI-NEXT: v_or_b32_e32 v59, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v58, v59, vcc
@@ -209745,7 +209740,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v58, 0x40c00000, v58
; VI-NEXT: v_bfe_u32 v59, v58, 16, 1
; VI-NEXT: v_add_u32_e32 v59, vcc, v59, v58
-; VI-NEXT: v_add_u32_e32 v59, vcc, s6, v59
+; VI-NEXT: v_add_u32_e32 v59, vcc, 0x7fff, v59
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v60, 0x400000, v58
; VI-NEXT: v_cmp_u_f32_e32 vcc, v58, v58
@@ -209753,7 +209748,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v58, v59, v60, vcc
; VI-NEXT: v_bfe_u32 v59, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v59, vcc, v59, v10
-; VI-NEXT: v_add_u32_e32 v59, vcc, s6, v59
+; VI-NEXT: v_add_u32_e32 v59, vcc, 0x7fff, v59
; VI-NEXT: v_or_b32_e32 v60, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v59, v60, vcc
@@ -209761,7 +209756,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v59, 0x40c00000, v59
; VI-NEXT: v_bfe_u32 v60, v59, 16, 1
; VI-NEXT: v_add_u32_e32 v60, vcc, v60, v59
-; VI-NEXT: v_add_u32_e32 v60, vcc, s6, v60
+; VI-NEXT: v_add_u32_e32 v60, vcc, 0x7fff, v60
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v61, 0x400000, v59
; VI-NEXT: v_cmp_u_f32_e32 vcc, v59, v59
@@ -209769,7 +209764,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v59, v60, v61, vcc
; VI-NEXT: v_bfe_u32 v60, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v60, vcc, v60, v11
-; VI-NEXT: v_add_u32_e32 v60, vcc, s6, v60
+; VI-NEXT: v_add_u32_e32 v60, vcc, 0x7fff, v60
; VI-NEXT: v_or_b32_e32 v61, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v60, v61, vcc
@@ -209777,7 +209772,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v60, 0x40c00000, v60
; VI-NEXT: v_bfe_u32 v61, v60, 16, 1
; VI-NEXT: v_add_u32_e32 v61, vcc, v61, v60
-; VI-NEXT: v_add_u32_e32 v61, vcc, s6, v61
+; VI-NEXT: v_add_u32_e32 v61, vcc, 0x7fff, v61
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v62, 0x400000, v60
; VI-NEXT: v_cmp_u_f32_e32 vcc, v60, v60
@@ -209785,7 +209780,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v60, v61, v62, vcc
; VI-NEXT: v_bfe_u32 v61, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v61, vcc, v61, v12
-; VI-NEXT: v_add_u32_e32 v61, vcc, s6, v61
+; VI-NEXT: v_add_u32_e32 v61, vcc, 0x7fff, v61
; VI-NEXT: v_or_b32_e32 v62, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v61, v62, vcc
@@ -209793,7 +209788,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v61, 0x40c00000, v61
; VI-NEXT: v_bfe_u32 v62, v61, 16, 1
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v61
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v61
; VI-NEXT: v_cmp_u_f32_e32 vcc, v61, v61
@@ -209801,7 +209796,7 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v61, v62, v63, vcc
; VI-NEXT: v_bfe_u32 v62, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v13
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v62, v63, vcc
@@ -209810,14 +209805,14 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_bfe_u32 v63, v62, 16, 1
; VI-NEXT: v_add_u32_e32 v63, vcc, v63, v62
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; VI-NEXT: v_add_u32_e32 v63, vcc, s6, v63
+; VI-NEXT: v_add_u32_e32 v63, vcc, 0x7fff, v63
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; VI-NEXT: v_or_b32_e32 v0, 0x400000, v62
; VI-NEXT: v_cmp_u_f32_e32 vcc, v62, v62
; VI-NEXT: v_bfe_u32 v62, v14, 16, 1
; VI-NEXT: v_cndmask_b32_e32 v1, v63, v0, vcc
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v14
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v62, v63, vcc
@@ -209826,14 +209821,14 @@ define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_bfe_u32 v63, v62, 16, 1
; VI-NEXT: v_add_u32_e32 v63, vcc, v63, v62
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; VI-NEXT: v_add_u32_e32 v63, vcc, s6, v63
+; VI-NEXT: v_add_u32_e32 v63, vcc, 0x7fff, v63
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_or_b32_e32 v0, 0x400000, v62
; VI-NEXT: v_cmp_u_f32_e32 vcc, v62, v62
; VI-NEXT: v_bfe_u32 v62, v15, 16, 1
; VI-NEXT: v_cndmask_b32_e32 v0, v63, v0, vcc
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v15
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v62, v63, vcc
@@ -220127,9 +220122,8 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc
; VI-NEXT: v_bfe_u32 v33, v16, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16
-; VI-NEXT: v_add_u32_e32 v33, vcc, s6, v33
+; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33
; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc
@@ -220137,7 +220131,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33
; VI-NEXT: v_bfe_u32 v34, v33, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33
; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33
@@ -220145,7 +220139,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc
; VI-NEXT: v_bfe_u32 v34, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17
-; VI-NEXT: v_add_u32_e32 v34, vcc, s6, v34
+; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34
; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
@@ -220154,7 +220148,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
; VI-NEXT: v_bfe_u32 v35, v34, 16, 1
; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v34
-; VI-NEXT: v_add_u32_e32 v35, vcc, s6, v35
+; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
; VI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
; VI-NEXT: v_or_b32_e32 v36, 0x400000, v34
; VI-NEXT: v_cmp_u_f32_e32 vcc, v34, v34
@@ -220162,7 +220156,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc
; VI-NEXT: v_bfe_u32 v35, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v18
-; VI-NEXT: v_add_u32_e32 v35, vcc, s6, v35
+; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35
; VI-NEXT: v_or_b32_e32 v36, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
; VI-NEXT: v_cndmask_b32_e32 v18, v35, v36, vcc
@@ -220170,7 +220164,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35
; VI-NEXT: v_bfe_u32 v36, v35, 16, 1
; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v35
-; VI-NEXT: v_add_u32_e32 v36, vcc, s6, v36
+; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
; VI-NEXT: v_or_b32_e32 v37, 0x400000, v35
; VI-NEXT: v_cmp_u_f32_e32 vcc, v35, v35
@@ -220178,7 +220172,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc
; VI-NEXT: v_bfe_u32 v36, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v19
-; VI-NEXT: v_add_u32_e32 v36, vcc, s6, v36
+; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36
; VI-NEXT: v_or_b32_e32 v37, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
; VI-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc
@@ -220186,7 +220180,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36
; VI-NEXT: v_bfe_u32 v37, v36, 16, 1
; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v36
-; VI-NEXT: v_add_u32_e32 v37, vcc, s6, v37
+; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
; VI-NEXT: v_or_b32_e32 v38, 0x400000, v36
; VI-NEXT: v_cmp_u_f32_e32 vcc, v36, v36
@@ -220194,7 +220188,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc
; VI-NEXT: v_bfe_u32 v37, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v20
-; VI-NEXT: v_add_u32_e32 v37, vcc, s6, v37
+; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37
; VI-NEXT: v_or_b32_e32 v38, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
; VI-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc
@@ -220202,7 +220196,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v37, 0x40c00000, v37
; VI-NEXT: v_bfe_u32 v38, v37, 16, 1
; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v37
-; VI-NEXT: v_add_u32_e32 v38, vcc, s6, v38
+; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
; VI-NEXT: v_or_b32_e32 v39, 0x400000, v37
; VI-NEXT: v_cmp_u_f32_e32 vcc, v37, v37
@@ -220210,7 +220204,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc
; VI-NEXT: v_bfe_u32 v38, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v21
-; VI-NEXT: v_add_u32_e32 v38, vcc, s6, v38
+; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38
; VI-NEXT: v_or_b32_e32 v39, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
; VI-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc
@@ -220218,7 +220212,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
; VI-NEXT: v_bfe_u32 v39, v38, 16, 1
; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v38
-; VI-NEXT: v_add_u32_e32 v39, vcc, s6, v39
+; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
; VI-NEXT: v_or_b32_e32 v48, 0x400000, v38
; VI-NEXT: v_cmp_u_f32_e32 vcc, v38, v38
@@ -220226,7 +220220,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc
; VI-NEXT: v_bfe_u32 v39, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v22
-; VI-NEXT: v_add_u32_e32 v39, vcc, s6, v39
+; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39
; VI-NEXT: v_or_b32_e32 v48, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
; VI-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc
@@ -220234,7 +220228,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v39, 0x40c00000, v39
; VI-NEXT: v_bfe_u32 v48, v39, 16, 1
; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v39
-; VI-NEXT: v_add_u32_e32 v48, vcc, s6, v48
+; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
; VI-NEXT: v_or_b32_e32 v49, 0x400000, v39
; VI-NEXT: v_cmp_u_f32_e32 vcc, v39, v39
@@ -220242,7 +220236,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc
; VI-NEXT: v_bfe_u32 v48, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v23
-; VI-NEXT: v_add_u32_e32 v48, vcc, s6, v48
+; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48
; VI-NEXT: v_or_b32_e32 v49, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
; VI-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc
@@ -220250,7 +220244,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v48, 0x40c00000, v48
; VI-NEXT: v_bfe_u32 v49, v48, 16, 1
; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v48
-; VI-NEXT: v_add_u32_e32 v49, vcc, s6, v49
+; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; VI-NEXT: v_or_b32_e32 v50, 0x400000, v48
; VI-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
@@ -220258,7 +220252,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc
; VI-NEXT: v_bfe_u32 v49, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v24
-; VI-NEXT: v_add_u32_e32 v49, vcc, s6, v49
+; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49
; VI-NEXT: v_or_b32_e32 v50, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
; VI-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc
@@ -220266,7 +220260,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49
; VI-NEXT: v_bfe_u32 v50, v49, 16, 1
; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v49
-; VI-NEXT: v_add_u32_e32 v50, vcc, s6, v50
+; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; VI-NEXT: v_or_b32_e32 v51, 0x400000, v49
; VI-NEXT: v_cmp_u_f32_e32 vcc, v49, v49
@@ -220274,7 +220268,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc
; VI-NEXT: v_bfe_u32 v50, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v25
-; VI-NEXT: v_add_u32_e32 v50, vcc, s6, v50
+; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50
; VI-NEXT: v_or_b32_e32 v51, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
; VI-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc
@@ -220282,7 +220276,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
; VI-NEXT: v_bfe_u32 v51, v50, 16, 1
; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v50
-; VI-NEXT: v_add_u32_e32 v51, vcc, s6, v51
+; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
; VI-NEXT: v_or_b32_e32 v52, 0x400000, v50
; VI-NEXT: v_cmp_u_f32_e32 vcc, v50, v50
@@ -220290,7 +220284,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc
; VI-NEXT: v_bfe_u32 v51, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v26
-; VI-NEXT: v_add_u32_e32 v51, vcc, s6, v51
+; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51
; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
; VI-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc
@@ -220298,7 +220292,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v51, 0x40c00000, v51
; VI-NEXT: v_bfe_u32 v52, v51, 16, 1
; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v51
-; VI-NEXT: v_add_u32_e32 v52, vcc, s6, v52
+; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
; VI-NEXT: v_or_b32_e32 v53, 0x400000, v51
; VI-NEXT: v_cmp_u_f32_e32 vcc, v51, v51
@@ -220306,7 +220300,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc
; VI-NEXT: v_bfe_u32 v52, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v27
-; VI-NEXT: v_add_u32_e32 v52, vcc, s6, v52
+; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52
; VI-NEXT: v_or_b32_e32 v53, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
; VI-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc
@@ -220314,7 +220308,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v52, 0x40c00000, v52
; VI-NEXT: v_bfe_u32 v53, v52, 16, 1
; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v52
-; VI-NEXT: v_add_u32_e32 v53, vcc, s6, v53
+; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
; VI-NEXT: v_or_b32_e32 v54, 0x400000, v52
; VI-NEXT: v_cmp_u_f32_e32 vcc, v52, v52
@@ -220322,7 +220316,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc
; VI-NEXT: v_bfe_u32 v53, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v28
-; VI-NEXT: v_add_u32_e32 v53, vcc, s6, v53
+; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53
; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
; VI-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc
@@ -220330,7 +220324,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v53, 0x40c00000, v53
; VI-NEXT: v_bfe_u32 v54, v53, 16, 1
; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v53
-; VI-NEXT: v_add_u32_e32 v54, vcc, s6, v54
+; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
; VI-NEXT: v_or_b32_e32 v55, 0x400000, v53
; VI-NEXT: v_cmp_u_f32_e32 vcc, v53, v53
@@ -220338,7 +220332,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc
; VI-NEXT: v_bfe_u32 v54, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v29
-; VI-NEXT: v_add_u32_e32 v54, vcc, s6, v54
+; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54
; VI-NEXT: v_or_b32_e32 v55, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
; VI-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc
@@ -220346,7 +220340,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54
; VI-NEXT: v_bfe_u32 v55, v54, 16, 1
; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54
-; VI-NEXT: v_add_u32_e32 v55, vcc, s6, v55
+; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54
; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54
@@ -220354,7 +220348,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc
; VI-NEXT: v_bfe_u32 v55, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v30
-; VI-NEXT: v_add_u32_e32 v55, vcc, s6, v55
+; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55
; VI-NEXT: v_or_b32_e32 v40, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
; VI-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc
@@ -220363,7 +220357,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55
; VI-NEXT: v_bfe_u32 v40, v55, 16, 1
; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v55
-; VI-NEXT: v_add_u32_e32 v40, vcc, s6, v40
+; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31
; VI-NEXT: v_or_b32_e32 v41, 0x400000, v55
; VI-NEXT: v_cmp_u_f32_e32 vcc, v55, v55
@@ -220371,7 +220365,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc
; VI-NEXT: v_bfe_u32 v40, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v31
-; VI-NEXT: v_add_u32_e32 v40, vcc, s6, v40
+; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40
; VI-NEXT: v_or_b32_e32 v41, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
; VI-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc
@@ -220379,7 +220373,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v40, 0x40c00000, v40
; VI-NEXT: v_bfe_u32 v41, v40, 16, 1
; VI-NEXT: v_add_u32_e32 v41, vcc, v41, v40
-; VI-NEXT: v_add_u32_e32 v41, vcc, s6, v41
+; VI-NEXT: v_add_u32_e32 v41, vcc, 0x7fff, v41
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v42, 0x400000, v40
; VI-NEXT: v_cmp_u_f32_e32 vcc, v40, v40
@@ -220387,7 +220381,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc
; VI-NEXT: v_bfe_u32 v41, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v41, vcc, v41, v0
-; VI-NEXT: v_add_u32_e32 v41, vcc, s6, v41
+; VI-NEXT: v_add_u32_e32 v41, vcc, 0x7fff, v41
; VI-NEXT: v_or_b32_e32 v42, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v17, v41, v42, vcc
@@ -220395,7 +220389,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v41, 0x40c00000, v41
; VI-NEXT: v_bfe_u32 v42, v41, 16, 1
; VI-NEXT: v_add_u32_e32 v42, vcc, v42, v41
-; VI-NEXT: v_add_u32_e32 v42, vcc, s6, v42
+; VI-NEXT: v_add_u32_e32 v42, vcc, 0x7fff, v42
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v43, 0x400000, v41
; VI-NEXT: v_cmp_u_f32_e32 vcc, v41, v41
@@ -220403,7 +220397,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc
; VI-NEXT: v_bfe_u32 v42, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v42, vcc, v42, v1
-; VI-NEXT: v_add_u32_e32 v42, vcc, s6, v42
+; VI-NEXT: v_add_u32_e32 v42, vcc, 0x7fff, v42
; VI-NEXT: v_or_b32_e32 v43, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
@@ -220412,7 +220406,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v42, 0x40c00000, v42
; VI-NEXT: v_bfe_u32 v43, v42, 16, 1
; VI-NEXT: v_add_u32_e32 v43, vcc, v43, v42
-; VI-NEXT: v_add_u32_e32 v43, vcc, s6, v43
+; VI-NEXT: v_add_u32_e32 v43, vcc, 0x7fff, v43
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v44, 0x400000, v42
; VI-NEXT: v_cmp_u_f32_e32 vcc, v42, v42
@@ -220420,7 +220414,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v42, v43, v44, vcc
; VI-NEXT: v_bfe_u32 v43, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v43, vcc, v43, v2
-; VI-NEXT: v_add_u32_e32 v43, vcc, s6, v43
+; VI-NEXT: v_add_u32_e32 v43, vcc, 0x7fff, v43
; VI-NEXT: v_or_b32_e32 v44, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v43, v44, vcc
@@ -220428,7 +220422,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v43, 0x40c00000, v43
; VI-NEXT: v_bfe_u32 v44, v43, 16, 1
; VI-NEXT: v_add_u32_e32 v44, vcc, v44, v43
-; VI-NEXT: v_add_u32_e32 v44, vcc, s6, v44
+; VI-NEXT: v_add_u32_e32 v44, vcc, 0x7fff, v44
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v45, 0x400000, v43
; VI-NEXT: v_cmp_u_f32_e32 vcc, v43, v43
@@ -220436,7 +220430,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v43, v44, v45, vcc
; VI-NEXT: v_bfe_u32 v44, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v44, vcc, v44, v3
-; VI-NEXT: v_add_u32_e32 v44, vcc, s6, v44
+; VI-NEXT: v_add_u32_e32 v44, vcc, 0x7fff, v44
; VI-NEXT: v_or_b32_e32 v45, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v44, v45, vcc
@@ -220444,7 +220438,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v44, 0x40c00000, v44
; VI-NEXT: v_bfe_u32 v45, v44, 16, 1
; VI-NEXT: v_add_u32_e32 v45, vcc, v45, v44
-; VI-NEXT: v_add_u32_e32 v45, vcc, s6, v45
+; VI-NEXT: v_add_u32_e32 v45, vcc, 0x7fff, v45
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v46, 0x400000, v44
; VI-NEXT: v_cmp_u_f32_e32 vcc, v44, v44
@@ -220452,7 +220446,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v44, v45, v46, vcc
; VI-NEXT: v_bfe_u32 v45, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v45, vcc, v45, v4
-; VI-NEXT: v_add_u32_e32 v45, vcc, s6, v45
+; VI-NEXT: v_add_u32_e32 v45, vcc, 0x7fff, v45
; VI-NEXT: v_or_b32_e32 v46, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v45, v46, vcc
@@ -220460,7 +220454,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v45, 0x40c00000, v45
; VI-NEXT: v_bfe_u32 v46, v45, 16, 1
; VI-NEXT: v_add_u32_e32 v46, vcc, v46, v45
-; VI-NEXT: v_add_u32_e32 v46, vcc, s6, v46
+; VI-NEXT: v_add_u32_e32 v46, vcc, 0x7fff, v46
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v47, 0x400000, v45
; VI-NEXT: v_cmp_u_f32_e32 vcc, v45, v45
@@ -220468,7 +220462,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v45, v46, v47, vcc
; VI-NEXT: v_bfe_u32 v46, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v46, vcc, v46, v5
-; VI-NEXT: v_add_u32_e32 v46, vcc, s6, v46
+; VI-NEXT: v_add_u32_e32 v46, vcc, 0x7fff, v46
; VI-NEXT: v_or_b32_e32 v47, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v46, v47, vcc
@@ -220476,7 +220470,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v46, 0x40c00000, v46
; VI-NEXT: v_bfe_u32 v47, v46, 16, 1
; VI-NEXT: v_add_u32_e32 v47, vcc, v47, v46
-; VI-NEXT: v_add_u32_e32 v47, vcc, s6, v47
+; VI-NEXT: v_add_u32_e32 v47, vcc, 0x7fff, v47
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v56, 0x400000, v46
; VI-NEXT: v_cmp_u_f32_e32 vcc, v46, v46
@@ -220484,7 +220478,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v46, v47, v56, vcc
; VI-NEXT: v_bfe_u32 v47, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v47, vcc, v47, v6
-; VI-NEXT: v_add_u32_e32 v47, vcc, s6, v47
+; VI-NEXT: v_add_u32_e32 v47, vcc, 0x7fff, v47
; VI-NEXT: v_or_b32_e32 v56, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v47, v56, vcc
@@ -220492,7 +220486,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v47, 0x40c00000, v47
; VI-NEXT: v_bfe_u32 v56, v47, 16, 1
; VI-NEXT: v_add_u32_e32 v56, vcc, v56, v47
-; VI-NEXT: v_add_u32_e32 v56, vcc, s6, v56
+; VI-NEXT: v_add_u32_e32 v56, vcc, 0x7fff, v56
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v57, 0x400000, v47
; VI-NEXT: v_cmp_u_f32_e32 vcc, v47, v47
@@ -220500,7 +220494,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v47, v56, v57, vcc
; VI-NEXT: v_bfe_u32 v56, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v56, vcc, v56, v7
-; VI-NEXT: v_add_u32_e32 v56, vcc, s6, v56
+; VI-NEXT: v_add_u32_e32 v56, vcc, 0x7fff, v56
; VI-NEXT: v_or_b32_e32 v57, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v56, v57, vcc
@@ -220508,7 +220502,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v56, 0x40c00000, v56
; VI-NEXT: v_bfe_u32 v57, v56, 16, 1
; VI-NEXT: v_add_u32_e32 v57, vcc, v57, v56
-; VI-NEXT: v_add_u32_e32 v57, vcc, s6, v57
+; VI-NEXT: v_add_u32_e32 v57, vcc, 0x7fff, v57
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v58, 0x400000, v56
; VI-NEXT: v_cmp_u_f32_e32 vcc, v56, v56
@@ -220516,7 +220510,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v56, v57, v58, vcc
; VI-NEXT: v_bfe_u32 v57, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v57, vcc, v57, v8
-; VI-NEXT: v_add_u32_e32 v57, vcc, s6, v57
+; VI-NEXT: v_add_u32_e32 v57, vcc, 0x7fff, v57
; VI-NEXT: v_or_b32_e32 v58, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v57, v58, vcc
@@ -220524,7 +220518,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v57, 0x40c00000, v57
; VI-NEXT: v_bfe_u32 v58, v57, 16, 1
; VI-NEXT: v_add_u32_e32 v58, vcc, v58, v57
-; VI-NEXT: v_add_u32_e32 v58, vcc, s6, v58
+; VI-NEXT: v_add_u32_e32 v58, vcc, 0x7fff, v58
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v59, 0x400000, v57
; VI-NEXT: v_cmp_u_f32_e32 vcc, v57, v57
@@ -220532,7 +220526,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v57, v58, v59, vcc
; VI-NEXT: v_bfe_u32 v58, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v58, vcc, v58, v9
-; VI-NEXT: v_add_u32_e32 v58, vcc, s6, v58
+; VI-NEXT: v_add_u32_e32 v58, vcc, 0x7fff, v58
; VI-NEXT: v_or_b32_e32 v59, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v58, v59, vcc
@@ -220540,7 +220534,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v58, 0x40c00000, v58
; VI-NEXT: v_bfe_u32 v59, v58, 16, 1
; VI-NEXT: v_add_u32_e32 v59, vcc, v59, v58
-; VI-NEXT: v_add_u32_e32 v59, vcc, s6, v59
+; VI-NEXT: v_add_u32_e32 v59, vcc, 0x7fff, v59
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v60, 0x400000, v58
; VI-NEXT: v_cmp_u_f32_e32 vcc, v58, v58
@@ -220548,7 +220542,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v58, v59, v60, vcc
; VI-NEXT: v_bfe_u32 v59, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v59, vcc, v59, v10
-; VI-NEXT: v_add_u32_e32 v59, vcc, s6, v59
+; VI-NEXT: v_add_u32_e32 v59, vcc, 0x7fff, v59
; VI-NEXT: v_or_b32_e32 v60, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v59, v60, vcc
@@ -220556,7 +220550,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v59, 0x40c00000, v59
; VI-NEXT: v_bfe_u32 v60, v59, 16, 1
; VI-NEXT: v_add_u32_e32 v60, vcc, v60, v59
-; VI-NEXT: v_add_u32_e32 v60, vcc, s6, v60
+; VI-NEXT: v_add_u32_e32 v60, vcc, 0x7fff, v60
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v61, 0x400000, v59
; VI-NEXT: v_cmp_u_f32_e32 vcc, v59, v59
@@ -220564,7 +220558,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v59, v60, v61, vcc
; VI-NEXT: v_bfe_u32 v60, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v60, vcc, v60, v11
-; VI-NEXT: v_add_u32_e32 v60, vcc, s6, v60
+; VI-NEXT: v_add_u32_e32 v60, vcc, 0x7fff, v60
; VI-NEXT: v_or_b32_e32 v61, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v60, v61, vcc
@@ -220572,7 +220566,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v60, 0x40c00000, v60
; VI-NEXT: v_bfe_u32 v61, v60, 16, 1
; VI-NEXT: v_add_u32_e32 v61, vcc, v61, v60
-; VI-NEXT: v_add_u32_e32 v61, vcc, s6, v61
+; VI-NEXT: v_add_u32_e32 v61, vcc, 0x7fff, v61
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v62, 0x400000, v60
; VI-NEXT: v_cmp_u_f32_e32 vcc, v60, v60
@@ -220580,7 +220574,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v60, v61, v62, vcc
; VI-NEXT: v_bfe_u32 v61, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v61, vcc, v61, v12
-; VI-NEXT: v_add_u32_e32 v61, vcc, s6, v61
+; VI-NEXT: v_add_u32_e32 v61, vcc, 0x7fff, v61
; VI-NEXT: v_or_b32_e32 v62, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v61, v62, vcc
@@ -220588,7 +220582,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v61, 0x40c00000, v61
; VI-NEXT: v_bfe_u32 v62, v61, 16, 1
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v61
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v61
; VI-NEXT: v_cmp_u_f32_e32 vcc, v61, v61
@@ -220596,7 +220590,7 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v61, v62, v63, vcc
; VI-NEXT: v_bfe_u32 v62, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v13
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v62, v63, vcc
@@ -220605,14 +220599,14 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_bfe_u32 v63, v62, 16, 1
; VI-NEXT: v_add_u32_e32 v63, vcc, v63, v62
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; VI-NEXT: v_add_u32_e32 v63, vcc, s6, v63
+; VI-NEXT: v_add_u32_e32 v63, vcc, 0x7fff, v63
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; VI-NEXT: v_or_b32_e32 v0, 0x400000, v62
; VI-NEXT: v_cmp_u_f32_e32 vcc, v62, v62
; VI-NEXT: v_bfe_u32 v62, v14, 16, 1
; VI-NEXT: v_cndmask_b32_e32 v1, v63, v0, vcc
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v14
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v62, v63, vcc
@@ -220621,14 +220615,14 @@ define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_bfe_u32 v63, v62, 16, 1
; VI-NEXT: v_add_u32_e32 v63, vcc, v63, v62
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; VI-NEXT: v_add_u32_e32 v63, vcc, s6, v63
+; VI-NEXT: v_add_u32_e32 v63, vcc, 0x7fff, v63
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_or_b32_e32 v0, 0x400000, v62
; VI-NEXT: v_cmp_u_f32_e32 vcc, v62, v62
; VI-NEXT: v_bfe_u32 v62, v15, 16, 1
; VI-NEXT: v_cndmask_b32_e32 v0, v63, v0, vcc
; VI-NEXT: v_add_u32_e32 v62, vcc, v62, v15
-; VI-NEXT: v_add_u32_e32 v62, vcc, s6, v62
+; VI-NEXT: v_add_u32_e32 v62, vcc, 0x7fff, v62
; VI-NEXT: v_or_b32_e32 v63, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v62, v63, vcc
@@ -226496,7 +226490,6 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -226504,171 +226497,171 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v1, v32, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v2, v33, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v4, v35, v4
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v6, v37, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v7, v38, v7
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v8, v39, v8
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v9, v48, v9
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v10, v49, v10
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v11, v50, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v9
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v12, v51, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v10
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v13, v52, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v11
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v14, v53, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v15, v54, v15
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v16, v55, v16
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v14
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v17, v40, v17
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v15
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_or_b32_e32 v18, v41, v18
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v16
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v19, v42, v19
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v17
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v20, v43, v20
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v18
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v21, v44, v21
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v19
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v22, v45, v22
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v20
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v23, v46, v23
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v21
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v24, v47, v24
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v22
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v25, v56, v25
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23
@@ -226677,7 +226670,7 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v26, v57, v26
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v24
@@ -226685,21 +226678,21 @@ define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v27, v58, v27
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v25
; SI-NEXT: v_or_b32_e32 v30, v61, v30
; SI-NEXT: v_or_b32_e32 v60, v60, v29
; SI-NEXT: v_or_b32_e32 v59, v59, v28
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v26
; SI-NEXT: v_add_i32_e32 v63, vcc, 3, v63
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v30
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v60
-; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v59
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v30
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v60
+; SI-NEXT: v_add_i32_e32 v60, vcc, 0x30000, v59
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v27
@@ -230396,406 +230389,404 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v4
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v49
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v48
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v39
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v38
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v28
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v36
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v38
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v58
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v1
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v24
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v3
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v58
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v60
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v5
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v7
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v60
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v40
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v11
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v11
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v54
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v13
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v51
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v13
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v56
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v15
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v47
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v46
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v17
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v45
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v30
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v29
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v27
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v26
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v21
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
-; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v19
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v20
+; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v18
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v14
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v12
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v52
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v37
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v33
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v46
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v44
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v37
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v31
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v59
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v31
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v59
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v57
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v44
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v42
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v55
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v53
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v52
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v43
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v42
+; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v41
+; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
+; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v55
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v52
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr46
+; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; kill: killed $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; kill: killed $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; kill: killed $vgpr8
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v58
-; SI-NEXT: v_or_b32_e32 v61, v1, v50
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v58
+; SI-NEXT: v_or_b32_e32 v61, v1, v8
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63
-; SI-NEXT: v_or_b32_e32 v47, v1, v3
+; SI-NEXT: v_or_b32_e32 v46, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60
; SI-NEXT: v_or_b32_e32 v62, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v59, v1, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
; SI-NEXT: v_or_b32_e32 v57, v1, v3
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v1, v61, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_alignbit_b32 v1, v61, v7, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v56, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_alignbit_b32 v1, v47, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v46, v8, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v46, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_or_b32_e32 v45, v1, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v62, v9, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v44, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v59, v11, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v43, v1, v3
; SI-NEXT: v_alignbit_b32 v1, v57, v13, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
; SI-NEXT: v_or_b32_e32 v42, v1, v48
; SI-NEXT: v_alignbit_b32 v1, v56, v15, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v41, v1, v49
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v1, v46, v17, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v45, v34, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
-; SI-NEXT: v_or_b32_e32 v55, v1, v39
-; SI-NEXT: v_alignbit_b32 v1, v44, v34, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v55, v1, v50
+; SI-NEXT: v_alignbit_b32 v1, v44, v47, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
-; SI-NEXT: v_or_b32_e32 v53, v1, v4
+; SI-NEXT: v_or_b32_e32 v53, v1, v51
; SI-NEXT: v_alignbit_b32 v1, v43, v35, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
-; SI-NEXT: v_or_b32_e32 v4, v1, v6
+; SI-NEXT: v_or_b32_e32 v5, v1, v39
; SI-NEXT: v_alignbit_b32 v1, v42, v32, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v29
-; SI-NEXT: v_or_b32_e32 v3, v1, v8
+; SI-NEXT: v_or_b32_e32 v3, v1, v4
; SI-NEXT: v_alignbit_b32 v1, v41, v36, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v37
-; SI-NEXT: v_or_b32_e32 v50, v1, v31
-; SI-NEXT: v_alignbit_b32 v1, v55, v45, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v33
+; SI-NEXT: v_or_b32_e32 v4, v1, v6
+; SI-NEXT: v_alignbit_b32 v1, v55, v37, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr50
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v5
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v7
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v53, v38, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v1, v1, v7
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v8
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v1, v4, v33, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v1, v5, v31, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v9
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v1, v3, v0, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v11
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v50, v2, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v1, v4, v2, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v1, v1, v13
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v1, v1, v15
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v1, v1, v17
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v34
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v1, v1, v34
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v47
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v1, v1, v35
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v1, v1, v32
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v1, v1, v36
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v1, v1, v45
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v37
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v1, v1, v33
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v1, v1, v31
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
@@ -230842,7 +230833,6 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr22
@@ -230851,13 +230841,14 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: .LBB110_2: ; %Flow
@@ -230868,245 +230859,244 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v0, v28
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v26
-; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
+; SI-NEXT: v_or_b32_e32 v4, v4, v28
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v30
-; SI-NEXT: v_or_b32_e32 v8, v8, v28
-; SI-NEXT: v_or_b32_e32 v0, v33, v0
-; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v0, v31, v0
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v30
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v27
+; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v6, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v2, v2, v30
+; SI-NEXT: v_or_b32_e32 v0, v39, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v38, v0
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v4, v0
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_add_i32_e32 v53, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v45, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v0, v37, v0
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v0, v50, v0
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v36, v0
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v49, v0
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v41, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v48, v0
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v37
+; SI-NEXT: v_add_i32_e32 v30, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
-; SI-NEXT: v_or_b32_e32 v30, v31, v30
-; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v30
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v50
+; SI-NEXT: v_or_b32_e32 v6, v6, v30
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v43, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v34, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v0, v47, v0
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v15, v0
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v44, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v12, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v0
+; SI-NEXT: v_or_b32_e32 v0, v34, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v13, v0
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v56
+; SI-NEXT: v_add_i32_e32 v56, vcc, 0x30000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v11, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v9, v0
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v57, vcc, 0x30000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v57
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v9, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v7, v0
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v59, vcc, 0x30000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v59
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v7, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v62, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v62, vcc, 0x30000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v62
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v47
+; SI-NEXT: v_add_i32_e32 v46, vcc, 0x30000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v46
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v61, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v61, v3, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v47, v5, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v46, v5, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v62, v7, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v59, v9, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v57, v11, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v56, v10, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v46, v12, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v45, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v44, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v43, v16, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v42, v18, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v41, v20, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v55, v4, 16
+; SI-NEXT: v_alignbit_b32 v0, v41, v20, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v53, v24, 16
+; SI-NEXT: v_alignbit_b32 v0, v55, v22, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v6, v8, 16
+; SI-NEXT: v_alignbit_b32 v0, v53, v24, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v2, v29, 16
+; SI-NEXT: v_alignbit_b32 v0, v4, v26, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v50, v28, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; SI-NEXT: v_alignbit_b32 v0, v2, v28, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_alignbit_b32 v0, v6, v8, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v46
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v56
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v45
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v44
@@ -231126,33 +231116,33 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v61
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v2
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v58
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v63
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v60
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v40
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v54
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v51
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -231162,42 +231152,44 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v52
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v61
; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; SI-NEXT: s_waitcnt vmcnt(11)
+; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; SI-NEXT: s_waitcnt vmcnt(10)
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(8)
@@ -231219,63 +231211,63 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
-; SI-NEXT: v_and_b32_e32 v3, 0xffff, v47
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v46
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v62
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v59
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v57
; SI-NEXT: v_or_b32_e32 v9, v9, v10
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v56
; SI-NEXT: v_or_b32_e32 v11, v11, v12
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff, v46
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v45
; SI-NEXT: v_or_b32_e32 v13, v13, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v44
; SI-NEXT: v_or_b32_e32 v15, v15, v16
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v43
; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v42
; SI-NEXT: v_or_b32_e32 v19, v19, v20
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v41
; SI-NEXT: v_or_b32_e32 v21, v21, v22
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -231297,33 +231289,35 @@ define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v23, v23, v24
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v24, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v53
; SI-NEXT: v_or_b32_e32 v25, v25, v26
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v26, v27
-; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
; SI-NEXT: v_or_b32_e32 v27, v27, v28
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_or_b32_e32 v28, v28, v29
-; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v29, 0xffff, v29
; SI-NEXT: v_or_b32_e32 v29, v29, v30
-; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v30, 0xffff, v30
; SI-NEXT: v_or_b32_e32 v30, v30, v31
-; SI-NEXT: v_and_b32_e32 v31, 0xffff, v50
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v31, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v31, v31, v32
; SI-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index c9af784cf88bc4..ba204b2b80688b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -2785,9 +2785,8 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
@@ -2797,7 +2796,7 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -2805,7 +2804,7 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
@@ -2815,7 +2814,7 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -2823,7 +2822,7 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
@@ -2833,7 +2832,7 @@ define <4 x i32> @bitcast_v8bf16_to_v4i32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -4361,10 +4360,9 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -7545,9 +7543,8 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
@@ -7557,7 +7554,7 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -7565,7 +7562,7 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
@@ -7575,7 +7572,7 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -7583,7 +7580,7 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
@@ -7593,7 +7590,7 @@ define <4 x float> @bitcast_v8bf16_to_v4f32(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -9146,10 +9143,9 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -11898,9 +11894,8 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
@@ -11910,7 +11905,7 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -11918,7 +11913,7 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
@@ -11928,7 +11923,7 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -11936,7 +11931,7 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
@@ -11946,7 +11941,7 @@ define <2 x i64> @bitcast_v8bf16_to_v2i64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -13474,10 +13469,9 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -15810,9 +15804,8 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
@@ -15822,7 +15815,7 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -15830,7 +15823,7 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
@@ -15840,7 +15833,7 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -15848,7 +15841,7 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
@@ -15858,7 +15851,7 @@ define <2 x double> @bitcast_v8bf16_to_v2f64(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -17398,10 +17391,9 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -18247,10 +18239,9 @@ define <8 x half> @bitcast_v8i16_to_v8f16(<8 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v2, v15, v2
; SI-NEXT: v_or_b32_e32 v0, v13, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v10, v8, v9, 16
; SI-NEXT: v_alignbit_b32 v11, v4, v7, 16
@@ -18919,12 +18910,11 @@ define <8 x bfloat> @bitcast_v8i16_to_v8bf16(<8 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v3, v7, v3
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v2, v6, v2
; SI-NEXT: v_or_b32_e32 v1, v5, v1
; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v0
@@ -19342,9 +19332,8 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
@@ -19352,7 +19341,7 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -19360,7 +19349,7 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; VI-NEXT: v_bfe_u32 v6, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v1
-; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc
@@ -19368,7 +19357,7 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
-; VI-NEXT: v_add_u32_e32 v7, vcc, s6, v7
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
@@ -19376,7 +19365,7 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
; VI-NEXT: v_bfe_u32 v7, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v2
-; VI-NEXT: v_add_u32_e32 v7, vcc, s6, v7
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc
@@ -19384,7 +19373,7 @@ define <8 x i16> @bitcast_v8bf16_to_v8i16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
-; VI-NEXT: v_add_u32_e32 v8, vcc, s6, v8
+; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
@@ -20162,12 +20151,12 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) #0 {
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v16, v3
-; SI-NEXT: v_mov_b32_e32 v18, v2
-; SI-NEXT: v_mov_b32_e32 v17, v1
+; SI-NEXT: v_mov_b32_e32 v17, v2
+; SI-NEXT: v_mov_b32_e32 v18, v1
; SI-NEXT: v_mov_b32_e32 v19, v0
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v16
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v17
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v18
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v19
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v1
@@ -20198,9 +20187,9 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
; SI-NEXT: .LBB96_3: ; %cmp.false
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v18
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v17
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v19
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v8, v5, v22
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v0, v0, v23
@@ -20216,34 +20205,33 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; SI-NEXT: v_bfe_u32 v7, v6, 8, 8
; SI-NEXT: v_bfe_u32 v15, v14, 8, 8
-; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr23
-; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB96_2
; SI-NEXT: .LBB96_4: ; %cmp.true
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v18
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v22, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v0, v20, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v17
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v0, v23, v0
; SI-NEXT: v_or_b32_e32 v1, v21, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v1
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
@@ -20996,8 +20984,7 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v22, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
@@ -21010,7 +20997,7 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v3, v20, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v0, v13, v0
@@ -21020,7 +21007,7 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v18, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
@@ -22364,9 +22351,8 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc
@@ -22374,7 +22360,7 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -22382,7 +22368,7 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; VI-NEXT: v_bfe_u32 v6, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v1
-; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc
@@ -22390,7 +22376,7 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
-; VI-NEXT: v_add_u32_e32 v7, vcc, s6, v7
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
@@ -22398,7 +22384,7 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
; VI-NEXT: v_bfe_u32 v7, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v2
-; VI-NEXT: v_add_u32_e32 v7, vcc, s6, v7
+; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v7, v8, vcc
@@ -22406,7 +22392,7 @@ define <8 x half> @bitcast_v8bf16_to_v8f16(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
-; VI-NEXT: v_add_u32_e32 v8, vcc, s6, v8
+; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
@@ -24069,8 +24055,7 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v22, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
@@ -24083,7 +24068,7 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v3, v20, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v0, v13, v0
@@ -24093,7 +24078,7 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v18, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
@@ -25099,9 +25084,8 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -25111,7 +25095,7 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
@@ -25119,7 +25103,7 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -25129,7 +25113,7 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
@@ -25137,7 +25121,7 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -25147,7 +25131,7 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
@@ -25155,7 +25139,7 @@ define <16 x i8> @bitcast_v8bf16_to_v16i8(<8 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -26399,8 +26383,7 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v22, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
@@ -26414,7 +26397,7 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v5, v20, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
@@ -26435,7 +26418,7 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
index 50037fb8e0a3ab..992d5bb18d4afa 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
@@ -787,13 +787,12 @@ define <5 x i32> @bitcast_v10i16_to_v5i32(<10 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v0, v14, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v13, v1
; SI-NEXT: v_or_b32_e32 v2, v12, v2
; SI-NEXT: v_or_b32_e32 v3, v11, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
@@ -2105,13 +2104,12 @@ define <5 x float> @bitcast_v10i16_to_v5f32(<10 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v0, v14, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v13, v1
; SI-NEXT: v_or_b32_e32 v2, v12, v2
; SI-NEXT: v_or_b32_e32 v3, v11, v3
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
@@ -3132,10 +3130,9 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v0, v17, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -3149,7 +3146,7 @@ define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v2, v18, v2
; SI-NEXT: v_or_b32_e32 v0, v15, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v12, v10, v11, 16
; SI-NEXT: v_alignbit_b32 v13, v5, v9, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
index b017b8ea65af55..4b9677d71c8e18 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
@@ -1739,15 +1739,14 @@ define <6 x i32> @bitcast_v12i16_to_v6i32(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v2, v15, v2
; SI-NEXT: v_or_b32_e32 v3, v14, v3
; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
@@ -4083,15 +4082,14 @@ define <6 x float> @bitcast_v12i16_to_v6f32(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v2, v15, v2
; SI-NEXT: v_or_b32_e32 v3, v14, v3
; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
@@ -5968,15 +5966,14 @@ define <3 x i64> @bitcast_v12i16_to_v3i64(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v2, v15, v2
; SI-NEXT: v_or_b32_e32 v3, v14, v3
; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
@@ -7394,15 +7391,14 @@ define <3 x double> @bitcast_v12i16_to_v3f64(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v0, v17, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v2, v15, v2
; SI-NEXT: v_or_b32_e32 v3, v14, v3
; SI-NEXT: v_or_b32_e32 v4, v13, v4
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
@@ -8456,8 +8452,8 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v12
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v8
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v11
-; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v7
-; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v10
+; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v10
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr13
@@ -8479,13 +8475,13 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v16, v0, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v6, v1, v22
+; SI-NEXT: v_or_b32_e32 v6, v1, v23
; SI-NEXT: v_or_b32_e32 v12, v0, v20
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
; SI-NEXT: v_alignbit_b32 v14, v13, v18, 16
; SI-NEXT: v_alignbit_b32 v15, v11, v20, 16
-; SI-NEXT: v_alignbit_b32 v17, v6, v23, 16
-; SI-NEXT: v_or_b32_e32 v10, v0, v23
+; SI-NEXT: v_alignbit_b32 v17, v6, v22, 16
+; SI-NEXT: v_or_b32_e32 v10, v0, v22
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
@@ -8496,8 +8492,8 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
@@ -8508,24 +8504,23 @@ define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v23, v4
-; SI-NEXT: s_mov_b32 s6, 0x30000
+; SI-NEXT: v_or_b32_e32 v4, v22, v4
; SI-NEXT: v_or_b32_e32 v2, v20, v2
; SI-NEXT: v_or_b32_e32 v0, v18, v0
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v22, v4
+; SI-NEXT: v_or_b32_e32 v4, v23, v4
; SI-NEXT: v_or_b32_e32 v2, v21, v2
; SI-NEXT: v_or_b32_e32 v0, v19, v0
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v14, v13, v16, 16
; SI-NEXT: v_alignbit_b32 v15, v11, v12, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
index 95793b95e155e0..f2adc313c8ba98 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
@@ -901,7 +901,6 @@ define <7 x i32> @bitcast_v14i16_to_v7i32(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v0, v20, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v19, v1
; SI-NEXT: v_or_b32_e32 v2, v18, v2
; SI-NEXT: v_or_b32_e32 v3, v17, v3
@@ -909,9 +908,9 @@ define <7 x i32> @bitcast_v14i16_to_v7i32(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v5, v15, v5
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
@@ -2474,7 +2473,6 @@ define <7 x float> @bitcast_v14i16_to_v7f32(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v0, v20, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v19, v1
; SI-NEXT: v_or_b32_e32 v2, v18, v2
; SI-NEXT: v_or_b32_e32 v3, v17, v3
@@ -2482,9 +2480,9 @@ define <7 x float> @bitcast_v14i16_to_v7f32(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v5, v15, v5
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
@@ -3652,8 +3650,8 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v13
-; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v9
-; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v9
+; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v8
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
@@ -3679,12 +3677,12 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v14, v0, v24
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v7, v1, v26
-; SI-NEXT: v_or_b32_e32 v11, v0, v27
+; SI-NEXT: v_or_b32_e32 v7, v1, v27
+; SI-NEXT: v_or_b32_e32 v11, v0, v26
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
; SI-NEXT: v_alignbit_b32 v17, v15, v22, 16
; SI-NEXT: v_alignbit_b32 v18, v13, v24, 16
-; SI-NEXT: v_alignbit_b32 v19, v7, v27, 16
+; SI-NEXT: v_alignbit_b32 v19, v7, v26, 16
; SI-NEXT: v_or_b32_e32 v20, v0, v21
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
@@ -3697,8 +3695,8 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: .LBB20_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
@@ -3706,32 +3704,31 @@ define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v0, v22, v0
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v27, v4
+; SI-NEXT: v_or_b32_e32 v4, v26, v4
; SI-NEXT: v_or_b32_e32 v2, v24, v2
; SI-NEXT: v_or_b32_e32 v0, v23, v0
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v26, v4
+; SI-NEXT: v_or_b32_e32 v4, v27, v4
; SI-NEXT: v_or_b32_e32 v2, v25, v2
; SI-NEXT: v_or_b32_e32 v0, v21, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v17, v15, v16, 16
; SI-NEXT: v_alignbit_b32 v18, v13, v14, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 65ce4e7da8a237..9a60f77fc36094 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -1942,7 +1942,6 @@ define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v22, v1
; SI-NEXT: v_or_b32_e32 v2, v21, v2
; SI-NEXT: v_or_b32_e32 v3, v20, v3
@@ -1951,10 +1950,10 @@ define <8 x i32> @bitcast_v16i16_to_v8i32(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
@@ -3755,9 +3754,8 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
@@ -3767,7 +3765,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -3775,7 +3773,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
@@ -3785,7 +3783,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -3793,7 +3791,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
@@ -3803,7 +3801,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -3811,7 +3809,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
@@ -3821,7 +3819,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -3829,7 +3827,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
@@ -3839,7 +3837,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -3847,7 +3845,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
@@ -3857,7 +3855,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -3865,7 +3863,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
@@ -3875,7 +3873,7 @@ define <8 x i32> @bitcast_v16bf16_to_v8i32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -6508,14 +6506,13 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -9391,7 +9388,6 @@ define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v22, v1
; SI-NEXT: v_or_b32_e32 v2, v21, v2
; SI-NEXT: v_or_b32_e32 v3, v20, v3
@@ -9400,10 +9396,10 @@ define <8 x float> @bitcast_v16i16_to_v8f32(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
@@ -11234,9 +11230,8 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
@@ -11246,7 +11241,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -11254,7 +11249,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
@@ -11264,7 +11259,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -11272,7 +11267,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
@@ -11282,7 +11277,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -11290,7 +11285,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
@@ -11300,7 +11295,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -11308,7 +11303,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
@@ -11318,7 +11313,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -11326,7 +11321,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
@@ -11336,7 +11331,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -11344,7 +11339,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
@@ -11354,7 +11349,7 @@ define <8 x float> @bitcast_v16bf16_to_v8f32(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -14030,14 +14025,13 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -16395,7 +16389,6 @@ define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v22, v1
; SI-NEXT: v_or_b32_e32 v2, v21, v2
; SI-NEXT: v_or_b32_e32 v3, v20, v3
@@ -16404,10 +16397,10 @@ define <4 x i64> @bitcast_v16i16_to_v4i64(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
@@ -18212,9 +18205,8 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
@@ -18224,7 +18216,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -18232,7 +18224,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
@@ -18242,7 +18234,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -18250,7 +18242,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
@@ -18260,7 +18252,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -18268,7 +18260,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
@@ -18278,7 +18270,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -18286,7 +18278,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
@@ -18296,7 +18288,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -18304,7 +18296,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
@@ -18314,7 +18306,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -18322,7 +18314,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
@@ -18332,7 +18324,7 @@ define <4 x i64> @bitcast_v16bf16_to_v4i64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -20971,14 +20963,13 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -22838,7 +22829,6 @@ define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v0, v23, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v22, v1
; SI-NEXT: v_or_b32_e32 v2, v21, v2
; SI-NEXT: v_or_b32_e32 v3, v20, v3
@@ -22847,10 +22837,10 @@ define <4 x double> @bitcast_v16i16_to_v4f64(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v6, v17, v6
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
@@ -24627,9 +24617,8 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
@@ -24639,7 +24628,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -24647,7 +24636,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v6
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
@@ -24657,7 +24646,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -24665,7 +24654,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc
@@ -24675,7 +24664,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -24683,7 +24672,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v4
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v9, v10, vcc
@@ -24693,7 +24682,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -24701,7 +24690,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
@@ -24711,7 +24700,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -24719,7 +24708,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v2
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v9, v10, vcc
@@ -24729,7 +24718,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -24737,7 +24726,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
@@ -24747,7 +24736,7 @@ define <4 x double> @bitcast_v16bf16_to_v4f64(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
@@ -27403,14 +27392,13 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -28927,17 +28915,16 @@ define <16 x half> @bitcast_v16i16_to_v16f16(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v6, v30, v6
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v4, v28, v4
; SI-NEXT: v_or_b32_e32 v2, v26, v2
; SI-NEXT: v_or_b32_e32 v0, v24, v0
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
@@ -28947,10 +28934,10 @@ define <16 x half> @bitcast_v16i16_to_v16f16(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v29, v4
; SI-NEXT: v_or_b32_e32 v2, v27, v2
; SI-NEXT: v_or_b32_e32 v0, v25, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v19, v17, v22, 16
; SI-NEXT: v_alignbit_b32 v20, v15, v18, 16
; SI-NEXT: v_alignbit_b32 v21, v13, v16, 16
@@ -29960,7 +29947,6 @@ define <16 x bfloat> @bitcast_v16i16_to_v16bf16(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v7, v15, v7
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v6, v14, v6
; SI-NEXT: v_or_b32_e32 v5, v13, v5
; SI-NEXT: v_or_b32_e32 v4, v12, v4
@@ -29969,13 +29955,13 @@ define <16 x bfloat> @bitcast_v16i16_to_v16bf16(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v9, v1
; SI-NEXT: v_or_b32_e32 v0, v8, v0
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v1
@@ -30623,9 +30609,8 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
@@ -30633,7 +30618,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
-; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
+; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
@@ -30641,7 +30626,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; VI-NEXT: v_bfe_u32 v10, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v1
-; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
+; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
@@ -30649,7 +30634,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
-; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
@@ -30657,7 +30642,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
; VI-NEXT: v_bfe_u32 v11, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v2
-; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc
@@ -30665,7 +30650,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
-; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
+; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
@@ -30673,7 +30658,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; VI-NEXT: v_bfe_u32 v12, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v3
-; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
+; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc
@@ -30681,7 +30666,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
-; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
@@ -30689,7 +30674,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
; VI-NEXT: v_bfe_u32 v13, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v4
-; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v13, v14, vcc
@@ -30697,7 +30682,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
+; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
@@ -30705,7 +30690,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
; VI-NEXT: v_bfe_u32 v14, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v5
-; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
+; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v14, v15, vcc
@@ -30713,7 +30698,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
-; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
@@ -30721,7 +30706,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; VI-NEXT: v_bfe_u32 v15, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v6
-; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
@@ -30729,7 +30714,7 @@ define <16 x i16> @bitcast_v16bf16_to_v16i16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
-; VI-NEXT: v_add_u32_e32 v16, vcc, s6, v16
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
@@ -32194,33 +32179,32 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v0, v54, v0
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v53, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v34
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v33
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v50, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v36
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v0, v49, v0
; SI-NEXT: v_or_b32_e32 v1, v48, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v1
; SI-NEXT: v_alignbit_b32 v3, v4, v0, 24
; SI-NEXT: v_alignbit_b32 v2, v4, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v4, v0, 8
@@ -33360,8 +33344,8 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v32i8_to_v16i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
@@ -33369,7 +33353,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v19
; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v29
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v27
@@ -33390,13 +33374,13 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v38
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
@@ -33422,7 +33406,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v10, v37, v7
+; SI-NEXT: v_or_b32_e32 v10, v48, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
; SI-NEXT: v_or_b32_e32 v15, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
@@ -33462,9 +33446,9 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_alignbit_b32 v25, v7, v14, 16
; SI-NEXT: v_or_b32_e32 v9, v0, v14
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr4
@@ -33488,7 +33472,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
@@ -33511,8 +33495,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v54, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
@@ -33524,7 +33507,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v52, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
@@ -33535,7 +33518,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v51, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
@@ -33544,9 +33527,9 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
+; SI-NEXT: v_or_b32_e32 v3, v48, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
@@ -33557,7 +33540,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v36, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
@@ -33569,7 +33552,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v3, v34, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v0, v19, v0
@@ -33579,7 +33562,7 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v33, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
@@ -33590,15 +33573,15 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT: v_alignbit_b32 v13, v1, v23, 16
; SI-NEXT: v_alignbit_b32 v17, v3, v15, 16
; SI-NEXT: v_alignbit_b32 v21, v5, v11, 16
; SI-NEXT: v_alignbit_b32 v25, v7, v9, 16
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
@@ -33611,19 +33594,19 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v17
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v37
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v21
; SI-NEXT: v_or_b32_e32 v4, v4, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
; SI-NEXT: v_or_b32_e32 v6, v6, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -36036,9 +36019,8 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; VI-NEXT: v_bfe_u32 v9, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, s6, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v9, v10, vcc
@@ -36046,7 +36028,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
-; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
+; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
@@ -36054,7 +36036,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; VI-NEXT: v_bfe_u32 v10, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v1
-; VI-NEXT: v_add_u32_e32 v10, vcc, s6, v10
+; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v10, v11, vcc
@@ -36062,7 +36044,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
-; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
@@ -36070,7 +36052,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
; VI-NEXT: v_bfe_u32 v11, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v2
-; VI-NEXT: v_add_u32_e32 v11, vcc, s6, v11
+; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v11, v12, vcc
@@ -36078,7 +36060,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
-; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
+; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
@@ -36086,7 +36068,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
; VI-NEXT: v_bfe_u32 v12, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v3
-; VI-NEXT: v_add_u32_e32 v12, vcc, s6, v12
+; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc
@@ -36094,7 +36076,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
-; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
@@ -36102,7 +36084,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
; VI-NEXT: v_bfe_u32 v13, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v4
-; VI-NEXT: v_add_u32_e32 v13, vcc, s6, v13
+; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v13, v14, vcc
@@ -36110,7 +36092,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
-; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
+; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
@@ -36118,7 +36100,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
; VI-NEXT: v_bfe_u32 v14, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v5
-; VI-NEXT: v_add_u32_e32 v14, vcc, s6, v14
+; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v14, v15, vcc
@@ -36126,7 +36108,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
-; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
@@ -36134,7 +36116,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; VI-NEXT: v_bfe_u32 v15, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v6
-; VI-NEXT: v_add_u32_e32 v15, vcc, s6, v15
+; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v15, v16, vcc
@@ -36142,7 +36124,7 @@ define <16 x half> @bitcast_v16bf16_to_v16f16(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
-; VI-NEXT: v_add_u32_e32 v16, vcc, s6, v16
+; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
@@ -38870,8 +38852,8 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v32i8_to_v16f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
@@ -38879,7 +38861,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v34, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v50, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
; SI-NEXT: v_lshlrev_b32_e32 v51, 24, v19
; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v29
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v27
@@ -38900,13 +38882,13 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr7
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v39
+; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v38
+; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
@@ -38932,7 +38914,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v5, v5, v50
-; SI-NEXT: v_or_b32_e32 v10, v37, v7
+; SI-NEXT: v_or_b32_e32 v10, v48, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
; SI-NEXT: v_or_b32_e32 v15, v0, v9
; SI-NEXT: v_and_b32_e32 v0, 0xff, v16
@@ -38972,9 +38954,9 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_alignbit_b32 v25, v7, v14, 16
; SI-NEXT: v_or_b32_e32 v9, v0, v14
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v6
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v10
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v12
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr4
@@ -38998,7 +38980,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
@@ -39021,8 +39003,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v54, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
@@ -39034,7 +39015,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v52, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
@@ -39045,7 +39026,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v51, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
@@ -39054,9 +39035,9 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
+; SI-NEXT: v_or_b32_e32 v3, v48, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
@@ -39067,7 +39048,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v36, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
@@ -39079,7 +39060,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v3, v34, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v0, v19, v0
@@ -39089,7 +39070,7 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v33, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
@@ -39100,15 +39081,15 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT: v_alignbit_b32 v13, v1, v23, 16
; SI-NEXT: v_alignbit_b32 v17, v3, v15, 16
; SI-NEXT: v_alignbit_b32 v21, v5, v11, 16
; SI-NEXT: v_alignbit_b32 v25, v7, v9, 16
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v1
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v3
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v23
@@ -39121,19 +39102,19 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v17
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v37
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v21
; SI-NEXT: v_or_b32_e32 v4, v4, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v25
; SI-NEXT: v_or_b32_e32 v6, v6, v8
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -41024,9 +41005,8 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
@@ -41036,7 +41016,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
@@ -41044,7 +41024,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
@@ -41054,7 +41034,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
@@ -41062,7 +41042,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -41072,7 +41052,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
@@ -41080,7 +41060,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -41090,7 +41070,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
@@ -41098,7 +41078,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -41108,7 +41088,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
@@ -41116,7 +41096,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -41126,7 +41106,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
@@ -41134,7 +41114,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -41144,7 +41124,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
@@ -41152,7 +41132,7 @@ define <32 x i8> @bitcast_v16bf16_to_v32i8(<16 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
@@ -43412,8 +43392,7 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v54, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v28, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v25
@@ -43426,7 +43405,7 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v52, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v24, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v22
@@ -43437,7 +43416,7 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v51, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v20, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
@@ -43449,7 +43428,7 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v49, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v16, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v14
@@ -43460,7 +43439,7 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v48, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9
@@ -43473,7 +43452,7 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v5, v35, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
@@ -43494,8 +43473,8 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v4
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
index f27721779bc862..a550e2000e2692 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
@@ -1012,7 +1012,6 @@ define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v0, v26, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v25, v1
; SI-NEXT: v_or_b32_e32 v2, v24, v2
; SI-NEXT: v_or_b32_e32 v3, v23, v3
@@ -1022,11 +1021,11 @@ define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v19, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
@@ -2855,7 +2854,6 @@ define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v0, v26, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v25, v1
; SI-NEXT: v_or_b32_e32 v2, v24, v2
; SI-NEXT: v_or_b32_e32 v3, v23, v3
@@ -2865,11 +2863,11 @@ define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v7, v19, v7
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
@@ -4308,12 +4306,11 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v0, v28, v0
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
@@ -4325,11 +4322,11 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v29, v0
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
@@ -4339,10 +4336,10 @@ define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v2, v31, v2
; SI-NEXT: v_or_b32_e32 v0, v27, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v21, v19, v22, 16
; SI-NEXT: v_alignbit_b32 v23, v17, v20, 16
; SI-NEXT: v_alignbit_b32 v24, v15, v18, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index f14faa1f45d57b..24b4570452a516 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -1074,7 +1074,6 @@ define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v0, v29, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v28, v1
; SI-NEXT: v_or_b32_e32 v2, v27, v2
; SI-NEXT: v_or_b32_e32 v3, v26, v3
@@ -1085,12 +1084,12 @@ define <10 x i32> @bitcast_v20i16_to_v10i32(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v21, v8
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
@@ -4435,16 +4434,15 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB14_4: ; %end
@@ -7849,7 +7847,6 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v0, v29, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v28, v1
; SI-NEXT: v_or_b32_e32 v2, v27, v2
; SI-NEXT: v_or_b32_e32 v3, v26, v3
@@ -7860,12 +7857,12 @@ define <10 x float> @bitcast_v20i16_to_v10f32(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v21, v8
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
@@ -11322,16 +11319,15 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB34_4: ; %end
@@ -14346,20 +14342,19 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v8, v38, v8
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v6, v36, v6
; SI-NEXT: v_or_b32_e32 v4, v34, v4
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v0, v30, v0
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
@@ -14371,11 +14366,11 @@ define <20 x half> @bitcast_v20i16_to_v20f16(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v35, v4
; SI-NEXT: v_or_b32_e32 v2, v33, v2
; SI-NEXT: v_or_b32_e32 v0, v31, v0
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v23, v22, v29, 16
; SI-NEXT: v_alignbit_b32 v25, v20, v24, 16
; SI-NEXT: v_alignbit_b32 v26, v17, v21, 16
@@ -15655,20 +15650,19 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v9, v60, v9
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v7, v58, v7
; SI-NEXT: v_or_b32_e32 v5, v56, v5
; SI-NEXT: v_or_b32_e32 v3, v46, v3
; SI-NEXT: v_or_b32_e32 v1, v44, v1
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
@@ -15680,11 +15674,11 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v5, v47, v5
; SI-NEXT: v_or_b32_e32 v3, v45, v3
; SI-NEXT: v_or_b32_e32 v1, v43, v1
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v1
; SI-NEXT: v_alignbit_b32 v34, v27, v26, 24
; SI-NEXT: v_alignbit_b32 v37, v27, v26, 16
; SI-NEXT: v_alignbit_b32 v48, v27, v26, 8
@@ -17497,11 +17491,11 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:20
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:12
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
@@ -17509,7 +17503,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v38, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v19
; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v45, 8, v29
@@ -17517,7 +17511,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v27
; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v17
+; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v17
; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v25
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr17
@@ -17579,7 +17573,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
; SI-NEXT: v_or_b32_e32 v4, v31, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v39, v7
+; SI-NEXT: v_or_b32_e32 v12, v48, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v21, v0, v10
@@ -17587,8 +17581,8 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v9, 0xff, v30
; SI-NEXT: v_or_b32_e32 v18, v56, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v48
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v42
+; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_or_b32_e32 v11, v52, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
@@ -17606,7 +17600,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v0, v44
; SI-NEXT: v_or_b32_e32 v7, v7, v14
; SI-NEXT: v_or_b32_e32 v13, v46, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v42
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v32
; SI-NEXT: v_or_b32_e32 v3, v3, v37
@@ -17615,7 +17609,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v9, v58
; SI-NEXT: v_or_b32_e32 v13, v0, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v49
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v39
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
@@ -17652,9 +17646,9 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
@@ -17663,7 +17657,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr47
@@ -17673,7 +17667,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: .LBB50_2: ; %Flow
@@ -17681,9 +17675,9 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v49
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v43
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT: v_or_b32_e32 v1, v57, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
@@ -17691,9 +17685,8 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v59, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v50
; SI-NEXT: s_movk_i32 s6, 0x300
@@ -17704,7 +17697,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v56, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
@@ -17715,7 +17708,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v46, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
@@ -17726,18 +17719,18 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v47, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_or_b32_e32 v1, v49, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v52, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
@@ -17746,9 +17739,9 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v48, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
@@ -17759,7 +17752,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v38, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
@@ -17771,7 +17764,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v3, v36, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v0, v23, v0
@@ -17781,7 +17774,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v33, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
@@ -17792,7 +17785,7 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT: v_alignbit_b32 v17, v1, v29, 16
; SI-NEXT: v_alignbit_b32 v19, v3, v21, 16
; SI-NEXT: v_alignbit_b32 v25, v5, v15, 16
@@ -20039,7 +20032,6 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v34, v1
; SI-NEXT: v_or_b32_e32 v2, v33, v2
; SI-NEXT: v_or_b32_e32 v3, v32, v3
@@ -20050,13 +20042,13 @@ define <5 x double> @bitcast_v20i16_to_v5f64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v27, v8
; SI-NEXT: v_or_b32_e32 v9, v26, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -21000,7 +20992,6 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v34, v1
; SI-NEXT: v_or_b32_e32 v2, v33, v2
; SI-NEXT: v_or_b32_e32 v3, v32, v3
@@ -21011,13 +21002,13 @@ define <5 x i64> @bitcast_v20i16_to_v5i64(<20 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v27, v8
; SI-NEXT: v_or_b32_e32 v9, v26, v9
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -23916,11 +23907,11 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:28
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:20
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:12
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v5
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v3
@@ -23928,7 +23919,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v15
; SI-NEXT: v_lshlrev_b32_e32 v38, 24, v11
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
-; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v23
+; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
; SI-NEXT: v_lshlrev_b32_e32 v52, 24, v19
; SI-NEXT: s_waitcnt expcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v45, 8, v29
@@ -23936,7 +23927,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v27
; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v48, 8, v17
+; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v17
; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v25
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr17
@@ -23998,7 +23989,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
; SI-NEXT: v_or_b32_e32 v4, v31, v3
; SI-NEXT: v_and_b32_e32 v3, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v12, v39, v7
+; SI-NEXT: v_or_b32_e32 v12, v48, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v18
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v21, v0, v10
@@ -24006,8 +23997,8 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_and_b32_e32 v9, 0xff, v30
; SI-NEXT: v_or_b32_e32 v18, v56, v15
-; SI-NEXT: v_and_b32_e32 v15, 0xff, v43
-; SI-NEXT: v_or_b32_e32 v0, v0, v48
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v42
+; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_or_b32_e32 v11, v52, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v28
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
@@ -24025,7 +24016,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v0, v44
; SI-NEXT: v_or_b32_e32 v7, v7, v14
; SI-NEXT: v_or_b32_e32 v13, v46, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v42
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v43
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v32
; SI-NEXT: v_or_b32_e32 v3, v3, v37
@@ -24034,7 +24025,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v9, v58
; SI-NEXT: v_or_b32_e32 v13, v0, v13
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v49
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v39
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
@@ -24071,9 +24062,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr31
@@ -24082,7 +24073,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr47
@@ -24092,7 +24083,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: .LBB62_2: ; %Flow
@@ -24100,9 +24091,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_cbranch_execz .LBB62_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v49
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v43
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v42
; SI-NEXT: v_or_b32_e32 v1, v57, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x300, v1
@@ -24110,9 +24101,8 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v59, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v42
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v43
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v50
; SI-NEXT: s_movk_i32 s6, 0x300
@@ -24123,7 +24113,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v56, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v26
@@ -24134,7 +24124,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v46, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
@@ -24145,18 +24135,18 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v47, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18
-; SI-NEXT: v_or_b32_e32 v1, v48, v1
+; SI-NEXT: v_or_b32_e32 v1, v49, v1
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v52, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22
@@ -24165,9 +24155,9 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v3, v39, v3
+; SI-NEXT: v_or_b32_e32 v3, v48, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v10
@@ -24178,7 +24168,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v38, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
-; SI-NEXT: v_add_i32_e32 v21, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v14
@@ -24190,7 +24180,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v3, v36, v3
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v1
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_or_b32_e32 v0, v23, v0
@@ -24200,7 +24190,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v33, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v29, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v6
@@ -24211,7 +24201,7 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT: v_alignbit_b32 v17, v1, v29, 16
; SI-NEXT: v_alignbit_b32 v19, v3, v21, 16
; SI-NEXT: v_alignbit_b32 v25, v5, v15, 16
@@ -28734,17 +28724,16 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v17, v10
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB72_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -32580,17 +32569,16 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_or_b32_e32 v10, v17, v10
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
; SI-NEXT: .LBB76_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
index ec56217a96b6dd..45266a4feef291 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
@@ -1131,7 +1131,6 @@ define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v2, v30, v2
; SI-NEXT: v_or_b32_e32 v3, v29, v3
@@ -1143,13 +1142,13 @@ define <11 x i32> @bitcast_v22i16_to_v11i32(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v23, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
@@ -3227,7 +3226,6 @@ define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v32, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v31, v1
; SI-NEXT: v_or_b32_e32 v2, v30, v2
; SI-NEXT: v_or_b32_e32 v3, v29, v3
@@ -3239,13 +3237,13 @@ define <11 x float> @bitcast_v22i16_to_v11f32(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v23, v9
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
@@ -4881,13 +4879,12 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v0, v33, v0
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
@@ -4901,13 +4898,13 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
@@ -4919,11 +4916,11 @@ define <22 x half> @bitcast_v22i16_to_v22f16(<22 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v39, v4
; SI-NEXT: v_or_b32_e32 v2, v37, v2
; SI-NEXT: v_or_b32_e32 v0, v34, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v26, v24, v29, 16
; SI-NEXT: v_alignbit_b32 v27, v22, v25, 16
; SI-NEXT: v_alignbit_b32 v28, v19, v23, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
index ab00b98ec0560b..0527d0739ffbe2 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
@@ -2350,7 +2350,6 @@ define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v34, v1
; SI-NEXT: v_or_b32_e32 v2, v33, v2
; SI-NEXT: v_or_b32_e32 v3, v32, v3
@@ -2363,14 +2362,14 @@ define <12 x i32> @bitcast_v24i16_to_v12i32(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v25, v10
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
@@ -5761,7 +5760,6 @@ define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v34, v1
; SI-NEXT: v_or_b32_e32 v2, v33, v2
; SI-NEXT: v_or_b32_e32 v3, v32, v3
@@ -5774,14 +5772,14 @@ define <12 x float> @bitcast_v24i16_to_v12f32(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v25, v10
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
@@ -8537,7 +8535,6 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v38, v1
; SI-NEXT: v_or_b32_e32 v2, v37, v2
; SI-NEXT: v_or_b32_e32 v3, v36, v3
@@ -8550,15 +8547,15 @@ define <6 x double> @bitcast_v24i16_to_v6f64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v29, v10
; SI-NEXT: v_or_b32_e32 v11, v28, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -10785,7 +10782,6 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v38, v1
; SI-NEXT: v_or_b32_e32 v2, v37, v2
; SI-NEXT: v_or_b32_e32 v3, v36, v3
@@ -10798,15 +10794,15 @@ define <6 x i64> @bitcast_v24i16_to_v6i64(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v29, v10
; SI-NEXT: v_or_b32_e32 v11, v28, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -12597,7 +12593,6 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v10, v54, v10
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v8, v52, v8
; SI-NEXT: v_or_b32_e32 v6, v50, v6
; SI-NEXT: v_or_b32_e32 v4, v39, v4
@@ -12605,15 +12600,15 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v36, v0
; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
@@ -12627,12 +12622,12 @@ define <24 x half> @bitcast_v24i16_to_v24f16(<24 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v49, v4
; SI-NEXT: v_or_b32_e32 v2, v48, v2
; SI-NEXT: v_or_b32_e32 v0, v38, v0
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v28, v27, v35, 16
; SI-NEXT: v_alignbit_b32 v29, v25, v30, 16
; SI-NEXT: v_alignbit_b32 v31, v22, v26, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
index cb85f607aca61b..5950507d70a97d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
@@ -2581,7 +2581,6 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v50, v1
; SI-NEXT: v_or_b32_e32 v2, v49, v2
; SI-NEXT: v_or_b32_e32 v3, v48, v3
@@ -2596,16 +2595,16 @@ define <14 x i32> @bitcast_v28i16_to_v14i32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v31, v12
; SI-NEXT: v_or_b32_e32 v13, v30, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
@@ -6400,7 +6399,6 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v50, v1
; SI-NEXT: v_or_b32_e32 v2, v49, v2
; SI-NEXT: v_or_b32_e32 v3, v48, v3
@@ -6415,16 +6413,16 @@ define <14 x float> @bitcast_v28i16_to_v14f32(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v31, v12
; SI-NEXT: v_or_b32_e32 v13, v30, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
@@ -9554,7 +9552,6 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v50, v1
; SI-NEXT: v_or_b32_e32 v2, v49, v2
; SI-NEXT: v_or_b32_e32 v3, v48, v3
@@ -9569,16 +9566,16 @@ define <7 x i64> @bitcast_v28i16_to_v7i64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v31, v12
; SI-NEXT: v_or_b32_e32 v13, v30, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
@@ -12044,7 +12041,6 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v51, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v50, v1
; SI-NEXT: v_or_b32_e32 v2, v49, v2
; SI-NEXT: v_or_b32_e32 v3, v48, v3
@@ -12059,16 +12055,16 @@ define <7 x double> @bitcast_v28i16_to_v7f64(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v31, v12
; SI-NEXT: v_or_b32_e32 v13, v30, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
@@ -14038,7 +14034,6 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v12, v46, v12
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v10, v43, v10
; SI-NEXT: v_or_b32_e32 v8, v41, v8
; SI-NEXT: v_or_b32_e32 v6, v55, v6
@@ -14047,17 +14042,17 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v50, v0
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v37, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
@@ -14073,13 +14068,13 @@ define <28 x half> @bitcast_v28i16_to_v28f16(<28 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v40, v4
; SI-NEXT: v_or_b32_e32 v2, v54, v2
; SI-NEXT: v_or_b32_e32 v0, v52, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v33, v31, v49, 16
; SI-NEXT: v_alignbit_b32 v34, v29, v37, 16
; SI-NEXT: v_alignbit_b32 v35, v27, v32, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
index 8f8cd9205e24bd..ab21a7fa9cfe7b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
@@ -73,9 +73,8 @@ define <3 x half> @bitcast_v3bf16_to_v3f16(<3 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
@@ -839,9 +838,8 @@ define <3 x i16> @bitcast_v3bf16_to_v3i16(<3 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 59725b5b5dea6c..7a73205e770083 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -2877,7 +2877,6 @@ define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v0, v55, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_or_b32_e32 v2, v53, v2
; SI-NEXT: v_or_b32_e32 v3, v52, v3
@@ -2894,18 +2893,18 @@ define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
@@ -5922,9 +5921,8 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
@@ -5934,7 +5932,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -5942,7 +5940,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
@@ -5952,7 +5950,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -5960,7 +5958,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
@@ -5970,7 +5968,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -5978,7 +5976,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
@@ -5988,7 +5986,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -5996,7 +5994,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
@@ -6006,7 +6004,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6014,7 +6012,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
@@ -6024,7 +6022,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6032,7 +6030,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
@@ -6042,7 +6040,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6050,7 +6048,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
@@ -6060,7 +6058,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6068,7 +6066,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
@@ -6078,7 +6076,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6086,7 +6084,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
@@ -6096,7 +6094,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6104,7 +6102,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
@@ -6114,7 +6112,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6122,7 +6120,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
@@ -6132,7 +6130,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6140,7 +6138,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
@@ -6150,7 +6148,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6158,7 +6156,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
@@ -6168,7 +6166,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -6176,7 +6174,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
@@ -6186,7 +6184,7 @@ define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -11989,9 +11987,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -12009,7 +12006,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -12040,7 +12037,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -12057,7 +12054,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -12066,7 +12063,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -12075,7 +12072,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -12126,13 +12123,13 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
@@ -17738,7 +17735,6 @@ define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v0, v55, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_or_b32_e32 v2, v53, v2
; SI-NEXT: v_or_b32_e32 v3, v52, v3
@@ -17755,18 +17751,18 @@ define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
@@ -20879,9 +20875,8 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
@@ -20891,7 +20886,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -20899,7 +20894,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
@@ -20909,7 +20904,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -20917,7 +20912,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
@@ -20927,7 +20922,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -20935,7 +20930,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
@@ -20945,7 +20940,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -20953,7 +20948,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
@@ -20963,7 +20958,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -20971,7 +20966,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
@@ -20981,7 +20976,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -20989,7 +20984,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
@@ -20999,7 +20994,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21007,7 +21002,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
@@ -21017,7 +21012,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21025,7 +21020,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
@@ -21035,7 +21030,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21043,7 +21038,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
@@ -21053,7 +21048,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21061,7 +21056,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
@@ -21071,7 +21066,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21079,7 +21074,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
@@ -21089,7 +21084,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21097,7 +21092,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
@@ -21107,7 +21102,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21115,7 +21110,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
@@ -21125,7 +21120,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -21133,7 +21128,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
@@ -21143,7 +21138,7 @@ define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -27211,9 +27206,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -27231,7 +27225,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -27262,7 +27256,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -27279,7 +27273,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -27288,7 +27282,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -27297,7 +27291,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -27348,13 +27342,13 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
@@ -32139,7 +32133,6 @@ define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v0, v55, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_or_b32_e32 v2, v53, v2
; SI-NEXT: v_or_b32_e32 v3, v52, v3
@@ -32156,18 +32149,18 @@ define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
@@ -35192,9 +35185,8 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
@@ -35204,7 +35196,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35212,7 +35204,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
@@ -35222,7 +35214,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35230,7 +35222,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
@@ -35240,7 +35232,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35248,7 +35240,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
@@ -35258,7 +35250,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35266,7 +35258,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
@@ -35276,7 +35268,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35284,7 +35276,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
@@ -35294,7 +35286,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35302,7 +35294,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
@@ -35312,7 +35304,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35320,7 +35312,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
@@ -35330,7 +35322,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35338,7 +35330,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
@@ -35348,7 +35340,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35356,7 +35348,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
@@ -35366,7 +35358,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35374,7 +35366,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
@@ -35384,7 +35376,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35392,7 +35384,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
@@ -35402,7 +35394,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35410,7 +35402,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
@@ -35420,7 +35412,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35428,7 +35420,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
@@ -35438,7 +35430,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -35446,7 +35438,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
@@ -35456,7 +35448,7 @@ define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -41332,9 +41324,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -41352,7 +41343,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -41383,7 +41374,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -41400,7 +41391,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -41409,7 +41400,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -41418,7 +41409,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -41469,13 +41460,13 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
@@ -45545,7 +45536,6 @@ define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_or_b32_e32 v0, v55, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_or_b32_e32 v2, v53, v2
; SI-NEXT: v_or_b32_e32 v3, v52, v3
@@ -45562,18 +45552,18 @@ define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v33, v14
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
@@ -48566,9 +48556,8 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
@@ -48578,7 +48567,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48586,7 +48575,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
@@ -48596,7 +48585,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48604,7 +48593,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
@@ -48614,7 +48603,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48622,7 +48611,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
@@ -48632,7 +48621,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48640,7 +48629,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
@@ -48650,7 +48639,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48658,7 +48647,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
@@ -48668,7 +48657,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48676,7 +48665,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
@@ -48686,7 +48675,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48694,7 +48683,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
@@ -48704,7 +48693,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48712,7 +48701,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
@@ -48722,7 +48711,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48730,7 +48719,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
@@ -48740,7 +48729,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48748,7 +48737,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
@@ -48758,7 +48747,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48766,7 +48755,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
@@ -48776,7 +48765,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48784,7 +48773,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
@@ -48794,7 +48783,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48802,7 +48791,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
@@ -48812,7 +48801,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -48820,7 +48809,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
@@ -48830,7 +48819,7 @@ define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
@@ -54872,9 +54861,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -54892,7 +54880,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
@@ -54923,7 +54911,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -54940,7 +54928,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
@@ -54949,7 +54937,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
@@ -54958,7 +54946,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
@@ -55009,13 +54997,13 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
@@ -58564,7 +58552,6 @@ define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v14, v61, v14
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v12, v59, v12
; SI-NEXT: v_or_b32_e32 v10, v57, v10
; SI-NEXT: v_or_b32_e32 v8, v47, v8
@@ -58574,19 +58561,19 @@ define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v40, v0
; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v51, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
@@ -58604,14 +58591,14 @@ define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v4, v46, v4
; SI-NEXT: v_or_b32_e32 v2, v44, v2
; SI-NEXT: v_or_b32_e32 v0, v42, v0
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v37, v36, v55, 16
; SI-NEXT: v_alignbit_b32 v38, v34, v51, 16
; SI-NEXT: v_alignbit_b32 v48, v32, v39, 16
@@ -60387,7 +60374,6 @@ define <32 x bfloat> @bitcast_v32i16_to_v32bf16(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v15, v31, v15
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v14, v30, v14
; SI-NEXT: v_or_b32_e32 v13, v29, v13
; SI-NEXT: v_or_b32_e32 v12, v28, v12
@@ -60404,21 +60390,21 @@ define <32 x bfloat> @bitcast_v32i16_to_v32bf16(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v17, v1
; SI-NEXT: v_or_b32_e32 v0, v16, v0
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v0
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
@@ -61604,9 +61590,8 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
@@ -61614,7 +61599,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -61622,7 +61607,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
@@ -61630,7 +61615,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
-; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
+; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
@@ -61638,7 +61623,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
; VI-NEXT: v_bfe_u32 v19, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v2
-; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
+; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc
@@ -61646,7 +61631,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
-; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
+; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
@@ -61654,7 +61639,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
; VI-NEXT: v_bfe_u32 v20, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v3
-; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
+; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc
@@ -61662,7 +61647,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
-; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
@@ -61670,7 +61655,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
; VI-NEXT: v_bfe_u32 v21, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v4
-; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc
@@ -61678,7 +61663,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
-; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
+; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
@@ -61686,7 +61671,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
; VI-NEXT: v_bfe_u32 v22, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v5
-; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
+; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc
@@ -61694,7 +61679,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
-; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
@@ -61702,7 +61687,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
; VI-NEXT: v_bfe_u32 v23, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v6
-; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc
@@ -61710,7 +61695,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; VI-NEXT: v_bfe_u32 v24, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23
-; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
+; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
@@ -61718,7 +61703,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
; VI-NEXT: v_bfe_u32 v24, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v7
-; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
+; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc
@@ -61726,7 +61711,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
-; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
@@ -61734,7 +61719,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
; VI-NEXT: v_bfe_u32 v25, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v8
-; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc
@@ -61742,7 +61727,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; VI-NEXT: v_bfe_u32 v26, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25
-; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
+; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
@@ -61750,7 +61735,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
; VI-NEXT: v_bfe_u32 v26, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v9
-; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
+; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc
@@ -61758,7 +61743,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
-; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
@@ -61766,7 +61751,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
; VI-NEXT: v_bfe_u32 v27, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v10
-; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc
@@ -61774,7 +61759,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; VI-NEXT: v_bfe_u32 v28, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27
-; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
+; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
@@ -61782,7 +61767,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
; VI-NEXT: v_bfe_u32 v28, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v11
-; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
+; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc
@@ -61790,7 +61775,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
-; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
@@ -61798,7 +61783,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
; VI-NEXT: v_bfe_u32 v29, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v12
-; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v29, v30, vcc
@@ -61806,7 +61791,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
; VI-NEXT: v_bfe_u32 v30, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29
-; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
+; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
@@ -61814,7 +61799,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc
; VI-NEXT: v_bfe_u32 v30, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v13
-; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
+; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v30, v31, vcc
@@ -61822,7 +61807,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; VI-NEXT: v_bfe_u32 v31, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v30
-; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
+; VI-NEXT: v_add_u32_e32 v31, vcc, 0x7fff, v31
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
@@ -61830,7 +61815,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v30, v31, v32, vcc
; VI-NEXT: v_bfe_u32 v31, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v14
-; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
+; VI-NEXT: v_add_u32_e32 v31, vcc, 0x7fff, v31
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
@@ -61838,7 +61823,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; VI-NEXT: v_bfe_u32 v32, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v31
-; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
+; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
@@ -61846,7 +61831,7 @@ define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc
; VI-NEXT: v_bfe_u32 v32, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v15
-; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
+; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v32, v33, vcc
@@ -64732,19 +64717,18 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v57, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_or_b32_e32 v3, v61, v3
; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v37, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v1
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 24
@@ -64754,9 +64738,9 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 16
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v3
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x30000, v3
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 8
@@ -64771,9 +64755,9 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v36, v37, 16
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x30000, v5
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v36, v37, 8
@@ -64788,9 +64772,9 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 16
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v7
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 8
@@ -64805,9 +64789,9 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 16
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v9
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 8
@@ -64822,9 +64806,9 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v29, v28, 16
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v11
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v11
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v29, v28, 8
@@ -64840,7 +64824,7 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_alignbit_b32 v1, v26, v25, 16
; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v16
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v13
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v26, v25, 8
@@ -64852,7 +64836,7 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v24, v23, 16
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v15
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v15
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v1, v24, v23, 8
@@ -68152,533 +68136,510 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v21
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v44, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v57, 8, v29
+; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v17
; SI-NEXT: v_lshlrev_b32_e32 v47, 8, v25
; SI-NEXT: ; kill: killed $vgpr3
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; kill: killed $vgpr3
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; kill: killed $vgpr5
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v4
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v16
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v10
-; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v26
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v28
+; SI-NEXT: v_lshlrev_b32_e32 v61, 8, v4
+; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v20
+; SI-NEXT: v_lshlrev_b32_e32 v58, 24, v10
+; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
+; SI-NEXT: v_lshlrev_b32_e32 v33, 8, v28
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:52
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:44
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v14
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v32
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v22
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v26
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v32
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:76
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v34
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v35
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v36
+; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v37
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:100
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB98_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v16, v16, v13
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v6, v1
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
+; SI-NEXT: v_or_b32_e32 v13, v13, v18
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v33
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v62
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v59, v2
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v39, v46, v9
+; SI-NEXT: v_or_b32_e32 v3, v3, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v18, v24, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v4, v4, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v21, v21, v15
+; SI-NEXT: v_or_b32_e32 v15, v8, v21
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v27, v8
+; SI-NEXT: v_or_b32_e32 v13, v13, v18
+; SI-NEXT: v_alignbit_b32 v26, v13, v4, 16
+; SI-NEXT: v_alignbit_b32 v32, v15, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v21
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v46, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v20
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v29, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v23, v0, v29
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v20, v58, v11
+; SI-NEXT: v_or_b32_e32 v11, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v1, v63, v1
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: v_alignbit_b32 v22, v11, v1, 16
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v29, v7, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v3, v29
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v39
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_or_b32_e32 v16, v16, v24
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_or_b32_e32 v12, v7, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v14, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v52
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v36, v7, v3
+; SI-NEXT: v_alignbit_b32 v3, v23, v12, 16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v3, v0, v36
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v12, v16, v12
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v3, v3, v36
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v3, v17, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v37, v7, v5
-; SI-NEXT: v_or_b32_e32 v5, v0, v37
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v37
-; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v54, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v14, v7, v5
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v5, v3, v14, 16
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v37, v9, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v37
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v53
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v38, v42, v7
-; SI-NEXT: v_alignbit_b32 v53, v5, v19, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_or_b32_e32 v17, v54, v7
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v38, v43, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: v_or_b32_e32 v60, v16, v17
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v55
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v37
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v38
+; SI-NEXT: v_alignbit_b32 v7, v5, v17, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v19, v45, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v47
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v41, v16, v19
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v57
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v38
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v48
+; SI-NEXT: v_alignbit_b32 v44, v7, v19, 16
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v61
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v48
+; SI-NEXT: v_alignbit_b32 v31, v9, v20, 16
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v0, v16, v0
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v7, v0, v38
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v25, v44, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v25, 16
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: v_or_b32_e32 v39, v0, v20
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v9, v0, v39
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v20, v57, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v12, v59, v11
-; SI-NEXT: v_or_b32_e32 v11, v0, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v26, v63, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v13, v0, v16
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v25, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v6
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: v_or_b32_e32 v0, v0, v34
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v4, v8
-; SI-NEXT: v_or_b32_e32 v15, v0, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v8, v27, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v20, 16
-; SI-NEXT: v_alignbit_b32 v22, v11, v26, 16
-; SI-NEXT: v_alignbit_b32 v21, v13, v2, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v8, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v19, v0, v4
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v51
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v14, v18
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v61, v17, v19
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v19, v1, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
-; SI-NEXT: v_or_b32_e32 v1, v1, v51
+; SI-NEXT: v_or_b32_e32 v17, v0, v8
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: .LBB98_2: ; %Flow
+; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; SI-NEXT: s_cbranch_execz .LBB98_4
+; SI-NEXT: ; %bb.3: ; %cmp.true
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_or_b32_e32 v1, v62, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v47
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v43, v17, v25
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v31
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v48, v17, v20
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
-; SI-NEXT: v_or_b32_e32 v17, v1, v8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_or_b32_e32 v25, v10, v26
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: .LBB98_2: ; %Flow
-; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; SI-NEXT: s_cbranch_execz .LBB98_4
-; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_or_b32_e32 v2, v59, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v3, v27, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
+; SI-NEXT: v_or_b32_e32 v3, v51, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
+; SI-NEXT: v_or_b32_e32 v5, v27, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v33, v5
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v5, v21, v5
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v40
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v52
-; SI-NEXT: v_or_b32_e32 v0, v18, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_alignbit_b32 v21, v13, v19, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_or_b32_e32 v3, v18, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_alignbit_b32 v32, v15, v17, 16
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v0, v62, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v57, v1
-; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v31, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
+; SI-NEXT: v_or_b32_e32 v0, v61, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v46, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v48, 16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
+; SI-NEXT: v_alignbit_b32 v31, v9, v39, 16
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
@@ -68689,9 +68650,9 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
+; SI-NEXT: v_or_b32_e32 v1, v45, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v41, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -68699,39 +68660,50 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v56, v0
+; SI-NEXT: v_or_b32_e32 v0, v57, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v43, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v43, 16
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v44, v7, v41, 16
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v0, v53, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v61, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v60, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v24, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v63, v4
+; SI-NEXT: v_alignbit_b32 v26, v13, v19, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_or_b32_e32 v0, v55, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
@@ -68740,16 +68712,23 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v53, v5, v61, 16
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_or_b32_e32 v3, v10, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v3
+; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
@@ -68760,29 +68739,27 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v0, v52, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
@@ -68797,66 +68774,73 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v1
-; SI-NEXT: v_alignbit_b32 v1, v23, v0, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v0, v23, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v3, v14, 16
+; SI-NEXT: v_alignbit_b32 v0, v3, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v5, v60, 16
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: .LBB98_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v60
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v29
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -68874,18 +68858,18 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v37
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v38
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v10, v10, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v48
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v26
; SI-NEXT: v_or_b32_e32 v12, v12, v14
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
@@ -73998,9 +73982,8 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
-; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
+; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
@@ -74008,7 +73991,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -74016,7 +73999,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
@@ -74024,7 +74007,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
-; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
+; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
@@ -74032,7 +74015,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
; VI-NEXT: v_bfe_u32 v19, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v2
-; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
+; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc
@@ -74040,7 +74023,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
-; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
+; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
@@ -74048,7 +74031,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
; VI-NEXT: v_bfe_u32 v20, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v3
-; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
+; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc
@@ -74056,7 +74039,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
-; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
@@ -74064,7 +74047,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
; VI-NEXT: v_bfe_u32 v21, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v4
-; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
+; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc
@@ -74072,7 +74055,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
-; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
+; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
@@ -74080,7 +74063,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
; VI-NEXT: v_bfe_u32 v22, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v5
-; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
+; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc
@@ -74088,7 +74071,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
-; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v22
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
@@ -74096,7 +74079,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
; VI-NEXT: v_bfe_u32 v23, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v6
-; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
+; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc
@@ -74104,7 +74087,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
; VI-NEXT: v_bfe_u32 v24, v23, 16, 1
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23
-; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
+; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
@@ -74112,7 +74095,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
; VI-NEXT: v_bfe_u32 v24, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v7
-; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
+; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc
@@ -74120,7 +74103,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
-; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
@@ -74128,7 +74111,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
; VI-NEXT: v_bfe_u32 v25, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v8
-; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
+; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc
@@ -74136,7 +74119,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
; VI-NEXT: v_bfe_u32 v26, v25, 16, 1
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25
-; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
+; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
@@ -74144,7 +74127,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
; VI-NEXT: v_bfe_u32 v26, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v9
-; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
+; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc
@@ -74152,7 +74135,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
-; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v26
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
@@ -74160,7 +74143,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
; VI-NEXT: v_bfe_u32 v27, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v10
-; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
+; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc
@@ -74168,7 +74151,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
; VI-NEXT: v_bfe_u32 v28, v27, 16, 1
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27
-; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
+; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
@@ -74176,7 +74159,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
; VI-NEXT: v_bfe_u32 v28, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v11
-; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
+; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc
@@ -74184,7 +74167,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
-; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v28
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
@@ -74192,7 +74175,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
; VI-NEXT: v_bfe_u32 v29, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v12
-; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
+; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v29, v30, vcc
@@ -74200,7 +74183,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
; VI-NEXT: v_bfe_u32 v30, v29, 16, 1
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29
-; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
+; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v29
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
@@ -74208,7 +74191,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc
; VI-NEXT: v_bfe_u32 v30, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v13
-; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
+; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v30, v31, vcc
@@ -74216,7 +74199,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
; VI-NEXT: v_bfe_u32 v31, v30, 16, 1
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v30
-; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
+; VI-NEXT: v_add_u32_e32 v31, vcc, 0x7fff, v31
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v30
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
@@ -74224,7 +74207,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v30, v31, v32, vcc
; VI-NEXT: v_bfe_u32 v31, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v14
-; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
+; VI-NEXT: v_add_u32_e32 v31, vcc, 0x7fff, v31
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
@@ -74232,7 +74215,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
; VI-NEXT: v_bfe_u32 v32, v31, 16, 1
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v31
-; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
+; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v31
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
@@ -74240,7 +74223,7 @@ define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc
; VI-NEXT: v_bfe_u32 v32, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v15
-; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
+; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v32, v33, vcc
@@ -80773,533 +80756,510 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
-; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:104
-; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:92
-; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:120
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:40
+; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr3
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v21
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v29
-; SI-NEXT: v_lshlrev_b32_e32 v44, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v57, 8, v29
+; SI-NEXT: v_lshlrev_b32_e32 v45, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v53, 8, v17
; SI-NEXT: v_lshlrev_b32_e32 v47, 8, v25
; SI-NEXT: ; kill: killed $vgpr3
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; kill: killed $vgpr3
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; kill: killed $vgpr5
; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: ; implicit-def: $vgpr29
+; SI-NEXT: ; implicit-def: $vgpr41
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr19
-; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
-; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v4
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v9
-; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v16
-; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
-; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v10
-; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v26
-; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v28
+; SI-NEXT: v_lshlrev_b32_e32 v61, 8, v4
+; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v18
+; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v20
+; SI-NEXT: v_lshlrev_b32_e32 v58, 24, v10
+; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
+; SI-NEXT: v_lshlrev_b32_e32 v33, 8, v28
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:52
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:44
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v14
-; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
-; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
-; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v31
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v17
-; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v32
+; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v22
+; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v26
; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v31
+; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v32
+; SI-NEXT: s_waitcnt vmcnt(13)
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:76
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v36
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v34
+; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v35
+; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v36
+; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v37
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr22
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:100
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:100
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_2
; SI-NEXT: ; %bb.1: ; %cmp.false
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v26
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v52
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v16, v16, v13
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v1, v6, v1
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
+; SI-NEXT: v_or_b32_e32 v13, v13, v18
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_or_b32_e32 v8, v8, v33
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_or_b32_e32 v1, v1, v62
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr52
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v2, v59, v2
+; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; SI-NEXT: ; implicit-def: $vgpr40
+; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_or_b32_e32 v0, v0, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v39, v46, v9
+; SI-NEXT: v_or_b32_e32 v3, v3, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v18, v24, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v42
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v4, v4, v15
+; SI-NEXT: v_and_b32_e32 v15, 0xff, v30
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; SI-NEXT: v_or_b32_e32 v21, v21, v15
+; SI-NEXT: v_or_b32_e32 v15, v8, v21
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v16
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_or_b32_e32 v8, v27, v8
+; SI-NEXT: v_or_b32_e32 v13, v13, v18
+; SI-NEXT: v_alignbit_b32 v26, v13, v4, 16
+; SI-NEXT: v_alignbit_b32 v32, v15, v8, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v18
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v21
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; implicit-def: $vgpr21
+; SI-NEXT: ; implicit-def: $vgpr27
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v48, v46, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v20
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v29, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v23, v0, v29
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; SI-NEXT: v_or_b32_e32 v20, v58, v11
+; SI-NEXT: v_or_b32_e32 v11, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v28
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v1, v63, v1
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: v_alignbit_b32 v22, v11, v1, 16
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_or_b32_e32 v29, v7, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v23, v3, v29
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v29
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v39
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_or_b32_e32 v16, v16, v24
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_or_b32_e32 v12, v7, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v14, v5, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v52
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v36, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v36, v7, v3
+; SI-NEXT: v_alignbit_b32 v3, v23, v12, 16
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
-; SI-NEXT: v_or_b32_e32 v3, v0, v36
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v5
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v12, v16, v12
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v3, v3, v36
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v5, v0
-; SI-NEXT: v_alignbit_b32 v0, v3, v17, 16
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v55
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v37, v7, v5
-; SI-NEXT: v_or_b32_e32 v5, v0, v37
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v37
-; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v54, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v14, v7, v5
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v5, v3, v14, 16
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v24
+; SI-NEXT: ; implicit-def: $vgpr24
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v14, v16, v14
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; SI-NEXT: v_or_b32_e32 v37, v9, v7
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v37
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v53
+; SI-NEXT: ; implicit-def: $vgpr53
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v38, v42, v7
-; SI-NEXT: v_alignbit_b32 v53, v5, v19, 16
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_or_b32_e32 v17, v54, v7
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v38, v43, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: v_or_b32_e32 v60, v16, v17
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v55
+; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; SI-NEXT: v_or_b32_e32 v5, v5, v37
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v38
+; SI-NEXT: v_alignbit_b32 v7, v5, v17, 16
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; SI-NEXT: v_or_b32_e32 v19, v45, v9
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr45
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v16, v16, v47
+; SI-NEXT: ; implicit-def: $vgpr47
+; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; SI-NEXT: v_or_b32_e32 v41, v16, v19
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v57
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v7, v7, v38
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v48
+; SI-NEXT: v_alignbit_b32 v44, v7, v19, 16
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v61
+; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; SI-NEXT: v_or_b32_e32 v9, v9, v48
+; SI-NEXT: v_alignbit_b32 v31, v9, v20, 16
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v2
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v56
+; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
+; SI-NEXT: v_or_b32_e32 v0, v16, v0
+; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v7, v0, v38
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v25, v44, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v25, 16
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: v_or_b32_e32 v39, v0, v20
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v9, v0, v39
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v20, v57, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v12, v59, v11
-; SI-NEXT: v_or_b32_e32 v11, v0, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v26, v63, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v40
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
+; SI-NEXT: v_or_b32_e32 v0, v0, v10
+; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v13, v0, v16
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v2, v2, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
+; SI-NEXT: v_or_b32_e32 v25, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v6
+; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: v_or_b32_e32 v0, v0, v34
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v4, v4, v8
-; SI-NEXT: v_or_b32_e32 v15, v0, v4
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v8, v27, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v20, 16
-; SI-NEXT: v_alignbit_b32 v22, v11, v26, 16
-; SI-NEXT: v_alignbit_b32 v21, v13, v2, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v8, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr57
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v0, v18
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v0, v14
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v14, v14, v18
-; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v14, v14, v17
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v17, v17, v18
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v61, v17, v19
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v19, v1, v2
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
-; SI-NEXT: v_or_b32_e32 v1, v1, v51
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: ; implicit-def: $vgpr58
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: v_or_b32_e32 v19, v0, v4
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: ; implicit-def: $vgpr56
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: v_or_b32_e32 v0, v0, v51
; SI-NEXT: ; implicit-def: $vgpr51
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v47
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v43, v17, v25
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v17, v17, v31
-; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v48, v17, v20
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
-; SI-NEXT: v_or_b32_e32 v10, v17, v10
-; SI-NEXT: v_or_b32_e32 v17, v1, v8
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_or_b32_e32 v25, v10, v26
-; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v17, v0, v8
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr1
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: .LBB106_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB106_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v58
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
-; SI-NEXT: v_or_b32_e32 v0, v51, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_or_b32_e32 v1, v62, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v2, v59, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v56
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
-; SI-NEXT: v_or_b32_e32 v3, v27, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v16
+; SI-NEXT: v_or_b32_e32 v3, v51, v3
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x300, v3
+; SI-NEXT: v_or_b32_e32 v5, v27, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v5, v33, v5
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v5
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v30
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v5, v21, v5
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_or_b32_e32 v3, v34, v3
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_or_b32_e32 v3, v4, v3
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v40
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v52
-; SI-NEXT: v_or_b32_e32 v0, v18, v0
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v16, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
-; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v63, v1
-; SI-NEXT: v_alignbit_b32 v21, v13, v19, 16
-; SI-NEXT: v_alignbit_b32 v33, v15, v17, 16
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v40
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_or_b32_e32 v3, v18, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_alignbit_b32 v32, v15, v17, 16
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v15
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v10, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
-; SI-NEXT: v_or_b32_e32 v0, v62, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v59, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v57, v1
-; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: v_or_b32_e32 v0, v31, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v60, v0
+; SI-NEXT: v_or_b32_e32 v0, v61, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v46, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v32, v9, v48, 16
-; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
+; SI-NEXT: v_alignbit_b32 v31, v9, v39, 16
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
@@ -81310,9 +81270,9 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v44, v1
+; SI-NEXT: v_or_b32_e32 v1, v45, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v41, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -81320,39 +81280,50 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
-; SI-NEXT: v_or_b32_e32 v0, v56, v0
+; SI-NEXT: v_or_b32_e32 v0, v57, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v1, v42, v1
+; SI-NEXT: v_or_b32_e32 v1, v43, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v45, v7, v43, 16
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v44, v7, v41, 16
+; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v0, v53, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v54, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v61, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v60, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v24, v4
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v28
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v4, v63, v4
+; SI-NEXT: v_alignbit_b32 v26, v13, v19, 16
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_or_b32_e32 v0, v55, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
@@ -81361,16 +81332,23 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v53, v5, v61, 16
-; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_or_b32_e32 v3, v10, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v3, v4, v3
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x3000000, v3
+; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
+; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
@@ -81381,29 +81359,27 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
+; SI-NEXT: v_or_b32_e32 v0, v52, v0
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
@@ -81418,66 +81394,73 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
-; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v1
-; SI-NEXT: v_alignbit_b32 v1, v23, v0, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x3000000, v0
+; SI-NEXT: v_alignbit_b32 v0, v23, v12, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, v3, v14, 16
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v3, v14, 16
+; SI-NEXT: v_alignbit_b32 v0, v5, v60, 16
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: .LBB106_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v44
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v2, v2, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
+; SI-NEXT: v_and_b32_e32 v4, 0xffff, v60
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v4, v4, v6
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v29
; SI-NEXT: v_or_b32_e32 v5, v5, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -81495,18 +81478,18 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v6, v6, v8
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v37
; SI-NEXT: v_or_b32_e32 v7, v7, v8
-; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
+; SI-NEXT: v_and_b32_e32 v8, 0xffff, v39
; SI-NEXT: v_or_b32_e32 v8, v8, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v38
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v10, v10, v12
-; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v48
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v26
; SI-NEXT: v_or_b32_e32 v12, v12, v14
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
@@ -86071,9 +86054,8 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v2, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v2
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v18, v19, vcc
@@ -86083,7 +86065,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86091,7 +86073,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
@@ -86101,7 +86083,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86109,7 +86091,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v4
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc
@@ -86119,7 +86101,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86127,7 +86109,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v3
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; VI-NEXT: v_cndmask_b32_e32 v3, v18, v19, vcc
@@ -86137,7 +86119,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86145,7 +86127,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v6, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v6
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v6
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v18, v19, vcc
@@ -86155,7 +86137,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86163,7 +86145,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v5
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v18, v19, vcc
@@ -86173,7 +86155,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86181,7 +86163,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v8, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v8
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v8
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; VI-NEXT: v_cndmask_b32_e32 v8, v18, v19, vcc
@@ -86191,7 +86173,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86199,7 +86181,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v7, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v7
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc
@@ -86209,7 +86191,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86217,7 +86199,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v10, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v10
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v10
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
; VI-NEXT: v_cndmask_b32_e32 v10, v18, v19, vcc
@@ -86227,7 +86209,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86235,7 +86217,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v9, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v9
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v9
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; VI-NEXT: v_cndmask_b32_e32 v9, v18, v19, vcc
@@ -86245,7 +86227,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86253,7 +86235,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v12, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v12
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v12
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
; VI-NEXT: v_cndmask_b32_e32 v12, v18, v19, vcc
@@ -86263,7 +86245,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86271,7 +86253,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v11, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v11
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v11
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
; VI-NEXT: v_cndmask_b32_e32 v11, v18, v19, vcc
@@ -86281,7 +86263,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86289,7 +86271,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v14, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v14
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v14
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
; VI-NEXT: v_cndmask_b32_e32 v14, v18, v19, vcc
@@ -86299,7 +86281,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86307,7 +86289,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v13, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v13
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
; VI-NEXT: v_cndmask_b32_e32 v13, v18, v19, vcc
@@ -86317,7 +86299,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86325,7 +86307,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v16, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v16
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v16
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
; VI-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc
@@ -86335,7 +86317,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
@@ -86343,7 +86325,7 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
-; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
+; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
; VI-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc
@@ -91446,28 +91428,28 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:48
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
-; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:48
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:56
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:64
+; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:88
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
-; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120
-; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
-; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:108
-; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:104
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112
+; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:120
+; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:128
+; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:108
+; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:104
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:100
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:36
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:28
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:28
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v5
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
@@ -91476,108 +91458,120 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
-; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:116
+; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:124
+; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; kill: killed $vgpr11
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; kill: killed $vgpr11
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v19
-; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
+; SI-NEXT: v_lshlrev_b32_e32 v52, 8, v21
; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
-; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v27
-; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v29
+; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v27
+; SI-NEXT: v_lshlrev_b32_e32 v44, 8, v29
; SI-NEXT: ; kill: killed $vgpr11
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; kill: killed $vgpr11
-; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr52
+; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr53
-; SI-NEXT: ; implicit-def: $vgpr55
+; SI-NEXT: ; implicit-def: $vgpr54
+; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr58
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr32
+; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr13
-; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr35
-; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v1
-; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v2
-; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v6
-; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v8
-; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v9
-; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v14
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v16
-; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v17
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v18
-; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v24
-; SI-NEXT: s_waitcnt vmcnt(12)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:68
-; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
-; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:52
-; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44
-; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:40
-; SI-NEXT: s_waitcnt vmcnt(14)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v28
-; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: v_lshlrev_b32_e32 v55, 24, v1
+; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
+; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v4
+; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v6
+; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v8
+; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v12
+; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v16
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v17
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:60
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:52
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:44
+; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:40
+; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v20
+; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v24
+; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v26
+; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr24
-; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: s_waitcnt vmcnt(13)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; SI-NEXT: ; implicit-def: $vgpr16
+; SI-NEXT: ; implicit-def: $vgpr20
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:12
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:8
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v9
+; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v22
+; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v32, v59, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v5
+; SI-NEXT: v_or_b32_e32 v4, v4, v14
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v4
+; SI-NEXT: v_and_b32_e32 v4, 0xff, v12
+; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; SI-NEXT: v_or_b32_e32 v26, v6, v4
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: ; implicit-def: $vgpr14
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
; SI-NEXT: v_or_b32_e32 v11, v13, v11
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
@@ -91586,25 +91580,27 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v13, v11
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v11, v11, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v21, v14, v13
+; SI-NEXT: v_or_b32_e32 v13, v15, v13
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
@@ -91618,7 +91614,7 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v27, v13, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_or_b32_e32 v11, v11, v38
@@ -91628,7 +91624,7 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v50, v13, v11
+; SI-NEXT: v_or_b32_e32 v49, v13, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -91636,7 +91632,7 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: v_or_b32_e32 v52, v13, v11
+; SI-NEXT: v_or_b32_e32 v51, v13, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
@@ -91649,98 +91645,89 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v11, v51
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v11
+; SI-NEXT: v_or_b32_e32 v11, v11, v52
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v41, v48, v11
+; SI-NEXT: v_or_b32_e32 v40, v48, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v44, v13, v11
+; SI-NEXT: v_or_b32_e32 v41, v13, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v45, v49, v11
+; SI-NEXT: v_or_b32_e32 v45, v50, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
-; SI-NEXT: ; implicit-def: $vgpr49
+; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: v_or_b32_e32 v11, v11, v42
+; SI-NEXT: v_or_b32_e32 v11, v11, v44
; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v57, v54, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: ; implicit-def: $vgpr54
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_or_b32_e32 v47, v55, v11
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v35
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v58, v13, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v25
-; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v17
+; SI-NEXT: ; implicit-def: $vgpr35
+; SI-NEXT: ; implicit-def: $vgpr17
+; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v61, v40, v11
+; SI-NEXT: v_or_b32_e32 v60, v42, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
-; SI-NEXT: v_or_b32_e32 v11, v11, v60
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v11, v11, v62
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr37
-; SI-NEXT: ; implicit-def: $vgpr40
-; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr42
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v31, v47, v11
+; SI-NEXT: v_or_b32_e32 v63, v56, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; SI-NEXT: v_or_b32_e32 v32, v13, v11
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v20
-; SI-NEXT: v_or_b32_e32 v13, v13, v22
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xff, v17
-; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; SI-NEXT: v_or_b32_e32 v13, v3, v13
-; SI-NEXT: v_and_b32_e32 v3, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_or_b32_e32 v33, v0, v3
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v30, v26, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v7
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v0
+; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: v_or_b32_e32 v13, v1, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v7
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v30, v0, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
+; SI-NEXT: v_or_b32_e32 v0, v0, v3
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v43
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v24, v16, v0
+; SI-NEXT: v_or_b32_e32 v24, v28, v0
; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v63
-; SI-NEXT: v_or_b32_e32 v28, v3, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v31
+; SI-NEXT: v_or_b32_e32 v16, v1, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v57
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v15, v1, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v0
-; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
+; SI-NEXT: v_or_b32_e32 v20, v9, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v25
+; SI-NEXT: v_or_b32_e32 v0, v0, v19
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; SI-NEXT: v_and_b32_e32 v0, 0xff, v18
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v19, v8, v0
+; SI-NEXT: v_or_b32_e32 v34, v21, v0
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
@@ -91780,244 +91767,226 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v18
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: v_or_b32_e32 v11, v59, v11
; SI-NEXT: ; kill: killed $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr39
-; SI-NEXT: ; implicit-def: $vgpr18
-; SI-NEXT: ; implicit-def: $vgpr20
-; SI-NEXT: ; implicit-def: $vgpr17
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr0
-; SI-NEXT: ; implicit-def: $vgpr5
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; kill: killed $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr7
+; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr57
+; SI-NEXT: ; implicit-def: $vgpr25
+; SI-NEXT: ; implicit-def: $vgpr18
+; SI-NEXT: ; kill: killed $vgpr0
; SI-NEXT: ; implicit-def: $vgpr56
-; SI-NEXT: ; implicit-def: $vgpr12
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; kill: killed $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr22
+; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr26
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: ; implicit-def: $vgpr16
-; SI-NEXT: ; implicit-def: $vgpr1
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr8
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: ; implicit-def: $vgpr19
+; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: .LBB110_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB110_4
; SI-NEXT: ; %bb.3: ; %cmp.true
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
-; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v7
+; SI-NEXT: s_movk_i32 s6, 0x300
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v5
+; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v12
+; SI-NEXT: v_or_b32_e32 v1, v14, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v2, v6, v2
+; SI-NEXT: v_or_b32_e32 v1, v2, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v39
+; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v17
+; SI-NEXT: v_or_b32_e32 v2, v5, v2
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
-; SI-NEXT: v_or_b32_e32 v2, v2, v11
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v2
-; SI-NEXT: v_or_b32_e32 v4, v8, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v4, v59, v4
; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v63
-; SI-NEXT: v_or_b32_e32 v4, v8, v4
-; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v56
-; SI-NEXT: s_movk_i32 s6, 0x300
-; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v1, v1, v8
-; SI-NEXT: v_or_b32_e32 v1, v1, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v4, v62, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; SI-NEXT: v_or_b32_e32 v6, v16, v6
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_or_b32_e32 v3, v3, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v43
+; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
+; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
+; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_or_b32_e32 v8, v28, v8
+; SI-NEXT: v_or_b32_e32 v3, v8, v3
+; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v25
+; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
+; SI-NEXT: v_or_b32_e32 v11, v19, v11
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x300, v11
+; SI-NEXT: v_or_b32_e32 v13, v21, v13
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
+; SI-NEXT: v_or_b32_e32 v11, v13, v11
+; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; SI-NEXT: v_or_b32_e32 v13, v13, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x3000000, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v13
+; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v57
+; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; SI-NEXT: v_or_b32_e32 v9, v9, v13
+; SI-NEXT: v_or_b32_e32 v9, v9, v11
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x3000000, v9
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v3
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
+; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v2
+; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v1
+; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v1
+; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
+; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v3
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
-; SI-NEXT: v_or_b32_e32 v0, v0, v6
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v5, v26, v5
-; SI-NEXT: v_or_b32_e32 v0, v5, v0
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
-; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
-; SI-NEXT: v_or_b32_e32 v5, v22, v5
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v3, v3, v6
-; SI-NEXT: v_or_b32_e32 v3, v3, v5
-; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v39
+; SI-NEXT: v_or_b32_e32 v5, v56, v5
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v35
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v25
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_or_b32_e32 v5, v6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v37
-; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; SI-NEXT: v_or_b32_e32 v6, v60, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
-; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
-; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v5
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v4
+; SI-NEXT: v_and_b32_e32 v63, 0xffff0000, v4
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; SI-NEXT: v_or_b32_e32 v7, v47, v7
-; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
-; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
-; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v6
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v6
-; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v4
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1
-; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v2
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; SI-NEXT: v_or_b32_e32 v7, v55, v7
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v4
+; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v9
+; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v10
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v10
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; SI-NEXT: v_or_b32_e32 v9, v54, v9
; SI-NEXT: s_waitcnt vmcnt(8)
-; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_or_b32_e32 v11, v48, v11
-; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
-; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; SI-NEXT: v_or_b32_e32 v6, v42, v6
+; SI-NEXT: v_or_b32_e32 v5, v6, v5
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x3000000, v5
+; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v5
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_or_b32_e32 v13, v14, v13
+; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; SI-NEXT: v_or_b32_e32 v6, v44, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
+; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v6, v7, v6
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x3000000, v6
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
+; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v6
+; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v6
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_or_b32_e32 v13, v14, v13
-; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_or_b32_e32 v8, v40, v8
+; SI-NEXT: v_or_b32_e32 v8, v50, v8
; SI-NEXT: v_or_b32_e32 v7, v8, v7
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
-; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v7
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
-; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v7
+; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x3000000, v7
+; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v7
+; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v7
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
-; SI-NEXT: v_or_b32_e32 v8, v42, v8
+; SI-NEXT: v_or_b32_e32 v8, v52, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
-; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v8
-; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v8
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_or_b32_e32 v10, v49, v10
-; SI-NEXT: v_or_b32_e32 v9, v10, v9
-; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
-; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v9
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v9
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
-; SI-NEXT: v_or_b32_e32 v10, v51, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; SI-NEXT: v_or_b32_e32 v10, v11, v10
+; SI-NEXT: v_or_b32_e32 v8, v11, v8
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
-; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v10
-; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v10
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v8
+; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v8
+; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v8
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
@@ -92032,10 +92001,10 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v36, v12
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v11
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v11
-; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
+; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
+; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
@@ -92044,8 +92013,8 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
-; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v12
+; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
@@ -92061,11 +92030,11 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v13
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v13
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v13
-; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
+; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
@@ -92082,16 +92051,11 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
-; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v14
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v3
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -92103,60 +92067,73 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_or_b32_e32 v15, v16, v15
-; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
-; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; SI-NEXT: .LBB110_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
-; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v23
-; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v29
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v52
-; SI-NEXT: v_mul_f32_e32 v6, 1.0, v55
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v44
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v51
+; SI-NEXT: v_mul_f32_e32 v6, 1.0, v54
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v41
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v46
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v58
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v62
-; SI-NEXT: v_mul_f32_e32 v12, 1.0, v14
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v61
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v12, 1.0, v22
+; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_mul_f32_e32 v16, 1.0, v35
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v16
+; SI-NEXT: v_mul_f32_e32 v16, 1.0, v33
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
-; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
-; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
+; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v53
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
-; SI-NEXT: v_mul_f32_e32 v5, 1.0, v41
+; SI-NEXT: v_mul_f32_e32 v5, 1.0, v40
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
-; SI-NEXT: v_mul_f32_e32 v7, 1.0, v57
+; SI-NEXT: v_mul_f32_e32 v7, 1.0, v47
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; SI-NEXT: v_mul_f32_e32 v8, 1.0, v61
+; SI-NEXT: v_mul_f32_e32 v8, 1.0, v60
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
+; SI-NEXT: v_mul_f32_e32 v9, 1.0, v63
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -92173,30 +92150,24 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
-; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
-; SI-NEXT: v_mul_f32_e32 v10, 1.0, v11
+; SI-NEXT: v_mul_f32_e32 v10, 1.0, v32
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v32
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
-; SI-NEXT: v_mul_f32_e32 v11, 1.0, v13
+; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v30
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; SI-NEXT: v_mul_f32_e32 v13, 1.0, v33
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
-; SI-NEXT: v_mul_f32_e32 v14, 1.0, v15
+; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v28
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
-; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
+; SI-NEXT: v_mul_f32_e32 v15, 1.0, v34
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
; SI-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
index 8f98706064595c..8c1a8729858968 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
@@ -4042,7 +4042,6 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v45, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v44, v1
; SI-NEXT: v_or_b32_e32 v2, v43, v2
; SI-NEXT: v_or_b32_e32 v3, v42, v3
@@ -4057,13 +4056,14 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v47, v12
; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
@@ -4078,16 +4078,15 @@ define <18 x i32> @bitcast_v36i16_to_v18i32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -11746,7 +11745,6 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v45, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v44, v1
; SI-NEXT: v_or_b32_e32 v2, v43, v2
; SI-NEXT: v_or_b32_e32 v3, v42, v3
@@ -11761,13 +11759,14 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v47, v12
; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
@@ -11782,16 +11781,15 @@ define <18 x float> @bitcast_v36i16_to_v18f32(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -18255,7 +18253,6 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v45, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v44, v1
; SI-NEXT: v_or_b32_e32 v2, v43, v2
; SI-NEXT: v_or_b32_e32 v3, v42, v3
@@ -18270,13 +18267,14 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v47, v12
; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
@@ -18291,16 +18289,15 @@ define <9 x i64> @bitcast_v36i16_to_v9i64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -23763,7 +23760,6 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v45, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v44, v1
; SI-NEXT: v_or_b32_e32 v2, v43, v2
; SI-NEXT: v_or_b32_e32 v3, v42, v3
@@ -23778,13 +23774,14 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v47, v12
; SI-NEXT: v_or_b32_e32 v13, v46, v13
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v34
@@ -23799,16 +23796,15 @@ define <9 x double> @bitcast_v36i16_to_v9f64(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -28120,92 +28116,91 @@ define <36 x half> @bitcast_v36i16_to_v36f16(<36 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v46, v0
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v2, v47, v2
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v4, v56, v4
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v53, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v57, v0
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v8, v61, v8
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v2, v58, v2
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v48, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v4, v60, v4
-; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v2
; SI-NEXT: v_alignbit_b32 v0, v48, v45, 16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v12, v51, v12
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v6, v62, v6
-; SI-NEXT: v_add_i32_e32 v37, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v37, vcc, 0x30000, v4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v39, v42, 16
; SI-NEXT: v_or_b32_e32 v16, v40, v16
; SI-NEXT: v_or_b32_e32 v14, v54, v14
-; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v8, v50, v8
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x30000, v6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v37, v53, 16
; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v10, v52, v10
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x30000, v8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v34, v49, 16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v12, v55, v12
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v10
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v31, v38, 16
; SI-NEXT: v_or_b32_e32 v16, v43, v16
; SI-NEXT: v_or_b32_e32 v14, v41, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v12
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v28, v36, 16
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v25, v32, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
index 1a4c5e9bf06a3c..a2d89fb22315e0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
@@ -4379,7 +4379,6 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v59, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_or_b32_e32 v2, v57, v2
; SI-NEXT: v_or_b32_e32 v3, v56, v3
@@ -4392,15 +4391,16 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
@@ -4431,15 +4431,14 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -12869,7 +12868,6 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v59, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_or_b32_e32 v2, v57, v2
; SI-NEXT: v_or_b32_e32 v3, v56, v3
@@ -12882,15 +12880,16 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
@@ -12921,15 +12920,14 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -20086,7 +20084,6 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v59, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_or_b32_e32 v2, v57, v2
; SI-NEXT: v_or_b32_e32 v3, v56, v3
@@ -20099,15 +20096,16 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
@@ -20138,15 +20136,14 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -26231,7 +26228,6 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v59, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v58, v1
; SI-NEXT: v_or_b32_e32 v2, v57, v2
; SI-NEXT: v_or_b32_e32 v3, v56, v3
@@ -26244,15 +26240,16 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v38
@@ -26283,15 +26280,14 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -31122,19 +31118,18 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v18, v52, v18
; SI-NEXT: v_or_b32_e32 v16, v32, v16
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v16, v50, v16
; SI-NEXT: v_or_b32_e32 v14, v58, v14
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
@@ -31143,8 +31138,8 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v12, v47, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
@@ -31159,50 +31154,50 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v2, v61, v2
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v59, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v4, v62, v4
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v56, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v6, v54, v6
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v43, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v0, v63, v0
; SI-NEXT: v_or_b32_e32 v10, v57, v10
; SI-NEXT: v_or_b32_e32 v8, v41, v8
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v2, v40, v2
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v0
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v53, vcc, 0x30000, v0
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v4, v42, v4
-; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v51, vcc, 0x30000, v2
; SI-NEXT: v_alignbit_b32 v0, v53, v59, 16
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v6, v45, v6
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v51, v56, 16
; SI-NEXT: v_or_b32_e32 v8, v46, v8
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v49, v43, 16
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x30000, v8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_alignbit_b32 v0, v38, v55, 16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 009da205edba14..69727ac65ee4b7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -2315,9 +2315,8 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
@@ -2327,7 +2326,7 @@ define i64 @bitcast_v4bf16_to_i64(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
@@ -5740,9 +5739,8 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
@@ -5752,7 +5750,7 @@ define double @bitcast_v4bf16_to_f64(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
@@ -8818,9 +8816,8 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
@@ -8830,7 +8827,7 @@ define <2 x i32> @bitcast_v4bf16_to_v2i32(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
@@ -11538,9 +11535,8 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
@@ -11550,7 +11546,7 @@ define <2 x float> @bitcast_v4bf16_to_v2f32(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
@@ -13883,9 +13879,8 @@ define <4 x i16> @bitcast_v4bf16_to_v4i16(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
@@ -13893,7 +13888,7 @@ define <4 x i16> @bitcast_v4bf16_to_v4i16(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -15805,9 +15800,8 @@ define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
@@ -15815,7 +15809,7 @@ define <4 x half> @bitcast_v4bf16_to_v4f16(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -17511,9 +17505,8 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
@@ -17522,7 +17515,7 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_bfe_u32 v3, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0
-; VI-NEXT: v_add_u32_e32 v3, vcc, s6, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v8
@@ -17530,7 +17523,7 @@ define <8 x i8> @bitcast_v4bf16_to_v8i8(<4 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
index 35a8e55d252def..048bfa8132a1d7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
@@ -4679,7 +4679,6 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v33, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v63, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v62, v3
@@ -4692,15 +4691,16 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v47, v10
; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
@@ -4733,16 +4733,15 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
@@ -4750,7 +4749,7 @@ define <22 x i32> @bitcast_v44i16_to_v22i32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -13931,7 +13930,6 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v33, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v63, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v62, v3
@@ -13944,15 +13942,16 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v47, v10
; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
@@ -13985,16 +13984,15 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
@@ -14002,7 +14000,7 @@ define <22 x float> @bitcast_v44i16_to_v22f32(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -21866,7 +21864,6 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v33, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v63, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v62, v3
@@ -21879,15 +21876,16 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v47, v10
; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
@@ -21920,16 +21918,15 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
@@ -21937,7 +21934,7 @@ define <11 x i64> @bitcast_v44i16_to_v11i64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -28673,7 +28670,6 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v33, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v63, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v62, v3
@@ -28686,15 +28682,16 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v47, v10
; SI-NEXT: v_or_b32_e32 v11, v46, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v48
@@ -28727,16 +28724,15 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
@@ -28744,7 +28740,7 @@ define <11 x double> @bitcast_v44i16_to_v11f64(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
@@ -34129,76 +34125,75 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v20, v60, v20
; SI-NEXT: v_or_b32_e32 v18, v58, v18
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v18, v57, v18
; SI-NEXT: v_or_b32_e32 v16, v55, v16
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v16, v63, v16
; SI-NEXT: v_or_b32_e32 v14, v50, v14
-; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v30, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v14, v45, v14
; SI-NEXT: v_or_b32_e32 v12, v36, v12
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v12, v41, v12
; SI-NEXT: v_or_b32_e32 v10, v43, v10
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v10, v53, v10
; SI-NEXT: v_or_b32_e32 v8, v61, v8
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v8, v39, v8
; SI-NEXT: v_or_b32_e32 v6, v59, v6
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v6, v32, v6
; SI-NEXT: v_or_b32_e32 v4, v56, v4
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v52, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v4, v62, v4
; SI-NEXT: v_or_b32_e32 v2, v47, v2
-; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v54, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
@@ -34215,8 +34210,8 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v40, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -34224,7 +34219,7 @@ define <44 x half> @bitcast_v44i16_to_v44f16(<44 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v42, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
index ceb81e46a53789..ddee91e20f7dd0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
@@ -4992,7 +4992,6 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
@@ -5005,15 +5004,16 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
@@ -5046,16 +5046,15 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -5065,19 +5064,19 @@ define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -14975,7 +14974,6 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
@@ -14988,15 +14986,16 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
@@ -15029,16 +15028,15 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -15048,19 +15046,19 @@ define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -23598,7 +23596,6 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
@@ -23611,15 +23608,16 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
@@ -23652,16 +23650,15 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -23671,19 +23668,19 @@ define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -31038,7 +31035,6 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
@@ -31051,15 +31047,16 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
@@ -31092,16 +31089,15 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -31111,19 +31107,19 @@ define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
@@ -37014,52 +37010,51 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v22, v26, v22
; SI-NEXT: v_or_b32_e32 v20, v42, v20
; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v20, v25, v20
; SI-NEXT: v_or_b32_e32 v18, v48, v18
-; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v31, vcc, 0x30000, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v18, v47, v18
; SI-NEXT: v_or_b32_e32 v16, v63, v16
-; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v16, v54, v16
; SI-NEXT: v_or_b32_e32 v14, v59, v14
-; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v14, v57, v14
; SI-NEXT: v_or_b32_e32 v12, v45, v12
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v12, v62, v12
; SI-NEXT: v_or_b32_e32 v10, v40, v10
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
@@ -37084,40 +37079,40 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v52, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v55
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v41, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v41
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v43, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v43
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v44, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -37125,7 +37120,7 @@ define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v46, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v46, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
index 8d46f9af9325a4..54180d9a672079 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
@@ -5339,7 +5339,6 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v36, v1
; SI-NEXT: v_or_b32_e32 v2, v59, v2
; SI-NEXT: v_or_b32_e32 v3, v35, v3
@@ -5351,89 +5350,88 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v32, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -16096,7 +16094,6 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v36, v1
; SI-NEXT: v_or_b32_e32 v2, v59, v2
; SI-NEXT: v_or_b32_e32 v3, v35, v3
@@ -16108,89 +16105,88 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v32, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -25462,7 +25458,6 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v36, v1
; SI-NEXT: v_or_b32_e32 v2, v59, v2
; SI-NEXT: v_or_b32_e32 v3, v35, v3
@@ -25474,89 +25469,88 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v32, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -33592,7 +33586,6 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v60, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v36, v1
; SI-NEXT: v_or_b32_e32 v2, v59, v2
; SI-NEXT: v_or_b32_e32 v3, v35, v3
@@ -33604,89 +33597,88 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v32, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
@@ -39862,18 +39854,18 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v49
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v48
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v38
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v36
+; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v36
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v34
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v31
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v30
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v29
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v29
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v47
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v45
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v43
-; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v55
+; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v42
+; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
; SI-NEXT: ; kill: killed $vgpr26
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
@@ -39960,7 +39952,7 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_alignbit_b32 v1, v55, v60, 16
+; SI-NEXT: v_alignbit_b32 v1, v55, v44, 16
; SI-NEXT: v_or_b32_e32 v0, v0, v58
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -39972,7 +39964,7 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v0, v0, v60
+; SI-NEXT: v_or_b32_e32 v0, v0, v44
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
@@ -39996,7 +39988,7 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v44
+; SI-NEXT: v_or_b32_e32 v0, v0, v60
; SI-NEXT: v_mov_b32_e32 v32, v26
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
@@ -40023,7 +40015,7 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr60
+; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_or_b32_e32 v52, v1, v3
; SI-NEXT: v_alignbit_b32 v1, v52, v56, 16
@@ -40052,7 +40044,7 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
; SI-NEXT: ; kill: killed $vgpr27
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_or_b32_e32 v34, v1, v48
+; SI-NEXT: v_or_b32_e32 v34, v1, v31
; SI-NEXT: ; kill: killed $vgpr27
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: v_alignbit_b32 v1, v34, v28, 16
@@ -40063,10 +40055,10 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
; SI-NEXT: ; kill: killed $vgpr27
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_or_b32_e32 v3, v1, v31
+; SI-NEXT: v_or_b32_e32 v3, v1, v48
; SI-NEXT: ; kill: killed $vgpr27
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: v_alignbit_b32 v1, v3, v44, 16
+; SI-NEXT: v_alignbit_b32 v1, v3, v60, 16
; SI-NEXT: ; kill: killed $vgpr27
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
@@ -40086,66 +40078,65 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr27
-; SI-NEXT: ; implicit-def: $vgpr48
-; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr31
-; SI-NEXT: ; implicit-def: $vgpr44
+; SI-NEXT: ; implicit-def: $vgpr28
+; SI-NEXT: ; implicit-def: $vgpr48
+; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v24, v44, v24
+; SI-NEXT: v_or_b32_e32 v24, v60, v24
; SI-NEXT: v_add_i32_e32 v32, vcc, 0x30000, v24
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v24, v31, v24
+; SI-NEXT: v_or_b32_e32 v24, v48, v24
; SI-NEXT: v_or_b32_e32 v22, v28, v22
; SI-NEXT: s_waitcnt expcnt(5)
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v22, v48, v22
+; SI-NEXT: v_or_b32_e32 v22, v31, v22
; SI-NEXT: v_or_b32_e32 v20, v27, v20
-; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v22
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v34, vcc, 0x30000, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v20, v51, v20
; SI-NEXT: v_or_b32_e32 v18, v62, v18
-; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v36, vcc, 0x30000, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v18, v30, v18
; SI-NEXT: v_or_b32_e32 v16, v61, v16
-; SI-NEXT: v_add_i32_e32 v38, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v16, v29, v16
; SI-NEXT: v_or_b32_e32 v14, v56, v14
-; SI-NEXT: v_add_i32_e32 v49, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v12, v60, v12
+; SI-NEXT: v_or_b32_e32 v12, v44, v12
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v63, v10
@@ -40165,67 +40156,67 @@ define <52 x half> @bitcast_v52i16_to_v52f16(<52 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v52, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v55
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v42
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v43, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v43, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v43
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v45
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v47, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v47
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v57, vcc, 0x30000, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v57
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v59, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v59, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
index d259d3d97aca12..d3b2949c2a1907 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
@@ -5427,17 +5427,17 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
@@ -5498,17 +5498,17 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v33
+; SI-NEXT: v_or_b32_e32 v2, v2, v38
+; SI-NEXT: v_or_b32_e32 v3, v3, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v37
+; SI-NEXT: v_or_b32_e32 v5, v5, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v60
+; SI-NEXT: v_or_b32_e32 v8, v8, v35
+; SI-NEXT: v_or_b32_e32 v9, v9, v63
+; SI-NEXT: v_or_b32_e32 v10, v10, v34
+; SI-NEXT: v_or_b32_e32 v11, v11, v62
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -5523,17 +5523,17 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -5691,28 +5691,28 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
+; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v2, v38, v2
+; SI-NEXT: v_or_b32_e32 v3, v61, v3
+; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v5, v32, v5
+; SI-NEXT: v_or_b32_e32 v6, v36, v6
+; SI-NEXT: v_or_b32_e32 v7, v60, v7
+; SI-NEXT: v_or_b32_e32 v8, v35, v8
+; SI-NEXT: v_or_b32_e32 v9, v63, v9
+; SI-NEXT: v_or_b32_e32 v10, v34, v10
+; SI-NEXT: v_or_b32_e32 v11, v62, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
@@ -5745,16 +5745,15 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -5768,37 +5767,37 @@ define <28 x i32> @bitcast_v56i16_to_v28i32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -16980,17 +16979,17 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
@@ -17051,17 +17050,17 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v33
+; SI-NEXT: v_or_b32_e32 v2, v2, v38
+; SI-NEXT: v_or_b32_e32 v3, v3, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v37
+; SI-NEXT: v_or_b32_e32 v5, v5, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v60
+; SI-NEXT: v_or_b32_e32 v8, v8, v35
+; SI-NEXT: v_or_b32_e32 v9, v9, v63
+; SI-NEXT: v_or_b32_e32 v10, v10, v34
+; SI-NEXT: v_or_b32_e32 v11, v11, v62
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -17076,17 +17075,17 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -17244,28 +17243,28 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
+; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v2, v38, v2
+; SI-NEXT: v_or_b32_e32 v3, v61, v3
+; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v5, v32, v5
+; SI-NEXT: v_or_b32_e32 v6, v36, v6
+; SI-NEXT: v_or_b32_e32 v7, v60, v7
+; SI-NEXT: v_or_b32_e32 v8, v35, v8
+; SI-NEXT: v_or_b32_e32 v9, v63, v9
+; SI-NEXT: v_or_b32_e32 v10, v34, v10
+; SI-NEXT: v_or_b32_e32 v11, v62, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
@@ -17298,16 +17297,15 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -17321,37 +17319,37 @@ define <28 x float> @bitcast_v56i16_to_v28f32(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -27113,17 +27111,17 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
@@ -27184,17 +27182,17 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v33
+; SI-NEXT: v_or_b32_e32 v2, v2, v38
+; SI-NEXT: v_or_b32_e32 v3, v3, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v37
+; SI-NEXT: v_or_b32_e32 v5, v5, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v60
+; SI-NEXT: v_or_b32_e32 v8, v8, v35
+; SI-NEXT: v_or_b32_e32 v9, v9, v63
+; SI-NEXT: v_or_b32_e32 v10, v10, v34
+; SI-NEXT: v_or_b32_e32 v11, v11, v62
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -27209,17 +27207,17 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -27377,28 +27375,28 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
+; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v2, v38, v2
+; SI-NEXT: v_or_b32_e32 v3, v61, v3
+; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v5, v32, v5
+; SI-NEXT: v_or_b32_e32 v6, v36, v6
+; SI-NEXT: v_or_b32_e32 v7, v60, v7
+; SI-NEXT: v_or_b32_e32 v8, v35, v8
+; SI-NEXT: v_or_b32_e32 v9, v63, v9
+; SI-NEXT: v_or_b32_e32 v10, v34, v10
+; SI-NEXT: v_or_b32_e32 v11, v62, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
@@ -27431,16 +27429,15 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -27454,37 +27451,37 @@ define <14 x i64> @bitcast_v56i16_to_v14i64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -35957,17 +35954,17 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v59
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v27
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v26
-; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v25
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v24
-; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
-; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v22
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v20
-; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
-; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v18
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v16
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v26
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v24
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v22
+; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v21
+; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v20
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v19
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v18
+; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v17
+; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
@@ -36028,17 +36025,17 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v40
; SI-NEXT: v_or_b32_e32 v0, v0, v39
-; SI-NEXT: v_or_b32_e32 v1, v1, v38
-; SI-NEXT: v_or_b32_e32 v2, v2, v62
-; SI-NEXT: v_or_b32_e32 v3, v3, v37
-; SI-NEXT: v_or_b32_e32 v4, v4, v32
-; SI-NEXT: v_or_b32_e32 v5, v5, v36
-; SI-NEXT: v_or_b32_e32 v6, v6, v61
-; SI-NEXT: v_or_b32_e32 v7, v7, v35
-; SI-NEXT: v_or_b32_e32 v8, v8, v60
-; SI-NEXT: v_or_b32_e32 v9, v9, v34
-; SI-NEXT: v_or_b32_e32 v10, v10, v63
-; SI-NEXT: v_or_b32_e32 v11, v11, v33
+; SI-NEXT: v_or_b32_e32 v1, v1, v33
+; SI-NEXT: v_or_b32_e32 v2, v2, v38
+; SI-NEXT: v_or_b32_e32 v3, v3, v61
+; SI-NEXT: v_or_b32_e32 v4, v4, v37
+; SI-NEXT: v_or_b32_e32 v5, v5, v32
+; SI-NEXT: v_or_b32_e32 v6, v6, v36
+; SI-NEXT: v_or_b32_e32 v7, v7, v60
+; SI-NEXT: v_or_b32_e32 v8, v8, v35
+; SI-NEXT: v_or_b32_e32 v9, v9, v63
+; SI-NEXT: v_or_b32_e32 v10, v10, v34
+; SI-NEXT: v_or_b32_e32 v11, v11, v62
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr57
@@ -36053,17 +36050,17 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr39
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr38
-; SI-NEXT: ; implicit-def: $vgpr62
+; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr36
-; SI-NEXT: ; implicit-def: $vgpr61
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr60
-; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr63
-; SI-NEXT: ; implicit-def: $vgpr33
+; SI-NEXT: ; implicit-def: $vgpr34
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -36221,28 +36218,28 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v39, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v1, v38, v1
-; SI-NEXT: v_or_b32_e32 v2, v62, v2
-; SI-NEXT: v_or_b32_e32 v3, v37, v3
-; SI-NEXT: v_or_b32_e32 v4, v32, v4
-; SI-NEXT: v_or_b32_e32 v5, v36, v5
-; SI-NEXT: v_or_b32_e32 v6, v61, v6
-; SI-NEXT: v_or_b32_e32 v7, v35, v7
-; SI-NEXT: v_or_b32_e32 v8, v60, v8
-; SI-NEXT: v_or_b32_e32 v9, v34, v9
-; SI-NEXT: v_or_b32_e32 v10, v63, v10
-; SI-NEXT: v_or_b32_e32 v11, v33, v11
+; SI-NEXT: v_or_b32_e32 v1, v33, v1
+; SI-NEXT: v_or_b32_e32 v2, v38, v2
+; SI-NEXT: v_or_b32_e32 v3, v61, v3
+; SI-NEXT: v_or_b32_e32 v4, v37, v4
+; SI-NEXT: v_or_b32_e32 v5, v32, v5
+; SI-NEXT: v_or_b32_e32 v6, v36, v6
+; SI-NEXT: v_or_b32_e32 v7, v60, v7
+; SI-NEXT: v_or_b32_e32 v8, v35, v8
+; SI-NEXT: v_or_b32_e32 v9, v63, v9
+; SI-NEXT: v_or_b32_e32 v10, v34, v10
+; SI-NEXT: v_or_b32_e32 v11, v62, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v54
@@ -36275,16 +36272,15 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -36298,37 +36294,37 @@ define <14 x double> @bitcast_v56i16_to_v14f64(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
@@ -42900,42 +42896,43 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
+; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v51
-; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v5
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v49
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v7
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v50
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v9
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v48
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v11
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v60
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v13
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v58
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v57
-; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15
-; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v47
+; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v17
+; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
@@ -42988,25 +42985,26 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v26
+; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v26
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v25
-; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v24
-; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
+; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v22
-; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v21
+; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
-; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v14
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v8
-; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
-; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v52
+; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v50
+; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v48
; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v38
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v37
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v36
@@ -43015,23 +43013,21 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v34
-; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v33
-; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v47
+; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v34
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v45
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v44
-; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v42
+; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v41
-; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v42
-; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v40
-; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v55
+; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v40
+; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v55
; SI-NEXT: ; kill: killed $vgpr28
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr60
@@ -43055,67 +43051,46 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v54
-; SI-NEXT: s_waitcnt expcnt(5)
+; SI-NEXT: s_waitcnt expcnt(4)
; SI-NEXT: v_or_b32_e32 v60, v1, v28
; SI-NEXT: v_mov_b32_e32 v28, v39
-; SI-NEXT: v_mov_b32_e32 v39, v43
-; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; SI-NEXT: v_mov_b32_e32 v48, v63
+; SI-NEXT: v_mov_b32_e32 v63, v43
+; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v60, v43, 16
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_alignbit_b32 v1, v60, v39, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51
; SI-NEXT: v_or_b32_e32 v58, v1, v3
-; SI-NEXT: v_alignbit_b32 v1, v58, v39, 16
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_alignbit_b32 v1, v58, v43, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49
; SI-NEXT: v_or_b32_e32 v57, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v43
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v57, v63, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
+; SI-NEXT: v_or_b32_e32 v0, v0, v39
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v39
+; SI-NEXT: v_or_b32_e32 v0, v0, v43
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
-; SI-NEXT: v_mov_b32_e32 v39, v28
-; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr4
-; SI-NEXT: ; implicit-def: $vgpr43
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_alignbit_b32 v1, v57, v5, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_or_b32_e32 v47, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v5
+; SI-NEXT: v_or_b32_e32 v0, v0, v63
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
-; SI-NEXT: ; implicit-def: $vgpr5
-; SI-NEXT: ; implicit-def: $vgpr6
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_alignbit_b32 v1, v47, v7, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
-; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_or_b32_e32 v45, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v45, v46, 16
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_or_b32_e32 v0, v0, v7
+; SI-NEXT: v_or_b32_e32 v0, v0, v48
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
@@ -43151,18 +43126,20 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v63
+; SI-NEXT: v_or_b32_e32 v0, v0, v33
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v0, v0, v61
+; SI-NEXT: v_or_b32_e32 v0, v0, v35
+; SI-NEXT: v_mov_b32_e32 v39, v28
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
+; SI-NEXT: ; implicit-def: $vgpr2
+; SI-NEXT: ; implicit-def: $vgpr4
+; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
-; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
-; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr16
@@ -43171,10 +43148,28 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr26
+; SI-NEXT: ; implicit-def: $vgpr43
+; SI-NEXT: ; implicit-def: $vgpr63
+; SI-NEXT: s_waitcnt vmcnt(14)
+; SI-NEXT: v_or_b32_e32 v47, v1, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v47, v48, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; SI-NEXT: ; implicit-def: $vgpr9
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v45, v1, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: v_alignbit_b32 v1, v45, v46, 16
+; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
+; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr46
-; SI-NEXT: s_waitcnt vmcnt(12)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v44, v1, v3
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v44, v56, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -43183,11 +43178,15 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v42, v1, v3
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_alignbit_b32 v1, v42, v59, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
-; SI-NEXT: v_or_b32_e32 v40, v1, v35
+; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr59
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_or_b32_e32 v40, v1, v3
; SI-NEXT: v_alignbit_b32 v1, v40, v62, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -43202,7 +43201,7 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v52, v1, v41
+; SI-NEXT: v_or_b32_e32 v52, v1, v37
; SI-NEXT: v_alignbit_b32 v1, v52, v31, 16
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
@@ -43210,7 +43209,7 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_or_b32_e32 v50, v1, v37
+; SI-NEXT: v_or_b32_e32 v50, v1, v41
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: v_alignbit_b32 v1, v50, v32, 16
@@ -43221,10 +43220,10 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_or_b32_e32 v48, v1, v33
+; SI-NEXT: v_or_b32_e32 v5, v1, v38
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_alignbit_b32 v1, v48, v63, 16
+; SI-NEXT: v_alignbit_b32 v1, v5, v33, 16
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
@@ -43232,17 +43231,18 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_or_b32_e32 v3, v1, v38
+; SI-NEXT: v_or_b32_e32 v3, v1, v61
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
-; SI-NEXT: v_alignbit_b32 v1, v3, v61, 16
+; SI-NEXT: v_alignbit_b32 v1, v3, v35, 16
; SI-NEXT: ; kill: killed $vgpr29
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v28, v3
+; SI-NEXT: v_mov_b32_e32 v48, v5
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr15
+; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr21
@@ -43250,70 +43250,67 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; kill: killed $vgpr29
-; SI-NEXT: ; implicit-def: $vgpr59
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: ; implicit-def: $vgpr41
-; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr37
+; SI-NEXT: ; implicit-def: $vgpr31
+; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr32
-; SI-NEXT: ; implicit-def: $vgpr33
-; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr61
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v26, v61, v26
-; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v26
+; SI-NEXT: v_or_b32_e32 v26, v35, v26
+; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v26
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v27
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v26, v38, v26
-; SI-NEXT: v_or_b32_e32 v24, v63, v24
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v26
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
+; SI-NEXT: v_or_b32_e32 v26, v61, v26
+; SI-NEXT: v_or_b32_e32 v24, v33, v24
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v24
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; SI-NEXT: v_or_b32_e32 v24, v33, v24
+; SI-NEXT: v_or_b32_e32 v24, v38, v24
; SI-NEXT: v_or_b32_e32 v22, v32, v22
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v24
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v48, vcc, 0x30000, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: v_or_b32_e32 v22, v37, v22
+; SI-NEXT: v_or_b32_e32 v22, v41, v22
; SI-NEXT: v_or_b32_e32 v20, v31, v20
-; SI-NEXT: v_add_i32_e32 v50, vcc, s6, v22
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v50, vcc, 0x30000, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v20, v41, v20
+; SI-NEXT: v_or_b32_e32 v20, v37, v20
; SI-NEXT: v_or_b32_e32 v18, v30, v18
-; SI-NEXT: v_add_i32_e32 v52, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v52, vcc, 0x30000, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v18, v34, v18
; SI-NEXT: v_or_b32_e32 v16, v29, v16
-; SI-NEXT: v_add_i32_e32 v53, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v53, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -43321,20 +43318,15 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v16, v36, v16
; SI-NEXT: v_or_b32_e32 v14, v62, v14
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
+; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: v_or_b32_e32 v14, v35, v14
; SI-NEXT: v_or_b32_e32 v12, v59, v12
-; SI-NEXT: v_add_i32_e32 v40, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
-; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
-; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v56, v10
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
@@ -43342,70 +43334,76 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v8, v46, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; SI-NEXT: v_or_b32_e32 v6, v63, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_or_b32_e32 v4, v43, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_or_b32_e32 v2, v43, v2
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v14, v15, v14
+; SI-NEXT: v_add_i32_e32 v40, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
+; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
-; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v44, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
-; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v8
-; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v6, v8, v6
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
-; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v47, vcc, s6, v6
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v47, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v47
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v57, vcc, 0x30000, v4
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v57
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v57
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v58, vcc, 0x30000, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v58
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v60, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v60, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v60, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
@@ -43456,9 +43454,9 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v48, v26, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_alignbit_b32 v0, v28, v39, 16
+; SI-NEXT: v_alignbit_b32 v0, v28, v35, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v45
@@ -43487,7 +43485,6 @@ define <56 x half> @bitcast_v56i16_to_v56f16(<56 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v60
-; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v47
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v28
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
index 1be266983c3503..bf7a8696a9f7c5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
@@ -6101,7 +6101,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v48, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v39, v3
@@ -6113,66 +6112,66 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v36, v9
; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
@@ -6181,43 +6180,42 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -18548,7 +18546,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v48, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v39, v3
@@ -18560,66 +18557,66 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v36, v9
; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
@@ -18628,43 +18625,42 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -29506,7 +29502,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v48, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v39, v3
@@ -29518,66 +29513,66 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v36, v9
; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
@@ -29586,43 +29581,42 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -39104,7 +39098,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v0, v35, v0
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v48, v1
; SI-NEXT: v_or_b32_e32 v2, v32, v2
; SI-NEXT: v_or_b32_e32 v3, v39, v3
@@ -39116,66 +39109,66 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v9, v36, v9
; SI-NEXT: v_or_b32_e32 v10, v62, v10
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
-; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
-; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
-; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
-; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
-; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
+; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
+; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v11, v12, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v41
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
-; SI-NEXT: s_waitcnt vmcnt(8)
+; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; SI-NEXT: s_waitcnt vmcnt(7)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v55
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v54
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
-; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v53
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
-; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
-; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
-; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
@@ -39184,43 +39177,42 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; SI-NEXT: s_waitcnt vmcnt(9)
+; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21
+; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23
+; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v25, v24
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v25, vcc, 3, v25
; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25
; SI-NEXT: v_or_b32_e32 v25, v26, v25
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v26
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v26, v27, v26
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v26
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v27, vcc, 3, v27
; SI-NEXT: v_and_b32_e32 v27, 0xffff, v27
@@ -46306,7 +46298,7 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
-; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v24
+; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v26
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v48
; SI-NEXT: ; implicit-def: $vgpr48
@@ -46419,8 +46411,8 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v28
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v27
-; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v26
; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v25
+; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v24
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v22
; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v21
@@ -46451,11 +46443,10 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; SI-NEXT: s_waitcnt expcnt(2)
-; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v46
-; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v45
+; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v46
; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v44
+; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v45
+; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v44
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v42
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v41
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v55
@@ -46488,26 +46479,25 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v54, v53
-; SI-NEXT: v_mov_b32_e32 v53, v31
-; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v43
; SI-NEXT: v_or_b32_e32 v45, v1, v48
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v45, v31, 16
+; SI-NEXT: v_alignbit_b32 v1, v45, v53, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40
; SI-NEXT: v_or_b32_e32 v63, v1, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; SI-NEXT: v_or_b32_e32 v0, v0, v31
+; SI-NEXT: v_or_b32_e32 v0, v0, v53
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
+; SI-NEXT: v_mov_b32_e32 v53, v54
; SI-NEXT: ; implicit-def: $vgpr2
-; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_alignbit_b32 v1, v63, v3, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
@@ -46548,7 +46538,7 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
-; SI-NEXT: v_or_b32_e32 v0, v0, v53
+; SI-NEXT: v_or_b32_e32 v0, v0, v31
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
@@ -46580,11 +46570,11 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v24
-; SI-NEXT: v_or_b32_e32 v0, v0, v62
+; SI-NEXT: v_or_b32_e32 v0, v0, v38
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v26
-; SI-NEXT: v_or_b32_e32 v0, v0, v38
+; SI-NEXT: v_or_b32_e32 v0, v0, v62
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v28
@@ -46606,12 +46596,12 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_or_b32_e32 v57, v1, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; SI-NEXT: v_alignbit_b32 v1, v57, v53, 16
+; SI-NEXT: v_alignbit_b32 v1, v57, v31, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
-; SI-NEXT: v_mov_b32_e32 v53, v54
; SI-NEXT: ; implicit-def: $vgpr11
+; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v56, v1, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
@@ -46636,17 +46626,17 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
-; SI-NEXT: v_or_b32_e32 v42, v1, v47
+; SI-NEXT: v_or_b32_e32 v42, v1, v49
; SI-NEXT: v_alignbit_b32 v1, v42, v35, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
-; SI-NEXT: v_or_b32_e32 v41, v1, v49
+; SI-NEXT: v_or_b32_e32 v41, v1, v30
; SI-NEXT: v_alignbit_b32 v1, v41, v36, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
-; SI-NEXT: v_or_b32_e32 v55, v1, v30
+; SI-NEXT: v_or_b32_e32 v55, v1, v47
; SI-NEXT: v_alignbit_b32 v1, v55, v60, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
@@ -46668,7 +46658,7 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_alignbit_b32 v1, v1, v62, 16
+; SI-NEXT: v_alignbit_b32 v1, v1, v38, 16
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
@@ -46679,7 +46669,7 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v48, v1, v51
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
-; SI-NEXT: v_alignbit_b32 v1, v48, v38, 16
+; SI-NEXT: v_alignbit_b32 v1, v48, v62, 16
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
@@ -46708,18 +46698,18 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; kill: killed $vgpr30
; SI-NEXT: ; implicit-def: $vgpr34
-; SI-NEXT: ; implicit-def: $vgpr47
-; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr49
-; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr30
+; SI-NEXT: ; implicit-def: $vgpr36
+; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr50
-; SI-NEXT: ; implicit-def: $vgpr62
-; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr38
+; SI-NEXT: ; implicit-def: $vgpr51
+; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: .LBB56_2: ; %Flow
@@ -46731,11 +46721,10 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26
; SI-NEXT: v_or_b32_e32 v28, v39, v28
-; SI-NEXT: s_mov_b32 s6, 0x30000
-; SI-NEXT: v_or_b32_e32 v26, v38, v26
+; SI-NEXT: v_or_b32_e32 v26, v62, v26
; SI-NEXT: v_add_i32_e32 v39, vcc, 0x30000, v28
; SI-NEXT: v_add_i32_e32 v28, vcc, 3, v29
-; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v26
+; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v26
; SI-NEXT: v_add_i32_e32 v26, vcc, 3, v27
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
@@ -46743,12 +46732,12 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v26, v51, v26
-; SI-NEXT: v_or_b32_e32 v24, v62, v24
+; SI-NEXT: v_or_b32_e32 v24, v38, v24
; SI-NEXT: v_or_b32_e32 v22, v37, v22
-; SI-NEXT: v_add_i32_e32 v48, vcc, s6, v26
-; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v48, vcc, 0x30000, v26
+; SI-NEXT: v_add_i32_e32 v26, vcc, 0x30000, v24
; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v25
-; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v22
+; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
@@ -46756,32 +46745,32 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v22, v58, v22
; SI-NEXT: v_or_b32_e32 v20, v60, v20
; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_add_i32_e32 v54, vcc, s6, v22
-; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v20
+; SI-NEXT: v_add_i32_e32 v54, vcc, 0x30000, v22
+; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
-; SI-NEXT: v_or_b32_e32 v20, v30, v20
+; SI-NEXT: v_or_b32_e32 v20, v47, v20
; SI-NEXT: v_or_b32_e32 v18, v36, v18
-; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v20
-; SI-NEXT: v_add_i32_e32 v20, vcc, s6, v18
+; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v20
+; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; SI-NEXT: v_or_b32_e32 v18, v49, v18
+; SI-NEXT: v_or_b32_e32 v18, v30, v18
; SI-NEXT: v_or_b32_e32 v16, v35, v16
-; SI-NEXT: v_add_i32_e32 v41, vcc, s6, v18
-; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v16
+; SI-NEXT: v_add_i32_e32 v41, vcc, 0x30000, v18
+; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; SI-NEXT: v_or_b32_e32 v16, v47, v16
+; SI-NEXT: v_or_b32_e32 v16, v49, v16
; SI-NEXT: v_or_b32_e32 v14, v34, v14
-; SI-NEXT: v_add_i32_e32 v42, vcc, s6, v16
-; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
+; SI-NEXT: v_add_i32_e32 v42, vcc, 0x30000, v16
+; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
@@ -46805,76 +46794,76 @@ define <60 x half> @bitcast_v60i16_to_v60f16(<60 x i16> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v24, 0xffff, v24
; SI-NEXT: v_or_b32_e32 v24, v50, v24
; SI-NEXT: v_and_b32_e32 v28, 0xffff, v28
-; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24
+; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24
; SI-NEXT: v_or_b32_e32 v28, v52, v28
-; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v28
+; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
-; SI-NEXT: v_add_i32_e32 v44, vcc, s6, v14
-; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v12
+; SI-NEXT: v_add_i32_e32 v44, vcc, 0x30000, v14
+; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
-; SI-NEXT: v_add_i32_e32 v46, vcc, s6, v12
-; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v10
+; SI-NEXT: v_add_i32_e32 v46, vcc, 0x30000, v12
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
-; SI-NEXT: v_add_i32_e32 v56, vcc, s6, v10
-; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v56, vcc, 0x30000, v10
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v8, v9, v8
-; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v8
+; SI-NEXT: v_add_i32_e32 v57, vcc, 0x30000, v8
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v6, v8, v6
-; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v6, v7, v6
-; SI-NEXT: v_add_i32_e32 v59, vcc, s6, v6
+; SI-NEXT: v_add_i32_e32 v59, vcc, 0x30000, v6
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v4, v6, v4
-; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v4, v5, v4
-; SI-NEXT: v_add_i32_e32 v61, vcc, s6, v4
+; SI-NEXT: v_add_i32_e32 v61, vcc, 0x30000, v4
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v61
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v4, v2
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v63, vcc, s6, v2
+; SI-NEXT: v_add_i32_e32 v63, vcc, 0x30000, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v0, v2, v0
-; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v45, vcc, s6, v0
+; SI-NEXT: v_add_i32_e32 v45, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v45, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index c20a4ae3cc6043..ec71f29615daf5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -1013,9 +1013,8 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -1995,9 +1994,8 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
@@ -2007,7 +2005,7 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -2015,7 +2013,7 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
@@ -2025,7 +2023,7 @@ define <3 x i32> @bitcast_v6bf16_to_v3i32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -4348,9 +4346,8 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v3, v3, v4
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_or_b32_e32 v2, v3, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3000000, v2
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -5341,9 +5338,8 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v4, v2, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
@@ -5353,7 +5349,7 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -5361,7 +5357,7 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v4, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
@@ -5371,7 +5367,7 @@ define <3 x float> @bitcast_v6bf16_to_v3f32(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -7141,9 +7137,8 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_or_b32_e32 v5, v16, v5
; SI-NEXT: v_or_b32_e32 v3, v5, v3
-; SI-NEXT: s_mov_b32 s7, 0x3000000
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
@@ -7165,7 +7160,7 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v12, v1
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v3
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x3000000, v3
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x3000000, v0
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0
@@ -7976,9 +7971,8 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -7988,7 +7982,7 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
@@ -7996,7 +7990,7 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -8006,7 +8000,7 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
-; VI-NEXT: v_add_u32_e32 v1, vcc, s6, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
@@ -8014,7 +8008,7 @@ define <12 x i8> @bitcast_v6bf16_to_v12i8(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
-; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
@@ -8952,7 +8946,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v3
; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
@@ -8960,7 +8954,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -8972,7 +8966,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v1, v15
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v12, v3
+; SI-NEXT: v_or_b32_e32 v4, v13, v3
; SI-NEXT: v_or_b32_e32 v3, v1, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
@@ -8989,7 +8983,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v11, v0, v2
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
@@ -8998,7 +8992,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr9
@@ -9017,8 +9011,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
@@ -9028,7 +9021,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v12, v2
+; SI-NEXT: v_or_b32_e32 v2, v13, v2
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v8
@@ -9043,7 +9036,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
; SI-NEXT: v_alignbit_b32 v7, v3, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v11
; SI-NEXT: .LBB40_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -9051,7 +9044,7 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
@@ -10357,7 +10350,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v5
-; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v7
+; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v7
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v3
; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v1
; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
@@ -10365,7 +10358,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr3
-; SI-NEXT: ; implicit-def: $vgpr13
+; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -10377,7 +10370,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v1, v1, v15
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: v_or_b32_e32 v4, v12, v3
+; SI-NEXT: v_or_b32_e32 v4, v13, v3
; SI-NEXT: v_or_b32_e32 v3, v1, v4
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
@@ -10394,7 +10387,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v11, v0, v2
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr2
@@ -10403,7 +10396,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr15
-; SI-NEXT: ; implicit-def: $vgpr12
+; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr9
@@ -10422,8 +10415,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: s_mov_b32 s7, 0x3000000
-; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v6
@@ -10433,7 +10425,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_or_b32_e32 v2, v12, v2
+; SI-NEXT: v_or_b32_e32 v2, v13, v2
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x3000000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v8
@@ -10448,7 +10440,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
; SI-NEXT: v_alignbit_b32 v7, v3, v1, 16
-; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v11
; SI-NEXT: .LBB44_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -10456,7 +10448,7 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v7
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
@@ -11178,10 +11170,9 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) #0 {
; SI-NEXT: .LBB46_4: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v13
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; SI-NEXT: s_mov_b32 s6, 0x30000
; SI-NEXT: v_or_b32_e32 v1, v16, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v14
-; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v1
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
@@ -11834,9 +11825,8 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
@@ -11844,7 +11834,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -11852,7 +11842,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
@@ -11860,7 +11850,7 @@ define <6 x half> @bitcast_v6bf16_to_v6f16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -12943,9 +12933,8 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; VI-NEXT: v_bfe_u32 v4, v0, 16, 1
-; VI-NEXT: s_movk_i32 s6, 0x7fff
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
-; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; VI-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
@@ -12953,7 +12942,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
@@ -12961,7 +12950,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; VI-NEXT: v_bfe_u32 v5, v1, 16, 1
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; VI-NEXT: v_add_u32_e32 v5, vcc, s6, v5
+; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v1
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; VI-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
@@ -12969,7 +12958,7 @@ define <6 x i16> @bitcast_v6bf16_to_v6i16(<6 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; VI-NEXT: v_add_u32_e32 v6, vcc, s6, v6
+; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 04fe0d297b84db..14dfc9d8314e90 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -9526,11 +9526,10 @@ define <3 x bfloat> @v_fadd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_add_f32_e32 v3, v4, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -9762,10 +9761,9 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -9776,7 +9774,7 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -10078,10 +10076,9 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX8-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
@@ -10092,14 +10089,14 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_add_f32_e32 v2, v2, v6
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX8-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
@@ -10110,14 +10107,14 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_add_f32_e32 v1, v1, v5
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc
@@ -10128,7 +10125,7 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -13895,11 +13892,10 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_sub_f32_e32 v3, v4, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -14131,10 +14127,9 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -14145,7 +14140,7 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -14696,11 +14691,10 @@ define <3 x bfloat> @v_fmul_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -14932,10 +14926,9 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -14946,7 +14939,7 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -15248,10 +15241,9 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX8-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
@@ -15262,14 +15254,14 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_mul_f32_e32 v2, v2, v6
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX8-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
@@ -15280,14 +15272,14 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_mul_f32_e32 v1, v1, v5
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc
@@ -15298,7 +15290,7 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -19450,11 +19442,10 @@ define <3 x bfloat> @v_minnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_min_f32_e32 v3, v4, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_min_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -19702,10 +19693,9 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -19716,7 +19706,7 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_min_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -20050,10 +20040,9 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX8-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
@@ -20064,14 +20053,14 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_min_f32_e32 v2, v2, v6
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX8-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
@@ -20082,14 +20071,14 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_min_f32_e32 v1, v1, v5
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc
@@ -20100,7 +20089,7 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_min_f32_e32 v0, v0, v4
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -23876,11 +23865,10 @@ define <3 x bfloat> @v_maxnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) #0 {
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_max_f32_e32 v3, v4, v3
; GFX8-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_max_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -24128,10 +24116,9 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -24142,7 +24129,7 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_max_f32_e32 v0, v0, v2
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -24476,10 +24463,9 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v8
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
; GFX8-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
@@ -24490,14 +24476,14 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v7
; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_max_f32_e32 v2, v2, v6
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; GFX8-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v2
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
@@ -24508,14 +24494,14 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v6
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_max_f32_e32 v1, v1, v5
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_bfe_u32 v5, v1, 16, 1
; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v1
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v9, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc
@@ -24526,7 +24512,7 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) #0 {
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v5
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; GFX8-NEXT: v_max_f32_e32 v0, v0, v4
; GFX8-NEXT: v_or_b32_e32 v10, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
@@ -35261,7 +35247,7 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX8-NEXT: v_cvt_f32_i32_sdwa v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_i32_sdwa v5, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
+; GFX8-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_bfe_u32 v4, v2, 16, 1
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
@@ -35270,14 +35256,13 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-NEXT: v_bfe_u32 v4, v5, 16, 1
-; GFX8-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, s4, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_or_b32_e32 v3, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
@@ -35941,7 +35926,7 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) #0 {
; GFX8-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX8-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
+; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX8-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
@@ -35950,12 +35935,11 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) #0 {
; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
; GFX8-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v0
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v0
@@ -38193,7 +38177,6 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX8-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_cvt_f32_u32_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
@@ -38202,7 +38185,7 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) #0 {
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX8-NEXT: v_bfe_u32 v2, v4, 16, 1
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, s4, v2
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
; GFX8-NEXT: v_or_b32_e32 v3, 0x400000, v4
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
@@ -38423,7 +38406,7 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX8-NEXT: v_cvt_f32_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_u32_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
+; GFX8-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_bfe_u32 v3, v2, 16, 1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
@@ -38432,14 +38415,13 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) #0 {
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX8-NEXT: v_bfe_u32 v3, v5, 16, 1
-; GFX8-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v5
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
@@ -39106,7 +39088,7 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) #0 {
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
+; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX8-NEXT: v_bfe_u32 v5, v2, 16, 1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v2
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
@@ -39115,12 +39097,11 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) #0 {
; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc
; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc
; GFX8-NEXT: v_bfe_u32 v5, v0, 16, 1
-; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v0
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_or_b32_e32 v4, 0x400000, v0
@@ -46402,12 +46383,11 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX8-NEXT: v_fma_f32 v3, v6, v5, v3
; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -46669,10 +46649,9 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -46685,7 +46664,7 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -51401,12 +51380,11 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX8-NEXT: v_fma_f32 v3, v6, v5, v3
; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v3
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
@@ -51684,10 +51662,9 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX8-NEXT: v_or_b32_e32 v8, 0x400000, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; GFX8-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v1
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v1
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
@@ -51700,7 +51677,7 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX8-NEXT: v_or_b32_e32 v7, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
index 3a2f21b7dc79fa..6789df5453d161 100644
--- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -487,11 +487,10 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v31, vcc, 0, v3, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 0x7f, v0
-; GISEL-NEXT: v_not_b32_e32 v0, 63
-; GISEL-NEXT: v_add_i32_e32 v20, vcc, v22, v0
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v22
; GISEL-NEXT: v_lshr_b64 v[0:1], v[16:17], v0
; GISEL-NEXT: v_lshl_b64 v[2:3], v[18:19], v22
+; GISEL-NEXT: v_add_i32_e32 v20, vcc, 0xffffffc0, v22
; GISEL-NEXT: v_lshl_b64 v[8:9], v[16:17], v22
; GISEL-NEXT: v_or_b32_e32 v2, v0, v2
; GISEL-NEXT: v_or_b32_e32 v3, v1, v3
@@ -677,11 +676,10 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v29, vcc, 0, v3, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v14, vcc, 0x7f, v0
-; GISEL-NEXT: v_not_b32_e32 v0, 63
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v14, v0
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v14
; GISEL-NEXT: v_lshr_b64 v[0:1], v[6:7], v0
; GISEL-NEXT: v_lshl_b64 v[2:3], v[10:11], v14
+; GISEL-NEXT: v_add_i32_e32 v15, vcc, 0xffffffc0, v14
; GISEL-NEXT: v_lshl_b64 v[12:13], v[6:7], v14
; GISEL-NEXT: v_or_b32_e32 v2, v0, v2
; GISEL-NEXT: v_or_b32_e32 v3, v1, v3
@@ -1289,11 +1287,10 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v29, vcc, 0, v23, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 0x7f, v20
-; GISEL-NEXT: v_not_b32_e32 v2, 63
-; GISEL-NEXT: v_add_i32_e32 v22, vcc, v24, v2
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, 64, v24
; GISEL-NEXT: v_lshr_b64 v[2:3], v[0:1], v2
; GISEL-NEXT: v_lshl_b64 v[18:19], v[16:17], v24
+; GISEL-NEXT: v_add_i32_e32 v22, vcc, 0xffffffc0, v24
; GISEL-NEXT: v_lshl_b64 v[20:21], v[0:1], v24
; GISEL-NEXT: v_or_b32_e32 v18, v2, v18
; GISEL-NEXT: v_or_b32_e32 v19, v3, v19
@@ -1461,11 +1458,10 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 0x7f, v0
-; GISEL-NEXT: v_not_b32_e32 v0, 63
-; GISEL-NEXT: v_add_i32_e32 v21, vcc, v20, v0
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v20
; GISEL-NEXT: v_lshr_b64 v[0:1], v[4:5], v0
; GISEL-NEXT: v_lshl_b64 v[8:9], v[6:7], v20
+; GISEL-NEXT: v_add_i32_e32 v21, vcc, 0xffffffc0, v20
; GISEL-NEXT: v_lshl_b64 v[10:11], v[4:5], v20
; GISEL-NEXT: v_or_b32_e32 v22, v0, v8
; GISEL-NEXT: v_or_b32_e32 v23, v1, v9
@@ -2144,11 +2140,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v34, vcc, 0, v3, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v21, vcc, 0x7f, v0
-; GISEL-NEXT: v_not_b32_e32 v0, 63
-; GISEL-NEXT: v_add_i32_e32 v22, vcc, v21, v0
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v21
; GISEL-NEXT: v_lshr_b64 v[0:1], v[10:11], v0
; GISEL-NEXT: v_lshl_b64 v[2:3], v[8:9], v21
+; GISEL-NEXT: v_add_i32_e32 v22, vcc, 0xffffffc0, v21
; GISEL-NEXT: v_lshl_b64 v[19:20], v[10:11], v21
; GISEL-NEXT: v_or_b32_e32 v2, v0, v2
; GISEL-NEXT: v_or_b32_e32 v3, v1, v3
@@ -2334,11 +2329,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v39, vcc, 0, v15, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 0x7f, v0
-; GISEL-NEXT: v_not_b32_e32 v0, 63
-; GISEL-NEXT: v_add_i32_e32 v21, vcc, v20, v0
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v20
; GISEL-NEXT: v_lshr_b64 v[0:1], v[6:7], v0
; GISEL-NEXT: v_lshl_b64 v[2:3], v[4:5], v20
+; GISEL-NEXT: v_add_i32_e32 v21, vcc, 0xffffffc0, v20
; GISEL-NEXT: v_lshl_b64 v[14:15], v[6:7], v20
; GISEL-NEXT: v_or_b32_e32 v2, v0, v2
; GISEL-NEXT: v_or_b32_e32 v3, v1, v3
@@ -2953,11 +2947,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v32, vcc, 0, v19, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 0x7f, v16
-; GISEL-NEXT: v_not_b32_e32 v16, 63
-; GISEL-NEXT: v_add_i32_e32 v23, vcc, v20, v16
; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 64, v20
; GISEL-NEXT: v_lshr_b64 v[16:17], v[0:1], v16
; GISEL-NEXT: v_lshl_b64 v[18:19], v[2:3], v20
+; GISEL-NEXT: v_add_i32_e32 v23, vcc, 0xffffffc0, v20
; GISEL-NEXT: v_lshl_b64 v[21:22], v[0:1], v20
; GISEL-NEXT: v_or_b32_e32 v18, v16, v18
; GISEL-NEXT: v_or_b32_e32 v19, v17, v19
@@ -3125,11 +3118,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
; GISEL-NEXT: v_addc_u32_e32 v37, vcc, 0, v23, vcc
; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 0x7f, v16
-; GISEL-NEXT: v_not_b32_e32 v16, 63
-; GISEL-NEXT: v_add_i32_e32 v25, vcc, v24, v16
; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 64, v24
; GISEL-NEXT: v_lshr_b64 v[16:17], v[4:5], v16
; GISEL-NEXT: v_lshl_b64 v[18:19], v[6:7], v24
+; GISEL-NEXT: v_add_i32_e32 v25, vcc, 0xffffffc0, v24
; GISEL-NEXT: v_lshl_b64 v[22:23], v[4:5], v24
; GISEL-NEXT: v_or_b32_e32 v18, v16, v18
; GISEL-NEXT: v_or_b32_e32 v19, v17, v19
diff --git a/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll b/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
index e888008d808716..f7101e1d939922 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu6.00 -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
; RUN: llc -mtriple=amdgpu7.04 -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
; RUN: llc -mtriple=amdgpu6.00 -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
@@ -26,6 +27,89 @@ declare void @llvm.amdgcn.s.barrier() #1
; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:3360
; CHECK: s_endpgm
define amdgpu_kernel void @signed_ds_offset_addressing_loop(ptr addrspace(1) noalias nocapture %out, ptr addrspace(3) noalias nocapture readonly %lptr, i32 %n) #2 {
+; SI-LABEL: signed_ds_offset_addressing_loop:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dword s0, s[4:5], 0xb
+; SI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_mov_b32 m0, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
+; SI-NEXT: s_movk_i32 s0, 0xf3e0
+; SI-NEXT: .LBB0_1: ; %for.body
+; SI-NEXT: ; =>This Inner Loop Header: Depth=1
+; SI-NEXT: v_add_i32_e32 v3, vcc, s0, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, 0xc20, v3
+; SI-NEXT: v_add_i32_e32 v5, vcc, 0xc28, v3
+; SI-NEXT: v_add_i32_e32 v6, vcc, 0xca0, v3
+; SI-NEXT: v_add_i32_e32 v7, vcc, 0xca8, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0xd20, v3
+; SI-NEXT: s_barrier
+; SI-NEXT: ds_read_b32 v4, v4
+; SI-NEXT: ds_read_b32 v5, v5
+; SI-NEXT: ds_read_b32 v6, v6
+; SI-NEXT: ds_read_b32 v7, v7
+; SI-NEXT: ds_read_b32 v3, v3
+; SI-NEXT: s_addk_i32 s0, 0x184
+; SI-NEXT: s_waitcnt lgkmcnt(3)
+; SI-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-NEXT: s_waitcnt lgkmcnt(2)
+; SI-NEXT: v_add_f32_e32 v4, v4, v6
+; SI-NEXT: s_waitcnt lgkmcnt(1)
+; SI-NEXT: v_add_f32_e32 v4, v4, v7
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_add_f32_e32 v3, v4, v3
+; SI-NEXT: s_cmp_lg_u32 s0, 0
+; SI-NEXT: v_add_f32_e32 v1, v1, v3
+; SI-NEXT: s_cbranch_scc1 .LBB0_1
+; SI-NEXT: ; %bb.2: ; %for.end
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; SI-NEXT: v_mov_b32_e32 v3, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v1, v[2:3], s[0:3], 0 addr64
+; SI-NEXT: s_endpgm
+;
+; CI-LABEL: signed_ds_offset_addressing_loop:
+; CI: ; %bb.0: ; %entry
+; CI-NEXT: s_load_dword s0, s[4:5], 0xb
+; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT: v_mov_b32_e32 v1, 0
+; CI-NEXT: s_movk_i32 s1, 0xc00
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
+; CI-NEXT: s_movk_i32 s0, 0xf3e0
+; CI-NEXT: .LBB0_1: ; %for.body
+; CI-NEXT: ; =>This Inner Loop Header: Depth=1
+; CI-NEXT: v_add_i32_e32 v7, vcc, s0, v2
+; CI-NEXT: v_add_i32_e32 v5, vcc, s1, v7
+; CI-NEXT: s_barrier
+; CI-NEXT: ds_read2_b32 v[3:4], v5 offset0:8 offset1:10
+; CI-NEXT: ds_read2_b32 v[5:6], v5 offset0:40 offset1:42
+; CI-NEXT: ds_read_b32 v7, v7 offset:3360
+; CI-NEXT: s_addk_i32 s0, 0x184
+; CI-NEXT: s_cmp_lg_u32 s0, 0
+; CI-NEXT: s_waitcnt lgkmcnt(2)
+; CI-NEXT: v_add_f32_e32 v3, v3, v4
+; CI-NEXT: s_waitcnt lgkmcnt(1)
+; CI-NEXT: v_add_f32_e32 v3, v3, v5
+; CI-NEXT: v_add_f32_e32 v3, v3, v6
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_add_f32_e32 v3, v3, v7
+; CI-NEXT: v_add_f32_e32 v1, v1, v3
+; CI-NEXT: s_cbranch_scc1 .LBB0_1
+; CI-NEXT: ; %bb.2: ; %for.end
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, 0
+; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT: v_mov_b32_e32 v3, 0
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: buffer_store_dword v1, v[2:3], s[0:3], 0 addr64
+; CI-NEXT: s_endpgm
entry:
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%mul = shl nsw i32 %x.i, 1
@@ -70,3 +154,5 @@ for.end: ; preds = %for.body
attributes #0 = { nounwind readnone }
attributes #1 = { convergent nounwind }
attributes #2 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 5ef571082d6274..31b868993156dd 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -5184,9 +5184,8 @@ define <3 x bfloat> @v_copysign_out_v3bf16_mag_v3f32_sign_v3bf16(<3 x float> %ma
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc
; GFX8-NEXT: v_bfe_u32 v6, v0, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v0
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc
@@ -6316,15 +6315,14 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4f32_sign_v4bf16(<4 x float> %ma
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v6, vcc
; GFX8-NEXT: v_bfe_u32 v7, v3, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v3
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc
; GFX8-NEXT: v_bfe_u32 v7, v0, 16, 1
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v0
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, s4, v7
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v0
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v6, vcc
@@ -6977,14 +6975,13 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4bf16_sign_v4f32(<4 x bfloat> %m
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; GFX8-NEXT: v_bfe_u32 v6, v5, 16, 1
-; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v5
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX8-NEXT: v_bfe_u32 v6, v2, 16, 1
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX8-NEXT: v_bfe_u32 v6, v3, 16, 1
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 80be6e5ef40ea8..f9cb5d91ff615d 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -864,9 +864,8 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v3
-; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; SI-NEXT: v_add_i32_e32 v1, vcc, s4, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0xfffffc10, v1
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v1
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_or_b32_e32 v4, v0, v4
@@ -910,9 +909,8 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; VI-NEXT: v_lshrrev_b32_e32 v5, v4, v3
; VI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v3
-; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; VI-NEXT: v_add_u32_e32 v1, vcc, s4, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0xfffffc10, v1
; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v1
; VI-NEXT: v_or_b32_e32 v3, v5, v3
; VI-NEXT: v_or_b32_e32 v4, v0, v4
@@ -6939,9 +6937,8 @@ define half @v_copysign_f16_0_f64(double %sign) {
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0xfffffc10, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v0, v0, v4
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index 31c8c7b2e11f74..4f053196bda3be 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -4087,9 +4087,8 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0xfffffc10, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v4, v0, v4
@@ -4134,9 +4133,8 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; VI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0xfffffc10, v3
; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
; VI-NEXT: v_or_b32_e32 v4, v0, v4
@@ -4557,9 +4555,8 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; SI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; SI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; SI-NEXT: s_movk_i32 s4, 0xfc10
; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; SI-NEXT: v_add_i32_e32 v3, vcc, s4, v3
+; SI-NEXT: v_add_i32_e32 v3, vcc, 0xfffffc10, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; SI-NEXT: v_or_b32_e32 v2, v5, v2
; SI-NEXT: v_or_b32_e32 v4, v0, v4
@@ -4605,9 +4602,8 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v5, v4, v2
; VI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v2
-; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 0xfffffc10, v3
; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
; VI-NEXT: v_or_b32_e32 v4, v0, v4
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
index 576095af509507..95c54f9f37e271 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir
@@ -17,7 +17,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], [[COPY]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
%1:vgpr_32 = COPY $vgpr0
@@ -42,7 +42,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[COPY]], [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[COPY]], [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
@@ -117,7 +117,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 %stack.0
%1:vgpr_32 = COPY $vgpr0
@@ -142,7 +142,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:sreg_32_xm0 = S_MOV_B32 %stack.0
@@ -163,7 +163,7 @@ body: |
; GCN-LABEL: name: shrink_vgpr_imm_fi_vgpr_v_add_i32_e64_no_carry_out_use
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 16, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 16, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
%1:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
@@ -204,7 +204,7 @@ body: |
; GCN-LABEL: name: shrink_vgpr_k_fi_vgpr_v_add_i32_e64_no_carry_out_use
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 1234, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 1234, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
%1:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
@@ -225,7 +225,7 @@ body: |
; GCN-LABEL: name: shrink_vgpr_k_vgpr_fi_v_add_i32_e64_no_carry_out_use
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, [[V_MOV_B32_e32_]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = V_MOV_B32_e32 1234, implicit $exec
%1:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
index 25140fe5aab5e4..bbcfc74b057b43 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
@@ -38,7 +38,7 @@ body: |
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY killed $vcc
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF1]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF1]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]], implicit [[V_ADD_CO_U32_e32_1]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
@@ -63,7 +63,7 @@ body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_dbg_only_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: DBG_VALUE %5:sreg_64_xexec, $noreg
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
diff --git a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
index ffd683f1811b9f..9625909bb54fad 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
@@ -11,7 +11,7 @@ body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
@@ -30,7 +30,7 @@ body: |
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32_xm0 = S_MOV_B32 12345
@@ -48,7 +48,7 @@ body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
@@ -265,7 +265,7 @@ body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
@@ -284,7 +284,7 @@ body: |
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
- ; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUBREV_CO_U32_e32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32_xm0 = S_MOV_B32 12345
@@ -303,7 +303,7 @@ body: |
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_SUBREV_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUBREV_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
@@ -322,7 +322,7 @@ body: |
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
- ; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_SUB_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e32_]]
%0:vgpr_32 = IMPLICIT_DEF
%1:sreg_32_xm0 = S_MOV_B32 12345
@@ -375,7 +375,7 @@ body: |
; GCN-NEXT: S_NOP 0
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: {{ $}}
@@ -441,7 +441,7 @@ body: |
; GCN-NEXT: S_NOP 0, implicit-def $vcc
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: {{ $}}
@@ -502,7 +502,7 @@ body: |
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:sreg_32_xm0 = S_MOV_B32 12345
%1:vgpr_32 = IMPLICIT_DEF
@@ -579,7 +579,7 @@ body: |
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
; GCN-NEXT: DBG_VALUE $noreg, 0
@@ -684,7 +684,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 killed [[V_MOV_B32_e32_]], [[COPY]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 killed [[V_MOV_B32_e32_]], [[COPY]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
@@ -703,7 +703,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
- ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], killed [[COPY]], implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], killed [[COPY]], implicit-def dead $vcc, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e32_]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = V_MOV_B32_e32 518144, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index 2856368268886a..e5e07ff1a94eb1 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -225,23 +225,21 @@ define float @local_atomic_fadd_ret_f32__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB1_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffc, v0
-; GFX6-NEXT: v_add_f32_e32 v3, 4.0, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_add_f32_e32 v0, 4.0, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB1_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr float, ptr addrspace(3) %ptr, i32 16383
%result = atomicrmw fadd ptr addrspace(3) %gep, float 4.0 seq_cst
@@ -453,16 +451,15 @@ define void @local_atomic_fadd_noret_f32__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-LABEL: local_atomic_fadd_noret_f32__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB3_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_add_f32_e32 v2, 4.0, v1
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xfffc, v0
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v3, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -842,10 +839,9 @@ define double @local_atomic_fadd_ret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-LABEL: local_atomic_fadd_ret_f64__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfff8, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfff8, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b64 v[0:1], v0
+; GFX6-NEXT: ds_read_b64 v[0:1], v2
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -853,8 +849,7 @@ define double @local_atomic_fadd_ret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-NEXT: v_mov_b32_e32 v4, v1
; GFX6-NEXT: v_mov_b32_e32 v3, v0
; GFX6-NEXT: v_add_f64 v[0:1], v[3:4], 4.0
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfff8, v2
-; GFX6-NEXT: ds_cmpst_rtn_b64 v[0:1], v5, v[3:4], v[0:1]
+; GFX6-NEXT: ds_cmpst_rtn_b64 v[0:1], v2, v[3:4], v[0:1]
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[3:4]
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -1212,21 +1207,20 @@ define void @local_atomic_fadd_noret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-LABEL: local_atomic_fadd_noret_f64__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfff8, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfff8, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b64 v[1:2], v1
+; GFX6-NEXT: ds_read_b64 v[0:1], v2
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB7_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_add_f64 v[3:4], v[1:2], 4.0
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfff8, v0
-; GFX6-NEXT: ds_cmpst_rtn_b64 v[3:4], v5, v[1:2], v[3:4]
+; GFX6-NEXT: v_add_f64 v[3:4], v[0:1], 4.0
+; GFX6-NEXT: ds_cmpst_rtn_b64 v[3:4], v2, v[0:1], v[3:4]
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[1:2]
-; GFX6-NEXT: v_mov_b32_e32 v1, v3
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, v3
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v2, v4
+; GFX6-NEXT: v_mov_b32_e32 v1, v4
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB7_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3053,27 +3047,25 @@ define half @local_atomic_fadd_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB12_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xfffe, v0
-; GFX6-NEXT: v_add_f32_e32 v1, 4.0, v1
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v3, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_add_f32_e32 v0, 4.0, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB12_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr half, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fadd ptr addrspace(3) %gep, half 4.0 seq_cst, align 4
@@ -3338,20 +3330,19 @@ define void @local_atomic_fadd_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fadd_noret_f16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_add_f32_e32 v2, 4.0, v2
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -5130,27 +5121,25 @@ define bfloat @local_atomic_fadd_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX6-NEXT: v_add_f32_e32 v3, 4.0, v3
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
-; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; GFX6-NEXT: v_add_f32_e32 v0, 4.0, v0
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB18_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr bfloat, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fadd ptr addrspace(3) %gep, bfloat 4.0 seq_cst, align 4
@@ -5413,9 +5402,9 @@ define void @local_atomic_fadd_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fadd_noret_bf16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5424,9 +5413,8 @@ define void @local_atomic_fadd_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: v_add_f32_e32 v2, 4.0, v2
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -5836,9 +5824,9 @@ define <2 x half> @local_atomic_fadd_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-LABEL: local_atomic_fadd_ret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -5856,10 +5844,9 @@ define <2 x half> @local_atomic_fadd_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6246,9 +6233,9 @@ define void @local_atomic_fadd_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-LABEL: local_atomic_fadd_noret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -6266,10 +6253,9 @@ define void @local_atomic_fadd_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6967,9 +6953,9 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-LABEL: local_atomic_fadd_ret_v2bf16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v1
@@ -6984,16 +6970,15 @@ define <2 x bfloat> @local_atomic_fadd_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_add_f32_e32 v7, v7, v2
-; GFX6-NEXT: v_add_f32_e32 v6, v6, v1
+; GFX6-NEXT: v_add_f32_e32 v6, v6, v2
+; GFX6-NEXT: v_add_f32_e32 v5, v5, v1
; GFX6-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
@@ -7662,9 +7647,9 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-LABEL: local_atomic_fadd_noret_v2bf16__ofset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v1
@@ -7679,16 +7664,15 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_add_f32_e32 v7, v7, v2
-; GFX6-NEXT: v_add_f32_e32 v6, v6, v1
+; GFX6-NEXT: v_add_f32_e32 v6, v6, v2
+; GFX6-NEXT: v_add_f32_e32 v5, v5, v1
; GFX6-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 3de6a80ef14b32..b74f6b1c346012 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -2616,27 +2616,25 @@ define half @local_atomic_fmax_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB12_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xfffe, v0
-; GFX6-NEXT: v_max_f32_e32 v1, 4.0, v1
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v3, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_max_f32_e32 v0, 4.0, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB12_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr half, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fmax ptr addrspace(3) %gep, half 4.0 seq_cst, align 4
@@ -2910,20 +2908,19 @@ define void @local_atomic_fmax_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fmax_noret_f16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_max_f32_e32 v2, 4.0, v2
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -4711,28 +4708,26 @@ define bfloat @local_atomic_fmax_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; GFX6-NEXT: v_max_f32_e32 v3, 4.0, v3
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
-; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; GFX6-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; GFX6-NEXT: v_max_f32_e32 v0, 4.0, v0
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB18_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr bfloat, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fmax ptr addrspace(3) %gep, bfloat 4.0 seq_cst, align 4
@@ -4996,9 +4991,9 @@ define void @local_atomic_fmax_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fmax_noret_bf16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5008,9 +5003,8 @@ define void @local_atomic_fmax_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: v_max_f32_e32 v2, 4.0, v2
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -5514,9 +5508,9 @@ define <2 x half> @local_atomic_fmax_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-LABEL: local_atomic_fmax_ret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -5534,10 +5528,9 @@ define <2 x half> @local_atomic_fmax_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6014,9 +6007,9 @@ define void @local_atomic_fmax_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-LABEL: local_atomic_fmax_noret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -6034,10 +6027,9 @@ define void @local_atomic_fmax_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6985,9 +6977,9 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-LABEL: local_atomic_fmax_ret_v2bf16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v5
@@ -7002,16 +6994,15 @@ define <2 x bfloat> @local_atomic_fmax_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_max_f32_e32 v6, v6, v1
-; GFX6-NEXT: v_max_f32_e32 v7, v7, v2
+; GFX6-NEXT: v_max_f32_e32 v5, v5, v1
+; GFX6-NEXT: v_max_f32_e32 v6, v6, v2
; GFX6-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v7, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v5, v3
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
@@ -7916,9 +7907,9 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-LABEL: local_atomic_fmax_noret_v2bf16__ofset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v5
@@ -7933,16 +7924,15 @@ define void @local_atomic_fmax_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_max_f32_e32 v6, v6, v1
-; GFX6-NEXT: v_max_f32_e32 v7, v7, v2
+; GFX6-NEXT: v_max_f32_e32 v5, v5, v1
+; GFX6-NEXT: v_max_f32_e32 v6, v6, v2
; GFX6-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v7, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v5, v3
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 606a390989cc3c..7c68c45a70a038 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -2616,27 +2616,25 @@ define half @local_atomic_fmin_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB12_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xfffe, v0
-; GFX6-NEXT: v_min_f32_e32 v1, 4.0, v1
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v3, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_min_f32_e32 v0, 4.0, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB12_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr half, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fmin ptr addrspace(3) %gep, half 4.0 seq_cst, align 4
@@ -2910,20 +2908,19 @@ define void @local_atomic_fmin_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fmin_noret_f16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_min_f32_e32 v2, 4.0, v2
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -4711,28 +4708,26 @@ define bfloat @local_atomic_fmin_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; GFX6-NEXT: v_min_f32_e32 v3, 4.0, v3
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
-; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; GFX6-NEXT: v_mul_f32_e32 v0, 1.0, v0
+; GFX6-NEXT: v_min_f32_e32 v0, 4.0, v0
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB18_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr bfloat, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fmin ptr addrspace(3) %gep, bfloat 4.0 seq_cst, align 4
@@ -4996,9 +4991,9 @@ define void @local_atomic_fmin_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fmin_noret_bf16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5008,9 +5003,8 @@ define void @local_atomic_fmin_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: v_min_f32_e32 v2, 4.0, v2
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -5514,9 +5508,9 @@ define <2 x half> @local_atomic_fmin_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-LABEL: local_atomic_fmin_ret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -5534,10 +5528,9 @@ define <2 x half> @local_atomic_fmin_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6014,9 +6007,9 @@ define void @local_atomic_fmin_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-LABEL: local_atomic_fmin_noret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -6034,10 +6027,9 @@ define void @local_atomic_fmin_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6985,9 +6977,9 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-LABEL: local_atomic_fmin_ret_v2bf16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v5
@@ -7002,16 +6994,15 @@ define <2 x bfloat> @local_atomic_fmin_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_min_f32_e32 v6, v6, v1
-; GFX6-NEXT: v_min_f32_e32 v7, v7, v2
+; GFX6-NEXT: v_min_f32_e32 v5, v5, v1
+; GFX6-NEXT: v_min_f32_e32 v6, v6, v2
; GFX6-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v7, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v5, v3
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
@@ -7916,9 +7907,9 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-LABEL: local_atomic_fmin_noret_v2bf16__ofset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v5
@@ -7933,16 +7924,15 @@ define void @local_atomic_fmin_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX6-NEXT: v_min_f32_e32 v6, v6, v1
-; GFX6-NEXT: v_min_f32_e32 v7, v7, v2
+; GFX6-NEXT: v_min_f32_e32 v5, v5, v1
+; GFX6-NEXT: v_min_f32_e32 v6, v6, v2
; GFX6-NEXT: v_alignbit_b32 v3, v4, v3, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v7, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v5, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v5, v3
; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index a11b5c81f4e839..5c988fcda1a8e4 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -419,23 +419,21 @@ define float @local_atomic_fsub_ret_f32__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB1_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffc, v0
-; GFX6-NEXT: v_add_f32_e32 v3, -4.0, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_add_f32_e32 v0, -4.0, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB1_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr float, ptr addrspace(3) %ptr, i32 16383
%result = atomicrmw fsub ptr addrspace(3) %gep, float 4.0 seq_cst
@@ -823,16 +821,15 @@ define void @local_atomic_fsub_noret_f32__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-LABEL: local_atomic_fsub_noret_f32__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB3_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_add_f32_e32 v2, -4.0, v1
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xfffc, v0
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v3, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -1262,10 +1259,9 @@ define double @local_atomic_fsub_ret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-LABEL: local_atomic_fsub_ret_f64__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfff8, v2
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfff8, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b64 v[0:1], v0
+; GFX6-NEXT: ds_read_b64 v[0:1], v2
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB5_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -1273,8 +1269,7 @@ define double @local_atomic_fsub_ret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-NEXT: v_mov_b32_e32 v4, v1
; GFX6-NEXT: v_mov_b32_e32 v3, v0
; GFX6-NEXT: v_add_f64 v[0:1], v[3:4], -4.0
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfff8, v2
-; GFX6-NEXT: ds_cmpst_rtn_b64 v[0:1], v5, v[3:4], v[0:1]
+; GFX6-NEXT: ds_cmpst_rtn_b64 v[0:1], v2, v[3:4], v[0:1]
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[0:1], v[3:4]
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -1678,21 +1673,20 @@ define void @local_atomic_fsub_noret_f64__offset(ptr addrspace(3) %ptr) nounwind
; GFX6-LABEL: local_atomic_fsub_noret_f64__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfff8, v0
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfff8, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b64 v[1:2], v1
+; GFX6-NEXT: ds_read_b64 v[0:1], v2
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB7_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_add_f64 v[3:4], v[1:2], -4.0
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfff8, v0
-; GFX6-NEXT: ds_cmpst_rtn_b64 v[3:4], v5, v[1:2], v[3:4]
+; GFX6-NEXT: v_add_f64 v[3:4], v[0:1], -4.0
+; GFX6-NEXT: ds_cmpst_rtn_b64 v[3:4], v2, v[0:1], v[3:4]
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[1:2]
-; GFX6-NEXT: v_mov_b32_e32 v1, v3
+; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[3:4], v[0:1]
+; GFX6-NEXT: v_mov_b32_e32 v0, v3
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v2, v4
+; GFX6-NEXT: v_mov_b32_e32 v1, v4
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB7_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3519,27 +3513,25 @@ define half @local_atomic_fsub_ret_f16__offset__align4(ptr addrspace(3) %ptr) no
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB12_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v2
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xfffe, v0
-; GFX6-NEXT: v_add_f32_e32 v1, -4.0, v1
-; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v4, v1
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v3, v2, v1
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v2
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_add_f32_e32 v0, -4.0, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB12_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr half, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fsub ptr addrspace(3) %gep, half 4.0 seq_cst, align 4
@@ -3804,20 +3796,19 @@ define void @local_atomic_fsub_noret_f16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fsub_noret_f16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB13_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_add_f32_e32 v2, -4.0, v2
; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -5596,27 +5587,25 @@ define bfloat @local_atomic_fsub_ret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v0, v1
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; GFX6-NEXT: v_add_f32_e32 v3, -4.0, v3
-; GFX6-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
-; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; GFX6-NEXT: v_add_f32_e32 v0, -4.0, v0
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
; GFX6-NEXT: s_cbranch_execnz .LBB18_1
; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr bfloat, ptr addrspace(3) %ptr, i32 32767
%result = atomicrmw fsub ptr addrspace(3) %gep, bfloat 4.0 seq_cst, align 4
@@ -5879,9 +5868,9 @@ define void @local_atomic_fsub_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-LABEL: local_atomic_fsub_noret_bf16__offset__align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0xfffe, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffe, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v1, v1
+; GFX6-NEXT: ds_read_b32 v1, v0
; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: .LBB19_1: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -5890,9 +5879,8 @@ define void @local_atomic_fsub_noret_bf16__offset__align4(ptr addrspace(3) %ptr)
; GFX6-NEXT: v_add_f32_e32 v2, -4.0, v2
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0xfffe, v0
; GFX6-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v4, v1, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6366,9 +6354,9 @@ define <2 x half> @local_atomic_fsub_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-LABEL: local_atomic_fsub_ret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -6386,10 +6374,9 @@ define <2 x half> @local_atomic_fsub_ret_v2f16__offset(ptr addrspace(3) %ptr, <2
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -6834,9 +6821,9 @@ define void @local_atomic_fsub_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-LABEL: local_atomic_fsub_noret_v2f16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v3, v2
+; GFX6-NEXT: ds_read_b32 v3, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
@@ -6854,10 +6841,9 @@ define void @local_atomic_fsub_noret_v2f16__offset(ptr addrspace(3) %ptr, <2 x h
; GFX6-NEXT: v_cvt_f16_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_f16_f32_e32 v6, v6
; GFX6-NEXT: v_or_b32_e32 v4, v3, v4
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0xfffc, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v5
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v7, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v3, v0, v4, v3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
@@ -7805,9 +7791,9 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-LABEL: local_atomic_fsub_ret_v2bf16__offset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v1
@@ -7822,16 +7808,15 @@ define <2 x bfloat> @local_atomic_fsub_ret_v2bf16__offset(ptr addrspace(3) %ptr,
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_sub_f32_e32 v7, v7, v2
-; GFX6-NEXT: v_sub_f32_e32 v6, v6, v1
+; GFX6-NEXT: v_sub_f32_e32 v6, v6, v2
+; GFX6-NEXT: v_sub_f32_e32 v5, v5, v1
; GFX6-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
@@ -8736,9 +8721,9 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-LABEL: local_atomic_fsub_noret_v2bf16__ofset:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xfffc, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0xfffc, v0
; GFX6-NEXT: s_mov_b32 m0, -1
-; GFX6-NEXT: ds_read_b32 v2, v2
+; GFX6-NEXT: ds_read_b32 v2, v0
; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_mul_f32_e32 v1, 1.0, v1
@@ -8753,16 +8738,15 @@ define void @local_atomic_fsub_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: v_mul_f32_e32 v3, 1.0, v3
; GFX6-NEXT: v_mul_f32_e32 v4, 1.0, v4
-; GFX6-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
-; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v4
+; GFX6-NEXT: v_and_b32_e32 v6, 0xffff0000, v3
+; GFX6-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX6-NEXT: v_sub_f32_e32 v7, v7, v2
-; GFX6-NEXT: v_sub_f32_e32 v6, v6, v1
+; GFX6-NEXT: v_sub_f32_e32 v6, v6, v2
+; GFX6-NEXT: v_sub_f32_e32 v5, v5, v1
; GFX6-NEXT: v_alignbit_b32 v3, v3, v4, 16
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0xfffc, v0
-; GFX6-NEXT: v_alignbit_b32 v4, v4, v6, 16
-; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v5, v3, v4
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v6
+; GFX6-NEXT: v_alignbit_b32 v4, v4, v5, 16
+; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
; GFX6-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
diff --git a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
index 0b0cdabeacee0f..f1d79f57dd983d 100644
--- a/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
+++ b/llvm/test/CodeGen/AMDGPU/scratch-simple.ll
@@ -22,124 +22,123 @@
define amdgpu_ps float @ps_main(i32 %idx) {
; SI-LABEL: ps_main:
; SI: ; %bb.0:
-; SI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; SI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0xe8f000
-; SI-NEXT: s_add_u32 s4, s4, s0
-; SI-NEXT: s_addc_u32 s5, s5, 0
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; SI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s3, 0xe8f000
+; SI-NEXT: s_add_u32 s0, s0, s4
+; SI-NEXT: s_addc_u32 s1, s1, 0
; SI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; SI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; SI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; SI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; SI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; SI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; SI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; SI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; SI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; SI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
+; SI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; SI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; SI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: s_waitcnt expcnt(0)
@@ -147,112 +146,111 @@ define amdgpu_ps float @ps_main(i32 %idx) {
;
; VI-LABEL: ps_main:
; VI: ; %bb.0:
-; VI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; VI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: s_mov_b32 s7, 0xe80000
-; VI-NEXT: s_add_u32 s4, s4, s0
-; VI-NEXT: s_addc_u32 s5, s5, 0
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; VI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s3, 0xe80000
+; VI-NEXT: s_add_u32 s0, s0, s4
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; VI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; VI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; VI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; VI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; VI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; VI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; VI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; VI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; VI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; VI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
+; VI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; VI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; VI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; VI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; VI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; VI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
@@ -1028,124 +1026,123 @@ define amdgpu_ps float @ps_main(i32 %idx) {
define amdgpu_vs float @vs_main(i32 %idx) {
; SI-LABEL: vs_main:
; SI: ; %bb.0:
-; SI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; SI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0xe8f000
-; SI-NEXT: s_add_u32 s4, s4, s0
-; SI-NEXT: s_addc_u32 s5, s5, 0
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; SI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s3, 0xe8f000
+; SI-NEXT: s_add_u32 s0, s0, s4
+; SI-NEXT: s_addc_u32 s1, s1, 0
; SI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; SI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; SI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; SI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; SI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; SI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; SI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; SI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; SI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; SI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
+; SI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; SI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; SI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: s_waitcnt expcnt(0)
@@ -1153,112 +1150,111 @@ define amdgpu_vs float @vs_main(i32 %idx) {
;
; VI-LABEL: vs_main:
; VI: ; %bb.0:
-; VI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; VI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: s_mov_b32 s7, 0xe80000
-; VI-NEXT: s_add_u32 s4, s4, s0
-; VI-NEXT: s_addc_u32 s5, s5, 0
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; VI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s3, 0xe80000
+; VI-NEXT: s_add_u32 s0, s0, s4
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; VI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; VI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; VI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; VI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; VI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; VI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; VI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; VI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; VI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; VI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
+; VI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; VI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; VI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; VI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; VI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; VI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
@@ -2034,124 +2030,123 @@ define amdgpu_vs float @vs_main(i32 %idx) {
define amdgpu_cs float @cs_main(i32 %idx) {
; SI-LABEL: cs_main:
; SI: ; %bb.0:
-; SI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; SI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0xe8f000
-; SI-NEXT: s_add_u32 s4, s4, s0
-; SI-NEXT: s_addc_u32 s5, s5, 0
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; SI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s3, 0xe8f000
+; SI-NEXT: s_add_u32 s0, s0, s4
+; SI-NEXT: s_addc_u32 s1, s1, 0
; SI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; SI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; SI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; SI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; SI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; SI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; SI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; SI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; SI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; SI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
+; SI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; SI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; SI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: s_waitcnt expcnt(0)
@@ -2159,112 +2154,111 @@ define amdgpu_cs float @cs_main(i32 %idx) {
;
; VI-LABEL: cs_main:
; VI: ; %bb.0:
-; VI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; VI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: s_mov_b32 s7, 0xe80000
-; VI-NEXT: s_add_u32 s4, s4, s0
-; VI-NEXT: s_addc_u32 s5, s5, 0
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; VI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s3, 0xe80000
+; VI-NEXT: s_add_u32 s0, s0, s4
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; VI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; VI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; VI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; VI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; VI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; VI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; VI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; VI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; VI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; VI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
+; VI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; VI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; VI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; VI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; VI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; VI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
@@ -3040,124 +3034,123 @@ define amdgpu_cs float @cs_main(i32 %idx) {
define amdgpu_hs float @hs_main(i32 %idx) {
; SI-LABEL: hs_main:
; SI: ; %bb.0:
-; SI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; SI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0xe8f000
-; SI-NEXT: s_add_u32 s4, s4, s0
-; SI-NEXT: s_addc_u32 s5, s5, 0
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; SI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s3, 0xe8f000
+; SI-NEXT: s_add_u32 s0, s0, s4
+; SI-NEXT: s_addc_u32 s1, s1, 0
; SI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; SI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; SI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; SI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; SI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; SI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; SI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; SI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; SI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; SI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
+; SI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; SI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; SI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: s_waitcnt expcnt(0)
@@ -3165,112 +3158,111 @@ define amdgpu_hs float @hs_main(i32 %idx) {
;
; VI-LABEL: hs_main:
; VI: ; %bb.0:
-; VI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; VI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: s_mov_b32 s7, 0xe80000
-; VI-NEXT: s_add_u32 s4, s4, s0
-; VI-NEXT: s_addc_u32 s5, s5, 0
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; VI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s3, 0xe80000
+; VI-NEXT: s_add_u32 s0, s0, s4
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; VI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; VI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; VI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; VI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; VI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; VI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; VI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; VI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; VI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; VI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
+; VI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; VI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; VI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; VI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; VI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; VI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
@@ -4043,124 +4035,123 @@ define amdgpu_hs float @hs_main(i32 %idx) {
define amdgpu_gs float @gs_main(i32 %idx) {
; SI-LABEL: gs_main:
; SI: ; %bb.0:
-; SI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; SI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0xe8f000
-; SI-NEXT: s_add_u32 s4, s4, s0
-; SI-NEXT: s_addc_u32 s5, s5, 0
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; SI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s3, 0xe8f000
+; SI-NEXT: s_add_u32 s0, s0, s4
+; SI-NEXT: s_addc_u32 s1, s1, 0
; SI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; SI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; SI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; SI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; SI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; SI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; SI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; SI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; SI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; SI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
+; SI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; SI-NEXT: s_waitcnt expcnt(3)
; SI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; SI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; SI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; SI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; SI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; SI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; SI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; SI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; SI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; SI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; SI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; SI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; SI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; SI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; SI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; SI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; SI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; SI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; SI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; SI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; SI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; SI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; SI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; SI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; SI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; SI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; SI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; SI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; SI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; SI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; SI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; SI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; SI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: s_waitcnt expcnt(0)
@@ -4168,112 +4159,111 @@ define amdgpu_gs float @gs_main(i32 %idx) {
;
; VI-LABEL: gs_main:
; VI: ; %bb.0:
-; VI-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; VI-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: s_mov_b32 s7, 0xe80000
-; VI-NEXT: s_add_u32 s4, s4, s0
-; VI-NEXT: s_addc_u32 s5, s5, 0
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+; VI-NEXT: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s3, 0xe80000
+; VI-NEXT: s_add_u32 s0, s0, s4
+; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v9, 0xbe31934f
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:264
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:264
; VI-NEXT: v_mov_b32_e32 v9, 0xb7043519
; VI-NEXT: v_mov_b32_e32 v2, 0xbf20e7f4
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:260
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:320
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
; VI-NEXT: v_mov_b32_e32 v5, 0x3f5f2ee2
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:304
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:300
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:296
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:292
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:288
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:304
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:300
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:296
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:292
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:288
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd8a3
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:256
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:256
; VI-NEXT: v_mov_b32_e32 v9, 0x3e31934f
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29d8
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:284
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
; VI-NEXT: v_mov_b32_e32 v8, 0xbe319356
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:252
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:252
; VI-NEXT: v_mov_b32_e32 v9, 0x3e319356
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:244
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:244
; VI-NEXT: v_mov_b32_e32 v10, 0x3eae29dc
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:236
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:236
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89f
; VI-NEXT: v_mov_b32_e32 v12, 0xbf20e7f5
; VI-NEXT: v_mov_b32_e32 v13, 0xbf3d349e
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:220
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:220
; VI-NEXT: v_mov_b32_e32 v15, 0xbf5f2ee3
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:212
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:208
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:204
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:200
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:212
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:208
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:204
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:316
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:312
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:308
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:280
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:276
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:272
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:268
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:248
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:240
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:232
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:228
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:224
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:216
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:196
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:316
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:312
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:308
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:280
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:276
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:272
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:268
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:248
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:240
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:232
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:228
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:224
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:216
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
-; VI-NEXT: buffer_load_dword v0, v0, s[4:7], 0 offen
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:832
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:828
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:824
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:820
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
+; VI-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:832
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:828
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:824
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:820
; VI-NEXT: v_mov_b32_e32 v17, 0x3703c499
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:796
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:792
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:788
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:796
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:792
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:788
; VI-NEXT: v_mov_b32_e32 v18, 0xbf523be1
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:816
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:812
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:808
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:804
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:800
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:784
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:780
-; VI-NEXT: buffer_store_dword v15, off, s[4:7], 0 offset:776
-; VI-NEXT: buffer_store_dword v6, off, s[4:7], 0 offset:772
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0 offset:768
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:764
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:816
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:812
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:808
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:804
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:800
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:784
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:780
+; VI-NEXT: buffer_store_dword v15, off, s[0:3], 0 offset:776
+; VI-NEXT: buffer_store_dword v6, off, s[0:3], 0 offset:772
+; VI-NEXT: buffer_store_dword v16, off, s[0:3], 0 offset:768
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:764
; VI-NEXT: v_mov_b32_e32 v5, 0xbf5f2ee2
-; VI-NEXT: buffer_store_dword v5, off, s[4:7], 0 offset:760
-; VI-NEXT: buffer_store_dword v4, off, s[4:7], 0 offset:756
-; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0 offset:752
-; VI-NEXT: buffer_store_dword v3, off, s[4:7], 0 offset:748
-; VI-NEXT: buffer_store_dword v13, off, s[4:7], 0 offset:744
-; VI-NEXT: buffer_store_dword v14, off, s[4:7], 0 offset:740
-; VI-NEXT: buffer_store_dword v11, off, s[4:7], 0 offset:736
-; VI-NEXT: buffer_store_dword v10, off, s[4:7], 0 offset:732
-; VI-NEXT: buffer_store_dword v9, off, s[4:7], 0 offset:728
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0 offset:724
-; VI-NEXT: buffer_store_dword v8, off, s[4:7], 0 offset:720
-; VI-NEXT: buffer_store_dword v7, off, s[4:7], 0 offset:716
-; VI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:712
-; VI-NEXT: buffer_store_dword v12, off, s[4:7], 0 offset:708
-; VI-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen
+; VI-NEXT: buffer_store_dword v5, off, s[0:3], 0 offset:760
+; VI-NEXT: buffer_store_dword v4, off, s[0:3], 0 offset:756
+; VI-NEXT: buffer_store_dword v18, off, s[0:3], 0 offset:752
+; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 offset:748
+; VI-NEXT: buffer_store_dword v13, off, s[0:3], 0 offset:744
+; VI-NEXT: buffer_store_dword v14, off, s[0:3], 0 offset:740
+; VI-NEXT: buffer_store_dword v11, off, s[0:3], 0 offset:736
+; VI-NEXT: buffer_store_dword v10, off, s[0:3], 0 offset:732
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], 0 offset:728
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], 0 offset:724
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], 0 offset:720
+; VI-NEXT: buffer_store_dword v7, off, s[0:3], 0 offset:716
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:712
+; VI-NEXT: buffer_store_dword v12, off, s[0:3], 0 offset:708
+; VI-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
@@ -5065,7 +5055,6 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: buffer_store_dword v9, off, s[8:11], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
@@ -5084,8 +5073,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
@@ -5110,8 +5098,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: buffer_store_dword v13, off, s[8:11], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
; SI-NEXT: buffer_store_dword v3, off, s[8:11], 0 offset:316
; SI-NEXT: buffer_store_dword v4, off, s[8:11], 0 offset:312
; SI-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:308
@@ -5128,6 +5115,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: buffer_store_dword v14, off, s[8:11], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
; SI-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen
; SI-NEXT: buffer_store_dword v17, off, s[8:11], 0 offset:832
; SI-NEXT: buffer_store_dword v11, off, s[8:11], 0 offset:828
@@ -5189,7 +5177,6 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
; VI-NEXT: buffer_store_dword v9, off, s[8:11], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
@@ -5206,8 +5193,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
@@ -5227,8 +5213,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: buffer_store_dword v14, off, s[8:11], 0 offset:204
; VI-NEXT: buffer_store_dword v13, off, s[8:11], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
; VI-NEXT: buffer_store_dword v3, off, s[8:11], 0 offset:316
; VI-NEXT: buffer_store_dword v4, off, s[8:11], 0 offset:312
; VI-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:308
@@ -5245,6 +5230,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: buffer_store_dword v14, off, s[8:11], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
; VI-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen
; VI-NEXT: buffer_store_dword v17, off, s[8:11], 0 offset:832
; VI-NEXT: buffer_store_dword v11, off, s[8:11], 0 offset:828
@@ -6078,7 +6064,6 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: buffer_store_dword v9, off, s[8:11], 0 offset:260
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:320
; SI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; SI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
@@ -6097,8 +6082,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; SI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; SI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; SI-NEXT: s_mov_b32 s0, 0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:284
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
@@ -6123,8 +6107,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: buffer_store_dword v13, off, s[8:11], 0 offset:200
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
+; SI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
; SI-NEXT: buffer_store_dword v3, off, s[8:11], 0 offset:316
; SI-NEXT: buffer_store_dword v4, off, s[8:11], 0 offset:312
; SI-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:308
@@ -6141,6 +6124,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; SI-NEXT: buffer_store_dword v14, off, s[8:11], 0 offset:196
; SI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; SI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x200, v0
; SI-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen
; SI-NEXT: buffer_store_dword v17, off, s[8:11], 0 offset:832
; SI-NEXT: buffer_store_dword v11, off, s[8:11], 0 offset:828
@@ -6202,7 +6186,6 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: v_mov_b32_e32 v6, 0x3f638e37
; VI-NEXT: buffer_store_dword v9, off, s[8:11], 0 offset:260
; VI-NEXT: v_mov_b32_e32 v9, 0xb702e758
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:320
; VI-NEXT: v_mov_b32_e32 v3, 0x3f3d349e
; VI-NEXT: v_mov_b32_e32 v4, 0x3f523be1
@@ -6219,8 +6202,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: v_mov_b32_e32 v11, 0x3efcd89c
; VI-NEXT: v_mov_b32_e32 v14, 0xbf523be3
; VI-NEXT: v_mov_b32_e32 v16, 0xbf638e39
-; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
-; VI-NEXT: s_mov_b32 s0, 0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: buffer_store_dword v2, off, s[8:11], 0 offset:284
; VI-NEXT: v_mov_b32_e32 v2, 0xbefcd89f
; VI-NEXT: v_mov_b32_e32 v7, 0xbeae29dc
@@ -6240,8 +6222,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: buffer_store_dword v14, off, s[8:11], 0 offset:204
; VI-NEXT: buffer_store_dword v13, off, s[8:11], 0 offset:200
; VI-NEXT: v_mov_b32_e32 v14, 0x3f20e7f5
-; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; VI-NEXT: v_and_b32_e32 v0, 0x1fc, v0
; VI-NEXT: buffer_store_dword v3, off, s[8:11], 0 offset:316
; VI-NEXT: buffer_store_dword v4, off, s[8:11], 0 offset:312
; VI-NEXT: buffer_store_dword v5, off, s[8:11], 0 offset:308
@@ -6258,6 +6239,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
; VI-NEXT: buffer_store_dword v14, off, s[8:11], 0 offset:196
; VI-NEXT: v_mov_b32_e32 v17, 0x3f20e7f4
; VI-NEXT: v_mov_b32_e32 v18, 0x3f3d349c
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x200, v0
; VI-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen
; VI-NEXT: buffer_store_dword v17, off, s[8:11], 0 offset:832
; VI-NEXT: buffer_store_dword v11, off, s[8:11], 0 offset:828
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store.ll b/llvm/test/CodeGen/AMDGPU/trunc-store.ll
index e57dec3f096398..9856ef2a870222 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc-store.ll
@@ -446,23 +446,22 @@ define void @global_fp_truncstore_v6f32_to_v6bf16(ptr addrspace(1) %ptr, <6 x fl
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
; VI-NEXT: v_cndmask_b32_e32 v6, v9, v8, vcc
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
-; VI-NEXT: s_movk_i32 s4, 0x7fff
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
-; VI-NEXT: v_add_u32_e32 v9, vcc, s4, v9
+; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v7
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
; VI-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc
; VI-NEXT: v_bfe_u32 v8, v4, 16, 1
; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v4
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_add_u32_e32 v8, vcc, s4, v8
+; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: v_alignbit_b32 v6, v7, v6, 16
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; VI-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc
; VI-NEXT: v_bfe_u32 v8, v5, 16, 1
; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v5
-; VI-NEXT: v_add_u32_e32 v8, vcc, s4, v8
+; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; VI-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc
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