[llvm] [AArch64][GlobalISel] Improve fixed-point int-to-fp selection (PR #224055)

[David Green via llvm-commits]

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@@ -1408,59 +1455,38 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     case Intrinsic::aarch64_neon_fcvtps:
     case Intrinsic::aarch64_neon_fcvtpu: {
       OpRegBankIdx[2] = PMI_FirstFPR;
-      if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {
-        OpRegBankIdx[0] = PMI_FirstFPR;
-        break;
-      }
-      TypeSize DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
-      TypeSize SrcSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, TRI);
-      // Fp conversions to i16 must be kept on fp register banks to ensure
-      // proper saturation, as there are no 16-bit gprs.
-      // In addition, conversion intrinsics have fpr output when the input
-      // size matches the output size, or FPRCVT is present.
-      if (DstSize == 16 ||
-          ((DstSize == SrcSize || STI.hasFeature(AArch64::FeatureFPRCVT)) &&
-           all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
-                  [&](const MachineInstr &UseMI) {
-                    return onlyUsesFP(UseMI, MRI, TRI) ||
-                           prefersFPUse(UseMI, MRI, TRI);
-                  })))
+      if (shouldUseFPRForCvtOperand(
+              MI, CvtBankedOperand::Def,
+              /*ForceFPRForBankedOp16=*/true,
+              /*ForceFPRForOtherOp16=*/false,
+              /*AllowFPRCVT=*/STI.hasFeature(AArch64::FeatureFPRCVT),
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davemgreen wrote:

STI.hasFPRCVT()

https://github.com/llvm/llvm-project/pull/224055