[llvm] [RISCV] Don't process scalar instructions in VLOptimizer. NFC (PR #225656)

[Luke Lau via llvm-commits]

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@@ -95,6 +95,14 @@ class RISCVVLOptimizerImpl {
              RISCVRegisterInfo::isRVVRegClass(MRI->getRegClass(MO.getReg()));
     });
   }
+
+  /// \returns all vector virtual registers that \p MI defines.
+  auto virtual_vec_defs(const MachineInstr &MI) const {
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lukel97 wrote:

Yeah, which is in turn to match `Machineinstr::all_uses` etc. I think there's some convention that ranges and iterators use snake_case for naming?

https://github.com/llvm/llvm-project/pull/225656