[llvm] [GlobalISel] [AArch64] Skip redundant shift amount masking during isel (PR #223136)

[David Green via llvm-commits]

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@@ -67,7 +73,8 @@ define i64 @test5(i64 %y, i32 %s) {
 ; CHECK-LABEL: test5:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
-; CHECK-NEXT:    asr x0, x0, x1
+; CHECK-NEXT:    sxtw x8, w1
+; CHECK-NEXT:    asr x0, x0, x8
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davemgreen wrote:

It looks like this is still causing regressions. We probably don't have tests for all patterns.

https://github.com/llvm/llvm-project/pull/223136