[llvm] [AArch64] Use `ZIP1/2` over `INS` for vector concat (PR #142427)

[Eduardo Moscoso Rubino via llvm-commits]

emrubino wrote:

Hi

Couldn’t you just restrain it for the case the user specifies the
Cortex-A55 as a target? I think the pattern “begs” for a zip here and it is
the best choice for most cores and it should, by default, emit the zip (but
that is just my opinion). I don’t know about the A55 but is this a target
in which we could/should switch ALL zip’s then? Wouldn’t it belong on a
target dependent pass that does the substitution?

Eduardo Moscoso Rubino

"Whenever an honest man discovers that he is mistaken, he will either cease
to be mistaken, or he will cease to be honest" - Unknown author


On Wed, Sep 23, 2026 at 10:35 Csanád Hajdú ***@***.***> wrote:

> *Il-Capitano* left a comment (llvm/llvm-project#142427)
> <https://github.com/llvm/llvm-project/pull/142427#issuecomment-5791674906>
>
> I stopped working on this because I couldn't come up with a good solution
> that handles both Cortex-A55 and bigger cores. I think ideally we would
> have a post-RA pass that converts zip1 vA.2d vA.2d vB.2d to mov vA.d[1],
> vB.d[0], but it doesn't fit into the current pass pipeline neatly.
>
> Feel free to pick this up if you think it's valuable for you.
>
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https://github.com/llvm/llvm-project/pull/142427