[llvm] [RISCV] Don't process scalar instructions in VLOptimizer. NFC (PR #225656)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/225656

If an instruction doesn't define or use a vector register it won't
take part in the dataflow analysis. Skipping these improves compile
time. Measured to reduce geomean −0.379% instructions retired on
CTMark w/ a stage2 rva23u64 -O3 Clang build.


>From 3889079341fd084f92a636d7df8e2c08bba81e3b Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 23 Sep 2026 10:26:14 +0100
Subject: [PATCH] [RISCV] Don't process scalar instructions in VLOptimizer. NFC
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If an instruction doesn't define or use a vector register it won't
take part in the dataflow analysis. Skipping these improves compile
time. Measured to reduce geomean −0.379% instructions retired on
CTMark w/ a stage2 rva23u64 -O3 Clang build.
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index f63cddc0eee68..404e1fecafeda 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -95,6 +95,14 @@ class RISCVVLOptimizerImpl {
              RISCVRegisterInfo::isRVVRegClass(MRI->getRegClass(MO.getReg()));
     });
   }
+
+  /// \returns all vector virtual registers that \p MI defines.
+  auto virtual_vec_defs(const MachineInstr &MI) const {
+    return make_filter_range(MI.all_defs(), [this](const MachineOperand &MO) {
+      return MO.getReg().isVirtual() &&
+             RISCVRegisterInfo::isRVVRegClass(MRI->getRegClass(MO.getReg()));
+    });
+  }
 };
 
 class RISCVVLOptimizerLegacy : public MachineFunctionPass {
@@ -1402,13 +1410,17 @@ bool RISCVVLOptimizerImpl::run(MachineFunction &MF) {
 
   assert(DemandedVLs.empty());
 
-  // For each instruction that defines a vector, propagate the VL it
+  // For each instruction that defines or uses a vector, propagate the VL it
   // uses to its inputs.
   for (MachineBasicBlock *MBB : post_order(&MF)) {
     assert(MDT->isReachableFromEntry(MBB));
-    for (MachineInstr &MI : reverse(*MBB))
-      if (!MI.isDebugInstr())
-        Worklist.insert(&MI);
+    for (MachineInstr &MI : reverse(*MBB)) {
+      if (MI.isDebugInstr())
+        continue;
+      if (virtual_vec_defs(MI).empty() && virtual_vec_uses(MI).empty())
+        continue;
+      Worklist.insert(&MI);
+    }
   }
 
   while (!Worklist.empty()) {