[llvm] [LLVM][CodeGen][AArch64] Implement expansion for fixed-length get.active.lane.mask. (PR #225459)

[Luke Lau via llvm-commits]

================
@@ -1737,6 +1743,42 @@ SDValue VectorLegalizer::ExpandVP_REM(SDNode *Node) {
   return DAG.getNode(ISD::SUB, DL, VT, Dividend, Mul);
 }
 
+SDValue VectorLegalizer::ExpandGET_ACTIVE_LANE_MASK(SDNode *N) {
+  SDLoc DL(N);
+
+  SDValue Start = N->getOperand(0);
+  SDValue End = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  EVT OpVT = Start.getValueType();
+
+  // First try a promoted result type to avoid range issues.
+  EVT PromoteVT = VT.changeVectorElementType(*DAG.getContext(), OpVT);
+  if (TLI.isTypeLegal(PromoteVT)) {
+    SDValue StartV = DAG.getSplat(PromoteVT, DL, Start);
+    SDValue Seq = DAG.getStepVector(DL, PromoteVT);
+    Seq = DAG.getNode(ISD::UADDSAT, DL, PromoteVT, Seq, StartV);
+
+    SDValue EndV = DAG.getSplat(PromoteVT, DL, End);
+    SDValue Mask = DAG.getSetCC(DL, PromoteVT, Seq, EndV, ISD::SETULT);
----------------
lukel97 wrote:

I think the mask needs to use the setcc type

```suggestion
    SDValue Mask = DAG.getSetCC(DL, TLI.getSetCCResultType(PromoteVT), Seq, EndV, ISD::SETULT);
    return DAG.getBoolExtOrTrunc(Mask, ...)
```

https://github.com/llvm/llvm-project/pull/225459