[llvm] [LLVM][CodeGen][AArch64] Implement expansion for fixed-length get.active.lane.mask. (PR #225459)

[Luke Lau via llvm-commits]

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@@ -1737,6 +1743,42 @@ SDValue VectorLegalizer::ExpandVP_REM(SDNode *Node) {
   return DAG.getNode(ISD::SUB, DL, VT, Dividend, Mul);
 }
 
+SDValue VectorLegalizer::ExpandGET_ACTIVE_LANE_MASK(SDNode *N) {
+  SDLoc DL(N);
+
+  SDValue Start = N->getOperand(0);
+  SDValue End = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  EVT OpVT = Start.getValueType();
+
+  // First try a promoted result type to avoid range issues.
+  EVT PromoteVT = VT.changeVectorElementType(*DAG.getContext(), OpVT);
+  if (TLI.isTypeLegal(PromoteVT)) {
+    SDValue StartV = DAG.getSplat(PromoteVT, DL, Start);
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lukel97 wrote:

Does anything guarantee that PromoteVT is large enough to fit the maximum number of elements? E.g. if OpVT = i8 but VT = <512 x i1> then I think the step vector will wrap. I think we need a similar `isUIntN(PromoteVT.getScalarSizeInBits(), PromoteVT.getVectorNumElements())` check like below

https://github.com/llvm/llvm-project/pull/225459